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Merge remote-tracking branch 'asoc/fix/wm8993' into asoc-linus
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
101 extern int radeon_runtime_pm;
102 extern int radeon_hard_reset;
103
104 /*
105 * Copy from radeon_drv.h so we don't have to include both and have conflicting
106 * symbol;
107 */
108 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
109 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
110 /* RADEON_IB_POOL_SIZE must be a power of 2 */
111 #define RADEON_IB_POOL_SIZE 16
112 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
113 #define RADEONFB_CONN_LIMIT 4
114 #define RADEON_BIOS_NUM_SCRATCH 8
115
116 /* max number of rings */
117 #define RADEON_NUM_RINGS 6
118
119 /* fence seq are set to this number when signaled */
120 #define RADEON_FENCE_SIGNALED_SEQ 0LL
121
122 /* internal ring indices */
123 /* r1xx+ has gfx CP ring */
124 #define RADEON_RING_TYPE_GFX_INDEX 0
125
126 /* cayman has 2 compute CP rings */
127 #define CAYMAN_RING_TYPE_CP1_INDEX 1
128 #define CAYMAN_RING_TYPE_CP2_INDEX 2
129
130 /* R600+ has an async dma ring */
131 #define R600_RING_TYPE_DMA_INDEX 3
132 /* cayman add a second async dma ring */
133 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
134
135 /* R600+ */
136 #define R600_RING_TYPE_UVD_INDEX 5
137
138 /* hardcode those limit for now */
139 #define RADEON_VA_IB_OFFSET (1 << 20)
140 #define RADEON_VA_RESERVED_SIZE (8 << 20)
141 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
142
143 /* hard reset data */
144 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
145
146 /* reset flags */
147 #define RADEON_RESET_GFX (1 << 0)
148 #define RADEON_RESET_COMPUTE (1 << 1)
149 #define RADEON_RESET_DMA (1 << 2)
150 #define RADEON_RESET_CP (1 << 3)
151 #define RADEON_RESET_GRBM (1 << 4)
152 #define RADEON_RESET_DMA1 (1 << 5)
153 #define RADEON_RESET_RLC (1 << 6)
154 #define RADEON_RESET_SEM (1 << 7)
155 #define RADEON_RESET_IH (1 << 8)
156 #define RADEON_RESET_VMC (1 << 9)
157 #define RADEON_RESET_MC (1 << 10)
158 #define RADEON_RESET_DISPLAY (1 << 11)
159
160 /* CG block flags */
161 #define RADEON_CG_BLOCK_GFX (1 << 0)
162 #define RADEON_CG_BLOCK_MC (1 << 1)
163 #define RADEON_CG_BLOCK_SDMA (1 << 2)
164 #define RADEON_CG_BLOCK_UVD (1 << 3)
165 #define RADEON_CG_BLOCK_VCE (1 << 4)
166 #define RADEON_CG_BLOCK_HDP (1 << 5)
167 #define RADEON_CG_BLOCK_BIF (1 << 6)
168
169 /* CG flags */
170 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
171 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
172 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
173 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
174 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
175 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
176 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
177 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
178 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
179 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
180 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
181 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
182 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
183 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
184 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
185 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
186 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
187
188 /* PG flags */
189 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
190 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
191 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
192 #define RADEON_PG_SUPPORT_UVD (1 << 3)
193 #define RADEON_PG_SUPPORT_VCE (1 << 4)
194 #define RADEON_PG_SUPPORT_CP (1 << 5)
195 #define RADEON_PG_SUPPORT_GDS (1 << 6)
196 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
197 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
198 #define RADEON_PG_SUPPORT_ACP (1 << 9)
199 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
200
201 /* max cursor sizes (in pixels) */
202 #define CURSOR_WIDTH 64
203 #define CURSOR_HEIGHT 64
204
205 #define CIK_CURSOR_WIDTH 128
206 #define CIK_CURSOR_HEIGHT 128
207
208 /*
209 * Errata workarounds.
210 */
211 enum radeon_pll_errata {
212 CHIP_ERRATA_R300_CG = 0x00000001,
213 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
214 CHIP_ERRATA_PLL_DELAY = 0x00000004
215 };
216
217
218 struct radeon_device;
219
220
221 /*
222 * BIOS.
223 */
224 bool radeon_get_bios(struct radeon_device *rdev);
225
226 /*
227 * Dummy page
228 */
229 struct radeon_dummy_page {
230 struct page *page;
231 dma_addr_t addr;
232 };
233 int radeon_dummy_page_init(struct radeon_device *rdev);
234 void radeon_dummy_page_fini(struct radeon_device *rdev);
235
236
237 /*
238 * Clocks
239 */
240 struct radeon_clock {
241 struct radeon_pll p1pll;
242 struct radeon_pll p2pll;
243 struct radeon_pll dcpll;
244 struct radeon_pll spll;
245 struct radeon_pll mpll;
246 /* 10 Khz units */
247 uint32_t default_mclk;
248 uint32_t default_sclk;
249 uint32_t default_dispclk;
250 uint32_t current_dispclk;
251 uint32_t dp_extclk;
252 uint32_t max_pixel_clock;
253 };
254
255 /*
256 * Power management
257 */
258 int radeon_pm_init(struct radeon_device *rdev);
259 int radeon_pm_late_init(struct radeon_device *rdev);
260 void radeon_pm_fini(struct radeon_device *rdev);
261 void radeon_pm_compute_clocks(struct radeon_device *rdev);
262 void radeon_pm_suspend(struct radeon_device *rdev);
263 void radeon_pm_resume(struct radeon_device *rdev);
264 void radeon_combios_get_power_modes(struct radeon_device *rdev);
265 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
266 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
267 u8 clock_type,
268 u32 clock,
269 bool strobe_mode,
270 struct atom_clock_dividers *dividers);
271 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
272 u32 clock,
273 bool strobe_mode,
274 struct atom_mpll_param *mpll_param);
275 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
276 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
277 u16 voltage_level, u8 voltage_type,
278 u32 *gpio_value, u32 *gpio_mask);
279 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
280 u32 eng_clock, u32 mem_clock);
281 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
282 u8 voltage_type, u16 *voltage_step);
283 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
284 u16 voltage_id, u16 *voltage);
285 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
286 u16 *voltage,
287 u16 leakage_idx);
288 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
289 u16 *leakage_id);
290 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
291 u16 *vddc, u16 *vddci,
292 u16 virtual_voltage_id,
293 u16 vbios_voltage_id);
294 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
295 u8 voltage_type,
296 u16 nominal_voltage,
297 u16 *true_voltage);
298 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
299 u8 voltage_type, u16 *min_voltage);
300 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
301 u8 voltage_type, u16 *max_voltage);
302 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
303 u8 voltage_type, u8 voltage_mode,
304 struct atom_voltage_table *voltage_table);
305 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
306 u8 voltage_type, u8 voltage_mode);
307 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
308 u32 mem_clock);
309 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
310 u32 mem_clock);
311 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
312 u8 module_index,
313 struct atom_mc_reg_table *reg_table);
314 int radeon_atom_get_memory_info(struct radeon_device *rdev,
315 u8 module_index, struct atom_memory_info *mem_info);
316 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
317 bool gddr5, u8 module_index,
318 struct atom_memory_clock_range_table *mclk_range_table);
319 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
320 u16 voltage_id, u16 *voltage);
321 void rs690_pm_info(struct radeon_device *rdev);
322 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
323 unsigned *bankh, unsigned *mtaspect,
324 unsigned *tile_split);
325
326 /*
327 * Fences.
328 */
329 struct radeon_fence_driver {
330 uint32_t scratch_reg;
331 uint64_t gpu_addr;
332 volatile uint32_t *cpu_addr;
333 /* sync_seq is protected by ring emission lock */
334 uint64_t sync_seq[RADEON_NUM_RINGS];
335 atomic64_t last_seq;
336 bool initialized;
337 };
338
339 struct radeon_fence {
340 struct radeon_device *rdev;
341 struct kref kref;
342 /* protected by radeon_fence.lock */
343 uint64_t seq;
344 /* RB, DMA, etc. */
345 unsigned ring;
346 };
347
348 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
349 int radeon_fence_driver_init(struct radeon_device *rdev);
350 void radeon_fence_driver_fini(struct radeon_device *rdev);
351 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
352 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
353 void radeon_fence_process(struct radeon_device *rdev, int ring);
354 bool radeon_fence_signaled(struct radeon_fence *fence);
355 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
356 int radeon_fence_wait_locked(struct radeon_fence *fence);
357 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
358 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
359 int radeon_fence_wait_any(struct radeon_device *rdev,
360 struct radeon_fence **fences,
361 bool intr);
362 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
363 void radeon_fence_unref(struct radeon_fence **fence);
364 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
365 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
366 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
367 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
368 struct radeon_fence *b)
369 {
370 if (!a) {
371 return b;
372 }
373
374 if (!b) {
375 return a;
376 }
377
378 BUG_ON(a->ring != b->ring);
379
380 if (a->seq > b->seq) {
381 return a;
382 } else {
383 return b;
384 }
385 }
386
387 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
388 struct radeon_fence *b)
389 {
390 if (!a) {
391 return false;
392 }
393
394 if (!b) {
395 return true;
396 }
397
398 BUG_ON(a->ring != b->ring);
399
400 return a->seq < b->seq;
401 }
402
403 /*
404 * Tiling registers
405 */
406 struct radeon_surface_reg {
407 struct radeon_bo *bo;
408 };
409
410 #define RADEON_GEM_MAX_SURFACES 8
411
412 /*
413 * TTM.
414 */
415 struct radeon_mman {
416 struct ttm_bo_global_ref bo_global_ref;
417 struct drm_global_reference mem_global_ref;
418 struct ttm_bo_device bdev;
419 bool mem_global_referenced;
420 bool initialized;
421
422 #if defined(CONFIG_DEBUG_FS)
423 struct dentry *vram;
424 struct dentry *gtt;
425 #endif
426 };
427
428 /* bo virtual address in a specific vm */
429 struct radeon_bo_va {
430 /* protected by bo being reserved */
431 struct list_head bo_list;
432 uint64_t soffset;
433 uint64_t eoffset;
434 uint32_t flags;
435 bool valid;
436 unsigned ref_count;
437
438 /* protected by vm mutex */
439 struct list_head vm_list;
440
441 /* constant after initialization */
442 struct radeon_vm *vm;
443 struct radeon_bo *bo;
444 };
445
446 struct radeon_bo {
447 /* Protected by gem.mutex */
448 struct list_head list;
449 /* Protected by tbo.reserved */
450 u32 placements[3];
451 struct ttm_placement placement;
452 struct ttm_buffer_object tbo;
453 struct ttm_bo_kmap_obj kmap;
454 unsigned pin_count;
455 void *kptr;
456 u32 tiling_flags;
457 u32 pitch;
458 int surface_reg;
459 /* list of all virtual address to which this bo
460 * is associated to
461 */
462 struct list_head va;
463 /* Constant after initialization */
464 struct radeon_device *rdev;
465 struct drm_gem_object gem_base;
466
467 struct ttm_bo_kmap_obj dma_buf_vmap;
468 pid_t pid;
469 };
470 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
471
472 struct radeon_bo_list {
473 struct ttm_validate_buffer tv;
474 struct radeon_bo *bo;
475 uint64_t gpu_offset;
476 bool written;
477 unsigned domain;
478 unsigned alt_domain;
479 u32 tiling_flags;
480 };
481
482 int radeon_gem_debugfs_init(struct radeon_device *rdev);
483
484 /* sub-allocation manager, it has to be protected by another lock.
485 * By conception this is an helper for other part of the driver
486 * like the indirect buffer or semaphore, which both have their
487 * locking.
488 *
489 * Principe is simple, we keep a list of sub allocation in offset
490 * order (first entry has offset == 0, last entry has the highest
491 * offset).
492 *
493 * When allocating new object we first check if there is room at
494 * the end total_size - (last_object_offset + last_object_size) >=
495 * alloc_size. If so we allocate new object there.
496 *
497 * When there is not enough room at the end, we start waiting for
498 * each sub object until we reach object_offset+object_size >=
499 * alloc_size, this object then become the sub object we return.
500 *
501 * Alignment can't be bigger than page size.
502 *
503 * Hole are not considered for allocation to keep things simple.
504 * Assumption is that there won't be hole (all object on same
505 * alignment).
506 */
507 struct radeon_sa_manager {
508 wait_queue_head_t wq;
509 struct radeon_bo *bo;
510 struct list_head *hole;
511 struct list_head flist[RADEON_NUM_RINGS];
512 struct list_head olist;
513 unsigned size;
514 uint64_t gpu_addr;
515 void *cpu_ptr;
516 uint32_t domain;
517 uint32_t align;
518 };
519
520 struct radeon_sa_bo;
521
522 /* sub-allocation buffer */
523 struct radeon_sa_bo {
524 struct list_head olist;
525 struct list_head flist;
526 struct radeon_sa_manager *manager;
527 unsigned soffset;
528 unsigned eoffset;
529 struct radeon_fence *fence;
530 };
531
532 /*
533 * GEM objects.
534 */
535 struct radeon_gem {
536 struct mutex mutex;
537 struct list_head objects;
538 };
539
540 int radeon_gem_init(struct radeon_device *rdev);
541 void radeon_gem_fini(struct radeon_device *rdev);
542 int radeon_gem_object_create(struct radeon_device *rdev, int size,
543 int alignment, int initial_domain,
544 bool discardable, bool kernel,
545 struct drm_gem_object **obj);
546
547 int radeon_mode_dumb_create(struct drm_file *file_priv,
548 struct drm_device *dev,
549 struct drm_mode_create_dumb *args);
550 int radeon_mode_dumb_mmap(struct drm_file *filp,
551 struct drm_device *dev,
552 uint32_t handle, uint64_t *offset_p);
553
554 /*
555 * Semaphores.
556 */
557 /* everything here is constant */
558 struct radeon_semaphore {
559 struct radeon_sa_bo *sa_bo;
560 signed waiters;
561 uint64_t gpu_addr;
562 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
563 };
564
565 int radeon_semaphore_create(struct radeon_device *rdev,
566 struct radeon_semaphore **semaphore);
567 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
568 struct radeon_semaphore *semaphore);
569 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
570 struct radeon_semaphore *semaphore);
571 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
572 struct radeon_fence *fence);
573 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
574 struct radeon_semaphore *semaphore,
575 int waiting_ring);
576 void radeon_semaphore_free(struct radeon_device *rdev,
577 struct radeon_semaphore **semaphore,
578 struct radeon_fence *fence);
579
580 /*
581 * GART structures, functions & helpers
582 */
583 struct radeon_mc;
584
585 #define RADEON_GPU_PAGE_SIZE 4096
586 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
587 #define RADEON_GPU_PAGE_SHIFT 12
588 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
589
590 struct radeon_gart {
591 dma_addr_t table_addr;
592 struct radeon_bo *robj;
593 void *ptr;
594 unsigned num_gpu_pages;
595 unsigned num_cpu_pages;
596 unsigned table_size;
597 struct page **pages;
598 dma_addr_t *pages_addr;
599 bool ready;
600 };
601
602 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
603 void radeon_gart_table_ram_free(struct radeon_device *rdev);
604 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
605 void radeon_gart_table_vram_free(struct radeon_device *rdev);
606 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
607 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
608 int radeon_gart_init(struct radeon_device *rdev);
609 void radeon_gart_fini(struct radeon_device *rdev);
610 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
611 int pages);
612 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
613 int pages, struct page **pagelist,
614 dma_addr_t *dma_addr);
615 void radeon_gart_restore(struct radeon_device *rdev);
616
617
618 /*
619 * GPU MC structures, functions & helpers
620 */
621 struct radeon_mc {
622 resource_size_t aper_size;
623 resource_size_t aper_base;
624 resource_size_t agp_base;
625 /* for some chips with <= 32MB we need to lie
626 * about vram size near mc fb location */
627 u64 mc_vram_size;
628 u64 visible_vram_size;
629 u64 gtt_size;
630 u64 gtt_start;
631 u64 gtt_end;
632 u64 vram_start;
633 u64 vram_end;
634 unsigned vram_width;
635 u64 real_vram_size;
636 int vram_mtrr;
637 bool vram_is_ddr;
638 bool igp_sideport_enabled;
639 u64 gtt_base_align;
640 u64 mc_mask;
641 };
642
643 bool radeon_combios_sideport_present(struct radeon_device *rdev);
644 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
645
646 /*
647 * GPU scratch registers structures, functions & helpers
648 */
649 struct radeon_scratch {
650 unsigned num_reg;
651 uint32_t reg_base;
652 bool free[32];
653 uint32_t reg[32];
654 };
655
656 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
657 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
658
659 /*
660 * GPU doorbell structures, functions & helpers
661 */
662 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
663
664 struct radeon_doorbell {
665 /* doorbell mmio */
666 resource_size_t base;
667 resource_size_t size;
668 u32 __iomem *ptr;
669 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
670 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
671 };
672
673 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
674 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
675
676 /*
677 * IRQS.
678 */
679
680 struct radeon_unpin_work {
681 struct work_struct work;
682 struct radeon_device *rdev;
683 int crtc_id;
684 struct radeon_fence *fence;
685 struct drm_pending_vblank_event *event;
686 struct radeon_bo *old_rbo;
687 u64 new_crtc_base;
688 };
689
690 struct r500_irq_stat_regs {
691 u32 disp_int;
692 u32 hdmi0_status;
693 };
694
695 struct r600_irq_stat_regs {
696 u32 disp_int;
697 u32 disp_int_cont;
698 u32 disp_int_cont2;
699 u32 d1grph_int;
700 u32 d2grph_int;
701 u32 hdmi0_status;
702 u32 hdmi1_status;
703 };
704
705 struct evergreen_irq_stat_regs {
706 u32 disp_int;
707 u32 disp_int_cont;
708 u32 disp_int_cont2;
709 u32 disp_int_cont3;
710 u32 disp_int_cont4;
711 u32 disp_int_cont5;
712 u32 d1grph_int;
713 u32 d2grph_int;
714 u32 d3grph_int;
715 u32 d4grph_int;
716 u32 d5grph_int;
717 u32 d6grph_int;
718 u32 afmt_status1;
719 u32 afmt_status2;
720 u32 afmt_status3;
721 u32 afmt_status4;
722 u32 afmt_status5;
723 u32 afmt_status6;
724 };
725
726 struct cik_irq_stat_regs {
727 u32 disp_int;
728 u32 disp_int_cont;
729 u32 disp_int_cont2;
730 u32 disp_int_cont3;
731 u32 disp_int_cont4;
732 u32 disp_int_cont5;
733 u32 disp_int_cont6;
734 };
735
736 union radeon_irq_stat_regs {
737 struct r500_irq_stat_regs r500;
738 struct r600_irq_stat_regs r600;
739 struct evergreen_irq_stat_regs evergreen;
740 struct cik_irq_stat_regs cik;
741 };
742
743 #define RADEON_MAX_HPD_PINS 6
744 #define RADEON_MAX_CRTCS 6
745 #define RADEON_MAX_AFMT_BLOCKS 7
746
747 struct radeon_irq {
748 bool installed;
749 spinlock_t lock;
750 atomic_t ring_int[RADEON_NUM_RINGS];
751 bool crtc_vblank_int[RADEON_MAX_CRTCS];
752 atomic_t pflip[RADEON_MAX_CRTCS];
753 wait_queue_head_t vblank_queue;
754 bool hpd[RADEON_MAX_HPD_PINS];
755 bool afmt[RADEON_MAX_AFMT_BLOCKS];
756 union radeon_irq_stat_regs stat_regs;
757 bool dpm_thermal;
758 };
759
760 int radeon_irq_kms_init(struct radeon_device *rdev);
761 void radeon_irq_kms_fini(struct radeon_device *rdev);
762 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
763 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
764 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
765 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
766 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
767 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
768 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
769 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
770
771 /*
772 * CP & rings.
773 */
774
775 struct radeon_ib {
776 struct radeon_sa_bo *sa_bo;
777 uint32_t length_dw;
778 uint64_t gpu_addr;
779 uint32_t *ptr;
780 int ring;
781 struct radeon_fence *fence;
782 struct radeon_vm *vm;
783 bool is_const_ib;
784 struct radeon_semaphore *semaphore;
785 };
786
787 struct radeon_ring {
788 struct radeon_bo *ring_obj;
789 volatile uint32_t *ring;
790 unsigned rptr;
791 unsigned rptr_offs;
792 unsigned rptr_save_reg;
793 u64 next_rptr_gpu_addr;
794 volatile u32 *next_rptr_cpu_addr;
795 unsigned wptr;
796 unsigned wptr_old;
797 unsigned ring_size;
798 unsigned ring_free_dw;
799 int count_dw;
800 unsigned long last_activity;
801 unsigned last_rptr;
802 uint64_t gpu_addr;
803 uint32_t align_mask;
804 uint32_t ptr_mask;
805 bool ready;
806 u32 nop;
807 u32 idx;
808 u64 last_semaphore_signal_addr;
809 u64 last_semaphore_wait_addr;
810 /* for CIK queues */
811 u32 me;
812 u32 pipe;
813 u32 queue;
814 struct radeon_bo *mqd_obj;
815 u32 doorbell_index;
816 unsigned wptr_offs;
817 };
818
819 struct radeon_mec {
820 struct radeon_bo *hpd_eop_obj;
821 u64 hpd_eop_gpu_addr;
822 u32 num_pipe;
823 u32 num_mec;
824 u32 num_queue;
825 };
826
827 /*
828 * VM
829 */
830
831 /* maximum number of VMIDs */
832 #define RADEON_NUM_VM 16
833
834 /* defines number of bits in page table versus page directory,
835 * a page is 4KB so we have 12 bits offset, 9 bits in the page
836 * table and the remaining 19 bits are in the page directory */
837 #define RADEON_VM_BLOCK_SIZE 9
838
839 /* number of entries in page table */
840 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
841
842 /* PTBs (Page Table Blocks) need to be aligned to 32K */
843 #define RADEON_VM_PTB_ALIGN_SIZE 32768
844 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
845 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
846
847 #define R600_PTE_VALID (1 << 0)
848 #define R600_PTE_SYSTEM (1 << 1)
849 #define R600_PTE_SNOOPED (1 << 2)
850 #define R600_PTE_READABLE (1 << 5)
851 #define R600_PTE_WRITEABLE (1 << 6)
852
853 struct radeon_vm {
854 struct list_head list;
855 struct list_head va;
856 unsigned id;
857
858 /* contains the page directory */
859 struct radeon_sa_bo *page_directory;
860 uint64_t pd_gpu_addr;
861
862 /* array of page tables, one for each page directory entry */
863 struct radeon_sa_bo **page_tables;
864
865 struct mutex mutex;
866 /* last fence for cs using this vm */
867 struct radeon_fence *fence;
868 /* last flush or NULL if we still need to flush */
869 struct radeon_fence *last_flush;
870 /* last use of vmid */
871 struct radeon_fence *last_id_use;
872 };
873
874 struct radeon_vm_manager {
875 struct mutex lock;
876 struct list_head lru_vm;
877 struct radeon_fence *active[RADEON_NUM_VM];
878 struct radeon_sa_manager sa_manager;
879 uint32_t max_pfn;
880 /* number of VMIDs */
881 unsigned nvm;
882 /* vram base address for page table entry */
883 u64 vram_base_offset;
884 /* is vm enabled? */
885 bool enabled;
886 };
887
888 /*
889 * file private structure
890 */
891 struct radeon_fpriv {
892 struct radeon_vm vm;
893 };
894
895 /*
896 * R6xx+ IH ring
897 */
898 struct r600_ih {
899 struct radeon_bo *ring_obj;
900 volatile uint32_t *ring;
901 unsigned rptr;
902 unsigned ring_size;
903 uint64_t gpu_addr;
904 uint32_t ptr_mask;
905 atomic_t lock;
906 bool enabled;
907 };
908
909 /*
910 * RLC stuff
911 */
912 #include "clearstate_defs.h"
913
914 struct radeon_rlc {
915 /* for power gating */
916 struct radeon_bo *save_restore_obj;
917 uint64_t save_restore_gpu_addr;
918 volatile uint32_t *sr_ptr;
919 const u32 *reg_list;
920 u32 reg_list_size;
921 /* for clear state */
922 struct radeon_bo *clear_state_obj;
923 uint64_t clear_state_gpu_addr;
924 volatile uint32_t *cs_ptr;
925 const struct cs_section_def *cs_data;
926 u32 clear_state_size;
927 /* for cp tables */
928 struct radeon_bo *cp_table_obj;
929 uint64_t cp_table_gpu_addr;
930 volatile uint32_t *cp_table_ptr;
931 u32 cp_table_size;
932 };
933
934 int radeon_ib_get(struct radeon_device *rdev, int ring,
935 struct radeon_ib *ib, struct radeon_vm *vm,
936 unsigned size);
937 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
938 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
939 struct radeon_ib *const_ib);
940 int radeon_ib_pool_init(struct radeon_device *rdev);
941 void radeon_ib_pool_fini(struct radeon_device *rdev);
942 int radeon_ib_ring_tests(struct radeon_device *rdev);
943 /* Ring access between begin & end cannot sleep */
944 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
945 struct radeon_ring *ring);
946 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
947 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
948 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
949 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
950 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
951 void radeon_ring_undo(struct radeon_ring *ring);
952 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
953 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
954 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
955 void radeon_ring_lockup_update(struct radeon_ring *ring);
956 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
957 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
958 uint32_t **data);
959 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
960 unsigned size, uint32_t *data);
961 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
962 unsigned rptr_offs, u32 nop);
963 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
964
965
966 /* r600 async dma */
967 void r600_dma_stop(struct radeon_device *rdev);
968 int r600_dma_resume(struct radeon_device *rdev);
969 void r600_dma_fini(struct radeon_device *rdev);
970
971 void cayman_dma_stop(struct radeon_device *rdev);
972 int cayman_dma_resume(struct radeon_device *rdev);
973 void cayman_dma_fini(struct radeon_device *rdev);
974
975 /*
976 * CS.
977 */
978 struct radeon_cs_reloc {
979 struct drm_gem_object *gobj;
980 struct radeon_bo *robj;
981 struct radeon_bo_list lobj;
982 uint32_t handle;
983 uint32_t flags;
984 };
985
986 struct radeon_cs_chunk {
987 uint32_t chunk_id;
988 uint32_t length_dw;
989 uint32_t *kdata;
990 void __user *user_ptr;
991 };
992
993 struct radeon_cs_parser {
994 struct device *dev;
995 struct radeon_device *rdev;
996 struct drm_file *filp;
997 /* chunks */
998 unsigned nchunks;
999 struct radeon_cs_chunk *chunks;
1000 uint64_t *chunks_array;
1001 /* IB */
1002 unsigned idx;
1003 /* relocations */
1004 unsigned nrelocs;
1005 struct radeon_cs_reloc *relocs;
1006 struct radeon_cs_reloc **relocs_ptr;
1007 struct list_head validated;
1008 unsigned dma_reloc_idx;
1009 /* indices of various chunks */
1010 int chunk_ib_idx;
1011 int chunk_relocs_idx;
1012 int chunk_flags_idx;
1013 int chunk_const_ib_idx;
1014 struct radeon_ib ib;
1015 struct radeon_ib const_ib;
1016 void *track;
1017 unsigned family;
1018 int parser_error;
1019 u32 cs_flags;
1020 u32 ring;
1021 s32 priority;
1022 struct ww_acquire_ctx ticket;
1023 };
1024
1025 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1026 {
1027 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1028
1029 if (ibc->kdata)
1030 return ibc->kdata[idx];
1031 return p->ib.ptr[idx];
1032 }
1033
1034
1035 struct radeon_cs_packet {
1036 unsigned idx;
1037 unsigned type;
1038 unsigned reg;
1039 unsigned opcode;
1040 int count;
1041 unsigned one_reg_wr;
1042 };
1043
1044 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1045 struct radeon_cs_packet *pkt,
1046 unsigned idx, unsigned reg);
1047 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1048 struct radeon_cs_packet *pkt);
1049
1050
1051 /*
1052 * AGP
1053 */
1054 int radeon_agp_init(struct radeon_device *rdev);
1055 void radeon_agp_resume(struct radeon_device *rdev);
1056 void radeon_agp_suspend(struct radeon_device *rdev);
1057 void radeon_agp_fini(struct radeon_device *rdev);
1058
1059
1060 /*
1061 * Writeback
1062 */
1063 struct radeon_wb {
1064 struct radeon_bo *wb_obj;
1065 volatile uint32_t *wb;
1066 uint64_t gpu_addr;
1067 bool enabled;
1068 bool use_event;
1069 };
1070
1071 #define RADEON_WB_SCRATCH_OFFSET 0
1072 #define RADEON_WB_RING0_NEXT_RPTR 256
1073 #define RADEON_WB_CP_RPTR_OFFSET 1024
1074 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1075 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1076 #define R600_WB_DMA_RPTR_OFFSET 1792
1077 #define R600_WB_IH_WPTR_OFFSET 2048
1078 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1079 #define R600_WB_EVENT_OFFSET 3072
1080 #define CIK_WB_CP1_WPTR_OFFSET 3328
1081 #define CIK_WB_CP2_WPTR_OFFSET 3584
1082
1083 /**
1084 * struct radeon_pm - power management datas
1085 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1086 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1087 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1088 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1089 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1090 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1091 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1092 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1093 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1094 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1095 * @needed_bandwidth: current bandwidth needs
1096 *
1097 * It keeps track of various data needed to take powermanagement decision.
1098 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1099 * Equation between gpu/memory clock and available bandwidth is hw dependent
1100 * (type of memory, bus size, efficiency, ...)
1101 */
1102
1103 enum radeon_pm_method {
1104 PM_METHOD_PROFILE,
1105 PM_METHOD_DYNPM,
1106 PM_METHOD_DPM,
1107 };
1108
1109 enum radeon_dynpm_state {
1110 DYNPM_STATE_DISABLED,
1111 DYNPM_STATE_MINIMUM,
1112 DYNPM_STATE_PAUSED,
1113 DYNPM_STATE_ACTIVE,
1114 DYNPM_STATE_SUSPENDED,
1115 };
1116 enum radeon_dynpm_action {
1117 DYNPM_ACTION_NONE,
1118 DYNPM_ACTION_MINIMUM,
1119 DYNPM_ACTION_DOWNCLOCK,
1120 DYNPM_ACTION_UPCLOCK,
1121 DYNPM_ACTION_DEFAULT
1122 };
1123
1124 enum radeon_voltage_type {
1125 VOLTAGE_NONE = 0,
1126 VOLTAGE_GPIO,
1127 VOLTAGE_VDDC,
1128 VOLTAGE_SW
1129 };
1130
1131 enum radeon_pm_state_type {
1132 /* not used for dpm */
1133 POWER_STATE_TYPE_DEFAULT,
1134 POWER_STATE_TYPE_POWERSAVE,
1135 /* user selectable states */
1136 POWER_STATE_TYPE_BATTERY,
1137 POWER_STATE_TYPE_BALANCED,
1138 POWER_STATE_TYPE_PERFORMANCE,
1139 /* internal states */
1140 POWER_STATE_TYPE_INTERNAL_UVD,
1141 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1142 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1143 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1144 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1145 POWER_STATE_TYPE_INTERNAL_BOOT,
1146 POWER_STATE_TYPE_INTERNAL_THERMAL,
1147 POWER_STATE_TYPE_INTERNAL_ACPI,
1148 POWER_STATE_TYPE_INTERNAL_ULV,
1149 POWER_STATE_TYPE_INTERNAL_3DPERF,
1150 };
1151
1152 enum radeon_pm_profile_type {
1153 PM_PROFILE_DEFAULT,
1154 PM_PROFILE_AUTO,
1155 PM_PROFILE_LOW,
1156 PM_PROFILE_MID,
1157 PM_PROFILE_HIGH,
1158 };
1159
1160 #define PM_PROFILE_DEFAULT_IDX 0
1161 #define PM_PROFILE_LOW_SH_IDX 1
1162 #define PM_PROFILE_MID_SH_IDX 2
1163 #define PM_PROFILE_HIGH_SH_IDX 3
1164 #define PM_PROFILE_LOW_MH_IDX 4
1165 #define PM_PROFILE_MID_MH_IDX 5
1166 #define PM_PROFILE_HIGH_MH_IDX 6
1167 #define PM_PROFILE_MAX 7
1168
1169 struct radeon_pm_profile {
1170 int dpms_off_ps_idx;
1171 int dpms_on_ps_idx;
1172 int dpms_off_cm_idx;
1173 int dpms_on_cm_idx;
1174 };
1175
1176 enum radeon_int_thermal_type {
1177 THERMAL_TYPE_NONE,
1178 THERMAL_TYPE_EXTERNAL,
1179 THERMAL_TYPE_EXTERNAL_GPIO,
1180 THERMAL_TYPE_RV6XX,
1181 THERMAL_TYPE_RV770,
1182 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1183 THERMAL_TYPE_EVERGREEN,
1184 THERMAL_TYPE_SUMO,
1185 THERMAL_TYPE_NI,
1186 THERMAL_TYPE_SI,
1187 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1188 THERMAL_TYPE_CI,
1189 THERMAL_TYPE_KV,
1190 };
1191
1192 struct radeon_voltage {
1193 enum radeon_voltage_type type;
1194 /* gpio voltage */
1195 struct radeon_gpio_rec gpio;
1196 u32 delay; /* delay in usec from voltage drop to sclk change */
1197 bool active_high; /* voltage drop is active when bit is high */
1198 /* VDDC voltage */
1199 u8 vddc_id; /* index into vddc voltage table */
1200 u8 vddci_id; /* index into vddci voltage table */
1201 bool vddci_enabled;
1202 /* r6xx+ sw */
1203 u16 voltage;
1204 /* evergreen+ vddci */
1205 u16 vddci;
1206 };
1207
1208 /* clock mode flags */
1209 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1210
1211 struct radeon_pm_clock_info {
1212 /* memory clock */
1213 u32 mclk;
1214 /* engine clock */
1215 u32 sclk;
1216 /* voltage info */
1217 struct radeon_voltage voltage;
1218 /* standardized clock flags */
1219 u32 flags;
1220 };
1221
1222 /* state flags */
1223 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1224
1225 struct radeon_power_state {
1226 enum radeon_pm_state_type type;
1227 struct radeon_pm_clock_info *clock_info;
1228 /* number of valid clock modes in this power state */
1229 int num_clock_modes;
1230 struct radeon_pm_clock_info *default_clock_mode;
1231 /* standardized state flags */
1232 u32 flags;
1233 u32 misc; /* vbios specific flags */
1234 u32 misc2; /* vbios specific flags */
1235 int pcie_lanes; /* pcie lanes */
1236 };
1237
1238 /*
1239 * Some modes are overclocked by very low value, accept them
1240 */
1241 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1242
1243 enum radeon_dpm_auto_throttle_src {
1244 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1245 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1246 };
1247
1248 enum radeon_dpm_event_src {
1249 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1250 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1251 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1252 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1253 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1254 };
1255
1256 struct radeon_ps {
1257 u32 caps; /* vbios flags */
1258 u32 class; /* vbios flags */
1259 u32 class2; /* vbios flags */
1260 /* UVD clocks */
1261 u32 vclk;
1262 u32 dclk;
1263 /* VCE clocks */
1264 u32 evclk;
1265 u32 ecclk;
1266 /* asic priv */
1267 void *ps_priv;
1268 };
1269
1270 struct radeon_dpm_thermal {
1271 /* thermal interrupt work */
1272 struct work_struct work;
1273 /* low temperature threshold */
1274 int min_temp;
1275 /* high temperature threshold */
1276 int max_temp;
1277 /* was interrupt low to high or high to low */
1278 bool high_to_low;
1279 };
1280
1281 enum radeon_clk_action
1282 {
1283 RADEON_SCLK_UP = 1,
1284 RADEON_SCLK_DOWN
1285 };
1286
1287 struct radeon_blacklist_clocks
1288 {
1289 u32 sclk;
1290 u32 mclk;
1291 enum radeon_clk_action action;
1292 };
1293
1294 struct radeon_clock_and_voltage_limits {
1295 u32 sclk;
1296 u32 mclk;
1297 u16 vddc;
1298 u16 vddci;
1299 };
1300
1301 struct radeon_clock_array {
1302 u32 count;
1303 u32 *values;
1304 };
1305
1306 struct radeon_clock_voltage_dependency_entry {
1307 u32 clk;
1308 u16 v;
1309 };
1310
1311 struct radeon_clock_voltage_dependency_table {
1312 u32 count;
1313 struct radeon_clock_voltage_dependency_entry *entries;
1314 };
1315
1316 union radeon_cac_leakage_entry {
1317 struct {
1318 u16 vddc;
1319 u32 leakage;
1320 };
1321 struct {
1322 u16 vddc1;
1323 u16 vddc2;
1324 u16 vddc3;
1325 };
1326 };
1327
1328 struct radeon_cac_leakage_table {
1329 u32 count;
1330 union radeon_cac_leakage_entry *entries;
1331 };
1332
1333 struct radeon_phase_shedding_limits_entry {
1334 u16 voltage;
1335 u32 sclk;
1336 u32 mclk;
1337 };
1338
1339 struct radeon_phase_shedding_limits_table {
1340 u32 count;
1341 struct radeon_phase_shedding_limits_entry *entries;
1342 };
1343
1344 struct radeon_uvd_clock_voltage_dependency_entry {
1345 u32 vclk;
1346 u32 dclk;
1347 u16 v;
1348 };
1349
1350 struct radeon_uvd_clock_voltage_dependency_table {
1351 u8 count;
1352 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1353 };
1354
1355 struct radeon_vce_clock_voltage_dependency_entry {
1356 u32 ecclk;
1357 u32 evclk;
1358 u16 v;
1359 };
1360
1361 struct radeon_vce_clock_voltage_dependency_table {
1362 u8 count;
1363 struct radeon_vce_clock_voltage_dependency_entry *entries;
1364 };
1365
1366 struct radeon_ppm_table {
1367 u8 ppm_design;
1368 u16 cpu_core_number;
1369 u32 platform_tdp;
1370 u32 small_ac_platform_tdp;
1371 u32 platform_tdc;
1372 u32 small_ac_platform_tdc;
1373 u32 apu_tdp;
1374 u32 dgpu_tdp;
1375 u32 dgpu_ulv_power;
1376 u32 tj_max;
1377 };
1378
1379 struct radeon_cac_tdp_table {
1380 u16 tdp;
1381 u16 configurable_tdp;
1382 u16 tdc;
1383 u16 battery_power_limit;
1384 u16 small_power_limit;
1385 u16 low_cac_leakage;
1386 u16 high_cac_leakage;
1387 u16 maximum_power_delivery_limit;
1388 };
1389
1390 struct radeon_dpm_dynamic_state {
1391 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1392 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1393 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1394 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1395 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1396 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1397 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1398 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1399 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1400 struct radeon_clock_array valid_sclk_values;
1401 struct radeon_clock_array valid_mclk_values;
1402 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1403 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1404 u32 mclk_sclk_ratio;
1405 u32 sclk_mclk_delta;
1406 u16 vddc_vddci_delta;
1407 u16 min_vddc_for_pcie_gen2;
1408 struct radeon_cac_leakage_table cac_leakage_table;
1409 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1410 struct radeon_ppm_table *ppm_table;
1411 struct radeon_cac_tdp_table *cac_tdp_table;
1412 };
1413
1414 struct radeon_dpm_fan {
1415 u16 t_min;
1416 u16 t_med;
1417 u16 t_high;
1418 u16 pwm_min;
1419 u16 pwm_med;
1420 u16 pwm_high;
1421 u8 t_hyst;
1422 u32 cycle_delay;
1423 u16 t_max;
1424 bool ucode_fan_control;
1425 };
1426
1427 enum radeon_pcie_gen {
1428 RADEON_PCIE_GEN1 = 0,
1429 RADEON_PCIE_GEN2 = 1,
1430 RADEON_PCIE_GEN3 = 2,
1431 RADEON_PCIE_GEN_INVALID = 0xffff
1432 };
1433
1434 enum radeon_dpm_forced_level {
1435 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1436 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1437 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1438 };
1439
1440 struct radeon_dpm {
1441 struct radeon_ps *ps;
1442 /* number of valid power states */
1443 int num_ps;
1444 /* current power state that is active */
1445 struct radeon_ps *current_ps;
1446 /* requested power state */
1447 struct radeon_ps *requested_ps;
1448 /* boot up power state */
1449 struct radeon_ps *boot_ps;
1450 /* default uvd power state */
1451 struct radeon_ps *uvd_ps;
1452 enum radeon_pm_state_type state;
1453 enum radeon_pm_state_type user_state;
1454 u32 platform_caps;
1455 u32 voltage_response_time;
1456 u32 backbias_response_time;
1457 void *priv;
1458 u32 new_active_crtcs;
1459 int new_active_crtc_count;
1460 u32 current_active_crtcs;
1461 int current_active_crtc_count;
1462 struct radeon_dpm_dynamic_state dyn_state;
1463 struct radeon_dpm_fan fan;
1464 u32 tdp_limit;
1465 u32 near_tdp_limit;
1466 u32 near_tdp_limit_adjusted;
1467 u32 sq_ramping_threshold;
1468 u32 cac_leakage;
1469 u16 tdp_od_limit;
1470 u32 tdp_adjustment;
1471 u16 load_line_slope;
1472 bool power_control;
1473 bool ac_power;
1474 /* special states active */
1475 bool thermal_active;
1476 bool uvd_active;
1477 /* thermal handling */
1478 struct radeon_dpm_thermal thermal;
1479 /* forced levels */
1480 enum radeon_dpm_forced_level forced_level;
1481 /* track UVD streams */
1482 unsigned sd;
1483 unsigned hd;
1484 };
1485
1486 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1487
1488 struct radeon_pm {
1489 struct mutex mutex;
1490 /* write locked while reprogramming mclk */
1491 struct rw_semaphore mclk_lock;
1492 u32 active_crtcs;
1493 int active_crtc_count;
1494 int req_vblank;
1495 bool vblank_sync;
1496 fixed20_12 max_bandwidth;
1497 fixed20_12 igp_sideport_mclk;
1498 fixed20_12 igp_system_mclk;
1499 fixed20_12 igp_ht_link_clk;
1500 fixed20_12 igp_ht_link_width;
1501 fixed20_12 k8_bandwidth;
1502 fixed20_12 sideport_bandwidth;
1503 fixed20_12 ht_bandwidth;
1504 fixed20_12 core_bandwidth;
1505 fixed20_12 sclk;
1506 fixed20_12 mclk;
1507 fixed20_12 needed_bandwidth;
1508 struct radeon_power_state *power_state;
1509 /* number of valid power states */
1510 int num_power_states;
1511 int current_power_state_index;
1512 int current_clock_mode_index;
1513 int requested_power_state_index;
1514 int requested_clock_mode_index;
1515 int default_power_state_index;
1516 u32 current_sclk;
1517 u32 current_mclk;
1518 u16 current_vddc;
1519 u16 current_vddci;
1520 u32 default_sclk;
1521 u32 default_mclk;
1522 u16 default_vddc;
1523 u16 default_vddci;
1524 struct radeon_i2c_chan *i2c_bus;
1525 /* selected pm method */
1526 enum radeon_pm_method pm_method;
1527 /* dynpm power management */
1528 struct delayed_work dynpm_idle_work;
1529 enum radeon_dynpm_state dynpm_state;
1530 enum radeon_dynpm_action dynpm_planned_action;
1531 unsigned long dynpm_action_timeout;
1532 bool dynpm_can_upclock;
1533 bool dynpm_can_downclock;
1534 /* profile-based power management */
1535 enum radeon_pm_profile_type profile;
1536 int profile_index;
1537 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1538 /* internal thermal controller on rv6xx+ */
1539 enum radeon_int_thermal_type int_thermal_type;
1540 struct device *int_hwmon_dev;
1541 /* dpm */
1542 bool dpm_enabled;
1543 struct radeon_dpm dpm;
1544 };
1545
1546 int radeon_pm_get_type_index(struct radeon_device *rdev,
1547 enum radeon_pm_state_type ps_type,
1548 int instance);
1549 /*
1550 * UVD
1551 */
1552 #define RADEON_MAX_UVD_HANDLES 10
1553 #define RADEON_UVD_STACK_SIZE (1024*1024)
1554 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1555
1556 struct radeon_uvd {
1557 struct radeon_bo *vcpu_bo;
1558 void *cpu_addr;
1559 uint64_t gpu_addr;
1560 void *saved_bo;
1561 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1562 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1563 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1564 struct delayed_work idle_work;
1565 };
1566
1567 int radeon_uvd_init(struct radeon_device *rdev);
1568 void radeon_uvd_fini(struct radeon_device *rdev);
1569 int radeon_uvd_suspend(struct radeon_device *rdev);
1570 int radeon_uvd_resume(struct radeon_device *rdev);
1571 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1572 uint32_t handle, struct radeon_fence **fence);
1573 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1574 uint32_t handle, struct radeon_fence **fence);
1575 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1576 void radeon_uvd_free_handles(struct radeon_device *rdev,
1577 struct drm_file *filp);
1578 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1579 void radeon_uvd_note_usage(struct radeon_device *rdev);
1580 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1581 unsigned vclk, unsigned dclk,
1582 unsigned vco_min, unsigned vco_max,
1583 unsigned fb_factor, unsigned fb_mask,
1584 unsigned pd_min, unsigned pd_max,
1585 unsigned pd_even,
1586 unsigned *optimal_fb_div,
1587 unsigned *optimal_vclk_div,
1588 unsigned *optimal_dclk_div);
1589 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1590 unsigned cg_upll_func_cntl);
1591
1592 struct r600_audio_pin {
1593 int channels;
1594 int rate;
1595 int bits_per_sample;
1596 u8 status_bits;
1597 u8 category_code;
1598 u32 offset;
1599 bool connected;
1600 u32 id;
1601 };
1602
1603 struct r600_audio {
1604 bool enabled;
1605 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1606 int num_pins;
1607 };
1608
1609 /*
1610 * Benchmarking
1611 */
1612 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1613
1614
1615 /*
1616 * Testing
1617 */
1618 void radeon_test_moves(struct radeon_device *rdev);
1619 void radeon_test_ring_sync(struct radeon_device *rdev,
1620 struct radeon_ring *cpA,
1621 struct radeon_ring *cpB);
1622 void radeon_test_syncing(struct radeon_device *rdev);
1623
1624
1625 /*
1626 * Debugfs
1627 */
1628 struct radeon_debugfs {
1629 struct drm_info_list *files;
1630 unsigned num_files;
1631 };
1632
1633 int radeon_debugfs_add_files(struct radeon_device *rdev,
1634 struct drm_info_list *files,
1635 unsigned nfiles);
1636 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1637
1638 /*
1639 * ASIC ring specific functions.
1640 */
1641 struct radeon_asic_ring {
1642 /* ring read/write ptr handling */
1643 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1644 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1645 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1646
1647 /* validating and patching of IBs */
1648 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1649 int (*cs_parse)(struct radeon_cs_parser *p);
1650
1651 /* command emmit functions */
1652 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1653 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1654 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1655 struct radeon_semaphore *semaphore, bool emit_wait);
1656 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1657
1658 /* testing functions */
1659 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1660 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1661 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1662
1663 /* deprecated */
1664 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1665 };
1666
1667 /*
1668 * ASIC specific functions.
1669 */
1670 struct radeon_asic {
1671 int (*init)(struct radeon_device *rdev);
1672 void (*fini)(struct radeon_device *rdev);
1673 int (*resume)(struct radeon_device *rdev);
1674 int (*suspend)(struct radeon_device *rdev);
1675 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1676 int (*asic_reset)(struct radeon_device *rdev);
1677 /* ioctl hw specific callback. Some hw might want to perform special
1678 * operation on specific ioctl. For instance on wait idle some hw
1679 * might want to perform and HDP flush through MMIO as it seems that
1680 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1681 * through ring.
1682 */
1683 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1684 /* check if 3D engine is idle */
1685 bool (*gui_idle)(struct radeon_device *rdev);
1686 /* wait for mc_idle */
1687 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1688 /* get the reference clock */
1689 u32 (*get_xclk)(struct radeon_device *rdev);
1690 /* get the gpu clock counter */
1691 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1692 /* gart */
1693 struct {
1694 void (*tlb_flush)(struct radeon_device *rdev);
1695 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1696 } gart;
1697 struct {
1698 int (*init)(struct radeon_device *rdev);
1699 void (*fini)(struct radeon_device *rdev);
1700 void (*set_page)(struct radeon_device *rdev,
1701 struct radeon_ib *ib,
1702 uint64_t pe,
1703 uint64_t addr, unsigned count,
1704 uint32_t incr, uint32_t flags);
1705 } vm;
1706 /* ring specific callbacks */
1707 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1708 /* irqs */
1709 struct {
1710 int (*set)(struct radeon_device *rdev);
1711 int (*process)(struct radeon_device *rdev);
1712 } irq;
1713 /* displays */
1714 struct {
1715 /* display watermarks */
1716 void (*bandwidth_update)(struct radeon_device *rdev);
1717 /* get frame count */
1718 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1719 /* wait for vblank */
1720 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1721 /* set backlight level */
1722 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1723 /* get backlight level */
1724 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1725 /* audio callbacks */
1726 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1727 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1728 } display;
1729 /* copy functions for bo handling */
1730 struct {
1731 int (*blit)(struct radeon_device *rdev,
1732 uint64_t src_offset,
1733 uint64_t dst_offset,
1734 unsigned num_gpu_pages,
1735 struct radeon_fence **fence);
1736 u32 blit_ring_index;
1737 int (*dma)(struct radeon_device *rdev,
1738 uint64_t src_offset,
1739 uint64_t dst_offset,
1740 unsigned num_gpu_pages,
1741 struct radeon_fence **fence);
1742 u32 dma_ring_index;
1743 /* method used for bo copy */
1744 int (*copy)(struct radeon_device *rdev,
1745 uint64_t src_offset,
1746 uint64_t dst_offset,
1747 unsigned num_gpu_pages,
1748 struct radeon_fence **fence);
1749 /* ring used for bo copies */
1750 u32 copy_ring_index;
1751 } copy;
1752 /* surfaces */
1753 struct {
1754 int (*set_reg)(struct radeon_device *rdev, int reg,
1755 uint32_t tiling_flags, uint32_t pitch,
1756 uint32_t offset, uint32_t obj_size);
1757 void (*clear_reg)(struct radeon_device *rdev, int reg);
1758 } surface;
1759 /* hotplug detect */
1760 struct {
1761 void (*init)(struct radeon_device *rdev);
1762 void (*fini)(struct radeon_device *rdev);
1763 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1764 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1765 } hpd;
1766 /* static power management */
1767 struct {
1768 void (*misc)(struct radeon_device *rdev);
1769 void (*prepare)(struct radeon_device *rdev);
1770 void (*finish)(struct radeon_device *rdev);
1771 void (*init_profile)(struct radeon_device *rdev);
1772 void (*get_dynpm_state)(struct radeon_device *rdev);
1773 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1774 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1775 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1776 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1777 int (*get_pcie_lanes)(struct radeon_device *rdev);
1778 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1779 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1780 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1781 int (*get_temperature)(struct radeon_device *rdev);
1782 } pm;
1783 /* dynamic power management */
1784 struct {
1785 int (*init)(struct radeon_device *rdev);
1786 void (*setup_asic)(struct radeon_device *rdev);
1787 int (*enable)(struct radeon_device *rdev);
1788 int (*late_enable)(struct radeon_device *rdev);
1789 void (*disable)(struct radeon_device *rdev);
1790 int (*pre_set_power_state)(struct radeon_device *rdev);
1791 int (*set_power_state)(struct radeon_device *rdev);
1792 void (*post_set_power_state)(struct radeon_device *rdev);
1793 void (*display_configuration_changed)(struct radeon_device *rdev);
1794 void (*fini)(struct radeon_device *rdev);
1795 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1796 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1797 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1798 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1799 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1800 bool (*vblank_too_short)(struct radeon_device *rdev);
1801 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1802 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1803 } dpm;
1804 /* pageflipping */
1805 struct {
1806 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1807 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1808 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1809 } pflip;
1810 };
1811
1812 /*
1813 * Asic structures
1814 */
1815 struct r100_asic {
1816 const unsigned *reg_safe_bm;
1817 unsigned reg_safe_bm_size;
1818 u32 hdp_cntl;
1819 };
1820
1821 struct r300_asic {
1822 const unsigned *reg_safe_bm;
1823 unsigned reg_safe_bm_size;
1824 u32 resync_scratch;
1825 u32 hdp_cntl;
1826 };
1827
1828 struct r600_asic {
1829 unsigned max_pipes;
1830 unsigned max_tile_pipes;
1831 unsigned max_simds;
1832 unsigned max_backends;
1833 unsigned max_gprs;
1834 unsigned max_threads;
1835 unsigned max_stack_entries;
1836 unsigned max_hw_contexts;
1837 unsigned max_gs_threads;
1838 unsigned sx_max_export_size;
1839 unsigned sx_max_export_pos_size;
1840 unsigned sx_max_export_smx_size;
1841 unsigned sq_num_cf_insts;
1842 unsigned tiling_nbanks;
1843 unsigned tiling_npipes;
1844 unsigned tiling_group_size;
1845 unsigned tile_config;
1846 unsigned backend_map;
1847 };
1848
1849 struct rv770_asic {
1850 unsigned max_pipes;
1851 unsigned max_tile_pipes;
1852 unsigned max_simds;
1853 unsigned max_backends;
1854 unsigned max_gprs;
1855 unsigned max_threads;
1856 unsigned max_stack_entries;
1857 unsigned max_hw_contexts;
1858 unsigned max_gs_threads;
1859 unsigned sx_max_export_size;
1860 unsigned sx_max_export_pos_size;
1861 unsigned sx_max_export_smx_size;
1862 unsigned sq_num_cf_insts;
1863 unsigned sx_num_of_sets;
1864 unsigned sc_prim_fifo_size;
1865 unsigned sc_hiz_tile_fifo_size;
1866 unsigned sc_earlyz_tile_fifo_fize;
1867 unsigned tiling_nbanks;
1868 unsigned tiling_npipes;
1869 unsigned tiling_group_size;
1870 unsigned tile_config;
1871 unsigned backend_map;
1872 };
1873
1874 struct evergreen_asic {
1875 unsigned num_ses;
1876 unsigned max_pipes;
1877 unsigned max_tile_pipes;
1878 unsigned max_simds;
1879 unsigned max_backends;
1880 unsigned max_gprs;
1881 unsigned max_threads;
1882 unsigned max_stack_entries;
1883 unsigned max_hw_contexts;
1884 unsigned max_gs_threads;
1885 unsigned sx_max_export_size;
1886 unsigned sx_max_export_pos_size;
1887 unsigned sx_max_export_smx_size;
1888 unsigned sq_num_cf_insts;
1889 unsigned sx_num_of_sets;
1890 unsigned sc_prim_fifo_size;
1891 unsigned sc_hiz_tile_fifo_size;
1892 unsigned sc_earlyz_tile_fifo_size;
1893 unsigned tiling_nbanks;
1894 unsigned tiling_npipes;
1895 unsigned tiling_group_size;
1896 unsigned tile_config;
1897 unsigned backend_map;
1898 };
1899
1900 struct cayman_asic {
1901 unsigned max_shader_engines;
1902 unsigned max_pipes_per_simd;
1903 unsigned max_tile_pipes;
1904 unsigned max_simds_per_se;
1905 unsigned max_backends_per_se;
1906 unsigned max_texture_channel_caches;
1907 unsigned max_gprs;
1908 unsigned max_threads;
1909 unsigned max_gs_threads;
1910 unsigned max_stack_entries;
1911 unsigned sx_num_of_sets;
1912 unsigned sx_max_export_size;
1913 unsigned sx_max_export_pos_size;
1914 unsigned sx_max_export_smx_size;
1915 unsigned max_hw_contexts;
1916 unsigned sq_num_cf_insts;
1917 unsigned sc_prim_fifo_size;
1918 unsigned sc_hiz_tile_fifo_size;
1919 unsigned sc_earlyz_tile_fifo_size;
1920
1921 unsigned num_shader_engines;
1922 unsigned num_shader_pipes_per_simd;
1923 unsigned num_tile_pipes;
1924 unsigned num_simds_per_se;
1925 unsigned num_backends_per_se;
1926 unsigned backend_disable_mask_per_asic;
1927 unsigned backend_map;
1928 unsigned num_texture_channel_caches;
1929 unsigned mem_max_burst_length_bytes;
1930 unsigned mem_row_size_in_kb;
1931 unsigned shader_engine_tile_size;
1932 unsigned num_gpus;
1933 unsigned multi_gpu_tile_size;
1934
1935 unsigned tile_config;
1936 };
1937
1938 struct si_asic {
1939 unsigned max_shader_engines;
1940 unsigned max_tile_pipes;
1941 unsigned max_cu_per_sh;
1942 unsigned max_sh_per_se;
1943 unsigned max_backends_per_se;
1944 unsigned max_texture_channel_caches;
1945 unsigned max_gprs;
1946 unsigned max_gs_threads;
1947 unsigned max_hw_contexts;
1948 unsigned sc_prim_fifo_size_frontend;
1949 unsigned sc_prim_fifo_size_backend;
1950 unsigned sc_hiz_tile_fifo_size;
1951 unsigned sc_earlyz_tile_fifo_size;
1952
1953 unsigned num_tile_pipes;
1954 unsigned backend_enable_mask;
1955 unsigned backend_disable_mask_per_asic;
1956 unsigned backend_map;
1957 unsigned num_texture_channel_caches;
1958 unsigned mem_max_burst_length_bytes;
1959 unsigned mem_row_size_in_kb;
1960 unsigned shader_engine_tile_size;
1961 unsigned num_gpus;
1962 unsigned multi_gpu_tile_size;
1963
1964 unsigned tile_config;
1965 uint32_t tile_mode_array[32];
1966 };
1967
1968 struct cik_asic {
1969 unsigned max_shader_engines;
1970 unsigned max_tile_pipes;
1971 unsigned max_cu_per_sh;
1972 unsigned max_sh_per_se;
1973 unsigned max_backends_per_se;
1974 unsigned max_texture_channel_caches;
1975 unsigned max_gprs;
1976 unsigned max_gs_threads;
1977 unsigned max_hw_contexts;
1978 unsigned sc_prim_fifo_size_frontend;
1979 unsigned sc_prim_fifo_size_backend;
1980 unsigned sc_hiz_tile_fifo_size;
1981 unsigned sc_earlyz_tile_fifo_size;
1982
1983 unsigned num_tile_pipes;
1984 unsigned backend_enable_mask;
1985 unsigned backend_disable_mask_per_asic;
1986 unsigned backend_map;
1987 unsigned num_texture_channel_caches;
1988 unsigned mem_max_burst_length_bytes;
1989 unsigned mem_row_size_in_kb;
1990 unsigned shader_engine_tile_size;
1991 unsigned num_gpus;
1992 unsigned multi_gpu_tile_size;
1993
1994 unsigned tile_config;
1995 uint32_t tile_mode_array[32];
1996 uint32_t macrotile_mode_array[16];
1997 };
1998
1999 union radeon_asic_config {
2000 struct r300_asic r300;
2001 struct r100_asic r100;
2002 struct r600_asic r600;
2003 struct rv770_asic rv770;
2004 struct evergreen_asic evergreen;
2005 struct cayman_asic cayman;
2006 struct si_asic si;
2007 struct cik_asic cik;
2008 };
2009
2010 /*
2011 * asic initizalization from radeon_asic.c
2012 */
2013 void radeon_agp_disable(struct radeon_device *rdev);
2014 int radeon_asic_init(struct radeon_device *rdev);
2015
2016
2017 /*
2018 * IOCTL.
2019 */
2020 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2021 struct drm_file *filp);
2022 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2023 struct drm_file *filp);
2024 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2025 struct drm_file *file_priv);
2026 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2027 struct drm_file *file_priv);
2028 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2029 struct drm_file *file_priv);
2030 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2031 struct drm_file *file_priv);
2032 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2033 struct drm_file *filp);
2034 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2035 struct drm_file *filp);
2036 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2037 struct drm_file *filp);
2038 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2039 struct drm_file *filp);
2040 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2041 struct drm_file *filp);
2042 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2043 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2044 struct drm_file *filp);
2045 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2046 struct drm_file *filp);
2047
2048 /* VRAM scratch page for HDP bug, default vram page */
2049 struct r600_vram_scratch {
2050 struct radeon_bo *robj;
2051 volatile uint32_t *ptr;
2052 u64 gpu_addr;
2053 };
2054
2055 /*
2056 * ACPI
2057 */
2058 struct radeon_atif_notification_cfg {
2059 bool enabled;
2060 int command_code;
2061 };
2062
2063 struct radeon_atif_notifications {
2064 bool display_switch;
2065 bool expansion_mode_change;
2066 bool thermal_state;
2067 bool forced_power_state;
2068 bool system_power_state;
2069 bool display_conf_change;
2070 bool px_gfx_switch;
2071 bool brightness_change;
2072 bool dgpu_display_event;
2073 };
2074
2075 struct radeon_atif_functions {
2076 bool system_params;
2077 bool sbios_requests;
2078 bool select_active_disp;
2079 bool lid_state;
2080 bool get_tv_standard;
2081 bool set_tv_standard;
2082 bool get_panel_expansion_mode;
2083 bool set_panel_expansion_mode;
2084 bool temperature_change;
2085 bool graphics_device_types;
2086 };
2087
2088 struct radeon_atif {
2089 struct radeon_atif_notifications notifications;
2090 struct radeon_atif_functions functions;
2091 struct radeon_atif_notification_cfg notification_cfg;
2092 struct radeon_encoder *encoder_for_bl;
2093 };
2094
2095 struct radeon_atcs_functions {
2096 bool get_ext_state;
2097 bool pcie_perf_req;
2098 bool pcie_dev_rdy;
2099 bool pcie_bus_width;
2100 };
2101
2102 struct radeon_atcs {
2103 struct radeon_atcs_functions functions;
2104 };
2105
2106 /*
2107 * Core structure, functions and helpers.
2108 */
2109 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2110 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2111
2112 struct radeon_device {
2113 struct device *dev;
2114 struct drm_device *ddev;
2115 struct pci_dev *pdev;
2116 struct rw_semaphore exclusive_lock;
2117 /* ASIC */
2118 union radeon_asic_config config;
2119 enum radeon_family family;
2120 unsigned long flags;
2121 int usec_timeout;
2122 enum radeon_pll_errata pll_errata;
2123 int num_gb_pipes;
2124 int num_z_pipes;
2125 int disp_priority;
2126 /* BIOS */
2127 uint8_t *bios;
2128 bool is_atom_bios;
2129 uint16_t bios_header_start;
2130 struct radeon_bo *stollen_vga_memory;
2131 /* Register mmio */
2132 resource_size_t rmmio_base;
2133 resource_size_t rmmio_size;
2134 /* protects concurrent MM_INDEX/DATA based register access */
2135 spinlock_t mmio_idx_lock;
2136 /* protects concurrent SMC based register access */
2137 spinlock_t smc_idx_lock;
2138 /* protects concurrent PLL register access */
2139 spinlock_t pll_idx_lock;
2140 /* protects concurrent MC register access */
2141 spinlock_t mc_idx_lock;
2142 /* protects concurrent PCIE register access */
2143 spinlock_t pcie_idx_lock;
2144 /* protects concurrent PCIE_PORT register access */
2145 spinlock_t pciep_idx_lock;
2146 /* protects concurrent PIF register access */
2147 spinlock_t pif_idx_lock;
2148 /* protects concurrent CG register access */
2149 spinlock_t cg_idx_lock;
2150 /* protects concurrent UVD register access */
2151 spinlock_t uvd_idx_lock;
2152 /* protects concurrent RCU register access */
2153 spinlock_t rcu_idx_lock;
2154 /* protects concurrent DIDT register access */
2155 spinlock_t didt_idx_lock;
2156 /* protects concurrent ENDPOINT (audio) register access */
2157 spinlock_t end_idx_lock;
2158 void __iomem *rmmio;
2159 radeon_rreg_t mc_rreg;
2160 radeon_wreg_t mc_wreg;
2161 radeon_rreg_t pll_rreg;
2162 radeon_wreg_t pll_wreg;
2163 uint32_t pcie_reg_mask;
2164 radeon_rreg_t pciep_rreg;
2165 radeon_wreg_t pciep_wreg;
2166 /* io port */
2167 void __iomem *rio_mem;
2168 resource_size_t rio_mem_size;
2169 struct radeon_clock clock;
2170 struct radeon_mc mc;
2171 struct radeon_gart gart;
2172 struct radeon_mode_info mode_info;
2173 struct radeon_scratch scratch;
2174 struct radeon_doorbell doorbell;
2175 struct radeon_mman mman;
2176 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2177 wait_queue_head_t fence_queue;
2178 struct mutex ring_lock;
2179 struct radeon_ring ring[RADEON_NUM_RINGS];
2180 bool ib_pool_ready;
2181 struct radeon_sa_manager ring_tmp_bo;
2182 struct radeon_irq irq;
2183 struct radeon_asic *asic;
2184 struct radeon_gem gem;
2185 struct radeon_pm pm;
2186 struct radeon_uvd uvd;
2187 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2188 struct radeon_wb wb;
2189 struct radeon_dummy_page dummy_page;
2190 bool shutdown;
2191 bool suspend;
2192 bool need_dma32;
2193 bool accel_working;
2194 bool fastfb_working; /* IGP feature*/
2195 bool needs_reset;
2196 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2197 const struct firmware *me_fw; /* all family ME firmware */
2198 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2199 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2200 const struct firmware *mc_fw; /* NI MC firmware */
2201 const struct firmware *ce_fw; /* SI CE firmware */
2202 const struct firmware *mec_fw; /* CIK MEC firmware */
2203 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2204 const struct firmware *smc_fw; /* SMC firmware */
2205 const struct firmware *uvd_fw; /* UVD firmware */
2206 struct r600_vram_scratch vram_scratch;
2207 int msi_enabled; /* msi enabled */
2208 struct r600_ih ih; /* r6/700 interrupt ring */
2209 struct radeon_rlc rlc;
2210 struct radeon_mec mec;
2211 struct work_struct hotplug_work;
2212 struct work_struct audio_work;
2213 struct work_struct reset_work;
2214 int num_crtc; /* number of crtcs */
2215 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2216 bool has_uvd;
2217 struct r600_audio audio; /* audio stuff */
2218 struct notifier_block acpi_nb;
2219 /* only one userspace can use Hyperz features or CMASK at a time */
2220 struct drm_file *hyperz_filp;
2221 struct drm_file *cmask_filp;
2222 /* i2c buses */
2223 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2224 /* debugfs */
2225 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2226 unsigned debugfs_count;
2227 /* virtual memory */
2228 struct radeon_vm_manager vm_manager;
2229 struct mutex gpu_clock_mutex;
2230 /* ACPI interface */
2231 struct radeon_atif atif;
2232 struct radeon_atcs atcs;
2233 /* srbm instance registers */
2234 struct mutex srbm_mutex;
2235 /* clock, powergating flags */
2236 u32 cg_flags;
2237 u32 pg_flags;
2238
2239 struct dev_pm_domain vga_pm_domain;
2240 bool have_disp_power_ref;
2241 };
2242
2243 int radeon_device_init(struct radeon_device *rdev,
2244 struct drm_device *ddev,
2245 struct pci_dev *pdev,
2246 uint32_t flags);
2247 void radeon_device_fini(struct radeon_device *rdev);
2248 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2249
2250 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2251 bool always_indirect);
2252 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2253 bool always_indirect);
2254 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2255 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2256
2257 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2258 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2259
2260 /*
2261 * Cast helper
2262 */
2263 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2264
2265 /*
2266 * Registers read & write functions.
2267 */
2268 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2269 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2270 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2271 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2272 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2273 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2274 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2275 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2276 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2277 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2278 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2279 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2280 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2281 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2282 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2283 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2284 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2285 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2286 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2287 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2288 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2289 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2290 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2291 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2292 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2293 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2294 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2295 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2296 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2297 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2298 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2299 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2300 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2301 #define WREG32_P(reg, val, mask) \
2302 do { \
2303 uint32_t tmp_ = RREG32(reg); \
2304 tmp_ &= (mask); \
2305 tmp_ |= ((val) & ~(mask)); \
2306 WREG32(reg, tmp_); \
2307 } while (0)
2308 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2309 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2310 #define WREG32_PLL_P(reg, val, mask) \
2311 do { \
2312 uint32_t tmp_ = RREG32_PLL(reg); \
2313 tmp_ &= (mask); \
2314 tmp_ |= ((val) & ~(mask)); \
2315 WREG32_PLL(reg, tmp_); \
2316 } while (0)
2317 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2318 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2319 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2320
2321 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2322 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2323
2324 /*
2325 * Indirect registers accessor
2326 */
2327 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2328 {
2329 unsigned long flags;
2330 uint32_t r;
2331
2332 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2333 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2334 r = RREG32(RADEON_PCIE_DATA);
2335 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2336 return r;
2337 }
2338
2339 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2340 {
2341 unsigned long flags;
2342
2343 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2344 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2345 WREG32(RADEON_PCIE_DATA, (v));
2346 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2347 }
2348
2349 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2350 {
2351 unsigned long flags;
2352 u32 r;
2353
2354 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2355 WREG32(TN_SMC_IND_INDEX_0, (reg));
2356 r = RREG32(TN_SMC_IND_DATA_0);
2357 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2358 return r;
2359 }
2360
2361 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2362 {
2363 unsigned long flags;
2364
2365 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2366 WREG32(TN_SMC_IND_INDEX_0, (reg));
2367 WREG32(TN_SMC_IND_DATA_0, (v));
2368 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2369 }
2370
2371 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2372 {
2373 unsigned long flags;
2374 u32 r;
2375
2376 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2377 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2378 r = RREG32(R600_RCU_DATA);
2379 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2380 return r;
2381 }
2382
2383 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2384 {
2385 unsigned long flags;
2386
2387 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2388 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2389 WREG32(R600_RCU_DATA, (v));
2390 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2391 }
2392
2393 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2394 {
2395 unsigned long flags;
2396 u32 r;
2397
2398 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2399 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2400 r = RREG32(EVERGREEN_CG_IND_DATA);
2401 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2402 return r;
2403 }
2404
2405 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2406 {
2407 unsigned long flags;
2408
2409 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2410 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2411 WREG32(EVERGREEN_CG_IND_DATA, (v));
2412 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2413 }
2414
2415 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2416 {
2417 unsigned long flags;
2418 u32 r;
2419
2420 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2421 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2422 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2423 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2424 return r;
2425 }
2426
2427 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2428 {
2429 unsigned long flags;
2430
2431 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2432 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2433 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2434 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2435 }
2436
2437 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2438 {
2439 unsigned long flags;
2440 u32 r;
2441
2442 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2443 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2444 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2445 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2446 return r;
2447 }
2448
2449 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2450 {
2451 unsigned long flags;
2452
2453 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2454 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2455 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2456 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2457 }
2458
2459 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2460 {
2461 unsigned long flags;
2462 u32 r;
2463
2464 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2465 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2466 r = RREG32(R600_UVD_CTX_DATA);
2467 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2468 return r;
2469 }
2470
2471 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2472 {
2473 unsigned long flags;
2474
2475 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2476 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2477 WREG32(R600_UVD_CTX_DATA, (v));
2478 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2479 }
2480
2481
2482 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2483 {
2484 unsigned long flags;
2485 u32 r;
2486
2487 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2488 WREG32(CIK_DIDT_IND_INDEX, (reg));
2489 r = RREG32(CIK_DIDT_IND_DATA);
2490 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2491 return r;
2492 }
2493
2494 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2495 {
2496 unsigned long flags;
2497
2498 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2499 WREG32(CIK_DIDT_IND_INDEX, (reg));
2500 WREG32(CIK_DIDT_IND_DATA, (v));
2501 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2502 }
2503
2504 void r100_pll_errata_after_index(struct radeon_device *rdev);
2505
2506
2507 /*
2508 * ASICs helpers.
2509 */
2510 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2511 (rdev->pdev->device == 0x5969))
2512 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2513 (rdev->family == CHIP_RV200) || \
2514 (rdev->family == CHIP_RS100) || \
2515 (rdev->family == CHIP_RS200) || \
2516 (rdev->family == CHIP_RV250) || \
2517 (rdev->family == CHIP_RV280) || \
2518 (rdev->family == CHIP_RS300))
2519 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2520 (rdev->family == CHIP_RV350) || \
2521 (rdev->family == CHIP_R350) || \
2522 (rdev->family == CHIP_RV380) || \
2523 (rdev->family == CHIP_R420) || \
2524 (rdev->family == CHIP_R423) || \
2525 (rdev->family == CHIP_RV410) || \
2526 (rdev->family == CHIP_RS400) || \
2527 (rdev->family == CHIP_RS480))
2528 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2529 (rdev->ddev->pdev->device == 0x9443) || \
2530 (rdev->ddev->pdev->device == 0x944B) || \
2531 (rdev->ddev->pdev->device == 0x9506) || \
2532 (rdev->ddev->pdev->device == 0x9509) || \
2533 (rdev->ddev->pdev->device == 0x950F) || \
2534 (rdev->ddev->pdev->device == 0x689C) || \
2535 (rdev->ddev->pdev->device == 0x689D))
2536 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2537 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2538 (rdev->family == CHIP_RS690) || \
2539 (rdev->family == CHIP_RS740) || \
2540 (rdev->family >= CHIP_R600))
2541 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2542 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2543 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2544 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2545 (rdev->flags & RADEON_IS_IGP))
2546 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2547 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2548 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2549 (rdev->flags & RADEON_IS_IGP))
2550 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2551 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2552 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2553
2554 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2555 (rdev->ddev->pdev->device == 0x6850) || \
2556 (rdev->ddev->pdev->device == 0x6858) || \
2557 (rdev->ddev->pdev->device == 0x6859) || \
2558 (rdev->ddev->pdev->device == 0x6840) || \
2559 (rdev->ddev->pdev->device == 0x6841) || \
2560 (rdev->ddev->pdev->device == 0x6842) || \
2561 (rdev->ddev->pdev->device == 0x6843))
2562
2563 /*
2564 * BIOS helpers.
2565 */
2566 #define RBIOS8(i) (rdev->bios[i])
2567 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2568 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2569
2570 int radeon_combios_init(struct radeon_device *rdev);
2571 void radeon_combios_fini(struct radeon_device *rdev);
2572 int radeon_atombios_init(struct radeon_device *rdev);
2573 void radeon_atombios_fini(struct radeon_device *rdev);
2574
2575
2576 /*
2577 * RING helpers.
2578 */
2579 #if DRM_DEBUG_CODE == 0
2580 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2581 {
2582 ring->ring[ring->wptr++] = v;
2583 ring->wptr &= ring->ptr_mask;
2584 ring->count_dw--;
2585 ring->ring_free_dw--;
2586 }
2587 #else
2588 /* With debugging this is just too big to inline */
2589 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2590 #endif
2591
2592 /*
2593 * ASICs macro.
2594 */
2595 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2596 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2597 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2598 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2599 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2600 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2601 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2602 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2603 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2604 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2605 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2606 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2607 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2608 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2609 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2610 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2611 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2612 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2613 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2614 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2615 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2616 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2617 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2618 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2619 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2620 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2621 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2622 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2623 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2624 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2625 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2626 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2627 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2628 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2629 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2630 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2631 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2632 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2633 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2634 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2635 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2636 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2637 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2638 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2639 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2640 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2641 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2642 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2643 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2644 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2645 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2646 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2647 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2648 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2649 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2650 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2651 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2652 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2653 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2654 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2655 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2656 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2657 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2658 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2659 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2660 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2661 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2662 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2663 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2664 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2665 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2666 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2667 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2668 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2669 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2670 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2671 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2672 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2673 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2674 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2675 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2676 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2677 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2678 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2679
2680 /* Common functions */
2681 /* AGP */
2682 extern int radeon_gpu_reset(struct radeon_device *rdev);
2683 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2684 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2685 extern void radeon_agp_disable(struct radeon_device *rdev);
2686 extern int radeon_modeset_init(struct radeon_device *rdev);
2687 extern void radeon_modeset_fini(struct radeon_device *rdev);
2688 extern bool radeon_card_posted(struct radeon_device *rdev);
2689 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2690 extern void radeon_update_display_priority(struct radeon_device *rdev);
2691 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2692 extern void radeon_scratch_init(struct radeon_device *rdev);
2693 extern void radeon_wb_fini(struct radeon_device *rdev);
2694 extern int radeon_wb_init(struct radeon_device *rdev);
2695 extern void radeon_wb_disable(struct radeon_device *rdev);
2696 extern void radeon_surface_init(struct radeon_device *rdev);
2697 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2698 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2699 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2700 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2701 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2702 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2703 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2704 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2705 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2706 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2707 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2708 const u32 *registers,
2709 const u32 array_size);
2710
2711 /*
2712 * vm
2713 */
2714 int radeon_vm_manager_init(struct radeon_device *rdev);
2715 void radeon_vm_manager_fini(struct radeon_device *rdev);
2716 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2717 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2718 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2719 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2720 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2721 struct radeon_vm *vm, int ring);
2722 void radeon_vm_fence(struct radeon_device *rdev,
2723 struct radeon_vm *vm,
2724 struct radeon_fence *fence);
2725 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2726 int radeon_vm_bo_update(struct radeon_device *rdev,
2727 struct radeon_vm *vm,
2728 struct radeon_bo *bo,
2729 struct ttm_mem_reg *mem);
2730 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2731 struct radeon_bo *bo);
2732 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2733 struct radeon_bo *bo);
2734 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2735 struct radeon_vm *vm,
2736 struct radeon_bo *bo);
2737 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2738 struct radeon_bo_va *bo_va,
2739 uint64_t offset,
2740 uint32_t flags);
2741 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2742 struct radeon_bo_va *bo_va);
2743
2744 /* audio */
2745 void r600_audio_update_hdmi(struct work_struct *work);
2746 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2747 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2748
2749 /*
2750 * R600 vram scratch functions
2751 */
2752 int r600_vram_scratch_init(struct radeon_device *rdev);
2753 void r600_vram_scratch_fini(struct radeon_device *rdev);
2754
2755 /*
2756 * r600 cs checking helper
2757 */
2758 unsigned r600_mip_minify(unsigned size, unsigned level);
2759 bool r600_fmt_is_valid_color(u32 format);
2760 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2761 int r600_fmt_get_blocksize(u32 format);
2762 int r600_fmt_get_nblocksx(u32 format, u32 w);
2763 int r600_fmt_get_nblocksy(u32 format, u32 h);
2764
2765 /*
2766 * r600 functions used by radeon_encoder.c
2767 */
2768 struct radeon_hdmi_acr {
2769 u32 clock;
2770
2771 int n_32khz;
2772 int cts_32khz;
2773
2774 int n_44_1khz;
2775 int cts_44_1khz;
2776
2777 int n_48khz;
2778 int cts_48khz;
2779
2780 };
2781
2782 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2783
2784 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2785 u32 tiling_pipe_num,
2786 u32 max_rb_num,
2787 u32 total_max_rb_num,
2788 u32 enabled_rb_mask);
2789
2790 /*
2791 * evergreen functions used by radeon_encoder.c
2792 */
2793
2794 extern int ni_init_microcode(struct radeon_device *rdev);
2795 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2796
2797 /* radeon_acpi.c */
2798 #if defined(CONFIG_ACPI)
2799 extern int radeon_acpi_init(struct radeon_device *rdev);
2800 extern void radeon_acpi_fini(struct radeon_device *rdev);
2801 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2802 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2803 u8 perf_req, bool advertise);
2804 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2805 #else
2806 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2807 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2808 #endif
2809
2810 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2811 struct radeon_cs_packet *pkt,
2812 unsigned idx);
2813 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2814 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2815 struct radeon_cs_packet *pkt);
2816 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2817 struct radeon_cs_reloc **cs_reloc,
2818 int nomm);
2819 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2820 uint32_t *vline_start_end,
2821 uint32_t *vline_status);
2822
2823 #include "radeon_object.h"
2824
2825 #endif
Linux kernel - Deliverables
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