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drm/radeon: add VCE version parsing and checking
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
101 extern int radeon_runtime_pm;
102 extern int radeon_hard_reset;
103
104 /*
105 * Copy from radeon_drv.h so we don't have to include both and have conflicting
106 * symbol;
107 */
108 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
109 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
110 /* RADEON_IB_POOL_SIZE must be a power of 2 */
111 #define RADEON_IB_POOL_SIZE 16
112 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
113 #define RADEONFB_CONN_LIMIT 4
114 #define RADEON_BIOS_NUM_SCRATCH 8
115
116 /* fence seq are set to this number when signaled */
117 #define RADEON_FENCE_SIGNALED_SEQ 0LL
118
119 /* internal ring indices */
120 /* r1xx+ has gfx CP ring */
121 #define RADEON_RING_TYPE_GFX_INDEX 0
122
123 /* cayman has 2 compute CP rings */
124 #define CAYMAN_RING_TYPE_CP1_INDEX 1
125 #define CAYMAN_RING_TYPE_CP2_INDEX 2
126
127 /* R600+ has an async dma ring */
128 #define R600_RING_TYPE_DMA_INDEX 3
129 /* cayman add a second async dma ring */
130 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
131
132 /* R600+ */
133 #define R600_RING_TYPE_UVD_INDEX 5
134
135 /* TN+ */
136 #define TN_RING_TYPE_VCE1_INDEX 6
137 #define TN_RING_TYPE_VCE2_INDEX 7
138
139 /* max number of rings */
140 #define RADEON_NUM_RINGS 8
141
142 /* number of hw syncs before falling back on blocking */
143 #define RADEON_NUM_SYNCS 4
144
145 /* hardcode those limit for now */
146 #define RADEON_VA_IB_OFFSET (1 << 20)
147 #define RADEON_VA_RESERVED_SIZE (8 << 20)
148 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
149
150 /* hard reset data */
151 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
152
153 /* reset flags */
154 #define RADEON_RESET_GFX (1 << 0)
155 #define RADEON_RESET_COMPUTE (1 << 1)
156 #define RADEON_RESET_DMA (1 << 2)
157 #define RADEON_RESET_CP (1 << 3)
158 #define RADEON_RESET_GRBM (1 << 4)
159 #define RADEON_RESET_DMA1 (1 << 5)
160 #define RADEON_RESET_RLC (1 << 6)
161 #define RADEON_RESET_SEM (1 << 7)
162 #define RADEON_RESET_IH (1 << 8)
163 #define RADEON_RESET_VMC (1 << 9)
164 #define RADEON_RESET_MC (1 << 10)
165 #define RADEON_RESET_DISPLAY (1 << 11)
166
167 /* CG block flags */
168 #define RADEON_CG_BLOCK_GFX (1 << 0)
169 #define RADEON_CG_BLOCK_MC (1 << 1)
170 #define RADEON_CG_BLOCK_SDMA (1 << 2)
171 #define RADEON_CG_BLOCK_UVD (1 << 3)
172 #define RADEON_CG_BLOCK_VCE (1 << 4)
173 #define RADEON_CG_BLOCK_HDP (1 << 5)
174 #define RADEON_CG_BLOCK_BIF (1 << 6)
175
176 /* CG flags */
177 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
178 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
179 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
180 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
181 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
182 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
183 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
184 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
185 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
186 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
187 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
188 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
189 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
190 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
191 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
192 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
193 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
194
195 /* PG flags */
196 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
197 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
198 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
199 #define RADEON_PG_SUPPORT_UVD (1 << 3)
200 #define RADEON_PG_SUPPORT_VCE (1 << 4)
201 #define RADEON_PG_SUPPORT_CP (1 << 5)
202 #define RADEON_PG_SUPPORT_GDS (1 << 6)
203 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
204 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
205 #define RADEON_PG_SUPPORT_ACP (1 << 9)
206 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
207
208 /* max cursor sizes (in pixels) */
209 #define CURSOR_WIDTH 64
210 #define CURSOR_HEIGHT 64
211
212 #define CIK_CURSOR_WIDTH 128
213 #define CIK_CURSOR_HEIGHT 128
214
215 /*
216 * Errata workarounds.
217 */
218 enum radeon_pll_errata {
219 CHIP_ERRATA_R300_CG = 0x00000001,
220 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
221 CHIP_ERRATA_PLL_DELAY = 0x00000004
222 };
223
224
225 struct radeon_device;
226
227
228 /*
229 * BIOS.
230 */
231 bool radeon_get_bios(struct radeon_device *rdev);
232
233 /*
234 * Dummy page
235 */
236 struct radeon_dummy_page {
237 struct page *page;
238 dma_addr_t addr;
239 };
240 int radeon_dummy_page_init(struct radeon_device *rdev);
241 void radeon_dummy_page_fini(struct radeon_device *rdev);
242
243
244 /*
245 * Clocks
246 */
247 struct radeon_clock {
248 struct radeon_pll p1pll;
249 struct radeon_pll p2pll;
250 struct radeon_pll dcpll;
251 struct radeon_pll spll;
252 struct radeon_pll mpll;
253 /* 10 Khz units */
254 uint32_t default_mclk;
255 uint32_t default_sclk;
256 uint32_t default_dispclk;
257 uint32_t current_dispclk;
258 uint32_t dp_extclk;
259 uint32_t max_pixel_clock;
260 };
261
262 /*
263 * Power management
264 */
265 int radeon_pm_init(struct radeon_device *rdev);
266 int radeon_pm_late_init(struct radeon_device *rdev);
267 void radeon_pm_fini(struct radeon_device *rdev);
268 void radeon_pm_compute_clocks(struct radeon_device *rdev);
269 void radeon_pm_suspend(struct radeon_device *rdev);
270 void radeon_pm_resume(struct radeon_device *rdev);
271 void radeon_combios_get_power_modes(struct radeon_device *rdev);
272 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
273 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
274 u8 clock_type,
275 u32 clock,
276 bool strobe_mode,
277 struct atom_clock_dividers *dividers);
278 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
279 u32 clock,
280 bool strobe_mode,
281 struct atom_mpll_param *mpll_param);
282 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
283 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
284 u16 voltage_level, u8 voltage_type,
285 u32 *gpio_value, u32 *gpio_mask);
286 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
287 u32 eng_clock, u32 mem_clock);
288 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
289 u8 voltage_type, u16 *voltage_step);
290 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
291 u16 voltage_id, u16 *voltage);
292 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
293 u16 *voltage,
294 u16 leakage_idx);
295 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
296 u16 *leakage_id);
297 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
298 u16 *vddc, u16 *vddci,
299 u16 virtual_voltage_id,
300 u16 vbios_voltage_id);
301 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
302 u8 voltage_type,
303 u16 nominal_voltage,
304 u16 *true_voltage);
305 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
306 u8 voltage_type, u16 *min_voltage);
307 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
308 u8 voltage_type, u16 *max_voltage);
309 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
310 u8 voltage_type, u8 voltage_mode,
311 struct atom_voltage_table *voltage_table);
312 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
313 u8 voltage_type, u8 voltage_mode);
314 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
315 u32 mem_clock);
316 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
317 u32 mem_clock);
318 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
319 u8 module_index,
320 struct atom_mc_reg_table *reg_table);
321 int radeon_atom_get_memory_info(struct radeon_device *rdev,
322 u8 module_index, struct atom_memory_info *mem_info);
323 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
324 bool gddr5, u8 module_index,
325 struct atom_memory_clock_range_table *mclk_range_table);
326 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
327 u16 voltage_id, u16 *voltage);
328 void rs690_pm_info(struct radeon_device *rdev);
329 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
330 unsigned *bankh, unsigned *mtaspect,
331 unsigned *tile_split);
332
333 /*
334 * Fences.
335 */
336 struct radeon_fence_driver {
337 uint32_t scratch_reg;
338 uint64_t gpu_addr;
339 volatile uint32_t *cpu_addr;
340 /* sync_seq is protected by ring emission lock */
341 uint64_t sync_seq[RADEON_NUM_RINGS];
342 atomic64_t last_seq;
343 bool initialized;
344 };
345
346 struct radeon_fence {
347 struct radeon_device *rdev;
348 struct kref kref;
349 /* protected by radeon_fence.lock */
350 uint64_t seq;
351 /* RB, DMA, etc. */
352 unsigned ring;
353 };
354
355 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
356 int radeon_fence_driver_init(struct radeon_device *rdev);
357 void radeon_fence_driver_fini(struct radeon_device *rdev);
358 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
359 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
360 void radeon_fence_process(struct radeon_device *rdev, int ring);
361 bool radeon_fence_signaled(struct radeon_fence *fence);
362 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
363 int radeon_fence_wait_locked(struct radeon_fence *fence);
364 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
365 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
366 int radeon_fence_wait_any(struct radeon_device *rdev,
367 struct radeon_fence **fences,
368 bool intr);
369 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
370 void radeon_fence_unref(struct radeon_fence **fence);
371 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
372 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
373 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
374 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
375 struct radeon_fence *b)
376 {
377 if (!a) {
378 return b;
379 }
380
381 if (!b) {
382 return a;
383 }
384
385 BUG_ON(a->ring != b->ring);
386
387 if (a->seq > b->seq) {
388 return a;
389 } else {
390 return b;
391 }
392 }
393
394 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
395 struct radeon_fence *b)
396 {
397 if (!a) {
398 return false;
399 }
400
401 if (!b) {
402 return true;
403 }
404
405 BUG_ON(a->ring != b->ring);
406
407 return a->seq < b->seq;
408 }
409
410 /*
411 * Tiling registers
412 */
413 struct radeon_surface_reg {
414 struct radeon_bo *bo;
415 };
416
417 #define RADEON_GEM_MAX_SURFACES 8
418
419 /*
420 * TTM.
421 */
422 struct radeon_mman {
423 struct ttm_bo_global_ref bo_global_ref;
424 struct drm_global_reference mem_global_ref;
425 struct ttm_bo_device bdev;
426 bool mem_global_referenced;
427 bool initialized;
428
429 #if defined(CONFIG_DEBUG_FS)
430 struct dentry *vram;
431 struct dentry *gtt;
432 #endif
433 };
434
435 /* bo virtual address in a specific vm */
436 struct radeon_bo_va {
437 /* protected by bo being reserved */
438 struct list_head bo_list;
439 uint64_t soffset;
440 uint64_t eoffset;
441 uint32_t flags;
442 bool valid;
443 unsigned ref_count;
444
445 /* protected by vm mutex */
446 struct list_head vm_list;
447
448 /* constant after initialization */
449 struct radeon_vm *vm;
450 struct radeon_bo *bo;
451 };
452
453 struct radeon_bo {
454 /* Protected by gem.mutex */
455 struct list_head list;
456 /* Protected by tbo.reserved */
457 u32 placements[3];
458 struct ttm_placement placement;
459 struct ttm_buffer_object tbo;
460 struct ttm_bo_kmap_obj kmap;
461 unsigned pin_count;
462 void *kptr;
463 u32 tiling_flags;
464 u32 pitch;
465 int surface_reg;
466 /* list of all virtual address to which this bo
467 * is associated to
468 */
469 struct list_head va;
470 /* Constant after initialization */
471 struct radeon_device *rdev;
472 struct drm_gem_object gem_base;
473
474 struct ttm_bo_kmap_obj dma_buf_vmap;
475 pid_t pid;
476 };
477 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
478
479 struct radeon_bo_list {
480 struct ttm_validate_buffer tv;
481 struct radeon_bo *bo;
482 uint64_t gpu_offset;
483 bool written;
484 unsigned domain;
485 unsigned alt_domain;
486 u32 tiling_flags;
487 };
488
489 int radeon_gem_debugfs_init(struct radeon_device *rdev);
490
491 /* sub-allocation manager, it has to be protected by another lock.
492 * By conception this is an helper for other part of the driver
493 * like the indirect buffer or semaphore, which both have their
494 * locking.
495 *
496 * Principe is simple, we keep a list of sub allocation in offset
497 * order (first entry has offset == 0, last entry has the highest
498 * offset).
499 *
500 * When allocating new object we first check if there is room at
501 * the end total_size - (last_object_offset + last_object_size) >=
502 * alloc_size. If so we allocate new object there.
503 *
504 * When there is not enough room at the end, we start waiting for
505 * each sub object until we reach object_offset+object_size >=
506 * alloc_size, this object then become the sub object we return.
507 *
508 * Alignment can't be bigger than page size.
509 *
510 * Hole are not considered for allocation to keep things simple.
511 * Assumption is that there won't be hole (all object on same
512 * alignment).
513 */
514 struct radeon_sa_manager {
515 wait_queue_head_t wq;
516 struct radeon_bo *bo;
517 struct list_head *hole;
518 struct list_head flist[RADEON_NUM_RINGS];
519 struct list_head olist;
520 unsigned size;
521 uint64_t gpu_addr;
522 void *cpu_ptr;
523 uint32_t domain;
524 uint32_t align;
525 };
526
527 struct radeon_sa_bo;
528
529 /* sub-allocation buffer */
530 struct radeon_sa_bo {
531 struct list_head olist;
532 struct list_head flist;
533 struct radeon_sa_manager *manager;
534 unsigned soffset;
535 unsigned eoffset;
536 struct radeon_fence *fence;
537 };
538
539 /*
540 * GEM objects.
541 */
542 struct radeon_gem {
543 struct mutex mutex;
544 struct list_head objects;
545 };
546
547 int radeon_gem_init(struct radeon_device *rdev);
548 void radeon_gem_fini(struct radeon_device *rdev);
549 int radeon_gem_object_create(struct radeon_device *rdev, int size,
550 int alignment, int initial_domain,
551 bool discardable, bool kernel,
552 struct drm_gem_object **obj);
553
554 int radeon_mode_dumb_create(struct drm_file *file_priv,
555 struct drm_device *dev,
556 struct drm_mode_create_dumb *args);
557 int radeon_mode_dumb_mmap(struct drm_file *filp,
558 struct drm_device *dev,
559 uint32_t handle, uint64_t *offset_p);
560
561 /*
562 * Semaphores.
563 */
564 struct radeon_semaphore {
565 struct radeon_sa_bo *sa_bo;
566 signed waiters;
567 uint64_t gpu_addr;
568 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
569 };
570
571 int radeon_semaphore_create(struct radeon_device *rdev,
572 struct radeon_semaphore **semaphore);
573 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
574 struct radeon_semaphore *semaphore);
575 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
576 struct radeon_semaphore *semaphore);
577 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
578 struct radeon_fence *fence);
579 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
580 struct radeon_semaphore *semaphore,
581 int waiting_ring);
582 void radeon_semaphore_free(struct radeon_device *rdev,
583 struct radeon_semaphore **semaphore,
584 struct radeon_fence *fence);
585
586 /*
587 * GART structures, functions & helpers
588 */
589 struct radeon_mc;
590
591 #define RADEON_GPU_PAGE_SIZE 4096
592 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
593 #define RADEON_GPU_PAGE_SHIFT 12
594 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
595
596 struct radeon_gart {
597 dma_addr_t table_addr;
598 struct radeon_bo *robj;
599 void *ptr;
600 unsigned num_gpu_pages;
601 unsigned num_cpu_pages;
602 unsigned table_size;
603 struct page **pages;
604 dma_addr_t *pages_addr;
605 bool ready;
606 };
607
608 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
609 void radeon_gart_table_ram_free(struct radeon_device *rdev);
610 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
611 void radeon_gart_table_vram_free(struct radeon_device *rdev);
612 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
613 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
614 int radeon_gart_init(struct radeon_device *rdev);
615 void radeon_gart_fini(struct radeon_device *rdev);
616 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
617 int pages);
618 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
619 int pages, struct page **pagelist,
620 dma_addr_t *dma_addr);
621 void radeon_gart_restore(struct radeon_device *rdev);
622
623
624 /*
625 * GPU MC structures, functions & helpers
626 */
627 struct radeon_mc {
628 resource_size_t aper_size;
629 resource_size_t aper_base;
630 resource_size_t agp_base;
631 /* for some chips with <= 32MB we need to lie
632 * about vram size near mc fb location */
633 u64 mc_vram_size;
634 u64 visible_vram_size;
635 u64 gtt_size;
636 u64 gtt_start;
637 u64 gtt_end;
638 u64 vram_start;
639 u64 vram_end;
640 unsigned vram_width;
641 u64 real_vram_size;
642 int vram_mtrr;
643 bool vram_is_ddr;
644 bool igp_sideport_enabled;
645 u64 gtt_base_align;
646 u64 mc_mask;
647 };
648
649 bool radeon_combios_sideport_present(struct radeon_device *rdev);
650 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
651
652 /*
653 * GPU scratch registers structures, functions & helpers
654 */
655 struct radeon_scratch {
656 unsigned num_reg;
657 uint32_t reg_base;
658 bool free[32];
659 uint32_t reg[32];
660 };
661
662 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
663 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
664
665 /*
666 * GPU doorbell structures, functions & helpers
667 */
668 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
669
670 struct radeon_doorbell {
671 /* doorbell mmio */
672 resource_size_t base;
673 resource_size_t size;
674 u32 __iomem *ptr;
675 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
676 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
677 };
678
679 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
680 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
681
682 /*
683 * IRQS.
684 */
685
686 struct radeon_unpin_work {
687 struct work_struct work;
688 struct radeon_device *rdev;
689 int crtc_id;
690 struct radeon_fence *fence;
691 struct drm_pending_vblank_event *event;
692 struct radeon_bo *old_rbo;
693 u64 new_crtc_base;
694 };
695
696 struct r500_irq_stat_regs {
697 u32 disp_int;
698 u32 hdmi0_status;
699 };
700
701 struct r600_irq_stat_regs {
702 u32 disp_int;
703 u32 disp_int_cont;
704 u32 disp_int_cont2;
705 u32 d1grph_int;
706 u32 d2grph_int;
707 u32 hdmi0_status;
708 u32 hdmi1_status;
709 };
710
711 struct evergreen_irq_stat_regs {
712 u32 disp_int;
713 u32 disp_int_cont;
714 u32 disp_int_cont2;
715 u32 disp_int_cont3;
716 u32 disp_int_cont4;
717 u32 disp_int_cont5;
718 u32 d1grph_int;
719 u32 d2grph_int;
720 u32 d3grph_int;
721 u32 d4grph_int;
722 u32 d5grph_int;
723 u32 d6grph_int;
724 u32 afmt_status1;
725 u32 afmt_status2;
726 u32 afmt_status3;
727 u32 afmt_status4;
728 u32 afmt_status5;
729 u32 afmt_status6;
730 };
731
732 struct cik_irq_stat_regs {
733 u32 disp_int;
734 u32 disp_int_cont;
735 u32 disp_int_cont2;
736 u32 disp_int_cont3;
737 u32 disp_int_cont4;
738 u32 disp_int_cont5;
739 u32 disp_int_cont6;
740 };
741
742 union radeon_irq_stat_regs {
743 struct r500_irq_stat_regs r500;
744 struct r600_irq_stat_regs r600;
745 struct evergreen_irq_stat_regs evergreen;
746 struct cik_irq_stat_regs cik;
747 };
748
749 #define RADEON_MAX_HPD_PINS 6
750 #define RADEON_MAX_CRTCS 6
751 #define RADEON_MAX_AFMT_BLOCKS 7
752
753 struct radeon_irq {
754 bool installed;
755 spinlock_t lock;
756 atomic_t ring_int[RADEON_NUM_RINGS];
757 bool crtc_vblank_int[RADEON_MAX_CRTCS];
758 atomic_t pflip[RADEON_MAX_CRTCS];
759 wait_queue_head_t vblank_queue;
760 bool hpd[RADEON_MAX_HPD_PINS];
761 bool afmt[RADEON_MAX_AFMT_BLOCKS];
762 union radeon_irq_stat_regs stat_regs;
763 bool dpm_thermal;
764 };
765
766 int radeon_irq_kms_init(struct radeon_device *rdev);
767 void radeon_irq_kms_fini(struct radeon_device *rdev);
768 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
769 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
770 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
771 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
772 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
773 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
774 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
775 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
776
777 /*
778 * CP & rings.
779 */
780
781 struct radeon_ib {
782 struct radeon_sa_bo *sa_bo;
783 uint32_t length_dw;
784 uint64_t gpu_addr;
785 uint32_t *ptr;
786 int ring;
787 struct radeon_fence *fence;
788 struct radeon_vm *vm;
789 bool is_const_ib;
790 struct radeon_semaphore *semaphore;
791 };
792
793 struct radeon_ring {
794 struct radeon_bo *ring_obj;
795 volatile uint32_t *ring;
796 unsigned rptr;
797 unsigned rptr_offs;
798 unsigned rptr_save_reg;
799 u64 next_rptr_gpu_addr;
800 volatile u32 *next_rptr_cpu_addr;
801 unsigned wptr;
802 unsigned wptr_old;
803 unsigned ring_size;
804 unsigned ring_free_dw;
805 int count_dw;
806 unsigned long last_activity;
807 unsigned last_rptr;
808 uint64_t gpu_addr;
809 uint32_t align_mask;
810 uint32_t ptr_mask;
811 bool ready;
812 u32 nop;
813 u32 idx;
814 u64 last_semaphore_signal_addr;
815 u64 last_semaphore_wait_addr;
816 /* for CIK queues */
817 u32 me;
818 u32 pipe;
819 u32 queue;
820 struct radeon_bo *mqd_obj;
821 u32 doorbell_index;
822 unsigned wptr_offs;
823 };
824
825 struct radeon_mec {
826 struct radeon_bo *hpd_eop_obj;
827 u64 hpd_eop_gpu_addr;
828 u32 num_pipe;
829 u32 num_mec;
830 u32 num_queue;
831 };
832
833 /*
834 * VM
835 */
836
837 /* maximum number of VMIDs */
838 #define RADEON_NUM_VM 16
839
840 /* defines number of bits in page table versus page directory,
841 * a page is 4KB so we have 12 bits offset, 9 bits in the page
842 * table and the remaining 19 bits are in the page directory */
843 #define RADEON_VM_BLOCK_SIZE 9
844
845 /* number of entries in page table */
846 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
847
848 /* PTBs (Page Table Blocks) need to be aligned to 32K */
849 #define RADEON_VM_PTB_ALIGN_SIZE 32768
850 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
851 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
852
853 #define R600_PTE_VALID (1 << 0)
854 #define R600_PTE_SYSTEM (1 << 1)
855 #define R600_PTE_SNOOPED (1 << 2)
856 #define R600_PTE_READABLE (1 << 5)
857 #define R600_PTE_WRITEABLE (1 << 6)
858
859 struct radeon_vm {
860 struct list_head list;
861 struct list_head va;
862 unsigned id;
863
864 /* contains the page directory */
865 struct radeon_sa_bo *page_directory;
866 uint64_t pd_gpu_addr;
867
868 /* array of page tables, one for each page directory entry */
869 struct radeon_sa_bo **page_tables;
870
871 struct mutex mutex;
872 /* last fence for cs using this vm */
873 struct radeon_fence *fence;
874 /* last flush or NULL if we still need to flush */
875 struct radeon_fence *last_flush;
876 /* last use of vmid */
877 struct radeon_fence *last_id_use;
878 };
879
880 struct radeon_vm_manager {
881 struct mutex lock;
882 struct list_head lru_vm;
883 struct radeon_fence *active[RADEON_NUM_VM];
884 struct radeon_sa_manager sa_manager;
885 uint32_t max_pfn;
886 /* number of VMIDs */
887 unsigned nvm;
888 /* vram base address for page table entry */
889 u64 vram_base_offset;
890 /* is vm enabled? */
891 bool enabled;
892 };
893
894 /*
895 * file private structure
896 */
897 struct radeon_fpriv {
898 struct radeon_vm vm;
899 };
900
901 /*
902 * R6xx+ IH ring
903 */
904 struct r600_ih {
905 struct radeon_bo *ring_obj;
906 volatile uint32_t *ring;
907 unsigned rptr;
908 unsigned ring_size;
909 uint64_t gpu_addr;
910 uint32_t ptr_mask;
911 atomic_t lock;
912 bool enabled;
913 };
914
915 /*
916 * RLC stuff
917 */
918 #include "clearstate_defs.h"
919
920 struct radeon_rlc {
921 /* for power gating */
922 struct radeon_bo *save_restore_obj;
923 uint64_t save_restore_gpu_addr;
924 volatile uint32_t *sr_ptr;
925 const u32 *reg_list;
926 u32 reg_list_size;
927 /* for clear state */
928 struct radeon_bo *clear_state_obj;
929 uint64_t clear_state_gpu_addr;
930 volatile uint32_t *cs_ptr;
931 const struct cs_section_def *cs_data;
932 u32 clear_state_size;
933 /* for cp tables */
934 struct radeon_bo *cp_table_obj;
935 uint64_t cp_table_gpu_addr;
936 volatile uint32_t *cp_table_ptr;
937 u32 cp_table_size;
938 };
939
940 int radeon_ib_get(struct radeon_device *rdev, int ring,
941 struct radeon_ib *ib, struct radeon_vm *vm,
942 unsigned size);
943 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
944 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
945 struct radeon_ib *const_ib);
946 int radeon_ib_pool_init(struct radeon_device *rdev);
947 void radeon_ib_pool_fini(struct radeon_device *rdev);
948 int radeon_ib_ring_tests(struct radeon_device *rdev);
949 /* Ring access between begin & end cannot sleep */
950 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
951 struct radeon_ring *ring);
952 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
953 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
954 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
955 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
956 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
957 void radeon_ring_undo(struct radeon_ring *ring);
958 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
959 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
960 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
961 void radeon_ring_lockup_update(struct radeon_ring *ring);
962 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
963 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
964 uint32_t **data);
965 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
966 unsigned size, uint32_t *data);
967 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
968 unsigned rptr_offs, u32 nop);
969 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
970
971
972 /* r600 async dma */
973 void r600_dma_stop(struct radeon_device *rdev);
974 int r600_dma_resume(struct radeon_device *rdev);
975 void r600_dma_fini(struct radeon_device *rdev);
976
977 void cayman_dma_stop(struct radeon_device *rdev);
978 int cayman_dma_resume(struct radeon_device *rdev);
979 void cayman_dma_fini(struct radeon_device *rdev);
980
981 /*
982 * CS.
983 */
984 struct radeon_cs_reloc {
985 struct drm_gem_object *gobj;
986 struct radeon_bo *robj;
987 struct radeon_bo_list lobj;
988 uint32_t handle;
989 uint32_t flags;
990 };
991
992 struct radeon_cs_chunk {
993 uint32_t chunk_id;
994 uint32_t length_dw;
995 uint32_t *kdata;
996 void __user *user_ptr;
997 };
998
999 struct radeon_cs_parser {
1000 struct device *dev;
1001 struct radeon_device *rdev;
1002 struct drm_file *filp;
1003 /* chunks */
1004 unsigned nchunks;
1005 struct radeon_cs_chunk *chunks;
1006 uint64_t *chunks_array;
1007 /* IB */
1008 unsigned idx;
1009 /* relocations */
1010 unsigned nrelocs;
1011 struct radeon_cs_reloc *relocs;
1012 struct radeon_cs_reloc **relocs_ptr;
1013 struct list_head validated;
1014 unsigned dma_reloc_idx;
1015 /* indices of various chunks */
1016 int chunk_ib_idx;
1017 int chunk_relocs_idx;
1018 int chunk_flags_idx;
1019 int chunk_const_ib_idx;
1020 struct radeon_ib ib;
1021 struct radeon_ib const_ib;
1022 void *track;
1023 unsigned family;
1024 int parser_error;
1025 u32 cs_flags;
1026 u32 ring;
1027 s32 priority;
1028 struct ww_acquire_ctx ticket;
1029 };
1030
1031 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1032 {
1033 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1034
1035 if (ibc->kdata)
1036 return ibc->kdata[idx];
1037 return p->ib.ptr[idx];
1038 }
1039
1040
1041 struct radeon_cs_packet {
1042 unsigned idx;
1043 unsigned type;
1044 unsigned reg;
1045 unsigned opcode;
1046 int count;
1047 unsigned one_reg_wr;
1048 };
1049
1050 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1051 struct radeon_cs_packet *pkt,
1052 unsigned idx, unsigned reg);
1053 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1054 struct radeon_cs_packet *pkt);
1055
1056
1057 /*
1058 * AGP
1059 */
1060 int radeon_agp_init(struct radeon_device *rdev);
1061 void radeon_agp_resume(struct radeon_device *rdev);
1062 void radeon_agp_suspend(struct radeon_device *rdev);
1063 void radeon_agp_fini(struct radeon_device *rdev);
1064
1065
1066 /*
1067 * Writeback
1068 */
1069 struct radeon_wb {
1070 struct radeon_bo *wb_obj;
1071 volatile uint32_t *wb;
1072 uint64_t gpu_addr;
1073 bool enabled;
1074 bool use_event;
1075 };
1076
1077 #define RADEON_WB_SCRATCH_OFFSET 0
1078 #define RADEON_WB_RING0_NEXT_RPTR 256
1079 #define RADEON_WB_CP_RPTR_OFFSET 1024
1080 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1081 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1082 #define R600_WB_DMA_RPTR_OFFSET 1792
1083 #define R600_WB_IH_WPTR_OFFSET 2048
1084 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1085 #define R600_WB_EVENT_OFFSET 3072
1086 #define CIK_WB_CP1_WPTR_OFFSET 3328
1087 #define CIK_WB_CP2_WPTR_OFFSET 3584
1088
1089 /**
1090 * struct radeon_pm - power management datas
1091 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1092 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1093 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1094 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1095 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1096 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1097 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1098 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1099 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1100 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1101 * @needed_bandwidth: current bandwidth needs
1102 *
1103 * It keeps track of various data needed to take powermanagement decision.
1104 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1105 * Equation between gpu/memory clock and available bandwidth is hw dependent
1106 * (type of memory, bus size, efficiency, ...)
1107 */
1108
1109 enum radeon_pm_method {
1110 PM_METHOD_PROFILE,
1111 PM_METHOD_DYNPM,
1112 PM_METHOD_DPM,
1113 };
1114
1115 enum radeon_dynpm_state {
1116 DYNPM_STATE_DISABLED,
1117 DYNPM_STATE_MINIMUM,
1118 DYNPM_STATE_PAUSED,
1119 DYNPM_STATE_ACTIVE,
1120 DYNPM_STATE_SUSPENDED,
1121 };
1122 enum radeon_dynpm_action {
1123 DYNPM_ACTION_NONE,
1124 DYNPM_ACTION_MINIMUM,
1125 DYNPM_ACTION_DOWNCLOCK,
1126 DYNPM_ACTION_UPCLOCK,
1127 DYNPM_ACTION_DEFAULT
1128 };
1129
1130 enum radeon_voltage_type {
1131 VOLTAGE_NONE = 0,
1132 VOLTAGE_GPIO,
1133 VOLTAGE_VDDC,
1134 VOLTAGE_SW
1135 };
1136
1137 enum radeon_pm_state_type {
1138 /* not used for dpm */
1139 POWER_STATE_TYPE_DEFAULT,
1140 POWER_STATE_TYPE_POWERSAVE,
1141 /* user selectable states */
1142 POWER_STATE_TYPE_BATTERY,
1143 POWER_STATE_TYPE_BALANCED,
1144 POWER_STATE_TYPE_PERFORMANCE,
1145 /* internal states */
1146 POWER_STATE_TYPE_INTERNAL_UVD,
1147 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1148 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1149 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1150 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1151 POWER_STATE_TYPE_INTERNAL_BOOT,
1152 POWER_STATE_TYPE_INTERNAL_THERMAL,
1153 POWER_STATE_TYPE_INTERNAL_ACPI,
1154 POWER_STATE_TYPE_INTERNAL_ULV,
1155 POWER_STATE_TYPE_INTERNAL_3DPERF,
1156 };
1157
1158 enum radeon_pm_profile_type {
1159 PM_PROFILE_DEFAULT,
1160 PM_PROFILE_AUTO,
1161 PM_PROFILE_LOW,
1162 PM_PROFILE_MID,
1163 PM_PROFILE_HIGH,
1164 };
1165
1166 #define PM_PROFILE_DEFAULT_IDX 0
1167 #define PM_PROFILE_LOW_SH_IDX 1
1168 #define PM_PROFILE_MID_SH_IDX 2
1169 #define PM_PROFILE_HIGH_SH_IDX 3
1170 #define PM_PROFILE_LOW_MH_IDX 4
1171 #define PM_PROFILE_MID_MH_IDX 5
1172 #define PM_PROFILE_HIGH_MH_IDX 6
1173 #define PM_PROFILE_MAX 7
1174
1175 struct radeon_pm_profile {
1176 int dpms_off_ps_idx;
1177 int dpms_on_ps_idx;
1178 int dpms_off_cm_idx;
1179 int dpms_on_cm_idx;
1180 };
1181
1182 enum radeon_int_thermal_type {
1183 THERMAL_TYPE_NONE,
1184 THERMAL_TYPE_EXTERNAL,
1185 THERMAL_TYPE_EXTERNAL_GPIO,
1186 THERMAL_TYPE_RV6XX,
1187 THERMAL_TYPE_RV770,
1188 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1189 THERMAL_TYPE_EVERGREEN,
1190 THERMAL_TYPE_SUMO,
1191 THERMAL_TYPE_NI,
1192 THERMAL_TYPE_SI,
1193 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1194 THERMAL_TYPE_CI,
1195 THERMAL_TYPE_KV,
1196 };
1197
1198 struct radeon_voltage {
1199 enum radeon_voltage_type type;
1200 /* gpio voltage */
1201 struct radeon_gpio_rec gpio;
1202 u32 delay; /* delay in usec from voltage drop to sclk change */
1203 bool active_high; /* voltage drop is active when bit is high */
1204 /* VDDC voltage */
1205 u8 vddc_id; /* index into vddc voltage table */
1206 u8 vddci_id; /* index into vddci voltage table */
1207 bool vddci_enabled;
1208 /* r6xx+ sw */
1209 u16 voltage;
1210 /* evergreen+ vddci */
1211 u16 vddci;
1212 };
1213
1214 /* clock mode flags */
1215 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1216
1217 struct radeon_pm_clock_info {
1218 /* memory clock */
1219 u32 mclk;
1220 /* engine clock */
1221 u32 sclk;
1222 /* voltage info */
1223 struct radeon_voltage voltage;
1224 /* standardized clock flags */
1225 u32 flags;
1226 };
1227
1228 /* state flags */
1229 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1230
1231 struct radeon_power_state {
1232 enum radeon_pm_state_type type;
1233 struct radeon_pm_clock_info *clock_info;
1234 /* number of valid clock modes in this power state */
1235 int num_clock_modes;
1236 struct radeon_pm_clock_info *default_clock_mode;
1237 /* standardized state flags */
1238 u32 flags;
1239 u32 misc; /* vbios specific flags */
1240 u32 misc2; /* vbios specific flags */
1241 int pcie_lanes; /* pcie lanes */
1242 };
1243
1244 /*
1245 * Some modes are overclocked by very low value, accept them
1246 */
1247 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1248
1249 enum radeon_dpm_auto_throttle_src {
1250 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1251 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1252 };
1253
1254 enum radeon_dpm_event_src {
1255 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1256 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1257 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1258 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1259 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1260 };
1261
1262 struct radeon_ps {
1263 u32 caps; /* vbios flags */
1264 u32 class; /* vbios flags */
1265 u32 class2; /* vbios flags */
1266 /* UVD clocks */
1267 u32 vclk;
1268 u32 dclk;
1269 /* VCE clocks */
1270 u32 evclk;
1271 u32 ecclk;
1272 /* asic priv */
1273 void *ps_priv;
1274 };
1275
1276 struct radeon_dpm_thermal {
1277 /* thermal interrupt work */
1278 struct work_struct work;
1279 /* low temperature threshold */
1280 int min_temp;
1281 /* high temperature threshold */
1282 int max_temp;
1283 /* was interrupt low to high or high to low */
1284 bool high_to_low;
1285 };
1286
1287 enum radeon_clk_action
1288 {
1289 RADEON_SCLK_UP = 1,
1290 RADEON_SCLK_DOWN
1291 };
1292
1293 struct radeon_blacklist_clocks
1294 {
1295 u32 sclk;
1296 u32 mclk;
1297 enum radeon_clk_action action;
1298 };
1299
1300 struct radeon_clock_and_voltage_limits {
1301 u32 sclk;
1302 u32 mclk;
1303 u16 vddc;
1304 u16 vddci;
1305 };
1306
1307 struct radeon_clock_array {
1308 u32 count;
1309 u32 *values;
1310 };
1311
1312 struct radeon_clock_voltage_dependency_entry {
1313 u32 clk;
1314 u16 v;
1315 };
1316
1317 struct radeon_clock_voltage_dependency_table {
1318 u32 count;
1319 struct radeon_clock_voltage_dependency_entry *entries;
1320 };
1321
1322 union radeon_cac_leakage_entry {
1323 struct {
1324 u16 vddc;
1325 u32 leakage;
1326 };
1327 struct {
1328 u16 vddc1;
1329 u16 vddc2;
1330 u16 vddc3;
1331 };
1332 };
1333
1334 struct radeon_cac_leakage_table {
1335 u32 count;
1336 union radeon_cac_leakage_entry *entries;
1337 };
1338
1339 struct radeon_phase_shedding_limits_entry {
1340 u16 voltage;
1341 u32 sclk;
1342 u32 mclk;
1343 };
1344
1345 struct radeon_phase_shedding_limits_table {
1346 u32 count;
1347 struct radeon_phase_shedding_limits_entry *entries;
1348 };
1349
1350 struct radeon_uvd_clock_voltage_dependency_entry {
1351 u32 vclk;
1352 u32 dclk;
1353 u16 v;
1354 };
1355
1356 struct radeon_uvd_clock_voltage_dependency_table {
1357 u8 count;
1358 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1359 };
1360
1361 struct radeon_vce_clock_voltage_dependency_entry {
1362 u32 ecclk;
1363 u32 evclk;
1364 u16 v;
1365 };
1366
1367 struct radeon_vce_clock_voltage_dependency_table {
1368 u8 count;
1369 struct radeon_vce_clock_voltage_dependency_entry *entries;
1370 };
1371
1372 struct radeon_ppm_table {
1373 u8 ppm_design;
1374 u16 cpu_core_number;
1375 u32 platform_tdp;
1376 u32 small_ac_platform_tdp;
1377 u32 platform_tdc;
1378 u32 small_ac_platform_tdc;
1379 u32 apu_tdp;
1380 u32 dgpu_tdp;
1381 u32 dgpu_ulv_power;
1382 u32 tj_max;
1383 };
1384
1385 struct radeon_cac_tdp_table {
1386 u16 tdp;
1387 u16 configurable_tdp;
1388 u16 tdc;
1389 u16 battery_power_limit;
1390 u16 small_power_limit;
1391 u16 low_cac_leakage;
1392 u16 high_cac_leakage;
1393 u16 maximum_power_delivery_limit;
1394 };
1395
1396 struct radeon_dpm_dynamic_state {
1397 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1398 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1399 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1400 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1401 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1402 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1403 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1404 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1405 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1406 struct radeon_clock_array valid_sclk_values;
1407 struct radeon_clock_array valid_mclk_values;
1408 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1409 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1410 u32 mclk_sclk_ratio;
1411 u32 sclk_mclk_delta;
1412 u16 vddc_vddci_delta;
1413 u16 min_vddc_for_pcie_gen2;
1414 struct radeon_cac_leakage_table cac_leakage_table;
1415 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1416 struct radeon_ppm_table *ppm_table;
1417 struct radeon_cac_tdp_table *cac_tdp_table;
1418 };
1419
1420 struct radeon_dpm_fan {
1421 u16 t_min;
1422 u16 t_med;
1423 u16 t_high;
1424 u16 pwm_min;
1425 u16 pwm_med;
1426 u16 pwm_high;
1427 u8 t_hyst;
1428 u32 cycle_delay;
1429 u16 t_max;
1430 bool ucode_fan_control;
1431 };
1432
1433 enum radeon_pcie_gen {
1434 RADEON_PCIE_GEN1 = 0,
1435 RADEON_PCIE_GEN2 = 1,
1436 RADEON_PCIE_GEN3 = 2,
1437 RADEON_PCIE_GEN_INVALID = 0xffff
1438 };
1439
1440 enum radeon_dpm_forced_level {
1441 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1442 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1443 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1444 };
1445
1446 struct radeon_dpm {
1447 struct radeon_ps *ps;
1448 /* number of valid power states */
1449 int num_ps;
1450 /* current power state that is active */
1451 struct radeon_ps *current_ps;
1452 /* requested power state */
1453 struct radeon_ps *requested_ps;
1454 /* boot up power state */
1455 struct radeon_ps *boot_ps;
1456 /* default uvd power state */
1457 struct radeon_ps *uvd_ps;
1458 enum radeon_pm_state_type state;
1459 enum radeon_pm_state_type user_state;
1460 u32 platform_caps;
1461 u32 voltage_response_time;
1462 u32 backbias_response_time;
1463 void *priv;
1464 u32 new_active_crtcs;
1465 int new_active_crtc_count;
1466 u32 current_active_crtcs;
1467 int current_active_crtc_count;
1468 struct radeon_dpm_dynamic_state dyn_state;
1469 struct radeon_dpm_fan fan;
1470 u32 tdp_limit;
1471 u32 near_tdp_limit;
1472 u32 near_tdp_limit_adjusted;
1473 u32 sq_ramping_threshold;
1474 u32 cac_leakage;
1475 u16 tdp_od_limit;
1476 u32 tdp_adjustment;
1477 u16 load_line_slope;
1478 bool power_control;
1479 bool ac_power;
1480 /* special states active */
1481 bool thermal_active;
1482 bool uvd_active;
1483 /* thermal handling */
1484 struct radeon_dpm_thermal thermal;
1485 /* forced levels */
1486 enum radeon_dpm_forced_level forced_level;
1487 /* track UVD streams */
1488 unsigned sd;
1489 unsigned hd;
1490 };
1491
1492 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1493
1494 struct radeon_pm {
1495 struct mutex mutex;
1496 /* write locked while reprogramming mclk */
1497 struct rw_semaphore mclk_lock;
1498 u32 active_crtcs;
1499 int active_crtc_count;
1500 int req_vblank;
1501 bool vblank_sync;
1502 fixed20_12 max_bandwidth;
1503 fixed20_12 igp_sideport_mclk;
1504 fixed20_12 igp_system_mclk;
1505 fixed20_12 igp_ht_link_clk;
1506 fixed20_12 igp_ht_link_width;
1507 fixed20_12 k8_bandwidth;
1508 fixed20_12 sideport_bandwidth;
1509 fixed20_12 ht_bandwidth;
1510 fixed20_12 core_bandwidth;
1511 fixed20_12 sclk;
1512 fixed20_12 mclk;
1513 fixed20_12 needed_bandwidth;
1514 struct radeon_power_state *power_state;
1515 /* number of valid power states */
1516 int num_power_states;
1517 int current_power_state_index;
1518 int current_clock_mode_index;
1519 int requested_power_state_index;
1520 int requested_clock_mode_index;
1521 int default_power_state_index;
1522 u32 current_sclk;
1523 u32 current_mclk;
1524 u16 current_vddc;
1525 u16 current_vddci;
1526 u32 default_sclk;
1527 u32 default_mclk;
1528 u16 default_vddc;
1529 u16 default_vddci;
1530 struct radeon_i2c_chan *i2c_bus;
1531 /* selected pm method */
1532 enum radeon_pm_method pm_method;
1533 /* dynpm power management */
1534 struct delayed_work dynpm_idle_work;
1535 enum radeon_dynpm_state dynpm_state;
1536 enum radeon_dynpm_action dynpm_planned_action;
1537 unsigned long dynpm_action_timeout;
1538 bool dynpm_can_upclock;
1539 bool dynpm_can_downclock;
1540 /* profile-based power management */
1541 enum radeon_pm_profile_type profile;
1542 int profile_index;
1543 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1544 /* internal thermal controller on rv6xx+ */
1545 enum radeon_int_thermal_type int_thermal_type;
1546 struct device *int_hwmon_dev;
1547 /* dpm */
1548 bool dpm_enabled;
1549 struct radeon_dpm dpm;
1550 };
1551
1552 int radeon_pm_get_type_index(struct radeon_device *rdev,
1553 enum radeon_pm_state_type ps_type,
1554 int instance);
1555 /*
1556 * UVD
1557 */
1558 #define RADEON_MAX_UVD_HANDLES 10
1559 #define RADEON_UVD_STACK_SIZE (1024*1024)
1560 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1561
1562 struct radeon_uvd {
1563 struct radeon_bo *vcpu_bo;
1564 void *cpu_addr;
1565 uint64_t gpu_addr;
1566 void *saved_bo;
1567 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1568 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1569 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1570 struct delayed_work idle_work;
1571 };
1572
1573 int radeon_uvd_init(struct radeon_device *rdev);
1574 void radeon_uvd_fini(struct radeon_device *rdev);
1575 int radeon_uvd_suspend(struct radeon_device *rdev);
1576 int radeon_uvd_resume(struct radeon_device *rdev);
1577 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1578 uint32_t handle, struct radeon_fence **fence);
1579 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1580 uint32_t handle, struct radeon_fence **fence);
1581 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1582 void radeon_uvd_free_handles(struct radeon_device *rdev,
1583 struct drm_file *filp);
1584 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1585 void radeon_uvd_note_usage(struct radeon_device *rdev);
1586 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1587 unsigned vclk, unsigned dclk,
1588 unsigned vco_min, unsigned vco_max,
1589 unsigned fb_factor, unsigned fb_mask,
1590 unsigned pd_min, unsigned pd_max,
1591 unsigned pd_even,
1592 unsigned *optimal_fb_div,
1593 unsigned *optimal_vclk_div,
1594 unsigned *optimal_dclk_div);
1595 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1596 unsigned cg_upll_func_cntl);
1597
1598 /*
1599 * VCE
1600 */
1601 #define RADEON_MAX_VCE_HANDLES 16
1602 #define RADEON_VCE_STACK_SIZE (1024*1024)
1603 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1604
1605 struct radeon_vce {
1606 struct radeon_bo *vcpu_bo;
1607 void *cpu_addr;
1608 uint64_t gpu_addr;
1609 unsigned fw_version;
1610 unsigned fb_version;
1611 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1612 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1613 };
1614
1615 int radeon_vce_init(struct radeon_device *rdev);
1616 void radeon_vce_fini(struct radeon_device *rdev);
1617 int radeon_vce_suspend(struct radeon_device *rdev);
1618 int radeon_vce_resume(struct radeon_device *rdev);
1619 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1620 uint32_t handle, struct radeon_fence **fence);
1621 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1622 uint32_t handle, struct radeon_fence **fence);
1623 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1624 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi);
1625 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1626 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1627 struct radeon_ring *ring,
1628 struct radeon_semaphore *semaphore,
1629 bool emit_wait);
1630 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1631 void radeon_vce_fence_emit(struct radeon_device *rdev,
1632 struct radeon_fence *fence);
1633 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1634 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1635
1636 struct r600_audio_pin {
1637 int channels;
1638 int rate;
1639 int bits_per_sample;
1640 u8 status_bits;
1641 u8 category_code;
1642 u32 offset;
1643 bool connected;
1644 u32 id;
1645 };
1646
1647 struct r600_audio {
1648 bool enabled;
1649 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1650 int num_pins;
1651 };
1652
1653 /*
1654 * Benchmarking
1655 */
1656 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1657
1658
1659 /*
1660 * Testing
1661 */
1662 void radeon_test_moves(struct radeon_device *rdev);
1663 void radeon_test_ring_sync(struct radeon_device *rdev,
1664 struct radeon_ring *cpA,
1665 struct radeon_ring *cpB);
1666 void radeon_test_syncing(struct radeon_device *rdev);
1667
1668
1669 /*
1670 * Debugfs
1671 */
1672 struct radeon_debugfs {
1673 struct drm_info_list *files;
1674 unsigned num_files;
1675 };
1676
1677 int radeon_debugfs_add_files(struct radeon_device *rdev,
1678 struct drm_info_list *files,
1679 unsigned nfiles);
1680 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1681
1682 /*
1683 * ASIC ring specific functions.
1684 */
1685 struct radeon_asic_ring {
1686 /* ring read/write ptr handling */
1687 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1688 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1689 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1690
1691 /* validating and patching of IBs */
1692 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1693 int (*cs_parse)(struct radeon_cs_parser *p);
1694
1695 /* command emmit functions */
1696 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1697 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1698 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1699 struct radeon_semaphore *semaphore, bool emit_wait);
1700 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1701
1702 /* testing functions */
1703 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1704 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1705 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1706
1707 /* deprecated */
1708 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1709 };
1710
1711 /*
1712 * ASIC specific functions.
1713 */
1714 struct radeon_asic {
1715 int (*init)(struct radeon_device *rdev);
1716 void (*fini)(struct radeon_device *rdev);
1717 int (*resume)(struct radeon_device *rdev);
1718 int (*suspend)(struct radeon_device *rdev);
1719 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1720 int (*asic_reset)(struct radeon_device *rdev);
1721 /* ioctl hw specific callback. Some hw might want to perform special
1722 * operation on specific ioctl. For instance on wait idle some hw
1723 * might want to perform and HDP flush through MMIO as it seems that
1724 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1725 * through ring.
1726 */
1727 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1728 /* check if 3D engine is idle */
1729 bool (*gui_idle)(struct radeon_device *rdev);
1730 /* wait for mc_idle */
1731 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1732 /* get the reference clock */
1733 u32 (*get_xclk)(struct radeon_device *rdev);
1734 /* get the gpu clock counter */
1735 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1736 /* gart */
1737 struct {
1738 void (*tlb_flush)(struct radeon_device *rdev);
1739 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1740 } gart;
1741 struct {
1742 int (*init)(struct radeon_device *rdev);
1743 void (*fini)(struct radeon_device *rdev);
1744 void (*set_page)(struct radeon_device *rdev,
1745 struct radeon_ib *ib,
1746 uint64_t pe,
1747 uint64_t addr, unsigned count,
1748 uint32_t incr, uint32_t flags);
1749 } vm;
1750 /* ring specific callbacks */
1751 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1752 /* irqs */
1753 struct {
1754 int (*set)(struct radeon_device *rdev);
1755 int (*process)(struct radeon_device *rdev);
1756 } irq;
1757 /* displays */
1758 struct {
1759 /* display watermarks */
1760 void (*bandwidth_update)(struct radeon_device *rdev);
1761 /* get frame count */
1762 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1763 /* wait for vblank */
1764 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1765 /* set backlight level */
1766 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1767 /* get backlight level */
1768 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1769 /* audio callbacks */
1770 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1771 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1772 } display;
1773 /* copy functions for bo handling */
1774 struct {
1775 int (*blit)(struct radeon_device *rdev,
1776 uint64_t src_offset,
1777 uint64_t dst_offset,
1778 unsigned num_gpu_pages,
1779 struct radeon_fence **fence);
1780 u32 blit_ring_index;
1781 int (*dma)(struct radeon_device *rdev,
1782 uint64_t src_offset,
1783 uint64_t dst_offset,
1784 unsigned num_gpu_pages,
1785 struct radeon_fence **fence);
1786 u32 dma_ring_index;
1787 /* method used for bo copy */
1788 int (*copy)(struct radeon_device *rdev,
1789 uint64_t src_offset,
1790 uint64_t dst_offset,
1791 unsigned num_gpu_pages,
1792 struct radeon_fence **fence);
1793 /* ring used for bo copies */
1794 u32 copy_ring_index;
1795 } copy;
1796 /* surfaces */
1797 struct {
1798 int (*set_reg)(struct radeon_device *rdev, int reg,
1799 uint32_t tiling_flags, uint32_t pitch,
1800 uint32_t offset, uint32_t obj_size);
1801 void (*clear_reg)(struct radeon_device *rdev, int reg);
1802 } surface;
1803 /* hotplug detect */
1804 struct {
1805 void (*init)(struct radeon_device *rdev);
1806 void (*fini)(struct radeon_device *rdev);
1807 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1808 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1809 } hpd;
1810 /* static power management */
1811 struct {
1812 void (*misc)(struct radeon_device *rdev);
1813 void (*prepare)(struct radeon_device *rdev);
1814 void (*finish)(struct radeon_device *rdev);
1815 void (*init_profile)(struct radeon_device *rdev);
1816 void (*get_dynpm_state)(struct radeon_device *rdev);
1817 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1818 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1819 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1820 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1821 int (*get_pcie_lanes)(struct radeon_device *rdev);
1822 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1823 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1824 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1825 int (*get_temperature)(struct radeon_device *rdev);
1826 } pm;
1827 /* dynamic power management */
1828 struct {
1829 int (*init)(struct radeon_device *rdev);
1830 void (*setup_asic)(struct radeon_device *rdev);
1831 int (*enable)(struct radeon_device *rdev);
1832 int (*late_enable)(struct radeon_device *rdev);
1833 void (*disable)(struct radeon_device *rdev);
1834 int (*pre_set_power_state)(struct radeon_device *rdev);
1835 int (*set_power_state)(struct radeon_device *rdev);
1836 void (*post_set_power_state)(struct radeon_device *rdev);
1837 void (*display_configuration_changed)(struct radeon_device *rdev);
1838 void (*fini)(struct radeon_device *rdev);
1839 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1840 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1841 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1842 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1843 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1844 bool (*vblank_too_short)(struct radeon_device *rdev);
1845 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1846 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1847 } dpm;
1848 /* pageflipping */
1849 struct {
1850 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1851 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1852 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1853 } pflip;
1854 };
1855
1856 /*
1857 * Asic structures
1858 */
1859 struct r100_asic {
1860 const unsigned *reg_safe_bm;
1861 unsigned reg_safe_bm_size;
1862 u32 hdp_cntl;
1863 };
1864
1865 struct r300_asic {
1866 const unsigned *reg_safe_bm;
1867 unsigned reg_safe_bm_size;
1868 u32 resync_scratch;
1869 u32 hdp_cntl;
1870 };
1871
1872 struct r600_asic {
1873 unsigned max_pipes;
1874 unsigned max_tile_pipes;
1875 unsigned max_simds;
1876 unsigned max_backends;
1877 unsigned max_gprs;
1878 unsigned max_threads;
1879 unsigned max_stack_entries;
1880 unsigned max_hw_contexts;
1881 unsigned max_gs_threads;
1882 unsigned sx_max_export_size;
1883 unsigned sx_max_export_pos_size;
1884 unsigned sx_max_export_smx_size;
1885 unsigned sq_num_cf_insts;
1886 unsigned tiling_nbanks;
1887 unsigned tiling_npipes;
1888 unsigned tiling_group_size;
1889 unsigned tile_config;
1890 unsigned backend_map;
1891 };
1892
1893 struct rv770_asic {
1894 unsigned max_pipes;
1895 unsigned max_tile_pipes;
1896 unsigned max_simds;
1897 unsigned max_backends;
1898 unsigned max_gprs;
1899 unsigned max_threads;
1900 unsigned max_stack_entries;
1901 unsigned max_hw_contexts;
1902 unsigned max_gs_threads;
1903 unsigned sx_max_export_size;
1904 unsigned sx_max_export_pos_size;
1905 unsigned sx_max_export_smx_size;
1906 unsigned sq_num_cf_insts;
1907 unsigned sx_num_of_sets;
1908 unsigned sc_prim_fifo_size;
1909 unsigned sc_hiz_tile_fifo_size;
1910 unsigned sc_earlyz_tile_fifo_fize;
1911 unsigned tiling_nbanks;
1912 unsigned tiling_npipes;
1913 unsigned tiling_group_size;
1914 unsigned tile_config;
1915 unsigned backend_map;
1916 };
1917
1918 struct evergreen_asic {
1919 unsigned num_ses;
1920 unsigned max_pipes;
1921 unsigned max_tile_pipes;
1922 unsigned max_simds;
1923 unsigned max_backends;
1924 unsigned max_gprs;
1925 unsigned max_threads;
1926 unsigned max_stack_entries;
1927 unsigned max_hw_contexts;
1928 unsigned max_gs_threads;
1929 unsigned sx_max_export_size;
1930 unsigned sx_max_export_pos_size;
1931 unsigned sx_max_export_smx_size;
1932 unsigned sq_num_cf_insts;
1933 unsigned sx_num_of_sets;
1934 unsigned sc_prim_fifo_size;
1935 unsigned sc_hiz_tile_fifo_size;
1936 unsigned sc_earlyz_tile_fifo_size;
1937 unsigned tiling_nbanks;
1938 unsigned tiling_npipes;
1939 unsigned tiling_group_size;
1940 unsigned tile_config;
1941 unsigned backend_map;
1942 };
1943
1944 struct cayman_asic {
1945 unsigned max_shader_engines;
1946 unsigned max_pipes_per_simd;
1947 unsigned max_tile_pipes;
1948 unsigned max_simds_per_se;
1949 unsigned max_backends_per_se;
1950 unsigned max_texture_channel_caches;
1951 unsigned max_gprs;
1952 unsigned max_threads;
1953 unsigned max_gs_threads;
1954 unsigned max_stack_entries;
1955 unsigned sx_num_of_sets;
1956 unsigned sx_max_export_size;
1957 unsigned sx_max_export_pos_size;
1958 unsigned sx_max_export_smx_size;
1959 unsigned max_hw_contexts;
1960 unsigned sq_num_cf_insts;
1961 unsigned sc_prim_fifo_size;
1962 unsigned sc_hiz_tile_fifo_size;
1963 unsigned sc_earlyz_tile_fifo_size;
1964
1965 unsigned num_shader_engines;
1966 unsigned num_shader_pipes_per_simd;
1967 unsigned num_tile_pipes;
1968 unsigned num_simds_per_se;
1969 unsigned num_backends_per_se;
1970 unsigned backend_disable_mask_per_asic;
1971 unsigned backend_map;
1972 unsigned num_texture_channel_caches;
1973 unsigned mem_max_burst_length_bytes;
1974 unsigned mem_row_size_in_kb;
1975 unsigned shader_engine_tile_size;
1976 unsigned num_gpus;
1977 unsigned multi_gpu_tile_size;
1978
1979 unsigned tile_config;
1980 };
1981
1982 struct si_asic {
1983 unsigned max_shader_engines;
1984 unsigned max_tile_pipes;
1985 unsigned max_cu_per_sh;
1986 unsigned max_sh_per_se;
1987 unsigned max_backends_per_se;
1988 unsigned max_texture_channel_caches;
1989 unsigned max_gprs;
1990 unsigned max_gs_threads;
1991 unsigned max_hw_contexts;
1992 unsigned sc_prim_fifo_size_frontend;
1993 unsigned sc_prim_fifo_size_backend;
1994 unsigned sc_hiz_tile_fifo_size;
1995 unsigned sc_earlyz_tile_fifo_size;
1996
1997 unsigned num_tile_pipes;
1998 unsigned backend_enable_mask;
1999 unsigned backend_disable_mask_per_asic;
2000 unsigned backend_map;
2001 unsigned num_texture_channel_caches;
2002 unsigned mem_max_burst_length_bytes;
2003 unsigned mem_row_size_in_kb;
2004 unsigned shader_engine_tile_size;
2005 unsigned num_gpus;
2006 unsigned multi_gpu_tile_size;
2007
2008 unsigned tile_config;
2009 uint32_t tile_mode_array[32];
2010 };
2011
2012 struct cik_asic {
2013 unsigned max_shader_engines;
2014 unsigned max_tile_pipes;
2015 unsigned max_cu_per_sh;
2016 unsigned max_sh_per_se;
2017 unsigned max_backends_per_se;
2018 unsigned max_texture_channel_caches;
2019 unsigned max_gprs;
2020 unsigned max_gs_threads;
2021 unsigned max_hw_contexts;
2022 unsigned sc_prim_fifo_size_frontend;
2023 unsigned sc_prim_fifo_size_backend;
2024 unsigned sc_hiz_tile_fifo_size;
2025 unsigned sc_earlyz_tile_fifo_size;
2026
2027 unsigned num_tile_pipes;
2028 unsigned backend_enable_mask;
2029 unsigned backend_disable_mask_per_asic;
2030 unsigned backend_map;
2031 unsigned num_texture_channel_caches;
2032 unsigned mem_max_burst_length_bytes;
2033 unsigned mem_row_size_in_kb;
2034 unsigned shader_engine_tile_size;
2035 unsigned num_gpus;
2036 unsigned multi_gpu_tile_size;
2037
2038 unsigned tile_config;
2039 uint32_t tile_mode_array[32];
2040 uint32_t macrotile_mode_array[16];
2041 };
2042
2043 union radeon_asic_config {
2044 struct r300_asic r300;
2045 struct r100_asic r100;
2046 struct r600_asic r600;
2047 struct rv770_asic rv770;
2048 struct evergreen_asic evergreen;
2049 struct cayman_asic cayman;
2050 struct si_asic si;
2051 struct cik_asic cik;
2052 };
2053
2054 /*
2055 * asic initizalization from radeon_asic.c
2056 */
2057 void radeon_agp_disable(struct radeon_device *rdev);
2058 int radeon_asic_init(struct radeon_device *rdev);
2059
2060
2061 /*
2062 * IOCTL.
2063 */
2064 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2065 struct drm_file *filp);
2066 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2067 struct drm_file *filp);
2068 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2069 struct drm_file *file_priv);
2070 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2071 struct drm_file *file_priv);
2072 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2073 struct drm_file *file_priv);
2074 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2075 struct drm_file *file_priv);
2076 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2077 struct drm_file *filp);
2078 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2079 struct drm_file *filp);
2080 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2081 struct drm_file *filp);
2082 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2083 struct drm_file *filp);
2084 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2085 struct drm_file *filp);
2086 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2087 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2088 struct drm_file *filp);
2089 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2090 struct drm_file *filp);
2091
2092 /* VRAM scratch page for HDP bug, default vram page */
2093 struct r600_vram_scratch {
2094 struct radeon_bo *robj;
2095 volatile uint32_t *ptr;
2096 u64 gpu_addr;
2097 };
2098
2099 /*
2100 * ACPI
2101 */
2102 struct radeon_atif_notification_cfg {
2103 bool enabled;
2104 int command_code;
2105 };
2106
2107 struct radeon_atif_notifications {
2108 bool display_switch;
2109 bool expansion_mode_change;
2110 bool thermal_state;
2111 bool forced_power_state;
2112 bool system_power_state;
2113 bool display_conf_change;
2114 bool px_gfx_switch;
2115 bool brightness_change;
2116 bool dgpu_display_event;
2117 };
2118
2119 struct radeon_atif_functions {
2120 bool system_params;
2121 bool sbios_requests;
2122 bool select_active_disp;
2123 bool lid_state;
2124 bool get_tv_standard;
2125 bool set_tv_standard;
2126 bool get_panel_expansion_mode;
2127 bool set_panel_expansion_mode;
2128 bool temperature_change;
2129 bool graphics_device_types;
2130 };
2131
2132 struct radeon_atif {
2133 struct radeon_atif_notifications notifications;
2134 struct radeon_atif_functions functions;
2135 struct radeon_atif_notification_cfg notification_cfg;
2136 struct radeon_encoder *encoder_for_bl;
2137 };
2138
2139 struct radeon_atcs_functions {
2140 bool get_ext_state;
2141 bool pcie_perf_req;
2142 bool pcie_dev_rdy;
2143 bool pcie_bus_width;
2144 };
2145
2146 struct radeon_atcs {
2147 struct radeon_atcs_functions functions;
2148 };
2149
2150 /*
2151 * Core structure, functions and helpers.
2152 */
2153 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2154 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2155
2156 struct radeon_device {
2157 struct device *dev;
2158 struct drm_device *ddev;
2159 struct pci_dev *pdev;
2160 struct rw_semaphore exclusive_lock;
2161 /* ASIC */
2162 union radeon_asic_config config;
2163 enum radeon_family family;
2164 unsigned long flags;
2165 int usec_timeout;
2166 enum radeon_pll_errata pll_errata;
2167 int num_gb_pipes;
2168 int num_z_pipes;
2169 int disp_priority;
2170 /* BIOS */
2171 uint8_t *bios;
2172 bool is_atom_bios;
2173 uint16_t bios_header_start;
2174 struct radeon_bo *stollen_vga_memory;
2175 /* Register mmio */
2176 resource_size_t rmmio_base;
2177 resource_size_t rmmio_size;
2178 /* protects concurrent MM_INDEX/DATA based register access */
2179 spinlock_t mmio_idx_lock;
2180 /* protects concurrent SMC based register access */
2181 spinlock_t smc_idx_lock;
2182 /* protects concurrent PLL register access */
2183 spinlock_t pll_idx_lock;
2184 /* protects concurrent MC register access */
2185 spinlock_t mc_idx_lock;
2186 /* protects concurrent PCIE register access */
2187 spinlock_t pcie_idx_lock;
2188 /* protects concurrent PCIE_PORT register access */
2189 spinlock_t pciep_idx_lock;
2190 /* protects concurrent PIF register access */
2191 spinlock_t pif_idx_lock;
2192 /* protects concurrent CG register access */
2193 spinlock_t cg_idx_lock;
2194 /* protects concurrent UVD register access */
2195 spinlock_t uvd_idx_lock;
2196 /* protects concurrent RCU register access */
2197 spinlock_t rcu_idx_lock;
2198 /* protects concurrent DIDT register access */
2199 spinlock_t didt_idx_lock;
2200 /* protects concurrent ENDPOINT (audio) register access */
2201 spinlock_t end_idx_lock;
2202 void __iomem *rmmio;
2203 radeon_rreg_t mc_rreg;
2204 radeon_wreg_t mc_wreg;
2205 radeon_rreg_t pll_rreg;
2206 radeon_wreg_t pll_wreg;
2207 uint32_t pcie_reg_mask;
2208 radeon_rreg_t pciep_rreg;
2209 radeon_wreg_t pciep_wreg;
2210 /* io port */
2211 void __iomem *rio_mem;
2212 resource_size_t rio_mem_size;
2213 struct radeon_clock clock;
2214 struct radeon_mc mc;
2215 struct radeon_gart gart;
2216 struct radeon_mode_info mode_info;
2217 struct radeon_scratch scratch;
2218 struct radeon_doorbell doorbell;
2219 struct radeon_mman mman;
2220 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2221 wait_queue_head_t fence_queue;
2222 struct mutex ring_lock;
2223 struct radeon_ring ring[RADEON_NUM_RINGS];
2224 bool ib_pool_ready;
2225 struct radeon_sa_manager ring_tmp_bo;
2226 struct radeon_irq irq;
2227 struct radeon_asic *asic;
2228 struct radeon_gem gem;
2229 struct radeon_pm pm;
2230 struct radeon_uvd uvd;
2231 struct radeon_vce vce;
2232 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2233 struct radeon_wb wb;
2234 struct radeon_dummy_page dummy_page;
2235 bool shutdown;
2236 bool suspend;
2237 bool need_dma32;
2238 bool accel_working;
2239 bool fastfb_working; /* IGP feature*/
2240 bool needs_reset;
2241 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2242 const struct firmware *me_fw; /* all family ME firmware */
2243 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2244 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2245 const struct firmware *mc_fw; /* NI MC firmware */
2246 const struct firmware *ce_fw; /* SI CE firmware */
2247 const struct firmware *mec_fw; /* CIK MEC firmware */
2248 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2249 const struct firmware *smc_fw; /* SMC firmware */
2250 const struct firmware *uvd_fw; /* UVD firmware */
2251 const struct firmware *vce_fw; /* VCE firmware */
2252 struct r600_vram_scratch vram_scratch;
2253 int msi_enabled; /* msi enabled */
2254 struct r600_ih ih; /* r6/700 interrupt ring */
2255 struct radeon_rlc rlc;
2256 struct radeon_mec mec;
2257 struct work_struct hotplug_work;
2258 struct work_struct audio_work;
2259 struct work_struct reset_work;
2260 int num_crtc; /* number of crtcs */
2261 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2262 bool has_uvd;
2263 struct r600_audio audio; /* audio stuff */
2264 struct notifier_block acpi_nb;
2265 /* only one userspace can use Hyperz features or CMASK at a time */
2266 struct drm_file *hyperz_filp;
2267 struct drm_file *cmask_filp;
2268 /* i2c buses */
2269 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2270 /* debugfs */
2271 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2272 unsigned debugfs_count;
2273 /* virtual memory */
2274 struct radeon_vm_manager vm_manager;
2275 struct mutex gpu_clock_mutex;
2276 /* ACPI interface */
2277 struct radeon_atif atif;
2278 struct radeon_atcs atcs;
2279 /* srbm instance registers */
2280 struct mutex srbm_mutex;
2281 /* clock, powergating flags */
2282 u32 cg_flags;
2283 u32 pg_flags;
2284
2285 struct dev_pm_domain vga_pm_domain;
2286 bool have_disp_power_ref;
2287 };
2288
2289 int radeon_device_init(struct radeon_device *rdev,
2290 struct drm_device *ddev,
2291 struct pci_dev *pdev,
2292 uint32_t flags);
2293 void radeon_device_fini(struct radeon_device *rdev);
2294 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2295
2296 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2297 bool always_indirect);
2298 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2299 bool always_indirect);
2300 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2301 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2302
2303 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2304 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2305
2306 /*
2307 * Cast helper
2308 */
2309 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2310
2311 /*
2312 * Registers read & write functions.
2313 */
2314 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2315 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2316 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2317 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2318 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2319 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2320 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2321 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2322 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2323 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2324 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2325 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2326 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2327 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2328 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2329 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2330 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2331 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2332 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2333 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2334 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2335 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2336 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2337 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2338 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2339 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2340 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2341 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2342 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2343 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2344 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2345 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2346 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2347 #define WREG32_P(reg, val, mask) \
2348 do { \
2349 uint32_t tmp_ = RREG32(reg); \
2350 tmp_ &= (mask); \
2351 tmp_ |= ((val) & ~(mask)); \
2352 WREG32(reg, tmp_); \
2353 } while (0)
2354 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2355 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2356 #define WREG32_PLL_P(reg, val, mask) \
2357 do { \
2358 uint32_t tmp_ = RREG32_PLL(reg); \
2359 tmp_ &= (mask); \
2360 tmp_ |= ((val) & ~(mask)); \
2361 WREG32_PLL(reg, tmp_); \
2362 } while (0)
2363 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2364 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2365 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2366
2367 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2368 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2369
2370 /*
2371 * Indirect registers accessor
2372 */
2373 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2374 {
2375 unsigned long flags;
2376 uint32_t r;
2377
2378 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2379 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2380 r = RREG32(RADEON_PCIE_DATA);
2381 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2382 return r;
2383 }
2384
2385 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2386 {
2387 unsigned long flags;
2388
2389 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2390 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2391 WREG32(RADEON_PCIE_DATA, (v));
2392 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2393 }
2394
2395 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2396 {
2397 unsigned long flags;
2398 u32 r;
2399
2400 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2401 WREG32(TN_SMC_IND_INDEX_0, (reg));
2402 r = RREG32(TN_SMC_IND_DATA_0);
2403 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2404 return r;
2405 }
2406
2407 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2408 {
2409 unsigned long flags;
2410
2411 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2412 WREG32(TN_SMC_IND_INDEX_0, (reg));
2413 WREG32(TN_SMC_IND_DATA_0, (v));
2414 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2415 }
2416
2417 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2418 {
2419 unsigned long flags;
2420 u32 r;
2421
2422 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2423 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2424 r = RREG32(R600_RCU_DATA);
2425 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2426 return r;
2427 }
2428
2429 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2430 {
2431 unsigned long flags;
2432
2433 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2434 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2435 WREG32(R600_RCU_DATA, (v));
2436 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2437 }
2438
2439 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2440 {
2441 unsigned long flags;
2442 u32 r;
2443
2444 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2445 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2446 r = RREG32(EVERGREEN_CG_IND_DATA);
2447 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2448 return r;
2449 }
2450
2451 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2452 {
2453 unsigned long flags;
2454
2455 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2456 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2457 WREG32(EVERGREEN_CG_IND_DATA, (v));
2458 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2459 }
2460
2461 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2462 {
2463 unsigned long flags;
2464 u32 r;
2465
2466 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2467 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2468 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2469 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2470 return r;
2471 }
2472
2473 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2474 {
2475 unsigned long flags;
2476
2477 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2478 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2479 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2480 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2481 }
2482
2483 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2484 {
2485 unsigned long flags;
2486 u32 r;
2487
2488 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2489 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2490 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2491 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2492 return r;
2493 }
2494
2495 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2496 {
2497 unsigned long flags;
2498
2499 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2500 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2501 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2502 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2503 }
2504
2505 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2506 {
2507 unsigned long flags;
2508 u32 r;
2509
2510 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2511 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2512 r = RREG32(R600_UVD_CTX_DATA);
2513 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2514 return r;
2515 }
2516
2517 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2518 {
2519 unsigned long flags;
2520
2521 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2522 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2523 WREG32(R600_UVD_CTX_DATA, (v));
2524 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2525 }
2526
2527
2528 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2529 {
2530 unsigned long flags;
2531 u32 r;
2532
2533 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2534 WREG32(CIK_DIDT_IND_INDEX, (reg));
2535 r = RREG32(CIK_DIDT_IND_DATA);
2536 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2537 return r;
2538 }
2539
2540 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2541 {
2542 unsigned long flags;
2543
2544 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2545 WREG32(CIK_DIDT_IND_INDEX, (reg));
2546 WREG32(CIK_DIDT_IND_DATA, (v));
2547 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2548 }
2549
2550 void r100_pll_errata_after_index(struct radeon_device *rdev);
2551
2552
2553 /*
2554 * ASICs helpers.
2555 */
2556 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2557 (rdev->pdev->device == 0x5969))
2558 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2559 (rdev->family == CHIP_RV200) || \
2560 (rdev->family == CHIP_RS100) || \
2561 (rdev->family == CHIP_RS200) || \
2562 (rdev->family == CHIP_RV250) || \
2563 (rdev->family == CHIP_RV280) || \
2564 (rdev->family == CHIP_RS300))
2565 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2566 (rdev->family == CHIP_RV350) || \
2567 (rdev->family == CHIP_R350) || \
2568 (rdev->family == CHIP_RV380) || \
2569 (rdev->family == CHIP_R420) || \
2570 (rdev->family == CHIP_R423) || \
2571 (rdev->family == CHIP_RV410) || \
2572 (rdev->family == CHIP_RS400) || \
2573 (rdev->family == CHIP_RS480))
2574 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2575 (rdev->ddev->pdev->device == 0x9443) || \
2576 (rdev->ddev->pdev->device == 0x944B) || \
2577 (rdev->ddev->pdev->device == 0x9506) || \
2578 (rdev->ddev->pdev->device == 0x9509) || \
2579 (rdev->ddev->pdev->device == 0x950F) || \
2580 (rdev->ddev->pdev->device == 0x689C) || \
2581 (rdev->ddev->pdev->device == 0x689D))
2582 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2583 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2584 (rdev->family == CHIP_RS690) || \
2585 (rdev->family == CHIP_RS740) || \
2586 (rdev->family >= CHIP_R600))
2587 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2588 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2589 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2590 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2591 (rdev->flags & RADEON_IS_IGP))
2592 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2593 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2594 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2595 (rdev->flags & RADEON_IS_IGP))
2596 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2597 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2598 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2599
2600 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2601 (rdev->ddev->pdev->device == 0x6850) || \
2602 (rdev->ddev->pdev->device == 0x6858) || \
2603 (rdev->ddev->pdev->device == 0x6859) || \
2604 (rdev->ddev->pdev->device == 0x6840) || \
2605 (rdev->ddev->pdev->device == 0x6841) || \
2606 (rdev->ddev->pdev->device == 0x6842) || \
2607 (rdev->ddev->pdev->device == 0x6843))
2608
2609 /*
2610 * BIOS helpers.
2611 */
2612 #define RBIOS8(i) (rdev->bios[i])
2613 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2614 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2615
2616 int radeon_combios_init(struct radeon_device *rdev);
2617 void radeon_combios_fini(struct radeon_device *rdev);
2618 int radeon_atombios_init(struct radeon_device *rdev);
2619 void radeon_atombios_fini(struct radeon_device *rdev);
2620
2621
2622 /*
2623 * RING helpers.
2624 */
2625 #if DRM_DEBUG_CODE == 0
2626 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2627 {
2628 ring->ring[ring->wptr++] = v;
2629 ring->wptr &= ring->ptr_mask;
2630 ring->count_dw--;
2631 ring->ring_free_dw--;
2632 }
2633 #else
2634 /* With debugging this is just too big to inline */
2635 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2636 #endif
2637
2638 /*
2639 * ASICs macro.
2640 */
2641 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2642 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2643 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2644 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2645 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2646 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2647 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2648 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2649 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2650 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2651 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2652 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2653 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2654 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2655 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2656 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2657 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2658 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2659 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2660 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2661 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2662 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2663 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2664 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2665 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2666 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2667 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2668 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2669 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2670 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2671 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2672 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2673 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2674 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2675 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2676 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2677 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2678 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2679 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2680 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2681 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2682 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2683 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2684 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2685 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2686 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2687 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2688 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2689 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2690 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2691 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2692 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2693 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2694 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2695 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2696 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2697 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2698 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2699 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2700 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2701 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2702 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2703 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2704 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2705 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2706 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2707 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2708 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2709 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2710 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2711 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2712 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2713 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2714 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2715 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2716 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2717 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2718 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2719 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2720 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2721 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2722 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2723 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2724 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2725
2726 /* Common functions */
2727 /* AGP */
2728 extern int radeon_gpu_reset(struct radeon_device *rdev);
2729 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2730 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2731 extern void radeon_agp_disable(struct radeon_device *rdev);
2732 extern int radeon_modeset_init(struct radeon_device *rdev);
2733 extern void radeon_modeset_fini(struct radeon_device *rdev);
2734 extern bool radeon_card_posted(struct radeon_device *rdev);
2735 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2736 extern void radeon_update_display_priority(struct radeon_device *rdev);
2737 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2738 extern void radeon_scratch_init(struct radeon_device *rdev);
2739 extern void radeon_wb_fini(struct radeon_device *rdev);
2740 extern int radeon_wb_init(struct radeon_device *rdev);
2741 extern void radeon_wb_disable(struct radeon_device *rdev);
2742 extern void radeon_surface_init(struct radeon_device *rdev);
2743 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2744 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2745 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2746 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2747 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2748 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2749 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2750 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2751 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2752 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2753 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2754 const u32 *registers,
2755 const u32 array_size);
2756
2757 /*
2758 * vm
2759 */
2760 int radeon_vm_manager_init(struct radeon_device *rdev);
2761 void radeon_vm_manager_fini(struct radeon_device *rdev);
2762 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2763 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2764 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2765 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2766 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2767 struct radeon_vm *vm, int ring);
2768 void radeon_vm_fence(struct radeon_device *rdev,
2769 struct radeon_vm *vm,
2770 struct radeon_fence *fence);
2771 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2772 int radeon_vm_bo_update(struct radeon_device *rdev,
2773 struct radeon_vm *vm,
2774 struct radeon_bo *bo,
2775 struct ttm_mem_reg *mem);
2776 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2777 struct radeon_bo *bo);
2778 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2779 struct radeon_bo *bo);
2780 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2781 struct radeon_vm *vm,
2782 struct radeon_bo *bo);
2783 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2784 struct radeon_bo_va *bo_va,
2785 uint64_t offset,
2786 uint32_t flags);
2787 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2788 struct radeon_bo_va *bo_va);
2789
2790 /* audio */
2791 void r600_audio_update_hdmi(struct work_struct *work);
2792 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2793 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2794
2795 /*
2796 * R600 vram scratch functions
2797 */
2798 int r600_vram_scratch_init(struct radeon_device *rdev);
2799 void r600_vram_scratch_fini(struct radeon_device *rdev);
2800
2801 /*
2802 * r600 cs checking helper
2803 */
2804 unsigned r600_mip_minify(unsigned size, unsigned level);
2805 bool r600_fmt_is_valid_color(u32 format);
2806 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2807 int r600_fmt_get_blocksize(u32 format);
2808 int r600_fmt_get_nblocksx(u32 format, u32 w);
2809 int r600_fmt_get_nblocksy(u32 format, u32 h);
2810
2811 /*
2812 * r600 functions used by radeon_encoder.c
2813 */
2814 struct radeon_hdmi_acr {
2815 u32 clock;
2816
2817 int n_32khz;
2818 int cts_32khz;
2819
2820 int n_44_1khz;
2821 int cts_44_1khz;
2822
2823 int n_48khz;
2824 int cts_48khz;
2825
2826 };
2827
2828 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2829
2830 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2831 u32 tiling_pipe_num,
2832 u32 max_rb_num,
2833 u32 total_max_rb_num,
2834 u32 enabled_rb_mask);
2835
2836 /*
2837 * evergreen functions used by radeon_encoder.c
2838 */
2839
2840 extern int ni_init_microcode(struct radeon_device *rdev);
2841 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2842
2843 /* radeon_acpi.c */
2844 #if defined(CONFIG_ACPI)
2845 extern int radeon_acpi_init(struct radeon_device *rdev);
2846 extern void radeon_acpi_fini(struct radeon_device *rdev);
2847 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2848 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2849 u8 perf_req, bool advertise);
2850 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2851 #else
2852 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2853 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2854 #endif
2855
2856 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2857 struct radeon_cs_packet *pkt,
2858 unsigned idx);
2859 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2860 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2861 struct radeon_cs_packet *pkt);
2862 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2863 struct radeon_cs_reloc **cs_reloc,
2864 int nomm);
2865 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2866 uint32_t *vline_start_end,
2867 uint32_t *vline_status);
2868
2869 #include "radeon_object.h"
2870
2871 #endif
Linux kernel - Deliverables
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