drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <asm/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72
  73 #include "radeon_family.h"
  74 #include "radeon_mode.h"
  75 #include "radeon_reg.h"
  76
  77 /*
  78  * Modules parameters.
  79  */
  80 extern int radeon_no_wb;
  81 extern int radeon_modeset;
  82 extern int radeon_dynclks;
  83 extern int radeon_r4xx_atom;
  84 extern int radeon_agpmode;
  85 extern int radeon_vram_limit;
  86 extern int radeon_gart_size;
  87 extern int radeon_benchmarking;
  88 extern int radeon_testing;
  89 extern int radeon_connector_table;
  90 extern int radeon_tv;
  91
  92 /*
  93  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  94  * symbol;
  95  */
  96 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  97 #define RADEON_IB_POOL_SIZE             16
  98 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
  99 #define RADEONFB_CONN_LIMIT             4
 100 #define RADEON_BIOS_NUM_SCRATCH         8
 101
 102 /*
 103  * Errata workarounds.
 104  */
 105 enum radeon_pll_errata {
 106         CHIP_ERRATA_R300_CG             = 0x00000001,
 107         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 108         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 109 };
 110
 111
 112 struct radeon_device;
 113
 114
 115 /*
 116  * BIOS.
 117  */
 118 bool radeon_get_bios(struct radeon_device *rdev);
 119
 120
 121 /*
 122  * Dummy page
 123  */
 124 struct radeon_dummy_page {
 125         struct page     *page;
 126         dma_addr_t      addr;
 127 };
 128 int radeon_dummy_page_init(struct radeon_device *rdev);
 129 void radeon_dummy_page_fini(struct radeon_device *rdev);
 130
 131
 132 /*
 133  * Clocks
 134  */
 135 struct radeon_clock {
 136         struct radeon_pll p1pll;
 137         struct radeon_pll p2pll;
 138         struct radeon_pll spll;
 139         struct radeon_pll mpll;
 140         /* 10 Khz units */
 141         uint32_t default_mclk;
 142         uint32_t default_sclk;
 143 };
 144
 145 /*
 146  * Power management
 147  */
 148 int radeon_pm_init(struct radeon_device *rdev);
 149
 150 /*
 151  * Fences.
 152  */
 153 struct radeon_fence_driver {
 154         uint32_t                        scratch_reg;
 155         atomic_t                        seq;
 156         uint32_t                        last_seq;
 157         unsigned long                   count_timeout;
 158         wait_queue_head_t               queue;
 159         rwlock_t                        lock;
 160         struct list_head                created;
 161         struct list_head                emited;
 162         struct list_head                signaled;
 163 };
 164
 165 struct radeon_fence {
 166         struct radeon_device            *rdev;
 167         struct kref                     kref;
 168         struct list_head                list;
 169         /* protected by radeon_fence.lock */
 170         uint32_t                        seq;
 171         unsigned long                   timeout;
 172         bool                            emited;
 173         bool                            signaled;
 174 };
 175
 176 int radeon_fence_driver_init(struct radeon_device *rdev);
 177 void radeon_fence_driver_fini(struct radeon_device *rdev);
 178 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
 179 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 180 void radeon_fence_process(struct radeon_device *rdev);
 181 bool radeon_fence_signaled(struct radeon_fence *fence);
 182 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 183 int radeon_fence_wait_next(struct radeon_device *rdev);
 184 int radeon_fence_wait_last(struct radeon_device *rdev);
 185 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 186 void radeon_fence_unref(struct radeon_fence **fence);
 187
 188 /*
 189  * Tiling registers
 190  */
 191 struct radeon_surface_reg {
 192         struct radeon_bo *bo;
 193 };
 194
 195 #define RADEON_GEM_MAX_SURFACES 8
 196
 197 /*
 198  * TTM.
 199  */
 200 struct radeon_mman {
 201         struct ttm_bo_global_ref        bo_global_ref;
 202         struct ttm_global_reference     mem_global_ref;
 203         bool                            mem_global_referenced;
 204         struct ttm_bo_device            bdev;
 205 };
 206
 207 struct radeon_bo {
 208         /* Protected by gem.mutex */
 209         struct list_head                list;
 210         /* Protected by tbo.reserved */
 211         struct ttm_buffer_object        tbo;
 212         struct ttm_bo_kmap_obj          kmap;
 213         unsigned                        pin_count;
 214         void                            *kptr;
 215         u32                             tiling_flags;
 216         u32                             pitch;
 217         int                             surface_reg;
 218         /* Constant after initialization */
 219         struct radeon_device            *rdev;
 220         struct drm_gem_object           *gobj;
 221 };
 222
 223 struct radeon_bo_list {
 224         struct list_head        list;
 225         struct radeon_bo        *bo;
 226         uint64_t                gpu_offset;
 227         unsigned                rdomain;
 228         unsigned                wdomain;
 229         u32                     tiling_flags;
 230 };
 231
 232 /*
 233  * GEM objects.
 234  */
 235 struct radeon_gem {
 236         struct mutex            mutex;
 237         struct list_head        objects;
 238 };
 239
 240 int radeon_gem_init(struct radeon_device *rdev);
 241 void radeon_gem_fini(struct radeon_device *rdev);
 242 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 243                                 int alignment, int initial_domain,
 244                                 bool discardable, bool kernel,
 245                                 struct drm_gem_object **obj);
 246 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 247                           uint64_t *gpu_addr);
 248 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 249
 250
 251 /*
 252  * GART structures, functions & helpers
 253  */
 254 struct radeon_mc;
 255
 256 struct radeon_gart_table_ram {
 257         volatile uint32_t               *ptr;
 258 };
 259
 260 struct radeon_gart_table_vram {
 261         struct radeon_bo                *robj;
 262         volatile uint32_t               *ptr;
 263 };
 264
 265 union radeon_gart_table {
 266         struct radeon_gart_table_ram    ram;
 267         struct radeon_gart_table_vram   vram;
 268 };
 269
 270 #define RADEON_GPU_PAGE_SIZE 4096
 271
 272 struct radeon_gart {
 273         dma_addr_t                      table_addr;
 274         unsigned                        num_gpu_pages;
 275         unsigned                        num_cpu_pages;
 276         unsigned                        table_size;
 277         union radeon_gart_table         table;
 278         struct page                     **pages;
 279         dma_addr_t                      *pages_addr;
 280         bool                            ready;
 281 };
 282
 283 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 284 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 285 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 286 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 287 int radeon_gart_init(struct radeon_device *rdev);
 288 void radeon_gart_fini(struct radeon_device *rdev);
 289 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 290                         int pages);
 291 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 292                      int pages, struct page **pagelist);
 293
 294
 295 /*
 296  * GPU MC structures, functions & helpers
 297  */
 298 struct radeon_mc {
 299         resource_size_t         aper_size;
 300         resource_size_t         aper_base;
 301         resource_size_t         agp_base;
 302         /* for some chips with <= 32MB we need to lie
 303          * about vram size near mc fb location */
 304         u64                     mc_vram_size;
 305         u64                     gtt_location;
 306         u64                     gtt_size;
 307         u64                     gtt_start;
 308         u64                     gtt_end;
 309         u64                     vram_location;
 310         u64                     vram_start;
 311         u64                     vram_end;
 312         unsigned                vram_width;
 313         u64                     real_vram_size;
 314         int                     vram_mtrr;
 315         bool                    vram_is_ddr;
 316 };
 317
 318 int radeon_mc_setup(struct radeon_device *rdev);
 319
 320
 321 /*
 322  * GPU scratch registers structures, functions & helpers
 323  */
 324 struct radeon_scratch {
 325         unsigned                num_reg;
 326         bool                    free[32];
 327         uint32_t                reg[32];
 328 };
 329
 330 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 331 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 332
 333
 334 /*
 335  * IRQS.
 336  */
 337 struct radeon_irq {
 338         bool            installed;
 339         bool            sw_int;
 340         /* FIXME: use a define max crtc rather than hardcode it */
 341         bool            crtc_vblank_int[2];
 342         /* FIXME: use defines for max hpd/dacs */
 343         bool            hpd[6];
 344         spinlock_t sw_lock;
 345         int sw_refcount;
 346 };
 347
 348 int radeon_irq_kms_init(struct radeon_device *rdev);
 349 void radeon_irq_kms_fini(struct radeon_device *rdev);
 350 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
 351 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
 352
 353 /*
 354  * CP & ring.
 355  */
 356 struct radeon_ib {
 357         struct list_head        list;
 358         unsigned long           idx;
 359         uint64_t                gpu_addr;
 360         struct radeon_fence     *fence;
 361         uint32_t        *ptr;
 362         uint32_t                length_dw;
 363 };
 364
 365 /*
 366  * locking -
 367  * mutex protects scheduled_ibs, ready, alloc_bm
 368  */
 369 struct radeon_ib_pool {
 370         struct mutex            mutex;
 371         struct radeon_bo        *robj;
 372         struct list_head        scheduled_ibs;
 373         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
 374         bool                    ready;
 375         DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
 376 };
 377
 378 struct radeon_cp {
 379         struct radeon_bo        *ring_obj;
 380         volatile uint32_t       *ring;
 381         unsigned                rptr;
 382         unsigned                wptr;
 383         unsigned                wptr_old;
 384         unsigned                ring_size;
 385         unsigned                ring_free_dw;
 386         int                     count_dw;
 387         uint64_t                gpu_addr;
 388         uint32_t                align_mask;
 389         uint32_t                ptr_mask;
 390         struct mutex            mutex;
 391         bool                    ready;
 392 };
 393
 394 /*
 395  * R6xx+ IH ring
 396  */
 397 struct r600_ih {
 398         struct radeon_bo        *ring_obj;
 399         volatile uint32_t       *ring;
 400         unsigned                rptr;
 401         unsigned                wptr;
 402         unsigned                wptr_old;
 403         unsigned                ring_size;
 404         uint64_t                gpu_addr;
 405         uint32_t                align_mask;
 406         uint32_t                ptr_mask;
 407         spinlock_t              lock;
 408         bool                    enabled;
 409 };
 410
 411 struct r600_blit {
 412         struct radeon_bo        *shader_obj;
 413         u64 shader_gpu_addr;
 414         u32 vs_offset, ps_offset;
 415         u32 state_offset;
 416         u32 state_len;
 417         u32 vb_used, vb_total;
 418         struct radeon_ib *vb_ib;
 419 };
 420
 421 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
 422 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 423 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 424 int radeon_ib_pool_init(struct radeon_device *rdev);
 425 void radeon_ib_pool_fini(struct radeon_device *rdev);
 426 int radeon_ib_test(struct radeon_device *rdev);
 427 /* Ring access between begin & end cannot sleep */
 428 void radeon_ring_free_size(struct radeon_device *rdev);
 429 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
 430 void radeon_ring_unlock_commit(struct radeon_device *rdev);
 431 void radeon_ring_unlock_undo(struct radeon_device *rdev);
 432 int radeon_ring_test(struct radeon_device *rdev);
 433 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
 434 void radeon_ring_fini(struct radeon_device *rdev);
 435
 436
 437 /*
 438  * CS.
 439  */
 440 struct radeon_cs_reloc {
 441         struct drm_gem_object           *gobj;
 442         struct radeon_bo                *robj;
 443         struct radeon_bo_list           lobj;
 444         uint32_t                        handle;
 445         uint32_t                        flags;
 446 };
 447
 448 struct radeon_cs_chunk {
 449         uint32_t                chunk_id;
 450         uint32_t                length_dw;
 451         int kpage_idx[2];
 452         uint32_t                *kpage[2];
 453         uint32_t                *kdata;
 454         void __user *user_ptr;
 455         int last_copied_page;
 456         int last_page_index;
 457 };
 458
 459 struct radeon_cs_parser {
 460         struct radeon_device    *rdev;
 461         struct drm_file         *filp;
 462         /* chunks */
 463         unsigned                nchunks;
 464         struct radeon_cs_chunk  *chunks;
 465         uint64_t                *chunks_array;
 466         /* IB */
 467         unsigned                idx;
 468         /* relocations */
 469         unsigned                nrelocs;
 470         struct radeon_cs_reloc  *relocs;
 471         struct radeon_cs_reloc  **relocs_ptr;
 472         struct list_head        validated;
 473         /* indices of various chunks */
 474         int                     chunk_ib_idx;
 475         int                     chunk_relocs_idx;
 476         struct radeon_ib        *ib;
 477         void                    *track;
 478         unsigned                family;
 479         int parser_error;
 480 };
 481
 482 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
 483 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 484
 485
 486 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
 487 {
 488         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 489         u32 pg_idx, pg_offset;
 490         u32 idx_value = 0;
 491         int new_page;
 492
 493         pg_idx = (idx * 4) / PAGE_SIZE;
 494         pg_offset = (idx * 4) % PAGE_SIZE;
 495
 496         if (ibc->kpage_idx[0] == pg_idx)
 497                 return ibc->kpage[0][pg_offset/4];
 498         if (ibc->kpage_idx[1] == pg_idx)
 499                 return ibc->kpage[1][pg_offset/4];
 500
 501         new_page = radeon_cs_update_pages(p, pg_idx);
 502         if (new_page < 0) {
 503                 p->parser_error = new_page;
 504                 return 0;
 505         }
 506
 507         idx_value = ibc->kpage[new_page][pg_offset/4];
 508         return idx_value;
 509 }
 510
 511 struct radeon_cs_packet {
 512         unsigned        idx;
 513         unsigned        type;
 514         unsigned        reg;
 515         unsigned        opcode;
 516         int             count;
 517         unsigned        one_reg_wr;
 518 };
 519
 520 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 521                                       struct radeon_cs_packet *pkt,
 522                                       unsigned idx, unsigned reg);
 523 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 524                                       struct radeon_cs_packet *pkt);
 525
 526
 527 /*
 528  * AGP
 529  */
 530 int radeon_agp_init(struct radeon_device *rdev);
 531 void radeon_agp_resume(struct radeon_device *rdev);
 532 void radeon_agp_fini(struct radeon_device *rdev);
 533
 534
 535 /*
 536  * Writeback
 537  */
 538 struct radeon_wb {
 539         struct radeon_bo        *wb_obj;
 540         volatile uint32_t       *wb;
 541         uint64_t                gpu_addr;
 542 };
 543
 544 /**
 545  * struct radeon_pm - power management datas
 546  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 547  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 548  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 549  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 550  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 551  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 552  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 553  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 554  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 555  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
 556  * @needed_bandwidth:   current bandwidth needs
 557  *
 558  * It keeps track of various data needed to take powermanagement decision.
 559  * Bandwith need is used to determine minimun clock of the GPU and memory.
 560  * Equation between gpu/memory clock and available bandwidth is hw dependent
 561  * (type of memory, bus size, efficiency, ...)
 562  */
 563 struct radeon_pm {
 564         fixed20_12              max_bandwidth;
 565         fixed20_12              igp_sideport_mclk;
 566         fixed20_12              igp_system_mclk;
 567         fixed20_12              igp_ht_link_clk;
 568         fixed20_12              igp_ht_link_width;
 569         fixed20_12              k8_bandwidth;
 570         fixed20_12              sideport_bandwidth;
 571         fixed20_12              ht_bandwidth;
 572         fixed20_12              core_bandwidth;
 573         fixed20_12              sclk;
 574         fixed20_12              needed_bandwidth;
 575 };
 576
 577
 578 /*
 579  * Benchmarking
 580  */
 581 void radeon_benchmark(struct radeon_device *rdev);
 582
 583
 584 /*
 585  * Testing
 586  */
 587 void radeon_test_moves(struct radeon_device *rdev);
 588
 589
 590 /*
 591  * Debugfs
 592  */
 593 int radeon_debugfs_add_files(struct radeon_device *rdev,
 594                              struct drm_info_list *files,
 595                              unsigned nfiles);
 596 int radeon_debugfs_fence_init(struct radeon_device *rdev);
 597 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
 598 int r100_debugfs_cp_init(struct radeon_device *rdev);
 599
 600
 601 /*
 602  * ASIC specific functions.
 603  */
 604 struct radeon_asic {
 605         int (*init)(struct radeon_device *rdev);
 606         void (*fini)(struct radeon_device *rdev);
 607         int (*resume)(struct radeon_device *rdev);
 608         int (*suspend)(struct radeon_device *rdev);
 609         void (*vga_set_state)(struct radeon_device *rdev, bool state);
 610         int (*gpu_reset)(struct radeon_device *rdev);
 611         void (*gart_tlb_flush)(struct radeon_device *rdev);
 612         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
 613         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
 614         void (*cp_fini)(struct radeon_device *rdev);
 615         void (*cp_disable)(struct radeon_device *rdev);
 616         void (*cp_commit)(struct radeon_device *rdev);
 617         void (*ring_start)(struct radeon_device *rdev);
 618         int (*ring_test)(struct radeon_device *rdev);
 619         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
 620         int (*irq_set)(struct radeon_device *rdev);
 621         int (*irq_process)(struct radeon_device *rdev);
 622         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
 623         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
 624         int (*cs_parse)(struct radeon_cs_parser *p);
 625         int (*copy_blit)(struct radeon_device *rdev,
 626                          uint64_t src_offset,
 627                          uint64_t dst_offset,
 628                          unsigned num_pages,
 629                          struct radeon_fence *fence);
 630         int (*copy_dma)(struct radeon_device *rdev,
 631                         uint64_t src_offset,
 632                         uint64_t dst_offset,
 633                         unsigned num_pages,
 634                         struct radeon_fence *fence);
 635         int (*copy)(struct radeon_device *rdev,
 636                     uint64_t src_offset,
 637                     uint64_t dst_offset,
 638                     unsigned num_pages,
 639                     struct radeon_fence *fence);
 640         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
 641         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
 642         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
 643         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
 644         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
 645         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
 646         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
 647                                uint32_t tiling_flags, uint32_t pitch,
 648                                uint32_t offset, uint32_t obj_size);
 649         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
 650         void (*bandwidth_update)(struct radeon_device *rdev);
 651         void (*hdp_flush)(struct radeon_device *rdev);
 652         void (*hpd_init)(struct radeon_device *rdev);
 653         void (*hpd_fini)(struct radeon_device *rdev);
 654         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 655         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 656 };
 657
 658 /*
 659  * Asic structures
 660  */
 661 struct r100_asic {
 662         const unsigned  *reg_safe_bm;
 663         unsigned        reg_safe_bm_size;
 664 };
 665
 666 struct r300_asic {
 667         const unsigned  *reg_safe_bm;
 668         unsigned        reg_safe_bm_size;
 669 };
 670
 671 struct r600_asic {
 672         unsigned max_pipes;
 673         unsigned max_tile_pipes;
 674         unsigned max_simds;
 675         unsigned max_backends;
 676         unsigned max_gprs;
 677         unsigned max_threads;
 678         unsigned max_stack_entries;
 679         unsigned max_hw_contexts;
 680         unsigned max_gs_threads;
 681         unsigned sx_max_export_size;
 682         unsigned sx_max_export_pos_size;
 683         unsigned sx_max_export_smx_size;
 684         unsigned sq_num_cf_insts;
 685 };
 686
 687 struct rv770_asic {
 688         unsigned max_pipes;
 689         unsigned max_tile_pipes;
 690         unsigned max_simds;
 691         unsigned max_backends;
 692         unsigned max_gprs;
 693         unsigned max_threads;
 694         unsigned max_stack_entries;
 695         unsigned max_hw_contexts;
 696         unsigned max_gs_threads;
 697         unsigned sx_max_export_size;
 698         unsigned sx_max_export_pos_size;
 699         unsigned sx_max_export_smx_size;
 700         unsigned sq_num_cf_insts;
 701         unsigned sx_num_of_sets;
 702         unsigned sc_prim_fifo_size;
 703         unsigned sc_hiz_tile_fifo_size;
 704         unsigned sc_earlyz_tile_fifo_fize;
 705 };
 706
 707 union radeon_asic_config {
 708         struct r300_asic        r300;
 709         struct r100_asic        r100;
 710         struct r600_asic        r600;
 711         struct rv770_asic       rv770;
 712 };
 713
 714
 715 /*
 716  * IOCTL.
 717  */
 718 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
 719                           struct drm_file *filp);
 720 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
 721                             struct drm_file *filp);
 722 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
 723                          struct drm_file *file_priv);
 724 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
 725                            struct drm_file *file_priv);
 726 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 727                             struct drm_file *file_priv);
 728 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
 729                            struct drm_file *file_priv);
 730 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 731                                 struct drm_file *filp);
 732 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
 733                           struct drm_file *filp);
 734 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
 735                           struct drm_file *filp);
 736 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 737                               struct drm_file *filp);
 738 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 739 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
 740                                 struct drm_file *filp);
 741 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
 742                                 struct drm_file *filp);
 743
 744
 745 /*
 746  * Core structure, functions and helpers.
 747  */
 748 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
 749 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
 750
 751 struct radeon_device {
 752         struct device                   *dev;
 753         struct drm_device               *ddev;
 754         struct pci_dev                  *pdev;
 755         /* ASIC */
 756         union radeon_asic_config        config;
 757         enum radeon_family              family;
 758         unsigned long                   flags;
 759         int                             usec_timeout;
 760         enum radeon_pll_errata          pll_errata;
 761         int                             num_gb_pipes;
 762         int                             num_z_pipes;
 763         int                             disp_priority;
 764         /* BIOS */
 765         uint8_t                         *bios;
 766         bool                            is_atom_bios;
 767         uint16_t                        bios_header_start;
 768         struct radeon_bo                *stollen_vga_memory;
 769         struct fb_info                  *fbdev_info;
 770         struct radeon_bo                *fbdev_rbo;
 771         struct radeon_framebuffer       *fbdev_rfb;
 772         /* Register mmio */
 773         resource_size_t                 rmmio_base;
 774         resource_size_t                 rmmio_size;
 775         void                            *rmmio;
 776         radeon_rreg_t                   mc_rreg;
 777         radeon_wreg_t                   mc_wreg;
 778         radeon_rreg_t                   pll_rreg;
 779         radeon_wreg_t                   pll_wreg;
 780         uint32_t                        pcie_reg_mask;
 781         radeon_rreg_t                   pciep_rreg;
 782         radeon_wreg_t                   pciep_wreg;
 783         struct radeon_clock             clock;
 784         struct radeon_mc                mc;
 785         struct radeon_gart              gart;
 786         struct radeon_mode_info         mode_info;
 787         struct radeon_scratch           scratch;
 788         struct radeon_mman              mman;
 789         struct radeon_fence_driver      fence_drv;
 790         struct radeon_cp                cp;
 791         struct radeon_ib_pool           ib_pool;
 792         struct radeon_irq               irq;
 793         struct radeon_asic              *asic;
 794         struct radeon_gem               gem;
 795         struct radeon_pm                pm;
 796         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
 797         struct mutex                    cs_mutex;
 798         struct radeon_wb                wb;
 799         struct radeon_dummy_page        dummy_page;
 800         bool                            gpu_lockup;
 801         bool                            shutdown;
 802         bool                            suspend;
 803         bool                            need_dma32;
 804         bool                            accel_working;
 805         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
 806         const struct firmware *me_fw;   /* all family ME firmware */
 807         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
 808         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
 809         struct r600_blit r600_blit;
 810         int msi_enabled; /* msi enabled */
 811         struct r600_ih ih; /* r6/700 interrupt ring */
 812         struct workqueue_struct *wq;
 813         struct work_struct hotplug_work;
 814 };
 815
 816 int radeon_device_init(struct radeon_device *rdev,
 817                        struct drm_device *ddev,
 818                        struct pci_dev *pdev,
 819                        uint32_t flags);
 820 void radeon_device_fini(struct radeon_device *rdev);
 821 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
 822
 823 /* r600 blit */
 824 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
 825 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
 826 void r600_kms_blit_copy(struct radeon_device *rdev,
 827                         u64 src_gpu_addr, u64 dst_gpu_addr,
 828                         int size_bytes);
 829
 830 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
 831 {
 832         if (reg < 0x10000)
 833                 return readl(((void __iomem *)rdev->rmmio) + reg);
 834         else {
 835                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 836                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 837         }
 838 }
 839
 840 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 841 {
 842         if (reg < 0x10000)
 843                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
 844         else {
 845                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 846                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 847         }
 848 }
 849
 850 /*
 851  * Cast helper
 852  */
 853 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
 854
 855 /*
 856  * Registers read & write functions.
 857  */
 858 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
 859 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
 860 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
 861 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
 862 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
 863 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 864 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 865 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
 866 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
 867 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
 868 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
 869 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
 870 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
 871 #define WREG32_P(reg, val, mask)                                \
 872         do {                                                    \
 873                 uint32_t tmp_ = RREG32(reg);                    \
 874                 tmp_ &= (mask);                                 \
 875                 tmp_ |= ((val) & ~(mask));                      \
 876                 WREG32(reg, tmp_);                              \
 877         } while (0)
 878 #define WREG32_PLL_P(reg, val, mask)                            \
 879         do {                                                    \
 880                 uint32_t tmp_ = RREG32_PLL(reg);                \
 881                 tmp_ &= (mask);                                 \
 882                 tmp_ |= ((val) & ~(mask));                      \
 883                 WREG32_PLL(reg, tmp_);                          \
 884         } while (0)
 885 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
 886
 887 /*
 888  * Indirect registers accessor
 889  */
 890 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
 891 {
 892         uint32_t r;
 893
 894         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 895         r = RREG32(RADEON_PCIE_DATA);
 896         return r;
 897 }
 898
 899 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 900 {
 901         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 902         WREG32(RADEON_PCIE_DATA, (v));
 903 }
 904
 905 void r100_pll_errata_after_index(struct radeon_device *rdev);
 906
 907
 908 /*
 909  * ASICs helpers.
 910  */
 911 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
 912                             (rdev->pdev->device == 0x5969))
 913 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
 914                 (rdev->family == CHIP_RV200) || \
 915                 (rdev->family == CHIP_RS100) || \
 916                 (rdev->family == CHIP_RS200) || \
 917                 (rdev->family == CHIP_RV250) || \
 918                 (rdev->family == CHIP_RV280) || \
 919                 (rdev->family == CHIP_RS300))
 920 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
 921                 (rdev->family == CHIP_RV350) ||                 \
 922                 (rdev->family == CHIP_R350)  ||                 \
 923                 (rdev->family == CHIP_RV380) ||                 \
 924                 (rdev->family == CHIP_R420)  ||                 \
 925                 (rdev->family == CHIP_R423)  ||                 \
 926                 (rdev->family == CHIP_RV410) ||                 \
 927                 (rdev->family == CHIP_RS400) ||                 \
 928                 (rdev->family == CHIP_RS480))
 929 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
 930 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
 931 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
 932
 933
 934 /*
 935  * BIOS helpers.
 936  */
 937 #define RBIOS8(i) (rdev->bios[i])
 938 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
 939 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
 940
 941 int radeon_combios_init(struct radeon_device *rdev);
 942 void radeon_combios_fini(struct radeon_device *rdev);
 943 int radeon_atombios_init(struct radeon_device *rdev);
 944 void radeon_atombios_fini(struct radeon_device *rdev);
 945
 946
 947 /*
 948  * RING helpers.
 949  */
 950 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 951 {
 952 #if DRM_DEBUG_CODE
 953         if (rdev->cp.count_dw <= 0) {
 954                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
 955         }
 956 #endif
 957         rdev->cp.ring[rdev->cp.wptr++] = v;
 958         rdev->cp.wptr &= rdev->cp.ptr_mask;
 959         rdev->cp.count_dw--;
 960         rdev->cp.ring_free_dw--;
 961 }
 962
 963
 964 /*
 965  * ASICs macro.
 966  */
 967 #define radeon_init(rdev) (rdev)->asic->init((rdev))
 968 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
 969 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
 970 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
 971 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
 972 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
 973 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
 974 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
 975 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
 976 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
 977 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
 978 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
 979 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
 980 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
 981 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
 982 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
 983 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
 984 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
 985 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
 986 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
 987 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
 988 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
 989 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
 990 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
 991 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
 992 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
 993 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
 994 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
 995 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
 996 #define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
 997 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
 998 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
 999 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1000 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1001
1002 /* Common functions */
1003 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1004 extern int radeon_modeset_init(struct radeon_device *rdev);
1005 extern void radeon_modeset_fini(struct radeon_device *rdev);
1006 extern bool radeon_card_posted(struct radeon_device *rdev);
1007 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1008 extern int radeon_clocks_init(struct radeon_device *rdev);
1009 extern void radeon_clocks_fini(struct radeon_device *rdev);
1010 extern void radeon_scratch_init(struct radeon_device *rdev);
1011 extern void radeon_surface_init(struct radeon_device *rdev);
1012 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1013 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1014 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1015
1016 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1017 struct r100_mc_save {
1018         u32     GENMO_WT;
1019         u32     CRTC_EXT_CNTL;
1020         u32     CRTC_GEN_CNTL;
1021         u32     CRTC2_GEN_CNTL;
1022         u32     CUR_OFFSET;
1023         u32     CUR2_OFFSET;
1024 };
1025 extern void r100_cp_disable(struct radeon_device *rdev);
1026 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1027 extern void r100_cp_fini(struct radeon_device *rdev);
1028 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1029 extern int r100_pci_gart_init(struct radeon_device *rdev);
1030 extern void r100_pci_gart_fini(struct radeon_device *rdev);
1031 extern int r100_pci_gart_enable(struct radeon_device *rdev);
1032 extern void r100_pci_gart_disable(struct radeon_device *rdev);
1033 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1034 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1035 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1036 extern void r100_ib_fini(struct radeon_device *rdev);
1037 extern int r100_ib_init(struct radeon_device *rdev);
1038 extern void r100_irq_disable(struct radeon_device *rdev);
1039 extern int r100_irq_set(struct radeon_device *rdev);
1040 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1041 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1042 extern void r100_vram_init_sizes(struct radeon_device *rdev);
1043 extern void r100_wb_disable(struct radeon_device *rdev);
1044 extern void r100_wb_fini(struct radeon_device *rdev);
1045 extern int r100_wb_init(struct radeon_device *rdev);
1046 extern void r100_hdp_reset(struct radeon_device *rdev);
1047 extern int r100_rb2d_reset(struct radeon_device *rdev);
1048 extern int r100_cp_reset(struct radeon_device *rdev);
1049 extern void r100_vga_render_disable(struct radeon_device *rdev);
1050 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1051                                                 struct radeon_cs_packet *pkt,
1052                                                 struct radeon_bo *robj);
1053 extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1054                                 struct radeon_cs_packet *pkt,
1055                                 const unsigned *auth, unsigned n,
1056                                 radeon_packet0_check_t check);
1057 extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1058                                 struct radeon_cs_packet *pkt,
1059                                 unsigned idx);
1060 extern void r100_enable_bm(struct radeon_device *rdev);
1061 extern void r100_set_common_regs(struct radeon_device *rdev);
1062
1063 /* rv200,rv250,rv280 */
1064 extern void r200_set_safe_registers(struct radeon_device *rdev);
1065
1066 /* r300,r350,rv350,rv370,rv380 */
1067 extern void r300_set_reg_safe(struct radeon_device *rdev);
1068 extern void r300_mc_program(struct radeon_device *rdev);
1069 extern void r300_vram_info(struct radeon_device *rdev);
1070 extern void r300_clock_startup(struct radeon_device *rdev);
1071 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1072 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1073 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1074 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1075 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1076
1077 /* r420,r423,rv410 */
1078 extern int r420_mc_init(struct radeon_device *rdev);
1079 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1080 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1081 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1082 extern void r420_pipes_init(struct radeon_device *rdev);
1083
1084 /* rv515 */
1085 struct rv515_mc_save {
1086         u32 d1vga_control;
1087         u32 d2vga_control;
1088         u32 vga_render_control;
1089         u32 vga_hdp_control;
1090         u32 d1crtc_control;
1091         u32 d2crtc_control;
1092 };
1093 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1094 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1095 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1096 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1097 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1098 extern void rv515_clock_startup(struct radeon_device *rdev);
1099 extern void rv515_debugfs(struct radeon_device *rdev);
1100 extern int rv515_suspend(struct radeon_device *rdev);
1101
1102 /* rs400 */
1103 extern int rs400_gart_init(struct radeon_device *rdev);
1104 extern int rs400_gart_enable(struct radeon_device *rdev);
1105 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1106 extern void rs400_gart_disable(struct radeon_device *rdev);
1107 extern void rs400_gart_fini(struct radeon_device *rdev);
1108
1109 /* rs600 */
1110 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1111 extern int rs600_irq_set(struct radeon_device *rdev);
1112 extern void rs600_irq_disable(struct radeon_device *rdev);
1113
1114 /* rs690, rs740 */
1115 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1116                                         struct drm_display_mode *mode1,
1117                                         struct drm_display_mode *mode2);
1118
1119 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1120 extern bool r600_card_posted(struct radeon_device *rdev);
1121 extern void r600_cp_stop(struct radeon_device *rdev);
1122 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1123 extern int r600_cp_resume(struct radeon_device *rdev);
1124 extern int r600_count_pipe_bits(uint32_t val);
1125 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1126 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1127 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1128 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1129 extern int r600_ib_test(struct radeon_device *rdev);
1130 extern int r600_ring_test(struct radeon_device *rdev);
1131 extern void r600_wb_fini(struct radeon_device *rdev);
1132 extern int r600_wb_enable(struct radeon_device *rdev);
1133 extern void r600_wb_disable(struct radeon_device *rdev);
1134 extern void r600_scratch_init(struct radeon_device *rdev);
1135 extern int r600_blit_init(struct radeon_device *rdev);
1136 extern void r600_blit_fini(struct radeon_device *rdev);
1137 extern int r600_init_microcode(struct radeon_device *rdev);
1138 extern int r600_gpu_reset(struct radeon_device *rdev);
1139 /* r600 irq */
1140 extern int r600_irq_init(struct radeon_device *rdev);
1141 extern void r600_irq_fini(struct radeon_device *rdev);
1142 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1143 extern int r600_irq_set(struct radeon_device *rdev);
1144
1145 #include "radeon_object.h"
1146
1147 #endif