drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <asm/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72
  73 #include "radeon_family.h"
  74 #include "radeon_mode.h"
  75 #include "radeon_reg.h"
  76
  77 /*
  78  * Modules parameters.
  79  */
  80 extern int radeon_no_wb;
  81 extern int radeon_modeset;
  82 extern int radeon_dynclks;
  83 extern int radeon_r4xx_atom;
  84 extern int radeon_agpmode;
  85 extern int radeon_vram_limit;
  86 extern int radeon_gart_size;
  87 extern int radeon_benchmarking;
  88 extern int radeon_testing;
  89 extern int radeon_connector_table;
  90 extern int radeon_tv;
  91 extern int radeon_new_pll;
  92 extern int radeon_dynpm;
  93 extern int radeon_audio;
  94
  95 /*
  96  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  97  * symbol;
  98  */
  99 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
 100 #define RADEON_IB_POOL_SIZE             16
 101 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
 102 #define RADEONFB_CONN_LIMIT             4
 103 #define RADEON_BIOS_NUM_SCRATCH         8
 104
 105 /*
 106  * Errata workarounds.
 107  */
 108 enum radeon_pll_errata {
 109         CHIP_ERRATA_R300_CG             = 0x00000001,
 110         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 111         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 112 };
 113
 114
 115 struct radeon_device;
 116
 117
 118 /*
 119  * BIOS.
 120  */
 121 bool radeon_get_bios(struct radeon_device *rdev);
 122
 123
 124 /*
 125  * Dummy page
 126  */
 127 struct radeon_dummy_page {
 128         struct page     *page;
 129         dma_addr_t      addr;
 130 };
 131 int radeon_dummy_page_init(struct radeon_device *rdev);
 132 void radeon_dummy_page_fini(struct radeon_device *rdev);
 133
 134
 135 /*
 136  * Clocks
 137  */
 138 struct radeon_clock {
 139         struct radeon_pll p1pll;
 140         struct radeon_pll p2pll;
 141         struct radeon_pll dcpll;
 142         struct radeon_pll spll;
 143         struct radeon_pll mpll;
 144         /* 10 Khz units */
 145         uint32_t default_mclk;
 146         uint32_t default_sclk;
 147         uint32_t default_dispclk;
 148         uint32_t dp_extclk;
 149 };
 150
 151 /*
 152  * Power management
 153  */
 154 int radeon_pm_init(struct radeon_device *rdev);
 155 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 156 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 157 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 158
 159 /*
 160  * Fences.
 161  */
 162 struct radeon_fence_driver {
 163         uint32_t                        scratch_reg;
 164         atomic_t                        seq;
 165         uint32_t                        last_seq;
 166         unsigned long                   count_timeout;
 167         wait_queue_head_t               queue;
 168         rwlock_t                        lock;
 169         struct list_head                created;
 170         struct list_head                emited;
 171         struct list_head                signaled;
 172         bool                            initialized;
 173 };
 174
 175 struct radeon_fence {
 176         struct radeon_device            *rdev;
 177         struct kref                     kref;
 178         struct list_head                list;
 179         /* protected by radeon_fence.lock */
 180         uint32_t                        seq;
 181         unsigned long                   timeout;
 182         bool                            emited;
 183         bool                            signaled;
 184 };
 185
 186 int radeon_fence_driver_init(struct radeon_device *rdev);
 187 void radeon_fence_driver_fini(struct radeon_device *rdev);
 188 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
 189 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 190 void radeon_fence_process(struct radeon_device *rdev);
 191 bool radeon_fence_signaled(struct radeon_fence *fence);
 192 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 193 int radeon_fence_wait_next(struct radeon_device *rdev);
 194 int radeon_fence_wait_last(struct radeon_device *rdev);
 195 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 196 void radeon_fence_unref(struct radeon_fence **fence);
 197
 198 /*
 199  * Tiling registers
 200  */
 201 struct radeon_surface_reg {
 202         struct radeon_bo *bo;
 203 };
 204
 205 #define RADEON_GEM_MAX_SURFACES 8
 206
 207 /*
 208  * TTM.
 209  */
 210 struct radeon_mman {
 211         struct ttm_bo_global_ref        bo_global_ref;
 212         struct ttm_global_reference     mem_global_ref;
 213         struct ttm_bo_device            bdev;
 214         bool                            mem_global_referenced;
 215         bool                            initialized;
 216 };
 217
 218 struct radeon_bo {
 219         /* Protected by gem.mutex */
 220         struct list_head                list;
 221         /* Protected by tbo.reserved */
 222         u32                             placements[3];
 223         struct ttm_placement            placement;
 224         struct ttm_buffer_object        tbo;
 225         struct ttm_bo_kmap_obj          kmap;
 226         unsigned                        pin_count;
 227         void                            *kptr;
 228         u32                             tiling_flags;
 229         u32                             pitch;
 230         int                             surface_reg;
 231         /* Constant after initialization */
 232         struct radeon_device            *rdev;
 233         struct drm_gem_object           *gobj;
 234 };
 235
 236 struct radeon_bo_list {
 237         struct list_head        list;
 238         struct radeon_bo        *bo;
 239         uint64_t                gpu_offset;
 240         unsigned                rdomain;
 241         unsigned                wdomain;
 242         u32                     tiling_flags;
 243 };
 244
 245 /*
 246  * GEM objects.
 247  */
 248 struct radeon_gem {
 249         struct mutex            mutex;
 250         struct list_head        objects;
 251 };
 252
 253 int radeon_gem_init(struct radeon_device *rdev);
 254 void radeon_gem_fini(struct radeon_device *rdev);
 255 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 256                                 int alignment, int initial_domain,
 257                                 bool discardable, bool kernel,
 258                                 struct drm_gem_object **obj);
 259 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 260                           uint64_t *gpu_addr);
 261 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 262
 263
 264 /*
 265  * GART structures, functions & helpers
 266  */
 267 struct radeon_mc;
 268
 269 struct radeon_gart_table_ram {
 270         volatile uint32_t               *ptr;
 271 };
 272
 273 struct radeon_gart_table_vram {
 274         struct radeon_bo                *robj;
 275         volatile uint32_t               *ptr;
 276 };
 277
 278 union radeon_gart_table {
 279         struct radeon_gart_table_ram    ram;
 280         struct radeon_gart_table_vram   vram;
 281 };
 282
 283 #define RADEON_GPU_PAGE_SIZE 4096
 284
 285 struct radeon_gart {
 286         dma_addr_t                      table_addr;
 287         unsigned                        num_gpu_pages;
 288         unsigned                        num_cpu_pages;
 289         unsigned                        table_size;
 290         union radeon_gart_table         table;
 291         struct page                     **pages;
 292         dma_addr_t                      *pages_addr;
 293         bool                            ready;
 294 };
 295
 296 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 297 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 298 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 299 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 300 int radeon_gart_init(struct radeon_device *rdev);
 301 void radeon_gart_fini(struct radeon_device *rdev);
 302 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 303                         int pages);
 304 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 305                      int pages, struct page **pagelist);
 306
 307
 308 /*
 309  * GPU MC structures, functions & helpers
 310  */
 311 struct radeon_mc {
 312         resource_size_t         aper_size;
 313         resource_size_t         aper_base;
 314         resource_size_t         agp_base;
 315         /* for some chips with <= 32MB we need to lie
 316          * about vram size near mc fb location */
 317         u64                     mc_vram_size;
 318         u64                     gtt_location;
 319         u64                     gtt_size;
 320         u64                     gtt_start;
 321         u64                     gtt_end;
 322         u64                     vram_location;
 323         u64                     vram_start;
 324         u64                     vram_end;
 325         unsigned                vram_width;
 326         u64                     real_vram_size;
 327         int                     vram_mtrr;
 328         bool                    vram_is_ddr;
 329         bool                    igp_sideport_enabled;
 330 };
 331
 332 int radeon_mc_setup(struct radeon_device *rdev);
 333 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 334 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 335
 336 /*
 337  * GPU scratch registers structures, functions & helpers
 338  */
 339 struct radeon_scratch {
 340         unsigned                num_reg;
 341         bool                    free[32];
 342         uint32_t                reg[32];
 343 };
 344
 345 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 346 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 347
 348
 349 /*
 350  * IRQS.
 351  */
 352 struct radeon_irq {
 353         bool            installed;
 354         bool            sw_int;
 355         /* FIXME: use a define max crtc rather than hardcode it */
 356         bool            crtc_vblank_int[2];
 357         wait_queue_head_t       vblank_queue;
 358         /* FIXME: use defines for max hpd/dacs */
 359         bool            hpd[6];
 360         spinlock_t sw_lock;
 361         int sw_refcount;
 362 };
 363
 364 int radeon_irq_kms_init(struct radeon_device *rdev);
 365 void radeon_irq_kms_fini(struct radeon_device *rdev);
 366 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
 367 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
 368
 369 /*
 370  * CP & ring.
 371  */
 372 struct radeon_ib {
 373         struct list_head        list;
 374         unsigned long           idx;
 375         uint64_t                gpu_addr;
 376         struct radeon_fence     *fence;
 377         uint32_t        *ptr;
 378         uint32_t                length_dw;
 379 };
 380
 381 /*
 382  * locking -
 383  * mutex protects scheduled_ibs, ready, alloc_bm
 384  */
 385 struct radeon_ib_pool {
 386         struct mutex            mutex;
 387         struct radeon_bo        *robj;
 388         struct list_head        scheduled_ibs;
 389         struct list_head        bogus_ib;
 390         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
 391         bool                    ready;
 392         DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
 393 };
 394
 395 struct radeon_cp {
 396         struct radeon_bo        *ring_obj;
 397         volatile uint32_t       *ring;
 398         unsigned                rptr;
 399         unsigned                wptr;
 400         unsigned                wptr_old;
 401         unsigned                ring_size;
 402         unsigned                ring_free_dw;
 403         int                     count_dw;
 404         uint64_t                gpu_addr;
 405         uint32_t                align_mask;
 406         uint32_t                ptr_mask;
 407         struct mutex            mutex;
 408         bool                    ready;
 409 };
 410
 411 /*
 412  * R6xx+ IH ring
 413  */
 414 struct r600_ih {
 415         struct radeon_bo        *ring_obj;
 416         volatile uint32_t       *ring;
 417         unsigned                rptr;
 418         unsigned                wptr;
 419         unsigned                wptr_old;
 420         unsigned                ring_size;
 421         uint64_t                gpu_addr;
 422         uint32_t                ptr_mask;
 423         spinlock_t              lock;
 424         bool                    enabled;
 425 };
 426
 427 struct r600_blit {
 428         struct mutex            mutex;
 429         struct radeon_bo        *shader_obj;
 430         u64 shader_gpu_addr;
 431         u32 vs_offset, ps_offset;
 432         u32 state_offset;
 433         u32 state_len;
 434         u32 vb_used, vb_total;
 435         struct radeon_ib *vb_ib;
 436 };
 437
 438 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
 439 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 440 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 441 int radeon_ib_pool_init(struct radeon_device *rdev);
 442 void radeon_ib_pool_fini(struct radeon_device *rdev);
 443 int radeon_ib_test(struct radeon_device *rdev);
 444 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
 445 /* Ring access between begin & end cannot sleep */
 446 void radeon_ring_free_size(struct radeon_device *rdev);
 447 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
 448 void radeon_ring_unlock_commit(struct radeon_device *rdev);
 449 void radeon_ring_unlock_undo(struct radeon_device *rdev);
 450 int radeon_ring_test(struct radeon_device *rdev);
 451 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
 452 void radeon_ring_fini(struct radeon_device *rdev);
 453
 454
 455 /*
 456  * CS.
 457  */
 458 struct radeon_cs_reloc {
 459         struct drm_gem_object           *gobj;
 460         struct radeon_bo                *robj;
 461         struct radeon_bo_list           lobj;
 462         uint32_t                        handle;
 463         uint32_t                        flags;
 464 };
 465
 466 struct radeon_cs_chunk {
 467         uint32_t                chunk_id;
 468         uint32_t                length_dw;
 469         int kpage_idx[2];
 470         uint32_t                *kpage[2];
 471         uint32_t                *kdata;
 472         void __user *user_ptr;
 473         int last_copied_page;
 474         int last_page_index;
 475 };
 476
 477 struct radeon_cs_parser {
 478         struct device           *dev;
 479         struct radeon_device    *rdev;
 480         struct drm_file         *filp;
 481         /* chunks */
 482         unsigned                nchunks;
 483         struct radeon_cs_chunk  *chunks;
 484         uint64_t                *chunks_array;
 485         /* IB */
 486         unsigned                idx;
 487         /* relocations */
 488         unsigned                nrelocs;
 489         struct radeon_cs_reloc  *relocs;
 490         struct radeon_cs_reloc  **relocs_ptr;
 491         struct list_head        validated;
 492         /* indices of various chunks */
 493         int                     chunk_ib_idx;
 494         int                     chunk_relocs_idx;
 495         struct radeon_ib        *ib;
 496         void                    *track;
 497         unsigned                family;
 498         int parser_error;
 499 };
 500
 501 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
 502 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 503
 504
 505 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
 506 {
 507         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 508         u32 pg_idx, pg_offset;
 509         u32 idx_value = 0;
 510         int new_page;
 511
 512         pg_idx = (idx * 4) / PAGE_SIZE;
 513         pg_offset = (idx * 4) % PAGE_SIZE;
 514
 515         if (ibc->kpage_idx[0] == pg_idx)
 516                 return ibc->kpage[0][pg_offset/4];
 517         if (ibc->kpage_idx[1] == pg_idx)
 518                 return ibc->kpage[1][pg_offset/4];
 519
 520         new_page = radeon_cs_update_pages(p, pg_idx);
 521         if (new_page < 0) {
 522                 p->parser_error = new_page;
 523                 return 0;
 524         }
 525
 526         idx_value = ibc->kpage[new_page][pg_offset/4];
 527         return idx_value;
 528 }
 529
 530 struct radeon_cs_packet {
 531         unsigned        idx;
 532         unsigned        type;
 533         unsigned        reg;
 534         unsigned        opcode;
 535         int             count;
 536         unsigned        one_reg_wr;
 537 };
 538
 539 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 540                                       struct radeon_cs_packet *pkt,
 541                                       unsigned idx, unsigned reg);
 542 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 543                                       struct radeon_cs_packet *pkt);
 544
 545
 546 /*
 547  * AGP
 548  */
 549 int radeon_agp_init(struct radeon_device *rdev);
 550 void radeon_agp_resume(struct radeon_device *rdev);
 551 void radeon_agp_fini(struct radeon_device *rdev);
 552
 553
 554 /*
 555  * Writeback
 556  */
 557 struct radeon_wb {
 558         struct radeon_bo        *wb_obj;
 559         volatile uint32_t       *wb;
 560         uint64_t                gpu_addr;
 561 };
 562
 563 /**
 564  * struct radeon_pm - power management datas
 565  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 566  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 567  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 568  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 569  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 570  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 571  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 572  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 573  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 574  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
 575  * @needed_bandwidth:   current bandwidth needs
 576  *
 577  * It keeps track of various data needed to take powermanagement decision.
 578  * Bandwith need is used to determine minimun clock of the GPU and memory.
 579  * Equation between gpu/memory clock and available bandwidth is hw dependent
 580  * (type of memory, bus size, efficiency, ...)
 581  */
 582 enum radeon_pm_state {
 583         PM_STATE_DISABLED,
 584         PM_STATE_MINIMUM,
 585         PM_STATE_PAUSED,
 586         PM_STATE_ACTIVE
 587 };
 588 enum radeon_pm_action {
 589         PM_ACTION_NONE,
 590         PM_ACTION_MINIMUM,
 591         PM_ACTION_DOWNCLOCK,
 592         PM_ACTION_UPCLOCK
 593 };
 594
 595 enum radeon_voltage_type {
 596         VOLTAGE_NONE = 0,
 597         VOLTAGE_GPIO,
 598         VOLTAGE_VDDC,
 599         VOLTAGE_SW
 600 };
 601
 602 enum radeon_pm_state_type {
 603         POWER_STATE_TYPE_DEFAULT,
 604         POWER_STATE_TYPE_POWERSAVE,
 605         POWER_STATE_TYPE_BATTERY,
 606         POWER_STATE_TYPE_BALANCED,
 607         POWER_STATE_TYPE_PERFORMANCE,
 608 };
 609
 610 enum radeon_pm_clock_mode_type {
 611         POWER_MODE_TYPE_DEFAULT,
 612         POWER_MODE_TYPE_LOW,
 613         POWER_MODE_TYPE_MID,
 614         POWER_MODE_TYPE_HIGH,
 615 };
 616
 617 struct radeon_voltage {
 618         enum radeon_voltage_type type;
 619         /* gpio voltage */
 620         struct radeon_gpio_rec gpio;
 621         u32 delay; /* delay in usec from voltage drop to sclk change */
 622         bool active_high; /* voltage drop is active when bit is high */
 623         /* VDDC voltage */
 624         u8 vddc_id; /* index into vddc voltage table */
 625         u8 vddci_id; /* index into vddci voltage table */
 626         bool vddci_enabled;
 627         /* r6xx+ sw */
 628         u32 voltage;
 629 };
 630
 631 struct radeon_pm_non_clock_info {
 632         /* pcie lanes */
 633         int pcie_lanes;
 634         /* standardized non-clock flags */
 635         u32 flags;
 636 };
 637
 638 struct radeon_pm_clock_info {
 639         /* memory clock */
 640         u32 mclk;
 641         /* engine clock */
 642         u32 sclk;
 643         /* voltage info */
 644         struct radeon_voltage voltage;
 645         /* standardized clock flags - not sure we'll need these */
 646         u32 flags;
 647 };
 648
 649 struct radeon_power_state {
 650         enum radeon_pm_state_type type;
 651         /* XXX: use a define for num clock modes */
 652         struct radeon_pm_clock_info clock_info[8];
 653         /* number of valid clock modes in this power state */
 654         int num_clock_modes;
 655         /* currently selected clock mode */
 656         struct radeon_pm_clock_info *current_clock_mode;
 657         struct radeon_pm_clock_info *requested_clock_mode;
 658         struct radeon_pm_clock_info *default_clock_mode;
 659         /* non clock info about this state */
 660         struct radeon_pm_non_clock_info non_clock_info;
 661         bool voltage_drop_active;
 662 };
 663
 664 struct radeon_pm {
 665         struct mutex            mutex;
 666         struct delayed_work     idle_work;
 667         enum radeon_pm_state    state;
 668         enum radeon_pm_action   planned_action;
 669         unsigned long           action_timeout;
 670         bool                    downclocked;
 671         int                     active_crtcs;
 672         int                     req_vblank;
 673         fixed20_12              max_bandwidth;
 674         fixed20_12              igp_sideport_mclk;
 675         fixed20_12              igp_system_mclk;
 676         fixed20_12              igp_ht_link_clk;
 677         fixed20_12              igp_ht_link_width;
 678         fixed20_12              k8_bandwidth;
 679         fixed20_12              sideport_bandwidth;
 680         fixed20_12              ht_bandwidth;
 681         fixed20_12              core_bandwidth;
 682         fixed20_12              sclk;
 683         fixed20_12              needed_bandwidth;
 684         /* XXX: use a define for num power modes */
 685         struct radeon_power_state power_state[8];
 686         /* number of valid power states */
 687         int                     num_power_states;
 688         struct radeon_power_state *current_power_state;
 689         struct radeon_power_state *requested_power_state;
 690         struct radeon_power_state *default_power_state;
 691 };
 692
 693
 694 /*
 695  * Benchmarking
 696  */
 697 void radeon_benchmark(struct radeon_device *rdev);
 698
 699
 700 /*
 701  * Testing
 702  */
 703 void radeon_test_moves(struct radeon_device *rdev);
 704
 705
 706 /*
 707  * Debugfs
 708  */
 709 int radeon_debugfs_add_files(struct radeon_device *rdev,
 710                              struct drm_info_list *files,
 711                              unsigned nfiles);
 712 int radeon_debugfs_fence_init(struct radeon_device *rdev);
 713 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
 714 int r100_debugfs_cp_init(struct radeon_device *rdev);
 715
 716
 717 /*
 718  * ASIC specific functions.
 719  */
 720 struct radeon_asic {
 721         int (*init)(struct radeon_device *rdev);
 722         void (*fini)(struct radeon_device *rdev);
 723         int (*resume)(struct radeon_device *rdev);
 724         int (*suspend)(struct radeon_device *rdev);
 725         void (*vga_set_state)(struct radeon_device *rdev, bool state);
 726         int (*gpu_reset)(struct radeon_device *rdev);
 727         void (*gart_tlb_flush)(struct radeon_device *rdev);
 728         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
 729         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
 730         void (*cp_fini)(struct radeon_device *rdev);
 731         void (*cp_disable)(struct radeon_device *rdev);
 732         void (*cp_commit)(struct radeon_device *rdev);
 733         void (*ring_start)(struct radeon_device *rdev);
 734         int (*ring_test)(struct radeon_device *rdev);
 735         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
 736         int (*irq_set)(struct radeon_device *rdev);
 737         int (*irq_process)(struct radeon_device *rdev);
 738         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
 739         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
 740         int (*cs_parse)(struct radeon_cs_parser *p);
 741         int (*copy_blit)(struct radeon_device *rdev,
 742                          uint64_t src_offset,
 743                          uint64_t dst_offset,
 744                          unsigned num_pages,
 745                          struct radeon_fence *fence);
 746         int (*copy_dma)(struct radeon_device *rdev,
 747                         uint64_t src_offset,
 748                         uint64_t dst_offset,
 749                         unsigned num_pages,
 750                         struct radeon_fence *fence);
 751         int (*copy)(struct radeon_device *rdev,
 752                     uint64_t src_offset,
 753                     uint64_t dst_offset,
 754                     unsigned num_pages,
 755                     struct radeon_fence *fence);
 756         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
 757         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
 758         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
 759         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
 760         int (*get_pcie_lanes)(struct radeon_device *rdev);
 761         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
 762         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
 763         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
 764                                uint32_t tiling_flags, uint32_t pitch,
 765                                uint32_t offset, uint32_t obj_size);
 766         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
 767         void (*bandwidth_update)(struct radeon_device *rdev);
 768         void (*hpd_init)(struct radeon_device *rdev);
 769         void (*hpd_fini)(struct radeon_device *rdev);
 770         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 771         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 772         /* ioctl hw specific callback. Some hw might want to perform special
 773          * operation on specific ioctl. For instance on wait idle some hw
 774          * might want to perform and HDP flush through MMIO as it seems that
 775          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
 776          * through ring.
 777          */
 778         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
 779 };
 780
 781 /*
 782  * Asic structures
 783  */
 784 struct r100_asic {
 785         const unsigned  *reg_safe_bm;
 786         unsigned        reg_safe_bm_size;
 787         u32             hdp_cntl;
 788 };
 789
 790 struct r300_asic {
 791         const unsigned  *reg_safe_bm;
 792         unsigned        reg_safe_bm_size;
 793         u32             resync_scratch;
 794         u32             hdp_cntl;
 795 };
 796
 797 struct r600_asic {
 798         unsigned max_pipes;
 799         unsigned max_tile_pipes;
 800         unsigned max_simds;
 801         unsigned max_backends;
 802         unsigned max_gprs;
 803         unsigned max_threads;
 804         unsigned max_stack_entries;
 805         unsigned max_hw_contexts;
 806         unsigned max_gs_threads;
 807         unsigned sx_max_export_size;
 808         unsigned sx_max_export_pos_size;
 809         unsigned sx_max_export_smx_size;
 810         unsigned sq_num_cf_insts;
 811         unsigned tiling_nbanks;
 812         unsigned tiling_npipes;
 813         unsigned tiling_group_size;
 814 };
 815
 816 struct rv770_asic {
 817         unsigned max_pipes;
 818         unsigned max_tile_pipes;
 819         unsigned max_simds;
 820         unsigned max_backends;
 821         unsigned max_gprs;
 822         unsigned max_threads;
 823         unsigned max_stack_entries;
 824         unsigned max_hw_contexts;
 825         unsigned max_gs_threads;
 826         unsigned sx_max_export_size;
 827         unsigned sx_max_export_pos_size;
 828         unsigned sx_max_export_smx_size;
 829         unsigned sq_num_cf_insts;
 830         unsigned sx_num_of_sets;
 831         unsigned sc_prim_fifo_size;
 832         unsigned sc_hiz_tile_fifo_size;
 833         unsigned sc_earlyz_tile_fifo_fize;
 834         unsigned tiling_nbanks;
 835         unsigned tiling_npipes;
 836         unsigned tiling_group_size;
 837 };
 838
 839 union radeon_asic_config {
 840         struct r300_asic        r300;
 841         struct r100_asic        r100;
 842         struct r600_asic        r600;
 843         struct rv770_asic       rv770;
 844 };
 845
 846
 847 /*
 848  * IOCTL.
 849  */
 850 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
 851                           struct drm_file *filp);
 852 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
 853                             struct drm_file *filp);
 854 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
 855                          struct drm_file *file_priv);
 856 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
 857                            struct drm_file *file_priv);
 858 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 859                             struct drm_file *file_priv);
 860 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
 861                            struct drm_file *file_priv);
 862 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 863                                 struct drm_file *filp);
 864 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
 865                           struct drm_file *filp);
 866 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
 867                           struct drm_file *filp);
 868 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 869                               struct drm_file *filp);
 870 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 871 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
 872                                 struct drm_file *filp);
 873 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
 874                                 struct drm_file *filp);
 875
 876
 877 /*
 878  * Core structure, functions and helpers.
 879  */
 880 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
 881 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
 882
 883 struct radeon_device {
 884         struct device                   *dev;
 885         struct drm_device               *ddev;
 886         struct pci_dev                  *pdev;
 887         /* ASIC */
 888         union radeon_asic_config        config;
 889         enum radeon_family              family;
 890         unsigned long                   flags;
 891         int                             usec_timeout;
 892         enum radeon_pll_errata          pll_errata;
 893         int                             num_gb_pipes;
 894         int                             num_z_pipes;
 895         int                             disp_priority;
 896         /* BIOS */
 897         uint8_t                         *bios;
 898         bool                            is_atom_bios;
 899         uint16_t                        bios_header_start;
 900         struct radeon_bo                *stollen_vga_memory;
 901         struct fb_info                  *fbdev_info;
 902         struct radeon_bo                *fbdev_rbo;
 903         struct radeon_framebuffer       *fbdev_rfb;
 904         /* Register mmio */
 905         resource_size_t                 rmmio_base;
 906         resource_size_t                 rmmio_size;
 907         void                            *rmmio;
 908         radeon_rreg_t                   mc_rreg;
 909         radeon_wreg_t                   mc_wreg;
 910         radeon_rreg_t                   pll_rreg;
 911         radeon_wreg_t                   pll_wreg;
 912         uint32_t                        pcie_reg_mask;
 913         radeon_rreg_t                   pciep_rreg;
 914         radeon_wreg_t                   pciep_wreg;
 915         struct radeon_clock             clock;
 916         struct radeon_mc                mc;
 917         struct radeon_gart              gart;
 918         struct radeon_mode_info         mode_info;
 919         struct radeon_scratch           scratch;
 920         struct radeon_mman              mman;
 921         struct radeon_fence_driver      fence_drv;
 922         struct radeon_cp                cp;
 923         struct radeon_ib_pool           ib_pool;
 924         struct radeon_irq               irq;
 925         struct radeon_asic              *asic;
 926         struct radeon_gem               gem;
 927         struct radeon_pm                pm;
 928         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
 929         struct mutex                    cs_mutex;
 930         struct radeon_wb                wb;
 931         struct radeon_dummy_page        dummy_page;
 932         bool                            gpu_lockup;
 933         bool                            shutdown;
 934         bool                            suspend;
 935         bool                            need_dma32;
 936         bool                            accel_working;
 937         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
 938         const struct firmware *me_fw;   /* all family ME firmware */
 939         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
 940         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
 941         struct r600_blit r600_blit;
 942         int msi_enabled; /* msi enabled */
 943         struct r600_ih ih; /* r6/700 interrupt ring */
 944         struct workqueue_struct *wq;
 945         struct work_struct hotplug_work;
 946         int num_crtc; /* number of crtcs */
 947         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
 948
 949         /* audio stuff */
 950         struct timer_list       audio_timer;
 951         int                     audio_channels;
 952         int                     audio_rate;
 953         int                     audio_bits_per_sample;
 954         uint8_t                 audio_status_bits;
 955         uint8_t                 audio_category_code;
 956 };
 957
 958 int radeon_device_init(struct radeon_device *rdev,
 959                        struct drm_device *ddev,
 960                        struct pci_dev *pdev,
 961                        uint32_t flags);
 962 void radeon_device_fini(struct radeon_device *rdev);
 963 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
 964
 965 /* r600 blit */
 966 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
 967 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
 968 void r600_kms_blit_copy(struct radeon_device *rdev,
 969                         u64 src_gpu_addr, u64 dst_gpu_addr,
 970                         int size_bytes);
 971
 972 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
 973 {
 974         if (reg < rdev->rmmio_size)
 975                 return readl(((void __iomem *)rdev->rmmio) + reg);
 976         else {
 977                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 978                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 979         }
 980 }
 981
 982 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 983 {
 984         if (reg < rdev->rmmio_size)
 985                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
 986         else {
 987                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 988                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 989         }
 990 }
 991
 992 /*
 993  * Cast helper
 994  */
 995 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
 996
 997 /*
 998  * Registers read & write functions.
 999  */
1000 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1001 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1002 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1003 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1004 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1005 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1006 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1007 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1008 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1009 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1010 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1011 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1012 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1013 #define WREG32_P(reg, val, mask)                                \
1014         do {                                                    \
1015                 uint32_t tmp_ = RREG32(reg);                    \
1016                 tmp_ &= (mask);                                 \
1017                 tmp_ |= ((val) & ~(mask));                      \
1018                 WREG32(reg, tmp_);                              \
1019         } while (0)
1020 #define WREG32_PLL_P(reg, val, mask)                            \
1021         do {                                                    \
1022                 uint32_t tmp_ = RREG32_PLL(reg);                \
1023                 tmp_ &= (mask);                                 \
1024                 tmp_ |= ((val) & ~(mask));                      \
1025                 WREG32_PLL(reg, tmp_);                          \
1026         } while (0)
1027 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1028
1029 /*
1030  * Indirect registers accessor
1031  */
1032 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1033 {
1034         uint32_t r;
1035
1036         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1037         r = RREG32(RADEON_PCIE_DATA);
1038         return r;
1039 }
1040
1041 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1042 {
1043         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1044         WREG32(RADEON_PCIE_DATA, (v));
1045 }
1046
1047 void r100_pll_errata_after_index(struct radeon_device *rdev);
1048
1049
1050 /*
1051  * ASICs helpers.
1052  */
1053 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1054                             (rdev->pdev->device == 0x5969))
1055 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1056                 (rdev->family == CHIP_RV200) || \
1057                 (rdev->family == CHIP_RS100) || \
1058                 (rdev->family == CHIP_RS200) || \
1059                 (rdev->family == CHIP_RV250) || \
1060                 (rdev->family == CHIP_RV280) || \
1061                 (rdev->family == CHIP_RS300))
1062 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
1063                 (rdev->family == CHIP_RV350) ||                 \
1064                 (rdev->family == CHIP_R350)  ||                 \
1065                 (rdev->family == CHIP_RV380) ||                 \
1066                 (rdev->family == CHIP_R420)  ||                 \
1067                 (rdev->family == CHIP_R423)  ||                 \
1068                 (rdev->family == CHIP_RV410) ||                 \
1069                 (rdev->family == CHIP_RS400) ||                 \
1070                 (rdev->family == CHIP_RS480))
1071 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1072 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1073 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1074 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1075
1076 /*
1077  * BIOS helpers.
1078  */
1079 #define RBIOS8(i) (rdev->bios[i])
1080 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1081 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1082
1083 int radeon_combios_init(struct radeon_device *rdev);
1084 void radeon_combios_fini(struct radeon_device *rdev);
1085 int radeon_atombios_init(struct radeon_device *rdev);
1086 void radeon_atombios_fini(struct radeon_device *rdev);
1087
1088
1089 /*
1090  * RING helpers.
1091  */
1092 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1093 {
1094 #if DRM_DEBUG_CODE
1095         if (rdev->cp.count_dw <= 0) {
1096                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1097         }
1098 #endif
1099         rdev->cp.ring[rdev->cp.wptr++] = v;
1100         rdev->cp.wptr &= rdev->cp.ptr_mask;
1101         rdev->cp.count_dw--;
1102         rdev->cp.ring_free_dw--;
1103 }
1104
1105
1106 /*
1107  * ASICs macro.
1108  */
1109 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1110 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1111 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1112 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1113 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1114 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1115 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
1116 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1117 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1118 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1119 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1120 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1121 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1122 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1123 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1124 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1125 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1126 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1127 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1128 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1129 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1130 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1131 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1132 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1133 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1134 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1135 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1136 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1137 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1138 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1139 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1140 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1141 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1142 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1143
1144 /* Common functions */
1145 /* AGP */
1146 extern void radeon_agp_disable(struct radeon_device *rdev);
1147 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1148 extern int radeon_modeset_init(struct radeon_device *rdev);
1149 extern void radeon_modeset_fini(struct radeon_device *rdev);
1150 extern bool radeon_card_posted(struct radeon_device *rdev);
1151 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1152 extern int radeon_clocks_init(struct radeon_device *rdev);
1153 extern void radeon_clocks_fini(struct radeon_device *rdev);
1154 extern void radeon_scratch_init(struct radeon_device *rdev);
1155 extern void radeon_surface_init(struct radeon_device *rdev);
1156 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1157 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1158 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1159 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1160 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1161
1162 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1163 struct r100_mc_save {
1164         u32     GENMO_WT;
1165         u32     CRTC_EXT_CNTL;
1166         u32     CRTC_GEN_CNTL;
1167         u32     CRTC2_GEN_CNTL;
1168         u32     CUR_OFFSET;
1169         u32     CUR2_OFFSET;
1170 };
1171 extern void r100_cp_disable(struct radeon_device *rdev);
1172 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1173 extern void r100_cp_fini(struct radeon_device *rdev);
1174 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1175 extern int r100_pci_gart_init(struct radeon_device *rdev);
1176 extern void r100_pci_gart_fini(struct radeon_device *rdev);
1177 extern int r100_pci_gart_enable(struct radeon_device *rdev);
1178 extern void r100_pci_gart_disable(struct radeon_device *rdev);
1179 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1180 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1181 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1182 extern void r100_ib_fini(struct radeon_device *rdev);
1183 extern int r100_ib_init(struct radeon_device *rdev);
1184 extern void r100_irq_disable(struct radeon_device *rdev);
1185 extern int r100_irq_set(struct radeon_device *rdev);
1186 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1187 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1188 extern void r100_vram_init_sizes(struct radeon_device *rdev);
1189 extern void r100_wb_disable(struct radeon_device *rdev);
1190 extern void r100_wb_fini(struct radeon_device *rdev);
1191 extern int r100_wb_init(struct radeon_device *rdev);
1192 extern void r100_hdp_reset(struct radeon_device *rdev);
1193 extern int r100_rb2d_reset(struct radeon_device *rdev);
1194 extern int r100_cp_reset(struct radeon_device *rdev);
1195 extern void r100_vga_render_disable(struct radeon_device *rdev);
1196 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1197                                                 struct radeon_cs_packet *pkt,
1198                                                 struct radeon_bo *robj);
1199 extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1200                                 struct radeon_cs_packet *pkt,
1201                                 const unsigned *auth, unsigned n,
1202                                 radeon_packet0_check_t check);
1203 extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1204                                 struct radeon_cs_packet *pkt,
1205                                 unsigned idx);
1206 extern void r100_enable_bm(struct radeon_device *rdev);
1207 extern void r100_set_common_regs(struct radeon_device *rdev);
1208
1209 /* rv200,rv250,rv280 */
1210 extern void r200_set_safe_registers(struct radeon_device *rdev);
1211
1212 /* r300,r350,rv350,rv370,rv380 */
1213 extern void r300_set_reg_safe(struct radeon_device *rdev);
1214 extern void r300_mc_program(struct radeon_device *rdev);
1215 extern void r300_vram_info(struct radeon_device *rdev);
1216 extern void r300_clock_startup(struct radeon_device *rdev);
1217 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1218 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1219 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1220 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1221 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1222
1223 /* r420,r423,rv410 */
1224 extern int r420_mc_init(struct radeon_device *rdev);
1225 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1226 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1227 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1228 extern void r420_pipes_init(struct radeon_device *rdev);
1229
1230 /* rv515 */
1231 struct rv515_mc_save {
1232         u32 d1vga_control;
1233         u32 d2vga_control;
1234         u32 vga_render_control;
1235         u32 vga_hdp_control;
1236         u32 d1crtc_control;
1237         u32 d2crtc_control;
1238 };
1239 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1240 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1241 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1242 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1243 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1244 extern void rv515_clock_startup(struct radeon_device *rdev);
1245 extern void rv515_debugfs(struct radeon_device *rdev);
1246 extern int rv515_suspend(struct radeon_device *rdev);
1247
1248 /* rs400 */
1249 extern int rs400_gart_init(struct radeon_device *rdev);
1250 extern int rs400_gart_enable(struct radeon_device *rdev);
1251 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1252 extern void rs400_gart_disable(struct radeon_device *rdev);
1253 extern void rs400_gart_fini(struct radeon_device *rdev);
1254
1255 /* rs600 */
1256 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1257 extern int rs600_irq_set(struct radeon_device *rdev);
1258 extern void rs600_irq_disable(struct radeon_device *rdev);
1259
1260 /* rs690, rs740 */
1261 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1262                                         struct drm_display_mode *mode1,
1263                                         struct drm_display_mode *mode2);
1264
1265 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1266 extern bool r600_card_posted(struct radeon_device *rdev);
1267 extern void r600_cp_stop(struct radeon_device *rdev);
1268 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1269 extern int r600_cp_resume(struct radeon_device *rdev);
1270 extern void r600_cp_fini(struct radeon_device *rdev);
1271 extern int r600_count_pipe_bits(uint32_t val);
1272 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1273 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1274 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1275 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1276 extern int r600_ib_test(struct radeon_device *rdev);
1277 extern int r600_ring_test(struct radeon_device *rdev);
1278 extern void r600_wb_fini(struct radeon_device *rdev);
1279 extern int r600_wb_enable(struct radeon_device *rdev);
1280 extern void r600_wb_disable(struct radeon_device *rdev);
1281 extern void r600_scratch_init(struct radeon_device *rdev);
1282 extern int r600_blit_init(struct radeon_device *rdev);
1283 extern void r600_blit_fini(struct radeon_device *rdev);
1284 extern int r600_init_microcode(struct radeon_device *rdev);
1285 extern int r600_gpu_reset(struct radeon_device *rdev);
1286 /* r600 irq */
1287 extern int r600_irq_init(struct radeon_device *rdev);
1288 extern void r600_irq_fini(struct radeon_device *rdev);
1289 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1290 extern int r600_irq_set(struct radeon_device *rdev);
1291 extern void r600_irq_suspend(struct radeon_device *rdev);
1292 /* r600 audio */
1293 extern int r600_audio_init(struct radeon_device *rdev);
1294 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1295 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1296 extern void r600_audio_fini(struct radeon_device *rdev);
1297 extern void r600_hdmi_init(struct drm_encoder *encoder);
1298 extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
1299 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1300 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1301 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1302                                             int channels,
1303                                             int rate,
1304                                             int bps,
1305                                             uint8_t status_bits,
1306                                             uint8_t category_code);
1307
1308 /* evergreen */
1309 struct evergreen_mc_save {
1310         u32 vga_control[6];
1311         u32 vga_render_control;
1312         u32 vga_hdp_control;
1313         u32 crtc_control[6];
1314 };
1315
1316 #include "radeon_object.h"
1317
1318 #endif