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drm/radeon/dpm: update cac leakage table parsing for CI
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
101
102 /*
103 * Copy from radeon_drv.h so we don't have to include both and have conflicting
104 * symbol;
105 */
106 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
107 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
108 /* RADEON_IB_POOL_SIZE must be a power of 2 */
109 #define RADEON_IB_POOL_SIZE 16
110 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
111 #define RADEONFB_CONN_LIMIT 4
112 #define RADEON_BIOS_NUM_SCRATCH 8
113
114 /* max number of rings */
115 #define RADEON_NUM_RINGS 6
116
117 /* fence seq are set to this number when signaled */
118 #define RADEON_FENCE_SIGNALED_SEQ 0LL
119
120 /* internal ring indices */
121 /* r1xx+ has gfx CP ring */
122 #define RADEON_RING_TYPE_GFX_INDEX 0
123
124 /* cayman has 2 compute CP rings */
125 #define CAYMAN_RING_TYPE_CP1_INDEX 1
126 #define CAYMAN_RING_TYPE_CP2_INDEX 2
127
128 /* R600+ has an async dma ring */
129 #define R600_RING_TYPE_DMA_INDEX 3
130 /* cayman add a second async dma ring */
131 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
132
133 /* R600+ */
134 #define R600_RING_TYPE_UVD_INDEX 5
135
136 /* hardcode those limit for now */
137 #define RADEON_VA_IB_OFFSET (1 << 20)
138 #define RADEON_VA_RESERVED_SIZE (8 << 20)
139 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
140
141 /* reset flags */
142 #define RADEON_RESET_GFX (1 << 0)
143 #define RADEON_RESET_COMPUTE (1 << 1)
144 #define RADEON_RESET_DMA (1 << 2)
145 #define RADEON_RESET_CP (1 << 3)
146 #define RADEON_RESET_GRBM (1 << 4)
147 #define RADEON_RESET_DMA1 (1 << 5)
148 #define RADEON_RESET_RLC (1 << 6)
149 #define RADEON_RESET_SEM (1 << 7)
150 #define RADEON_RESET_IH (1 << 8)
151 #define RADEON_RESET_VMC (1 << 9)
152 #define RADEON_RESET_MC (1 << 10)
153 #define RADEON_RESET_DISPLAY (1 << 11)
154
155 /* CG block flags */
156 #define RADEON_CG_BLOCK_GFX (1 << 0)
157 #define RADEON_CG_BLOCK_MC (1 << 1)
158 #define RADEON_CG_BLOCK_SDMA (1 << 2)
159 #define RADEON_CG_BLOCK_UVD (1 << 3)
160 #define RADEON_CG_BLOCK_VCE (1 << 4)
161 #define RADEON_CG_BLOCK_HDP (1 << 5)
162
163 /* max cursor sizes (in pixels) */
164 #define CURSOR_WIDTH 64
165 #define CURSOR_HEIGHT 64
166
167 #define CIK_CURSOR_WIDTH 128
168 #define CIK_CURSOR_HEIGHT 128
169
170 /*
171 * Errata workarounds.
172 */
173 enum radeon_pll_errata {
174 CHIP_ERRATA_R300_CG = 0x00000001,
175 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
176 CHIP_ERRATA_PLL_DELAY = 0x00000004
177 };
178
179
180 struct radeon_device;
181
182
183 /*
184 * BIOS.
185 */
186 bool radeon_get_bios(struct radeon_device *rdev);
187
188 /*
189 * Dummy page
190 */
191 struct radeon_dummy_page {
192 struct page *page;
193 dma_addr_t addr;
194 };
195 int radeon_dummy_page_init(struct radeon_device *rdev);
196 void radeon_dummy_page_fini(struct radeon_device *rdev);
197
198
199 /*
200 * Clocks
201 */
202 struct radeon_clock {
203 struct radeon_pll p1pll;
204 struct radeon_pll p2pll;
205 struct radeon_pll dcpll;
206 struct radeon_pll spll;
207 struct radeon_pll mpll;
208 /* 10 Khz units */
209 uint32_t default_mclk;
210 uint32_t default_sclk;
211 uint32_t default_dispclk;
212 uint32_t current_dispclk;
213 uint32_t dp_extclk;
214 uint32_t max_pixel_clock;
215 };
216
217 /*
218 * Power management
219 */
220 int radeon_pm_init(struct radeon_device *rdev);
221 void radeon_pm_fini(struct radeon_device *rdev);
222 void radeon_pm_compute_clocks(struct radeon_device *rdev);
223 void radeon_pm_suspend(struct radeon_device *rdev);
224 void radeon_pm_resume(struct radeon_device *rdev);
225 void radeon_combios_get_power_modes(struct radeon_device *rdev);
226 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
227 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
228 u8 clock_type,
229 u32 clock,
230 bool strobe_mode,
231 struct atom_clock_dividers *dividers);
232 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
233 u32 clock,
234 bool strobe_mode,
235 struct atom_mpll_param *mpll_param);
236 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
237 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
238 u16 voltage_level, u8 voltage_type,
239 u32 *gpio_value, u32 *gpio_mask);
240 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
241 u32 eng_clock, u32 mem_clock);
242 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
243 u8 voltage_type, u16 *voltage_step);
244 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
245 u16 voltage_id, u16 *voltage);
246 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
247 u16 *voltage,
248 u16 leakage_idx);
249 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
250 u8 voltage_type,
251 u16 nominal_voltage,
252 u16 *true_voltage);
253 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
254 u8 voltage_type, u16 *min_voltage);
255 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
256 u8 voltage_type, u16 *max_voltage);
257 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
258 u8 voltage_type, u8 voltage_mode,
259 struct atom_voltage_table *voltage_table);
260 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
261 u8 voltage_type, u8 voltage_mode);
262 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
263 u32 mem_clock);
264 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
265 u32 mem_clock);
266 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
267 u8 module_index,
268 struct atom_mc_reg_table *reg_table);
269 int radeon_atom_get_memory_info(struct radeon_device *rdev,
270 u8 module_index, struct atom_memory_info *mem_info);
271 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
272 bool gddr5, u8 module_index,
273 struct atom_memory_clock_range_table *mclk_range_table);
274 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
275 u16 voltage_id, u16 *voltage);
276 void rs690_pm_info(struct radeon_device *rdev);
277 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
278 unsigned *bankh, unsigned *mtaspect,
279 unsigned *tile_split);
280
281 /*
282 * Fences.
283 */
284 struct radeon_fence_driver {
285 uint32_t scratch_reg;
286 uint64_t gpu_addr;
287 volatile uint32_t *cpu_addr;
288 /* sync_seq is protected by ring emission lock */
289 uint64_t sync_seq[RADEON_NUM_RINGS];
290 atomic64_t last_seq;
291 unsigned long last_activity;
292 bool initialized;
293 };
294
295 struct radeon_fence {
296 struct radeon_device *rdev;
297 struct kref kref;
298 /* protected by radeon_fence.lock */
299 uint64_t seq;
300 /* RB, DMA, etc. */
301 unsigned ring;
302 };
303
304 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
305 int radeon_fence_driver_init(struct radeon_device *rdev);
306 void radeon_fence_driver_fini(struct radeon_device *rdev);
307 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
308 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
309 void radeon_fence_process(struct radeon_device *rdev, int ring);
310 bool radeon_fence_signaled(struct radeon_fence *fence);
311 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
312 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
313 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
314 int radeon_fence_wait_any(struct radeon_device *rdev,
315 struct radeon_fence **fences,
316 bool intr);
317 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
318 void radeon_fence_unref(struct radeon_fence **fence);
319 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
320 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
321 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
322 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
323 struct radeon_fence *b)
324 {
325 if (!a) {
326 return b;
327 }
328
329 if (!b) {
330 return a;
331 }
332
333 BUG_ON(a->ring != b->ring);
334
335 if (a->seq > b->seq) {
336 return a;
337 } else {
338 return b;
339 }
340 }
341
342 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
343 struct radeon_fence *b)
344 {
345 if (!a) {
346 return false;
347 }
348
349 if (!b) {
350 return true;
351 }
352
353 BUG_ON(a->ring != b->ring);
354
355 return a->seq < b->seq;
356 }
357
358 /*
359 * Tiling registers
360 */
361 struct radeon_surface_reg {
362 struct radeon_bo *bo;
363 };
364
365 #define RADEON_GEM_MAX_SURFACES 8
366
367 /*
368 * TTM.
369 */
370 struct radeon_mman {
371 struct ttm_bo_global_ref bo_global_ref;
372 struct drm_global_reference mem_global_ref;
373 struct ttm_bo_device bdev;
374 bool mem_global_referenced;
375 bool initialized;
376 };
377
378 /* bo virtual address in a specific vm */
379 struct radeon_bo_va {
380 /* protected by bo being reserved */
381 struct list_head bo_list;
382 uint64_t soffset;
383 uint64_t eoffset;
384 uint32_t flags;
385 bool valid;
386 unsigned ref_count;
387
388 /* protected by vm mutex */
389 struct list_head vm_list;
390
391 /* constant after initialization */
392 struct radeon_vm *vm;
393 struct radeon_bo *bo;
394 };
395
396 struct radeon_bo {
397 /* Protected by gem.mutex */
398 struct list_head list;
399 /* Protected by tbo.reserved */
400 u32 placements[3];
401 struct ttm_placement placement;
402 struct ttm_buffer_object tbo;
403 struct ttm_bo_kmap_obj kmap;
404 unsigned pin_count;
405 void *kptr;
406 u32 tiling_flags;
407 u32 pitch;
408 int surface_reg;
409 /* list of all virtual address to which this bo
410 * is associated to
411 */
412 struct list_head va;
413 /* Constant after initialization */
414 struct radeon_device *rdev;
415 struct drm_gem_object gem_base;
416
417 struct ttm_bo_kmap_obj dma_buf_vmap;
418 pid_t pid;
419 };
420 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
421
422 struct radeon_bo_list {
423 struct ttm_validate_buffer tv;
424 struct radeon_bo *bo;
425 uint64_t gpu_offset;
426 bool written;
427 unsigned domain;
428 unsigned alt_domain;
429 u32 tiling_flags;
430 };
431
432 int radeon_gem_debugfs_init(struct radeon_device *rdev);
433
434 /* sub-allocation manager, it has to be protected by another lock.
435 * By conception this is an helper for other part of the driver
436 * like the indirect buffer or semaphore, which both have their
437 * locking.
438 *
439 * Principe is simple, we keep a list of sub allocation in offset
440 * order (first entry has offset == 0, last entry has the highest
441 * offset).
442 *
443 * When allocating new object we first check if there is room at
444 * the end total_size - (last_object_offset + last_object_size) >=
445 * alloc_size. If so we allocate new object there.
446 *
447 * When there is not enough room at the end, we start waiting for
448 * each sub object until we reach object_offset+object_size >=
449 * alloc_size, this object then become the sub object we return.
450 *
451 * Alignment can't be bigger than page size.
452 *
453 * Hole are not considered for allocation to keep things simple.
454 * Assumption is that there won't be hole (all object on same
455 * alignment).
456 */
457 struct radeon_sa_manager {
458 wait_queue_head_t wq;
459 struct radeon_bo *bo;
460 struct list_head *hole;
461 struct list_head flist[RADEON_NUM_RINGS];
462 struct list_head olist;
463 unsigned size;
464 uint64_t gpu_addr;
465 void *cpu_ptr;
466 uint32_t domain;
467 uint32_t align;
468 };
469
470 struct radeon_sa_bo;
471
472 /* sub-allocation buffer */
473 struct radeon_sa_bo {
474 struct list_head olist;
475 struct list_head flist;
476 struct radeon_sa_manager *manager;
477 unsigned soffset;
478 unsigned eoffset;
479 struct radeon_fence *fence;
480 };
481
482 /*
483 * GEM objects.
484 */
485 struct radeon_gem {
486 struct mutex mutex;
487 struct list_head objects;
488 };
489
490 int radeon_gem_init(struct radeon_device *rdev);
491 void radeon_gem_fini(struct radeon_device *rdev);
492 int radeon_gem_object_create(struct radeon_device *rdev, int size,
493 int alignment, int initial_domain,
494 bool discardable, bool kernel,
495 struct drm_gem_object **obj);
496
497 int radeon_mode_dumb_create(struct drm_file *file_priv,
498 struct drm_device *dev,
499 struct drm_mode_create_dumb *args);
500 int radeon_mode_dumb_mmap(struct drm_file *filp,
501 struct drm_device *dev,
502 uint32_t handle, uint64_t *offset_p);
503 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
504 struct drm_device *dev,
505 uint32_t handle);
506
507 /*
508 * Semaphores.
509 */
510 /* everything here is constant */
511 struct radeon_semaphore {
512 struct radeon_sa_bo *sa_bo;
513 signed waiters;
514 uint64_t gpu_addr;
515 };
516
517 int radeon_semaphore_create(struct radeon_device *rdev,
518 struct radeon_semaphore **semaphore);
519 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
520 struct radeon_semaphore *semaphore);
521 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
522 struct radeon_semaphore *semaphore);
523 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
524 struct radeon_semaphore *semaphore,
525 int signaler, int waiter);
526 void radeon_semaphore_free(struct radeon_device *rdev,
527 struct radeon_semaphore **semaphore,
528 struct radeon_fence *fence);
529
530 /*
531 * GART structures, functions & helpers
532 */
533 struct radeon_mc;
534
535 #define RADEON_GPU_PAGE_SIZE 4096
536 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
537 #define RADEON_GPU_PAGE_SHIFT 12
538 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
539
540 struct radeon_gart {
541 dma_addr_t table_addr;
542 struct radeon_bo *robj;
543 void *ptr;
544 unsigned num_gpu_pages;
545 unsigned num_cpu_pages;
546 unsigned table_size;
547 struct page **pages;
548 dma_addr_t *pages_addr;
549 bool ready;
550 };
551
552 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
553 void radeon_gart_table_ram_free(struct radeon_device *rdev);
554 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
555 void radeon_gart_table_vram_free(struct radeon_device *rdev);
556 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
557 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
558 int radeon_gart_init(struct radeon_device *rdev);
559 void radeon_gart_fini(struct radeon_device *rdev);
560 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
561 int pages);
562 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
563 int pages, struct page **pagelist,
564 dma_addr_t *dma_addr);
565 void radeon_gart_restore(struct radeon_device *rdev);
566
567
568 /*
569 * GPU MC structures, functions & helpers
570 */
571 struct radeon_mc {
572 resource_size_t aper_size;
573 resource_size_t aper_base;
574 resource_size_t agp_base;
575 /* for some chips with <= 32MB we need to lie
576 * about vram size near mc fb location */
577 u64 mc_vram_size;
578 u64 visible_vram_size;
579 u64 gtt_size;
580 u64 gtt_start;
581 u64 gtt_end;
582 u64 vram_start;
583 u64 vram_end;
584 unsigned vram_width;
585 u64 real_vram_size;
586 int vram_mtrr;
587 bool vram_is_ddr;
588 bool igp_sideport_enabled;
589 u64 gtt_base_align;
590 u64 mc_mask;
591 };
592
593 bool radeon_combios_sideport_present(struct radeon_device *rdev);
594 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
595
596 /*
597 * GPU scratch registers structures, functions & helpers
598 */
599 struct radeon_scratch {
600 unsigned num_reg;
601 uint32_t reg_base;
602 bool free[32];
603 uint32_t reg[32];
604 };
605
606 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
607 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
608
609 /*
610 * GPU doorbell structures, functions & helpers
611 */
612 struct radeon_doorbell {
613 u32 num_pages;
614 bool free[1024];
615 /* doorbell mmio */
616 resource_size_t base;
617 resource_size_t size;
618 void __iomem *ptr;
619 };
620
621 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
622 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
623
624 /*
625 * IRQS.
626 */
627
628 struct radeon_unpin_work {
629 struct work_struct work;
630 struct radeon_device *rdev;
631 int crtc_id;
632 struct radeon_fence *fence;
633 struct drm_pending_vblank_event *event;
634 struct radeon_bo *old_rbo;
635 u64 new_crtc_base;
636 };
637
638 struct r500_irq_stat_regs {
639 u32 disp_int;
640 u32 hdmi0_status;
641 };
642
643 struct r600_irq_stat_regs {
644 u32 disp_int;
645 u32 disp_int_cont;
646 u32 disp_int_cont2;
647 u32 d1grph_int;
648 u32 d2grph_int;
649 u32 hdmi0_status;
650 u32 hdmi1_status;
651 };
652
653 struct evergreen_irq_stat_regs {
654 u32 disp_int;
655 u32 disp_int_cont;
656 u32 disp_int_cont2;
657 u32 disp_int_cont3;
658 u32 disp_int_cont4;
659 u32 disp_int_cont5;
660 u32 d1grph_int;
661 u32 d2grph_int;
662 u32 d3grph_int;
663 u32 d4grph_int;
664 u32 d5grph_int;
665 u32 d6grph_int;
666 u32 afmt_status1;
667 u32 afmt_status2;
668 u32 afmt_status3;
669 u32 afmt_status4;
670 u32 afmt_status5;
671 u32 afmt_status6;
672 };
673
674 struct cik_irq_stat_regs {
675 u32 disp_int;
676 u32 disp_int_cont;
677 u32 disp_int_cont2;
678 u32 disp_int_cont3;
679 u32 disp_int_cont4;
680 u32 disp_int_cont5;
681 u32 disp_int_cont6;
682 };
683
684 union radeon_irq_stat_regs {
685 struct r500_irq_stat_regs r500;
686 struct r600_irq_stat_regs r600;
687 struct evergreen_irq_stat_regs evergreen;
688 struct cik_irq_stat_regs cik;
689 };
690
691 #define RADEON_MAX_HPD_PINS 6
692 #define RADEON_MAX_CRTCS 6
693 #define RADEON_MAX_AFMT_BLOCKS 6
694
695 struct radeon_irq {
696 bool installed;
697 spinlock_t lock;
698 atomic_t ring_int[RADEON_NUM_RINGS];
699 bool crtc_vblank_int[RADEON_MAX_CRTCS];
700 atomic_t pflip[RADEON_MAX_CRTCS];
701 wait_queue_head_t vblank_queue;
702 bool hpd[RADEON_MAX_HPD_PINS];
703 bool afmt[RADEON_MAX_AFMT_BLOCKS];
704 union radeon_irq_stat_regs stat_regs;
705 bool dpm_thermal;
706 };
707
708 int radeon_irq_kms_init(struct radeon_device *rdev);
709 void radeon_irq_kms_fini(struct radeon_device *rdev);
710 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
711 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
712 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
713 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
714 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
715 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
716 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
717 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
718
719 /*
720 * CP & rings.
721 */
722
723 struct radeon_ib {
724 struct radeon_sa_bo *sa_bo;
725 uint32_t length_dw;
726 uint64_t gpu_addr;
727 uint32_t *ptr;
728 int ring;
729 struct radeon_fence *fence;
730 struct radeon_vm *vm;
731 bool is_const_ib;
732 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
733 struct radeon_semaphore *semaphore;
734 };
735
736 struct radeon_ring {
737 struct radeon_bo *ring_obj;
738 volatile uint32_t *ring;
739 unsigned rptr;
740 unsigned rptr_offs;
741 unsigned rptr_reg;
742 unsigned rptr_save_reg;
743 u64 next_rptr_gpu_addr;
744 volatile u32 *next_rptr_cpu_addr;
745 unsigned wptr;
746 unsigned wptr_old;
747 unsigned wptr_reg;
748 unsigned ring_size;
749 unsigned ring_free_dw;
750 int count_dw;
751 unsigned long last_activity;
752 unsigned last_rptr;
753 uint64_t gpu_addr;
754 uint32_t align_mask;
755 uint32_t ptr_mask;
756 bool ready;
757 u32 ptr_reg_shift;
758 u32 ptr_reg_mask;
759 u32 nop;
760 u32 idx;
761 u64 last_semaphore_signal_addr;
762 u64 last_semaphore_wait_addr;
763 /* for CIK queues */
764 u32 me;
765 u32 pipe;
766 u32 queue;
767 struct radeon_bo *mqd_obj;
768 u32 doorbell_page_num;
769 u32 doorbell_offset;
770 unsigned wptr_offs;
771 };
772
773 struct radeon_mec {
774 struct radeon_bo *hpd_eop_obj;
775 u64 hpd_eop_gpu_addr;
776 u32 num_pipe;
777 u32 num_mec;
778 u32 num_queue;
779 };
780
781 /*
782 * VM
783 */
784
785 /* maximum number of VMIDs */
786 #define RADEON_NUM_VM 16
787
788 /* defines number of bits in page table versus page directory,
789 * a page is 4KB so we have 12 bits offset, 9 bits in the page
790 * table and the remaining 19 bits are in the page directory */
791 #define RADEON_VM_BLOCK_SIZE 9
792
793 /* number of entries in page table */
794 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
795
796 /* PTBs (Page Table Blocks) need to be aligned to 32K */
797 #define RADEON_VM_PTB_ALIGN_SIZE 32768
798 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
799 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
800
801 struct radeon_vm {
802 struct list_head list;
803 struct list_head va;
804 unsigned id;
805
806 /* contains the page directory */
807 struct radeon_sa_bo *page_directory;
808 uint64_t pd_gpu_addr;
809
810 /* array of page tables, one for each page directory entry */
811 struct radeon_sa_bo **page_tables;
812
813 struct mutex mutex;
814 /* last fence for cs using this vm */
815 struct radeon_fence *fence;
816 /* last flush or NULL if we still need to flush */
817 struct radeon_fence *last_flush;
818 };
819
820 struct radeon_vm_manager {
821 struct mutex lock;
822 struct list_head lru_vm;
823 struct radeon_fence *active[RADEON_NUM_VM];
824 struct radeon_sa_manager sa_manager;
825 uint32_t max_pfn;
826 /* number of VMIDs */
827 unsigned nvm;
828 /* vram base address for page table entry */
829 u64 vram_base_offset;
830 /* is vm enabled? */
831 bool enabled;
832 };
833
834 /*
835 * file private structure
836 */
837 struct radeon_fpriv {
838 struct radeon_vm vm;
839 };
840
841 /*
842 * R6xx+ IH ring
843 */
844 struct r600_ih {
845 struct radeon_bo *ring_obj;
846 volatile uint32_t *ring;
847 unsigned rptr;
848 unsigned ring_size;
849 uint64_t gpu_addr;
850 uint32_t ptr_mask;
851 atomic_t lock;
852 bool enabled;
853 };
854
855 /*
856 * RLC stuff
857 */
858 #include "clearstate_defs.h"
859
860 struct radeon_rlc {
861 /* for power gating */
862 struct radeon_bo *save_restore_obj;
863 uint64_t save_restore_gpu_addr;
864 volatile uint32_t *sr_ptr;
865 const u32 *reg_list;
866 u32 reg_list_size;
867 /* for clear state */
868 struct radeon_bo *clear_state_obj;
869 uint64_t clear_state_gpu_addr;
870 volatile uint32_t *cs_ptr;
871 const struct cs_section_def *cs_data;
872 u32 clear_state_size;
873 /* for cp tables */
874 struct radeon_bo *cp_table_obj;
875 uint64_t cp_table_gpu_addr;
876 volatile uint32_t *cp_table_ptr;
877 u32 cp_table_size;
878 };
879
880 int radeon_ib_get(struct radeon_device *rdev, int ring,
881 struct radeon_ib *ib, struct radeon_vm *vm,
882 unsigned size);
883 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
884 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
885 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
886 struct radeon_ib *const_ib);
887 int radeon_ib_pool_init(struct radeon_device *rdev);
888 void radeon_ib_pool_fini(struct radeon_device *rdev);
889 int radeon_ib_ring_tests(struct radeon_device *rdev);
890 /* Ring access between begin & end cannot sleep */
891 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
892 struct radeon_ring *ring);
893 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
894 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
895 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
896 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
897 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
898 void radeon_ring_undo(struct radeon_ring *ring);
899 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
900 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
901 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
902 void radeon_ring_lockup_update(struct radeon_ring *ring);
903 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
904 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
905 uint32_t **data);
906 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
907 unsigned size, uint32_t *data);
908 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
909 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
910 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
911 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
912
913
914 /* r600 async dma */
915 void r600_dma_stop(struct radeon_device *rdev);
916 int r600_dma_resume(struct radeon_device *rdev);
917 void r600_dma_fini(struct radeon_device *rdev);
918
919 void cayman_dma_stop(struct radeon_device *rdev);
920 int cayman_dma_resume(struct radeon_device *rdev);
921 void cayman_dma_fini(struct radeon_device *rdev);
922
923 /*
924 * CS.
925 */
926 struct radeon_cs_reloc {
927 struct drm_gem_object *gobj;
928 struct radeon_bo *robj;
929 struct radeon_bo_list lobj;
930 uint32_t handle;
931 uint32_t flags;
932 };
933
934 struct radeon_cs_chunk {
935 uint32_t chunk_id;
936 uint32_t length_dw;
937 int kpage_idx[2];
938 uint32_t *kpage[2];
939 uint32_t *kdata;
940 void __user *user_ptr;
941 int last_copied_page;
942 int last_page_index;
943 };
944
945 struct radeon_cs_parser {
946 struct device *dev;
947 struct radeon_device *rdev;
948 struct drm_file *filp;
949 /* chunks */
950 unsigned nchunks;
951 struct radeon_cs_chunk *chunks;
952 uint64_t *chunks_array;
953 /* IB */
954 unsigned idx;
955 /* relocations */
956 unsigned nrelocs;
957 struct radeon_cs_reloc *relocs;
958 struct radeon_cs_reloc **relocs_ptr;
959 struct list_head validated;
960 unsigned dma_reloc_idx;
961 /* indices of various chunks */
962 int chunk_ib_idx;
963 int chunk_relocs_idx;
964 int chunk_flags_idx;
965 int chunk_const_ib_idx;
966 struct radeon_ib ib;
967 struct radeon_ib const_ib;
968 void *track;
969 unsigned family;
970 int parser_error;
971 u32 cs_flags;
972 u32 ring;
973 s32 priority;
974 struct ww_acquire_ctx ticket;
975 };
976
977 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
978 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
979
980 struct radeon_cs_packet {
981 unsigned idx;
982 unsigned type;
983 unsigned reg;
984 unsigned opcode;
985 int count;
986 unsigned one_reg_wr;
987 };
988
989 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
990 struct radeon_cs_packet *pkt,
991 unsigned idx, unsigned reg);
992 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
993 struct radeon_cs_packet *pkt);
994
995
996 /*
997 * AGP
998 */
999 int radeon_agp_init(struct radeon_device *rdev);
1000 void radeon_agp_resume(struct radeon_device *rdev);
1001 void radeon_agp_suspend(struct radeon_device *rdev);
1002 void radeon_agp_fini(struct radeon_device *rdev);
1003
1004
1005 /*
1006 * Writeback
1007 */
1008 struct radeon_wb {
1009 struct radeon_bo *wb_obj;
1010 volatile uint32_t *wb;
1011 uint64_t gpu_addr;
1012 bool enabled;
1013 bool use_event;
1014 };
1015
1016 #define RADEON_WB_SCRATCH_OFFSET 0
1017 #define RADEON_WB_RING0_NEXT_RPTR 256
1018 #define RADEON_WB_CP_RPTR_OFFSET 1024
1019 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1020 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1021 #define R600_WB_DMA_RPTR_OFFSET 1792
1022 #define R600_WB_IH_WPTR_OFFSET 2048
1023 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1024 #define R600_WB_UVD_RPTR_OFFSET 2560
1025 #define R600_WB_EVENT_OFFSET 3072
1026 #define CIK_WB_CP1_WPTR_OFFSET 3328
1027 #define CIK_WB_CP2_WPTR_OFFSET 3584
1028
1029 /**
1030 * struct radeon_pm - power management datas
1031 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1032 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1033 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1034 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1035 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1036 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1037 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1038 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1039 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1040 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1041 * @needed_bandwidth: current bandwidth needs
1042 *
1043 * It keeps track of various data needed to take powermanagement decision.
1044 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1045 * Equation between gpu/memory clock and available bandwidth is hw dependent
1046 * (type of memory, bus size, efficiency, ...)
1047 */
1048
1049 enum radeon_pm_method {
1050 PM_METHOD_PROFILE,
1051 PM_METHOD_DYNPM,
1052 PM_METHOD_DPM,
1053 };
1054
1055 enum radeon_dynpm_state {
1056 DYNPM_STATE_DISABLED,
1057 DYNPM_STATE_MINIMUM,
1058 DYNPM_STATE_PAUSED,
1059 DYNPM_STATE_ACTIVE,
1060 DYNPM_STATE_SUSPENDED,
1061 };
1062 enum radeon_dynpm_action {
1063 DYNPM_ACTION_NONE,
1064 DYNPM_ACTION_MINIMUM,
1065 DYNPM_ACTION_DOWNCLOCK,
1066 DYNPM_ACTION_UPCLOCK,
1067 DYNPM_ACTION_DEFAULT
1068 };
1069
1070 enum radeon_voltage_type {
1071 VOLTAGE_NONE = 0,
1072 VOLTAGE_GPIO,
1073 VOLTAGE_VDDC,
1074 VOLTAGE_SW
1075 };
1076
1077 enum radeon_pm_state_type {
1078 /* not used for dpm */
1079 POWER_STATE_TYPE_DEFAULT,
1080 POWER_STATE_TYPE_POWERSAVE,
1081 /* user selectable states */
1082 POWER_STATE_TYPE_BATTERY,
1083 POWER_STATE_TYPE_BALANCED,
1084 POWER_STATE_TYPE_PERFORMANCE,
1085 /* internal states */
1086 POWER_STATE_TYPE_INTERNAL_UVD,
1087 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1088 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1089 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1090 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1091 POWER_STATE_TYPE_INTERNAL_BOOT,
1092 POWER_STATE_TYPE_INTERNAL_THERMAL,
1093 POWER_STATE_TYPE_INTERNAL_ACPI,
1094 POWER_STATE_TYPE_INTERNAL_ULV,
1095 POWER_STATE_TYPE_INTERNAL_3DPERF,
1096 };
1097
1098 enum radeon_pm_profile_type {
1099 PM_PROFILE_DEFAULT,
1100 PM_PROFILE_AUTO,
1101 PM_PROFILE_LOW,
1102 PM_PROFILE_MID,
1103 PM_PROFILE_HIGH,
1104 };
1105
1106 #define PM_PROFILE_DEFAULT_IDX 0
1107 #define PM_PROFILE_LOW_SH_IDX 1
1108 #define PM_PROFILE_MID_SH_IDX 2
1109 #define PM_PROFILE_HIGH_SH_IDX 3
1110 #define PM_PROFILE_LOW_MH_IDX 4
1111 #define PM_PROFILE_MID_MH_IDX 5
1112 #define PM_PROFILE_HIGH_MH_IDX 6
1113 #define PM_PROFILE_MAX 7
1114
1115 struct radeon_pm_profile {
1116 int dpms_off_ps_idx;
1117 int dpms_on_ps_idx;
1118 int dpms_off_cm_idx;
1119 int dpms_on_cm_idx;
1120 };
1121
1122 enum radeon_int_thermal_type {
1123 THERMAL_TYPE_NONE,
1124 THERMAL_TYPE_EXTERNAL,
1125 THERMAL_TYPE_EXTERNAL_GPIO,
1126 THERMAL_TYPE_RV6XX,
1127 THERMAL_TYPE_RV770,
1128 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1129 THERMAL_TYPE_EVERGREEN,
1130 THERMAL_TYPE_SUMO,
1131 THERMAL_TYPE_NI,
1132 THERMAL_TYPE_SI,
1133 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1134 THERMAL_TYPE_CI,
1135 THERMAL_TYPE_KV,
1136 };
1137
1138 struct radeon_voltage {
1139 enum radeon_voltage_type type;
1140 /* gpio voltage */
1141 struct radeon_gpio_rec gpio;
1142 u32 delay; /* delay in usec from voltage drop to sclk change */
1143 bool active_high; /* voltage drop is active when bit is high */
1144 /* VDDC voltage */
1145 u8 vddc_id; /* index into vddc voltage table */
1146 u8 vddci_id; /* index into vddci voltage table */
1147 bool vddci_enabled;
1148 /* r6xx+ sw */
1149 u16 voltage;
1150 /* evergreen+ vddci */
1151 u16 vddci;
1152 };
1153
1154 /* clock mode flags */
1155 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1156
1157 struct radeon_pm_clock_info {
1158 /* memory clock */
1159 u32 mclk;
1160 /* engine clock */
1161 u32 sclk;
1162 /* voltage info */
1163 struct radeon_voltage voltage;
1164 /* standardized clock flags */
1165 u32 flags;
1166 };
1167
1168 /* state flags */
1169 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1170
1171 struct radeon_power_state {
1172 enum radeon_pm_state_type type;
1173 struct radeon_pm_clock_info *clock_info;
1174 /* number of valid clock modes in this power state */
1175 int num_clock_modes;
1176 struct radeon_pm_clock_info *default_clock_mode;
1177 /* standardized state flags */
1178 u32 flags;
1179 u32 misc; /* vbios specific flags */
1180 u32 misc2; /* vbios specific flags */
1181 int pcie_lanes; /* pcie lanes */
1182 };
1183
1184 /*
1185 * Some modes are overclocked by very low value, accept them
1186 */
1187 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1188
1189 enum radeon_dpm_auto_throttle_src {
1190 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1191 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1192 };
1193
1194 enum radeon_dpm_event_src {
1195 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1196 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1197 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1198 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1199 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1200 };
1201
1202 struct radeon_ps {
1203 u32 caps; /* vbios flags */
1204 u32 class; /* vbios flags */
1205 u32 class2; /* vbios flags */
1206 /* UVD clocks */
1207 u32 vclk;
1208 u32 dclk;
1209 /* asic priv */
1210 void *ps_priv;
1211 };
1212
1213 struct radeon_dpm_thermal {
1214 /* thermal interrupt work */
1215 struct work_struct work;
1216 /* low temperature threshold */
1217 int min_temp;
1218 /* high temperature threshold */
1219 int max_temp;
1220 /* was interrupt low to high or high to low */
1221 bool high_to_low;
1222 };
1223
1224 enum radeon_clk_action
1225 {
1226 RADEON_SCLK_UP = 1,
1227 RADEON_SCLK_DOWN
1228 };
1229
1230 struct radeon_blacklist_clocks
1231 {
1232 u32 sclk;
1233 u32 mclk;
1234 enum radeon_clk_action action;
1235 };
1236
1237 struct radeon_clock_and_voltage_limits {
1238 u32 sclk;
1239 u32 mclk;
1240 u32 vddc;
1241 u32 vddci;
1242 };
1243
1244 struct radeon_clock_array {
1245 u32 count;
1246 u32 *values;
1247 };
1248
1249 struct radeon_clock_voltage_dependency_entry {
1250 u32 clk;
1251 u16 v;
1252 };
1253
1254 struct radeon_clock_voltage_dependency_table {
1255 u32 count;
1256 struct radeon_clock_voltage_dependency_entry *entries;
1257 };
1258
1259 union radeon_cac_leakage_entry {
1260 struct {
1261 u16 vddc;
1262 u32 leakage;
1263 };
1264 struct {
1265 u16 vddc1;
1266 u16 vddc2;
1267 u16 vddc3;
1268 };
1269 };
1270
1271 struct radeon_cac_leakage_table {
1272 u32 count;
1273 union radeon_cac_leakage_entry *entries;
1274 };
1275
1276 struct radeon_phase_shedding_limits_entry {
1277 u16 voltage;
1278 u32 sclk;
1279 u32 mclk;
1280 };
1281
1282 struct radeon_phase_shedding_limits_table {
1283 u32 count;
1284 struct radeon_phase_shedding_limits_entry *entries;
1285 };
1286
1287 struct radeon_uvd_clock_voltage_dependency_entry {
1288 u32 vclk;
1289 u32 dclk;
1290 u16 v;
1291 };
1292
1293 struct radeon_uvd_clock_voltage_dependency_table {
1294 u8 count;
1295 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1296 };
1297
1298 struct radeon_ppm_table {
1299 u8 ppm_design;
1300 u16 cpu_core_number;
1301 u32 platform_tdp;
1302 u32 small_ac_platform_tdp;
1303 u32 platform_tdc;
1304 u32 small_ac_platform_tdc;
1305 u32 apu_tdp;
1306 u32 dgpu_tdp;
1307 u32 dgpu_ulv_power;
1308 u32 tj_max;
1309 };
1310
1311 struct radeon_dpm_dynamic_state {
1312 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1313 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1314 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1315 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1316 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1317 struct radeon_clock_array valid_sclk_values;
1318 struct radeon_clock_array valid_mclk_values;
1319 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1320 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1321 u32 mclk_sclk_ratio;
1322 u32 sclk_mclk_delta;
1323 u16 vddc_vddci_delta;
1324 u16 min_vddc_for_pcie_gen2;
1325 struct radeon_cac_leakage_table cac_leakage_table;
1326 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1327 struct radeon_ppm_table *ppm_table;
1328 };
1329
1330 struct radeon_dpm_fan {
1331 u16 t_min;
1332 u16 t_med;
1333 u16 t_high;
1334 u16 pwm_min;
1335 u16 pwm_med;
1336 u16 pwm_high;
1337 u8 t_hyst;
1338 u32 cycle_delay;
1339 u16 t_max;
1340 bool ucode_fan_control;
1341 };
1342
1343 enum radeon_pcie_gen {
1344 RADEON_PCIE_GEN1 = 0,
1345 RADEON_PCIE_GEN2 = 1,
1346 RADEON_PCIE_GEN3 = 2,
1347 RADEON_PCIE_GEN_INVALID = 0xffff
1348 };
1349
1350 enum radeon_dpm_forced_level {
1351 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1352 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1353 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1354 };
1355
1356 struct radeon_dpm {
1357 struct radeon_ps *ps;
1358 /* number of valid power states */
1359 int num_ps;
1360 /* current power state that is active */
1361 struct radeon_ps *current_ps;
1362 /* requested power state */
1363 struct radeon_ps *requested_ps;
1364 /* boot up power state */
1365 struct radeon_ps *boot_ps;
1366 /* default uvd power state */
1367 struct radeon_ps *uvd_ps;
1368 enum radeon_pm_state_type state;
1369 enum radeon_pm_state_type user_state;
1370 u32 platform_caps;
1371 u32 voltage_response_time;
1372 u32 backbias_response_time;
1373 void *priv;
1374 u32 new_active_crtcs;
1375 int new_active_crtc_count;
1376 u32 current_active_crtcs;
1377 int current_active_crtc_count;
1378 struct radeon_dpm_dynamic_state dyn_state;
1379 struct radeon_dpm_fan fan;
1380 u32 tdp_limit;
1381 u32 near_tdp_limit;
1382 u32 near_tdp_limit_adjusted;
1383 u32 sq_ramping_threshold;
1384 u32 cac_leakage;
1385 u16 tdp_od_limit;
1386 u32 tdp_adjustment;
1387 u16 load_line_slope;
1388 bool power_control;
1389 bool ac_power;
1390 /* special states active */
1391 bool thermal_active;
1392 bool uvd_active;
1393 /* thermal handling */
1394 struct radeon_dpm_thermal thermal;
1395 /* forced levels */
1396 enum radeon_dpm_forced_level forced_level;
1397 /* track UVD streams */
1398 unsigned sd;
1399 unsigned hd;
1400 };
1401
1402 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1403
1404 struct radeon_pm {
1405 struct mutex mutex;
1406 /* write locked while reprogramming mclk */
1407 struct rw_semaphore mclk_lock;
1408 u32 active_crtcs;
1409 int active_crtc_count;
1410 int req_vblank;
1411 bool vblank_sync;
1412 fixed20_12 max_bandwidth;
1413 fixed20_12 igp_sideport_mclk;
1414 fixed20_12 igp_system_mclk;
1415 fixed20_12 igp_ht_link_clk;
1416 fixed20_12 igp_ht_link_width;
1417 fixed20_12 k8_bandwidth;
1418 fixed20_12 sideport_bandwidth;
1419 fixed20_12 ht_bandwidth;
1420 fixed20_12 core_bandwidth;
1421 fixed20_12 sclk;
1422 fixed20_12 mclk;
1423 fixed20_12 needed_bandwidth;
1424 struct radeon_power_state *power_state;
1425 /* number of valid power states */
1426 int num_power_states;
1427 int current_power_state_index;
1428 int current_clock_mode_index;
1429 int requested_power_state_index;
1430 int requested_clock_mode_index;
1431 int default_power_state_index;
1432 u32 current_sclk;
1433 u32 current_mclk;
1434 u16 current_vddc;
1435 u16 current_vddci;
1436 u32 default_sclk;
1437 u32 default_mclk;
1438 u16 default_vddc;
1439 u16 default_vddci;
1440 struct radeon_i2c_chan *i2c_bus;
1441 /* selected pm method */
1442 enum radeon_pm_method pm_method;
1443 /* dynpm power management */
1444 struct delayed_work dynpm_idle_work;
1445 enum radeon_dynpm_state dynpm_state;
1446 enum radeon_dynpm_action dynpm_planned_action;
1447 unsigned long dynpm_action_timeout;
1448 bool dynpm_can_upclock;
1449 bool dynpm_can_downclock;
1450 /* profile-based power management */
1451 enum radeon_pm_profile_type profile;
1452 int profile_index;
1453 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1454 /* internal thermal controller on rv6xx+ */
1455 enum radeon_int_thermal_type int_thermal_type;
1456 struct device *int_hwmon_dev;
1457 /* dpm */
1458 bool dpm_enabled;
1459 struct radeon_dpm dpm;
1460 };
1461
1462 int radeon_pm_get_type_index(struct radeon_device *rdev,
1463 enum radeon_pm_state_type ps_type,
1464 int instance);
1465 /*
1466 * UVD
1467 */
1468 #define RADEON_MAX_UVD_HANDLES 10
1469 #define RADEON_UVD_STACK_SIZE (1024*1024)
1470 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1471
1472 struct radeon_uvd {
1473 struct radeon_bo *vcpu_bo;
1474 void *cpu_addr;
1475 uint64_t gpu_addr;
1476 void *saved_bo;
1477 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1478 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1479 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1480 struct delayed_work idle_work;
1481 };
1482
1483 int radeon_uvd_init(struct radeon_device *rdev);
1484 void radeon_uvd_fini(struct radeon_device *rdev);
1485 int radeon_uvd_suspend(struct radeon_device *rdev);
1486 int radeon_uvd_resume(struct radeon_device *rdev);
1487 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1488 uint32_t handle, struct radeon_fence **fence);
1489 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1490 uint32_t handle, struct radeon_fence **fence);
1491 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1492 void radeon_uvd_free_handles(struct radeon_device *rdev,
1493 struct drm_file *filp);
1494 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1495 void radeon_uvd_note_usage(struct radeon_device *rdev);
1496 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1497 unsigned vclk, unsigned dclk,
1498 unsigned vco_min, unsigned vco_max,
1499 unsigned fb_factor, unsigned fb_mask,
1500 unsigned pd_min, unsigned pd_max,
1501 unsigned pd_even,
1502 unsigned *optimal_fb_div,
1503 unsigned *optimal_vclk_div,
1504 unsigned *optimal_dclk_div);
1505 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1506 unsigned cg_upll_func_cntl);
1507
1508 struct r600_audio {
1509 int channels;
1510 int rate;
1511 int bits_per_sample;
1512 u8 status_bits;
1513 u8 category_code;
1514 };
1515
1516 /*
1517 * Benchmarking
1518 */
1519 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1520
1521
1522 /*
1523 * Testing
1524 */
1525 void radeon_test_moves(struct radeon_device *rdev);
1526 void radeon_test_ring_sync(struct radeon_device *rdev,
1527 struct radeon_ring *cpA,
1528 struct radeon_ring *cpB);
1529 void radeon_test_syncing(struct radeon_device *rdev);
1530
1531
1532 /*
1533 * Debugfs
1534 */
1535 struct radeon_debugfs {
1536 struct drm_info_list *files;
1537 unsigned num_files;
1538 };
1539
1540 int radeon_debugfs_add_files(struct radeon_device *rdev,
1541 struct drm_info_list *files,
1542 unsigned nfiles);
1543 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1544
1545
1546 /*
1547 * ASIC specific functions.
1548 */
1549 struct radeon_asic {
1550 int (*init)(struct radeon_device *rdev);
1551 void (*fini)(struct radeon_device *rdev);
1552 int (*resume)(struct radeon_device *rdev);
1553 int (*suspend)(struct radeon_device *rdev);
1554 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1555 int (*asic_reset)(struct radeon_device *rdev);
1556 /* ioctl hw specific callback. Some hw might want to perform special
1557 * operation on specific ioctl. For instance on wait idle some hw
1558 * might want to perform and HDP flush through MMIO as it seems that
1559 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1560 * through ring.
1561 */
1562 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1563 /* check if 3D engine is idle */
1564 bool (*gui_idle)(struct radeon_device *rdev);
1565 /* wait for mc_idle */
1566 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1567 /* get the reference clock */
1568 u32 (*get_xclk)(struct radeon_device *rdev);
1569 /* get the gpu clock counter */
1570 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1571 /* gart */
1572 struct {
1573 void (*tlb_flush)(struct radeon_device *rdev);
1574 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1575 } gart;
1576 struct {
1577 int (*init)(struct radeon_device *rdev);
1578 void (*fini)(struct radeon_device *rdev);
1579
1580 u32 pt_ring_index;
1581 void (*set_page)(struct radeon_device *rdev,
1582 struct radeon_ib *ib,
1583 uint64_t pe,
1584 uint64_t addr, unsigned count,
1585 uint32_t incr, uint32_t flags);
1586 } vm;
1587 /* ring specific callbacks */
1588 struct {
1589 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1590 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1591 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1592 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1593 struct radeon_semaphore *semaphore, bool emit_wait);
1594 int (*cs_parse)(struct radeon_cs_parser *p);
1595 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1596 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1597 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1598 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1599 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1600
1601 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1602 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1603 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1604 } ring[RADEON_NUM_RINGS];
1605 /* irqs */
1606 struct {
1607 int (*set)(struct radeon_device *rdev);
1608 int (*process)(struct radeon_device *rdev);
1609 } irq;
1610 /* displays */
1611 struct {
1612 /* display watermarks */
1613 void (*bandwidth_update)(struct radeon_device *rdev);
1614 /* get frame count */
1615 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1616 /* wait for vblank */
1617 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1618 /* set backlight level */
1619 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1620 /* get backlight level */
1621 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1622 /* audio callbacks */
1623 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1624 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1625 } display;
1626 /* copy functions for bo handling */
1627 struct {
1628 int (*blit)(struct radeon_device *rdev,
1629 uint64_t src_offset,
1630 uint64_t dst_offset,
1631 unsigned num_gpu_pages,
1632 struct radeon_fence **fence);
1633 u32 blit_ring_index;
1634 int (*dma)(struct radeon_device *rdev,
1635 uint64_t src_offset,
1636 uint64_t dst_offset,
1637 unsigned num_gpu_pages,
1638 struct radeon_fence **fence);
1639 u32 dma_ring_index;
1640 /* method used for bo copy */
1641 int (*copy)(struct radeon_device *rdev,
1642 uint64_t src_offset,
1643 uint64_t dst_offset,
1644 unsigned num_gpu_pages,
1645 struct radeon_fence **fence);
1646 /* ring used for bo copies */
1647 u32 copy_ring_index;
1648 } copy;
1649 /* surfaces */
1650 struct {
1651 int (*set_reg)(struct radeon_device *rdev, int reg,
1652 uint32_t tiling_flags, uint32_t pitch,
1653 uint32_t offset, uint32_t obj_size);
1654 void (*clear_reg)(struct radeon_device *rdev, int reg);
1655 } surface;
1656 /* hotplug detect */
1657 struct {
1658 void (*init)(struct radeon_device *rdev);
1659 void (*fini)(struct radeon_device *rdev);
1660 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1661 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1662 } hpd;
1663 /* static power management */
1664 struct {
1665 void (*misc)(struct radeon_device *rdev);
1666 void (*prepare)(struct radeon_device *rdev);
1667 void (*finish)(struct radeon_device *rdev);
1668 void (*init_profile)(struct radeon_device *rdev);
1669 void (*get_dynpm_state)(struct radeon_device *rdev);
1670 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1671 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1672 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1673 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1674 int (*get_pcie_lanes)(struct radeon_device *rdev);
1675 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1676 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1677 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1678 int (*get_temperature)(struct radeon_device *rdev);
1679 } pm;
1680 /* dynamic power management */
1681 struct {
1682 int (*init)(struct radeon_device *rdev);
1683 void (*setup_asic)(struct radeon_device *rdev);
1684 int (*enable)(struct radeon_device *rdev);
1685 void (*disable)(struct radeon_device *rdev);
1686 int (*pre_set_power_state)(struct radeon_device *rdev);
1687 int (*set_power_state)(struct radeon_device *rdev);
1688 void (*post_set_power_state)(struct radeon_device *rdev);
1689 void (*display_configuration_changed)(struct radeon_device *rdev);
1690 void (*fini)(struct radeon_device *rdev);
1691 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1692 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1693 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1694 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1695 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1696 bool (*vblank_too_short)(struct radeon_device *rdev);
1697 } dpm;
1698 /* pageflipping */
1699 struct {
1700 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1701 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1702 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1703 } pflip;
1704 };
1705
1706 /*
1707 * Asic structures
1708 */
1709 struct r100_asic {
1710 const unsigned *reg_safe_bm;
1711 unsigned reg_safe_bm_size;
1712 u32 hdp_cntl;
1713 };
1714
1715 struct r300_asic {
1716 const unsigned *reg_safe_bm;
1717 unsigned reg_safe_bm_size;
1718 u32 resync_scratch;
1719 u32 hdp_cntl;
1720 };
1721
1722 struct r600_asic {
1723 unsigned max_pipes;
1724 unsigned max_tile_pipes;
1725 unsigned max_simds;
1726 unsigned max_backends;
1727 unsigned max_gprs;
1728 unsigned max_threads;
1729 unsigned max_stack_entries;
1730 unsigned max_hw_contexts;
1731 unsigned max_gs_threads;
1732 unsigned sx_max_export_size;
1733 unsigned sx_max_export_pos_size;
1734 unsigned sx_max_export_smx_size;
1735 unsigned sq_num_cf_insts;
1736 unsigned tiling_nbanks;
1737 unsigned tiling_npipes;
1738 unsigned tiling_group_size;
1739 unsigned tile_config;
1740 unsigned backend_map;
1741 };
1742
1743 struct rv770_asic {
1744 unsigned max_pipes;
1745 unsigned max_tile_pipes;
1746 unsigned max_simds;
1747 unsigned max_backends;
1748 unsigned max_gprs;
1749 unsigned max_threads;
1750 unsigned max_stack_entries;
1751 unsigned max_hw_contexts;
1752 unsigned max_gs_threads;
1753 unsigned sx_max_export_size;
1754 unsigned sx_max_export_pos_size;
1755 unsigned sx_max_export_smx_size;
1756 unsigned sq_num_cf_insts;
1757 unsigned sx_num_of_sets;
1758 unsigned sc_prim_fifo_size;
1759 unsigned sc_hiz_tile_fifo_size;
1760 unsigned sc_earlyz_tile_fifo_fize;
1761 unsigned tiling_nbanks;
1762 unsigned tiling_npipes;
1763 unsigned tiling_group_size;
1764 unsigned tile_config;
1765 unsigned backend_map;
1766 };
1767
1768 struct evergreen_asic {
1769 unsigned num_ses;
1770 unsigned max_pipes;
1771 unsigned max_tile_pipes;
1772 unsigned max_simds;
1773 unsigned max_backends;
1774 unsigned max_gprs;
1775 unsigned max_threads;
1776 unsigned max_stack_entries;
1777 unsigned max_hw_contexts;
1778 unsigned max_gs_threads;
1779 unsigned sx_max_export_size;
1780 unsigned sx_max_export_pos_size;
1781 unsigned sx_max_export_smx_size;
1782 unsigned sq_num_cf_insts;
1783 unsigned sx_num_of_sets;
1784 unsigned sc_prim_fifo_size;
1785 unsigned sc_hiz_tile_fifo_size;
1786 unsigned sc_earlyz_tile_fifo_size;
1787 unsigned tiling_nbanks;
1788 unsigned tiling_npipes;
1789 unsigned tiling_group_size;
1790 unsigned tile_config;
1791 unsigned backend_map;
1792 };
1793
1794 struct cayman_asic {
1795 unsigned max_shader_engines;
1796 unsigned max_pipes_per_simd;
1797 unsigned max_tile_pipes;
1798 unsigned max_simds_per_se;
1799 unsigned max_backends_per_se;
1800 unsigned max_texture_channel_caches;
1801 unsigned max_gprs;
1802 unsigned max_threads;
1803 unsigned max_gs_threads;
1804 unsigned max_stack_entries;
1805 unsigned sx_num_of_sets;
1806 unsigned sx_max_export_size;
1807 unsigned sx_max_export_pos_size;
1808 unsigned sx_max_export_smx_size;
1809 unsigned max_hw_contexts;
1810 unsigned sq_num_cf_insts;
1811 unsigned sc_prim_fifo_size;
1812 unsigned sc_hiz_tile_fifo_size;
1813 unsigned sc_earlyz_tile_fifo_size;
1814
1815 unsigned num_shader_engines;
1816 unsigned num_shader_pipes_per_simd;
1817 unsigned num_tile_pipes;
1818 unsigned num_simds_per_se;
1819 unsigned num_backends_per_se;
1820 unsigned backend_disable_mask_per_asic;
1821 unsigned backend_map;
1822 unsigned num_texture_channel_caches;
1823 unsigned mem_max_burst_length_bytes;
1824 unsigned mem_row_size_in_kb;
1825 unsigned shader_engine_tile_size;
1826 unsigned num_gpus;
1827 unsigned multi_gpu_tile_size;
1828
1829 unsigned tile_config;
1830 };
1831
1832 struct si_asic {
1833 unsigned max_shader_engines;
1834 unsigned max_tile_pipes;
1835 unsigned max_cu_per_sh;
1836 unsigned max_sh_per_se;
1837 unsigned max_backends_per_se;
1838 unsigned max_texture_channel_caches;
1839 unsigned max_gprs;
1840 unsigned max_gs_threads;
1841 unsigned max_hw_contexts;
1842 unsigned sc_prim_fifo_size_frontend;
1843 unsigned sc_prim_fifo_size_backend;
1844 unsigned sc_hiz_tile_fifo_size;
1845 unsigned sc_earlyz_tile_fifo_size;
1846
1847 unsigned num_tile_pipes;
1848 unsigned num_backends_per_se;
1849 unsigned backend_disable_mask_per_asic;
1850 unsigned backend_map;
1851 unsigned num_texture_channel_caches;
1852 unsigned mem_max_burst_length_bytes;
1853 unsigned mem_row_size_in_kb;
1854 unsigned shader_engine_tile_size;
1855 unsigned num_gpus;
1856 unsigned multi_gpu_tile_size;
1857
1858 unsigned tile_config;
1859 uint32_t tile_mode_array[32];
1860 };
1861
1862 struct cik_asic {
1863 unsigned max_shader_engines;
1864 unsigned max_tile_pipes;
1865 unsigned max_cu_per_sh;
1866 unsigned max_sh_per_se;
1867 unsigned max_backends_per_se;
1868 unsigned max_texture_channel_caches;
1869 unsigned max_gprs;
1870 unsigned max_gs_threads;
1871 unsigned max_hw_contexts;
1872 unsigned sc_prim_fifo_size_frontend;
1873 unsigned sc_prim_fifo_size_backend;
1874 unsigned sc_hiz_tile_fifo_size;
1875 unsigned sc_earlyz_tile_fifo_size;
1876
1877 unsigned num_tile_pipes;
1878 unsigned num_backends_per_se;
1879 unsigned backend_disable_mask_per_asic;
1880 unsigned backend_map;
1881 unsigned num_texture_channel_caches;
1882 unsigned mem_max_burst_length_bytes;
1883 unsigned mem_row_size_in_kb;
1884 unsigned shader_engine_tile_size;
1885 unsigned num_gpus;
1886 unsigned multi_gpu_tile_size;
1887
1888 unsigned tile_config;
1889 uint32_t tile_mode_array[32];
1890 };
1891
1892 union radeon_asic_config {
1893 struct r300_asic r300;
1894 struct r100_asic r100;
1895 struct r600_asic r600;
1896 struct rv770_asic rv770;
1897 struct evergreen_asic evergreen;
1898 struct cayman_asic cayman;
1899 struct si_asic si;
1900 struct cik_asic cik;
1901 };
1902
1903 /*
1904 * asic initizalization from radeon_asic.c
1905 */
1906 void radeon_agp_disable(struct radeon_device *rdev);
1907 int radeon_asic_init(struct radeon_device *rdev);
1908
1909
1910 /*
1911 * IOCTL.
1912 */
1913 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1914 struct drm_file *filp);
1915 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1916 struct drm_file *filp);
1917 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1918 struct drm_file *file_priv);
1919 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1920 struct drm_file *file_priv);
1921 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1922 struct drm_file *file_priv);
1923 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1924 struct drm_file *file_priv);
1925 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1926 struct drm_file *filp);
1927 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1928 struct drm_file *filp);
1929 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1930 struct drm_file *filp);
1931 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1932 struct drm_file *filp);
1933 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1934 struct drm_file *filp);
1935 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1936 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1937 struct drm_file *filp);
1938 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1939 struct drm_file *filp);
1940
1941 /* VRAM scratch page for HDP bug, default vram page */
1942 struct r600_vram_scratch {
1943 struct radeon_bo *robj;
1944 volatile uint32_t *ptr;
1945 u64 gpu_addr;
1946 };
1947
1948 /*
1949 * ACPI
1950 */
1951 struct radeon_atif_notification_cfg {
1952 bool enabled;
1953 int command_code;
1954 };
1955
1956 struct radeon_atif_notifications {
1957 bool display_switch;
1958 bool expansion_mode_change;
1959 bool thermal_state;
1960 bool forced_power_state;
1961 bool system_power_state;
1962 bool display_conf_change;
1963 bool px_gfx_switch;
1964 bool brightness_change;
1965 bool dgpu_display_event;
1966 };
1967
1968 struct radeon_atif_functions {
1969 bool system_params;
1970 bool sbios_requests;
1971 bool select_active_disp;
1972 bool lid_state;
1973 bool get_tv_standard;
1974 bool set_tv_standard;
1975 bool get_panel_expansion_mode;
1976 bool set_panel_expansion_mode;
1977 bool temperature_change;
1978 bool graphics_device_types;
1979 };
1980
1981 struct radeon_atif {
1982 struct radeon_atif_notifications notifications;
1983 struct radeon_atif_functions functions;
1984 struct radeon_atif_notification_cfg notification_cfg;
1985 struct radeon_encoder *encoder_for_bl;
1986 };
1987
1988 struct radeon_atcs_functions {
1989 bool get_ext_state;
1990 bool pcie_perf_req;
1991 bool pcie_dev_rdy;
1992 bool pcie_bus_width;
1993 };
1994
1995 struct radeon_atcs {
1996 struct radeon_atcs_functions functions;
1997 };
1998
1999 /*
2000 * Core structure, functions and helpers.
2001 */
2002 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2003 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2004
2005 struct radeon_device {
2006 struct device *dev;
2007 struct drm_device *ddev;
2008 struct pci_dev *pdev;
2009 struct rw_semaphore exclusive_lock;
2010 /* ASIC */
2011 union radeon_asic_config config;
2012 enum radeon_family family;
2013 unsigned long flags;
2014 int usec_timeout;
2015 enum radeon_pll_errata pll_errata;
2016 int num_gb_pipes;
2017 int num_z_pipes;
2018 int disp_priority;
2019 /* BIOS */
2020 uint8_t *bios;
2021 bool is_atom_bios;
2022 uint16_t bios_header_start;
2023 struct radeon_bo *stollen_vga_memory;
2024 /* Register mmio */
2025 resource_size_t rmmio_base;
2026 resource_size_t rmmio_size;
2027 /* protects concurrent MM_INDEX/DATA based register access */
2028 spinlock_t mmio_idx_lock;
2029 void __iomem *rmmio;
2030 radeon_rreg_t mc_rreg;
2031 radeon_wreg_t mc_wreg;
2032 radeon_rreg_t pll_rreg;
2033 radeon_wreg_t pll_wreg;
2034 uint32_t pcie_reg_mask;
2035 radeon_rreg_t pciep_rreg;
2036 radeon_wreg_t pciep_wreg;
2037 /* io port */
2038 void __iomem *rio_mem;
2039 resource_size_t rio_mem_size;
2040 struct radeon_clock clock;
2041 struct radeon_mc mc;
2042 struct radeon_gart gart;
2043 struct radeon_mode_info mode_info;
2044 struct radeon_scratch scratch;
2045 struct radeon_doorbell doorbell;
2046 struct radeon_mman mman;
2047 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2048 wait_queue_head_t fence_queue;
2049 struct mutex ring_lock;
2050 struct radeon_ring ring[RADEON_NUM_RINGS];
2051 bool ib_pool_ready;
2052 struct radeon_sa_manager ring_tmp_bo;
2053 struct radeon_irq irq;
2054 struct radeon_asic *asic;
2055 struct radeon_gem gem;
2056 struct radeon_pm pm;
2057 struct radeon_uvd uvd;
2058 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2059 struct radeon_wb wb;
2060 struct radeon_dummy_page dummy_page;
2061 bool shutdown;
2062 bool suspend;
2063 bool need_dma32;
2064 bool accel_working;
2065 bool fastfb_working; /* IGP feature*/
2066 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2067 const struct firmware *me_fw; /* all family ME firmware */
2068 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2069 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2070 const struct firmware *mc_fw; /* NI MC firmware */
2071 const struct firmware *ce_fw; /* SI CE firmware */
2072 const struct firmware *mec_fw; /* CIK MEC firmware */
2073 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2074 const struct firmware *smc_fw; /* SMC firmware */
2075 const struct firmware *uvd_fw; /* UVD firmware */
2076 struct r600_vram_scratch vram_scratch;
2077 int msi_enabled; /* msi enabled */
2078 struct r600_ih ih; /* r6/700 interrupt ring */
2079 struct radeon_rlc rlc;
2080 struct radeon_mec mec;
2081 struct work_struct hotplug_work;
2082 struct work_struct audio_work;
2083 struct work_struct reset_work;
2084 int num_crtc; /* number of crtcs */
2085 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2086 bool audio_enabled;
2087 bool has_uvd;
2088 struct r600_audio audio_status; /* audio stuff */
2089 struct notifier_block acpi_nb;
2090 /* only one userspace can use Hyperz features or CMASK at a time */
2091 struct drm_file *hyperz_filp;
2092 struct drm_file *cmask_filp;
2093 /* i2c buses */
2094 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2095 /* debugfs */
2096 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2097 unsigned debugfs_count;
2098 /* virtual memory */
2099 struct radeon_vm_manager vm_manager;
2100 struct mutex gpu_clock_mutex;
2101 /* ACPI interface */
2102 struct radeon_atif atif;
2103 struct radeon_atcs atcs;
2104 /* srbm instance registers */
2105 struct mutex srbm_mutex;
2106 };
2107
2108 int radeon_device_init(struct radeon_device *rdev,
2109 struct drm_device *ddev,
2110 struct pci_dev *pdev,
2111 uint32_t flags);
2112 void radeon_device_fini(struct radeon_device *rdev);
2113 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2114
2115 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2116 bool always_indirect);
2117 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2118 bool always_indirect);
2119 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2120 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2121
2122 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2123 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2124
2125 /*
2126 * Cast helper
2127 */
2128 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2129
2130 /*
2131 * Registers read & write functions.
2132 */
2133 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2134 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2135 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2136 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2137 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2138 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2139 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2140 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2141 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2142 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2143 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2144 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2145 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2146 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2147 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2148 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2149 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2150 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2151 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2152 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2153 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2154 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2155 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2156 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2157 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2158 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2159 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2160 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2161 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2162 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2163 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2164 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2165 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2166 #define WREG32_P(reg, val, mask) \
2167 do { \
2168 uint32_t tmp_ = RREG32(reg); \
2169 tmp_ &= (mask); \
2170 tmp_ |= ((val) & ~(mask)); \
2171 WREG32(reg, tmp_); \
2172 } while (0)
2173 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2174 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2175 #define WREG32_PLL_P(reg, val, mask) \
2176 do { \
2177 uint32_t tmp_ = RREG32_PLL(reg); \
2178 tmp_ &= (mask); \
2179 tmp_ |= ((val) & ~(mask)); \
2180 WREG32_PLL(reg, tmp_); \
2181 } while (0)
2182 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2183 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2184 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2185
2186 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2187 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2188
2189 /*
2190 * Indirect registers accessor
2191 */
2192 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2193 {
2194 uint32_t r;
2195
2196 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2197 r = RREG32(RADEON_PCIE_DATA);
2198 return r;
2199 }
2200
2201 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2202 {
2203 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2204 WREG32(RADEON_PCIE_DATA, (v));
2205 }
2206
2207 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2208 {
2209 u32 r;
2210
2211 WREG32(TN_SMC_IND_INDEX_0, (reg));
2212 r = RREG32(TN_SMC_IND_DATA_0);
2213 return r;
2214 }
2215
2216 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2217 {
2218 WREG32(TN_SMC_IND_INDEX_0, (reg));
2219 WREG32(TN_SMC_IND_DATA_0, (v));
2220 }
2221
2222 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2223 {
2224 u32 r;
2225
2226 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2227 r = RREG32(R600_RCU_DATA);
2228 return r;
2229 }
2230
2231 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2232 {
2233 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2234 WREG32(R600_RCU_DATA, (v));
2235 }
2236
2237 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2238 {
2239 u32 r;
2240
2241 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2242 r = RREG32(EVERGREEN_CG_IND_DATA);
2243 return r;
2244 }
2245
2246 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2247 {
2248 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2249 WREG32(EVERGREEN_CG_IND_DATA, (v));
2250 }
2251
2252 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2253 {
2254 u32 r;
2255
2256 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2257 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2258 return r;
2259 }
2260
2261 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2262 {
2263 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2264 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2265 }
2266
2267 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2268 {
2269 u32 r;
2270
2271 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2272 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2273 return r;
2274 }
2275
2276 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2277 {
2278 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2279 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2280 }
2281
2282 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2283 {
2284 u32 r;
2285
2286 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2287 r = RREG32(R600_UVD_CTX_DATA);
2288 return r;
2289 }
2290
2291 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2292 {
2293 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2294 WREG32(R600_UVD_CTX_DATA, (v));
2295 }
2296
2297
2298 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2299 {
2300 u32 r;
2301
2302 WREG32(CIK_DIDT_IND_INDEX, (reg));
2303 r = RREG32(CIK_DIDT_IND_DATA);
2304 return r;
2305 }
2306
2307 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2308 {
2309 WREG32(CIK_DIDT_IND_INDEX, (reg));
2310 WREG32(CIK_DIDT_IND_DATA, (v));
2311 }
2312
2313 void r100_pll_errata_after_index(struct radeon_device *rdev);
2314
2315
2316 /*
2317 * ASICs helpers.
2318 */
2319 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2320 (rdev->pdev->device == 0x5969))
2321 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2322 (rdev->family == CHIP_RV200) || \
2323 (rdev->family == CHIP_RS100) || \
2324 (rdev->family == CHIP_RS200) || \
2325 (rdev->family == CHIP_RV250) || \
2326 (rdev->family == CHIP_RV280) || \
2327 (rdev->family == CHIP_RS300))
2328 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2329 (rdev->family == CHIP_RV350) || \
2330 (rdev->family == CHIP_R350) || \
2331 (rdev->family == CHIP_RV380) || \
2332 (rdev->family == CHIP_R420) || \
2333 (rdev->family == CHIP_R423) || \
2334 (rdev->family == CHIP_RV410) || \
2335 (rdev->family == CHIP_RS400) || \
2336 (rdev->family == CHIP_RS480))
2337 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2338 (rdev->ddev->pdev->device == 0x9443) || \
2339 (rdev->ddev->pdev->device == 0x944B) || \
2340 (rdev->ddev->pdev->device == 0x9506) || \
2341 (rdev->ddev->pdev->device == 0x9509) || \
2342 (rdev->ddev->pdev->device == 0x950F) || \
2343 (rdev->ddev->pdev->device == 0x689C) || \
2344 (rdev->ddev->pdev->device == 0x689D))
2345 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2346 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2347 (rdev->family == CHIP_RS690) || \
2348 (rdev->family == CHIP_RS740) || \
2349 (rdev->family >= CHIP_R600))
2350 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2351 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2352 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2353 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2354 (rdev->flags & RADEON_IS_IGP))
2355 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2356 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2357 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2358 (rdev->flags & RADEON_IS_IGP))
2359 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2360 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2361 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2362
2363 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2364 (rdev->ddev->pdev->device == 0x6850) || \
2365 (rdev->ddev->pdev->device == 0x6858) || \
2366 (rdev->ddev->pdev->device == 0x6859) || \
2367 (rdev->ddev->pdev->device == 0x6840) || \
2368 (rdev->ddev->pdev->device == 0x6841) || \
2369 (rdev->ddev->pdev->device == 0x6842) || \
2370 (rdev->ddev->pdev->device == 0x6843))
2371
2372 /*
2373 * BIOS helpers.
2374 */
2375 #define RBIOS8(i) (rdev->bios[i])
2376 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2377 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2378
2379 int radeon_combios_init(struct radeon_device *rdev);
2380 void radeon_combios_fini(struct radeon_device *rdev);
2381 int radeon_atombios_init(struct radeon_device *rdev);
2382 void radeon_atombios_fini(struct radeon_device *rdev);
2383
2384
2385 /*
2386 * RING helpers.
2387 */
2388 #if DRM_DEBUG_CODE == 0
2389 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2390 {
2391 ring->ring[ring->wptr++] = v;
2392 ring->wptr &= ring->ptr_mask;
2393 ring->count_dw--;
2394 ring->ring_free_dw--;
2395 }
2396 #else
2397 /* With debugging this is just too big to inline */
2398 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2399 #endif
2400
2401 /*
2402 * ASICs macro.
2403 */
2404 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2405 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2406 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2407 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2408 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
2409 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2410 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2411 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2412 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2413 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2414 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2415 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2416 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
2417 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
2418 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
2419 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
2420 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
2421 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
2422 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
2423 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
2424 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
2425 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
2426 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2427 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2428 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2429 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2430 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2431 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2432 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2433 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
2434 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2435 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2436 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2437 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2438 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2439 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2440 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2441 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2442 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2443 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2444 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2445 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2446 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2447 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2448 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2449 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2450 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2451 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2452 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2453 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2454 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2455 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2456 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2457 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2458 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2459 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2460 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2461 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2462 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2463 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2464 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2465 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2466 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2467 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2468 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2469 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2470 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2471 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2472 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2473 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2474 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2475 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2476 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2477 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2478 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2479 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2480 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2481 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2482 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2483 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2484 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2485
2486 /* Common functions */
2487 /* AGP */
2488 extern int radeon_gpu_reset(struct radeon_device *rdev);
2489 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2490 extern void radeon_agp_disable(struct radeon_device *rdev);
2491 extern int radeon_modeset_init(struct radeon_device *rdev);
2492 extern void radeon_modeset_fini(struct radeon_device *rdev);
2493 extern bool radeon_card_posted(struct radeon_device *rdev);
2494 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2495 extern void radeon_update_display_priority(struct radeon_device *rdev);
2496 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2497 extern void radeon_scratch_init(struct radeon_device *rdev);
2498 extern void radeon_wb_fini(struct radeon_device *rdev);
2499 extern int radeon_wb_init(struct radeon_device *rdev);
2500 extern void radeon_wb_disable(struct radeon_device *rdev);
2501 extern void radeon_surface_init(struct radeon_device *rdev);
2502 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2503 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2504 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2505 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2506 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2507 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2508 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2509 extern int radeon_resume_kms(struct drm_device *dev);
2510 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
2511 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2512 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2513 const u32 *registers,
2514 const u32 array_size);
2515
2516 /*
2517 * vm
2518 */
2519 int radeon_vm_manager_init(struct radeon_device *rdev);
2520 void radeon_vm_manager_fini(struct radeon_device *rdev);
2521 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2522 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2523 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2524 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2525 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2526 struct radeon_vm *vm, int ring);
2527 void radeon_vm_fence(struct radeon_device *rdev,
2528 struct radeon_vm *vm,
2529 struct radeon_fence *fence);
2530 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2531 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2532 struct radeon_vm *vm,
2533 struct radeon_bo *bo,
2534 struct ttm_mem_reg *mem);
2535 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2536 struct radeon_bo *bo);
2537 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2538 struct radeon_bo *bo);
2539 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2540 struct radeon_vm *vm,
2541 struct radeon_bo *bo);
2542 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2543 struct radeon_bo_va *bo_va,
2544 uint64_t offset,
2545 uint32_t flags);
2546 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2547 struct radeon_bo_va *bo_va);
2548
2549 /* audio */
2550 void r600_audio_update_hdmi(struct work_struct *work);
2551
2552 /*
2553 * R600 vram scratch functions
2554 */
2555 int r600_vram_scratch_init(struct radeon_device *rdev);
2556 void r600_vram_scratch_fini(struct radeon_device *rdev);
2557
2558 /*
2559 * r600 cs checking helper
2560 */
2561 unsigned r600_mip_minify(unsigned size, unsigned level);
2562 bool r600_fmt_is_valid_color(u32 format);
2563 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2564 int r600_fmt_get_blocksize(u32 format);
2565 int r600_fmt_get_nblocksx(u32 format, u32 w);
2566 int r600_fmt_get_nblocksy(u32 format, u32 h);
2567
2568 /*
2569 * r600 functions used by radeon_encoder.c
2570 */
2571 struct radeon_hdmi_acr {
2572 u32 clock;
2573
2574 int n_32khz;
2575 int cts_32khz;
2576
2577 int n_44_1khz;
2578 int cts_44_1khz;
2579
2580 int n_48khz;
2581 int cts_48khz;
2582
2583 };
2584
2585 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2586
2587 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2588 u32 tiling_pipe_num,
2589 u32 max_rb_num,
2590 u32 total_max_rb_num,
2591 u32 enabled_rb_mask);
2592
2593 /*
2594 * evergreen functions used by radeon_encoder.c
2595 */
2596
2597 extern int ni_init_microcode(struct radeon_device *rdev);
2598 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2599
2600 /* radeon_acpi.c */
2601 #if defined(CONFIG_ACPI)
2602 extern int radeon_acpi_init(struct radeon_device *rdev);
2603 extern void radeon_acpi_fini(struct radeon_device *rdev);
2604 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2605 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2606 u8 perf_req, bool advertise);
2607 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2608 #else
2609 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2610 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2611 #endif
2612
2613 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2614 struct radeon_cs_packet *pkt,
2615 unsigned idx);
2616 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2617 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2618 struct radeon_cs_packet *pkt);
2619 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2620 struct radeon_cs_reloc **cs_reloc,
2621 int nomm);
2622 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2623 uint32_t *vline_start_end,
2624 uint32_t *vline_status);
2625
2626 #include "radeon_object.h"
2627
2628 #endif
Linux kernel - Deliverables
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