2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/console.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
37 #include "radeon_asic.h"
41 * Registers accessors functions.
44 * radeon_invalid_rreg - dummy reg read function
46 * @rdev: radeon device pointer
47 * @reg: offset of register
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
53 static uint32_t radeon_invalid_rreg(struct radeon_device
*rdev
, uint32_t reg
)
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
61 * radeon_invalid_wreg - dummy reg write function
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
70 static void radeon_invalid_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
78 * radeon_register_accessor_init - sets up the register accessor callbacks
80 * @rdev: radeon device pointer
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
85 static void radeon_register_accessor_init(struct radeon_device
*rdev
)
87 rdev
->mc_rreg
= &radeon_invalid_rreg
;
88 rdev
->mc_wreg
= &radeon_invalid_wreg
;
89 rdev
->pll_rreg
= &radeon_invalid_rreg
;
90 rdev
->pll_wreg
= &radeon_invalid_wreg
;
91 rdev
->pciep_rreg
= &radeon_invalid_rreg
;
92 rdev
->pciep_wreg
= &radeon_invalid_wreg
;
94 /* Don't change order as we are overridding accessor. */
95 if (rdev
->family
< CHIP_RV515
) {
96 rdev
->pcie_reg_mask
= 0xff;
98 rdev
->pcie_reg_mask
= 0x7ff;
100 /* FIXME: not sure here */
101 if (rdev
->family
<= CHIP_R580
) {
102 rdev
->pll_rreg
= &r100_pll_rreg
;
103 rdev
->pll_wreg
= &r100_pll_wreg
;
105 if (rdev
->family
>= CHIP_R420
) {
106 rdev
->mc_rreg
= &r420_mc_rreg
;
107 rdev
->mc_wreg
= &r420_mc_wreg
;
109 if (rdev
->family
>= CHIP_RV515
) {
110 rdev
->mc_rreg
= &rv515_mc_rreg
;
111 rdev
->mc_wreg
= &rv515_mc_wreg
;
113 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
114 rdev
->mc_rreg
= &rs400_mc_rreg
;
115 rdev
->mc_wreg
= &rs400_mc_wreg
;
117 if (rdev
->family
== CHIP_RS690
|| rdev
->family
== CHIP_RS740
) {
118 rdev
->mc_rreg
= &rs690_mc_rreg
;
119 rdev
->mc_wreg
= &rs690_mc_wreg
;
121 if (rdev
->family
== CHIP_RS600
) {
122 rdev
->mc_rreg
= &rs600_mc_rreg
;
123 rdev
->mc_wreg
= &rs600_mc_wreg
;
125 if (rdev
->family
== CHIP_RS780
|| rdev
->family
== CHIP_RS880
) {
126 rdev
->mc_rreg
= &rs780_mc_rreg
;
127 rdev
->mc_wreg
= &rs780_mc_wreg
;
130 if (rdev
->family
>= CHIP_BONAIRE
) {
131 rdev
->pciep_rreg
= &cik_pciep_rreg
;
132 rdev
->pciep_wreg
= &cik_pciep_wreg
;
133 } else if (rdev
->family
>= CHIP_R600
) {
134 rdev
->pciep_rreg
= &r600_pciep_rreg
;
135 rdev
->pciep_wreg
= &r600_pciep_wreg
;
140 /* helper to disable agp */
142 * radeon_agp_disable - AGP disable helper function
144 * @rdev: radeon device pointer
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
149 void radeon_agp_disable(struct radeon_device
*rdev
)
151 rdev
->flags
&= ~RADEON_IS_AGP
;
152 if (rdev
->family
>= CHIP_R600
) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev
->flags
|= RADEON_IS_PCIE
;
155 } else if (rdev
->family
>= CHIP_RV515
||
156 rdev
->family
== CHIP_RV380
||
157 rdev
->family
== CHIP_RV410
||
158 rdev
->family
== CHIP_R423
) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev
->flags
|= RADEON_IS_PCIE
;
161 rdev
->asic
->gart
.tlb_flush
= &rv370_pcie_gart_tlb_flush
;
162 rdev
->asic
->gart
.get_page_entry
= &rv370_pcie_gart_get_page_entry
;
163 rdev
->asic
->gart
.set_page
= &rv370_pcie_gart_set_page
;
165 DRM_INFO("Forcing AGP to PCI mode\n");
166 rdev
->flags
|= RADEON_IS_PCI
;
167 rdev
->asic
->gart
.tlb_flush
= &r100_pci_gart_tlb_flush
;
168 rdev
->asic
->gart
.get_page_entry
= &r100_pci_gart_get_page_entry
;
169 rdev
->asic
->gart
.set_page
= &r100_pci_gart_set_page
;
171 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
178 static struct radeon_asic_ring r100_gfx_ring
= {
179 .ib_execute
= &r100_ring_ib_execute
,
180 .emit_fence
= &r100_fence_ring_emit
,
181 .emit_semaphore
= &r100_semaphore_ring_emit
,
182 .cs_parse
= &r100_cs_parse
,
183 .ring_start
= &r100_ring_start
,
184 .ring_test
= &r100_ring_test
,
185 .ib_test
= &r100_ib_test
,
186 .is_lockup
= &r100_gpu_is_lockup
,
187 .get_rptr
= &r100_gfx_get_rptr
,
188 .get_wptr
= &r100_gfx_get_wptr
,
189 .set_wptr
= &r100_gfx_set_wptr
,
192 static struct radeon_asic r100_asic
= {
195 .suspend
= &r100_suspend
,
196 .resume
= &r100_resume
,
197 .vga_set_state
= &r100_vga_set_state
,
198 .asic_reset
= &r100_asic_reset
,
199 .mmio_hdp_flush
= NULL
,
200 .gui_idle
= &r100_gui_idle
,
201 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
203 .tlb_flush
= &r100_pci_gart_tlb_flush
,
204 .get_page_entry
= &r100_pci_gart_get_page_entry
,
205 .set_page
= &r100_pci_gart_set_page
,
208 [RADEON_RING_TYPE_GFX_INDEX
] = &r100_gfx_ring
211 .set
= &r100_irq_set
,
212 .process
= &r100_irq_process
,
215 .bandwidth_update
= &r100_bandwidth_update
,
216 .get_vblank_counter
= &r100_get_vblank_counter
,
217 .wait_for_vblank
= &r100_wait_for_vblank
,
218 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
219 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
222 .blit
= &r100_copy_blit
,
223 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
225 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
226 .copy
= &r100_copy_blit
,
227 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
230 .set_reg
= r100_set_surface_reg
,
231 .clear_reg
= r100_clear_surface_reg
,
234 .init
= &r100_hpd_init
,
235 .fini
= &r100_hpd_fini
,
236 .sense
= &r100_hpd_sense
,
237 .set_polarity
= &r100_hpd_set_polarity
,
240 .misc
= &r100_pm_misc
,
241 .prepare
= &r100_pm_prepare
,
242 .finish
= &r100_pm_finish
,
243 .init_profile
= &r100_pm_init_profile
,
244 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
245 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
246 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
247 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
248 .set_memory_clock
= NULL
,
249 .get_pcie_lanes
= NULL
,
250 .set_pcie_lanes
= NULL
,
251 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
254 .page_flip
= &r100_page_flip
,
255 .page_flip_pending
= &r100_page_flip_pending
,
259 static struct radeon_asic r200_asic
= {
262 .suspend
= &r100_suspend
,
263 .resume
= &r100_resume
,
264 .vga_set_state
= &r100_vga_set_state
,
265 .asic_reset
= &r100_asic_reset
,
266 .mmio_hdp_flush
= NULL
,
267 .gui_idle
= &r100_gui_idle
,
268 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
270 .tlb_flush
= &r100_pci_gart_tlb_flush
,
271 .get_page_entry
= &r100_pci_gart_get_page_entry
,
272 .set_page
= &r100_pci_gart_set_page
,
275 [RADEON_RING_TYPE_GFX_INDEX
] = &r100_gfx_ring
278 .set
= &r100_irq_set
,
279 .process
= &r100_irq_process
,
282 .bandwidth_update
= &r100_bandwidth_update
,
283 .get_vblank_counter
= &r100_get_vblank_counter
,
284 .wait_for_vblank
= &r100_wait_for_vblank
,
285 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
286 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
289 .blit
= &r100_copy_blit
,
290 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
291 .dma
= &r200_copy_dma
,
292 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
293 .copy
= &r100_copy_blit
,
294 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
297 .set_reg
= r100_set_surface_reg
,
298 .clear_reg
= r100_clear_surface_reg
,
301 .init
= &r100_hpd_init
,
302 .fini
= &r100_hpd_fini
,
303 .sense
= &r100_hpd_sense
,
304 .set_polarity
= &r100_hpd_set_polarity
,
307 .misc
= &r100_pm_misc
,
308 .prepare
= &r100_pm_prepare
,
309 .finish
= &r100_pm_finish
,
310 .init_profile
= &r100_pm_init_profile
,
311 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
312 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
313 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
314 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
315 .set_memory_clock
= NULL
,
316 .get_pcie_lanes
= NULL
,
317 .set_pcie_lanes
= NULL
,
318 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
321 .page_flip
= &r100_page_flip
,
322 .page_flip_pending
= &r100_page_flip_pending
,
326 static struct radeon_asic_ring r300_gfx_ring
= {
327 .ib_execute
= &r100_ring_ib_execute
,
328 .emit_fence
= &r300_fence_ring_emit
,
329 .emit_semaphore
= &r100_semaphore_ring_emit
,
330 .cs_parse
= &r300_cs_parse
,
331 .ring_start
= &r300_ring_start
,
332 .ring_test
= &r100_ring_test
,
333 .ib_test
= &r100_ib_test
,
334 .is_lockup
= &r100_gpu_is_lockup
,
335 .get_rptr
= &r100_gfx_get_rptr
,
336 .get_wptr
= &r100_gfx_get_wptr
,
337 .set_wptr
= &r100_gfx_set_wptr
,
340 static struct radeon_asic_ring rv515_gfx_ring
= {
341 .ib_execute
= &r100_ring_ib_execute
,
342 .emit_fence
= &r300_fence_ring_emit
,
343 .emit_semaphore
= &r100_semaphore_ring_emit
,
344 .cs_parse
= &r300_cs_parse
,
345 .ring_start
= &rv515_ring_start
,
346 .ring_test
= &r100_ring_test
,
347 .ib_test
= &r100_ib_test
,
348 .is_lockup
= &r100_gpu_is_lockup
,
349 .get_rptr
= &r100_gfx_get_rptr
,
350 .get_wptr
= &r100_gfx_get_wptr
,
351 .set_wptr
= &r100_gfx_set_wptr
,
354 static struct radeon_asic r300_asic
= {
357 .suspend
= &r300_suspend
,
358 .resume
= &r300_resume
,
359 .vga_set_state
= &r100_vga_set_state
,
360 .asic_reset
= &r300_asic_reset
,
361 .mmio_hdp_flush
= NULL
,
362 .gui_idle
= &r100_gui_idle
,
363 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
365 .tlb_flush
= &r100_pci_gart_tlb_flush
,
366 .get_page_entry
= &r100_pci_gart_get_page_entry
,
367 .set_page
= &r100_pci_gart_set_page
,
370 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
373 .set
= &r100_irq_set
,
374 .process
= &r100_irq_process
,
377 .bandwidth_update
= &r100_bandwidth_update
,
378 .get_vblank_counter
= &r100_get_vblank_counter
,
379 .wait_for_vblank
= &r100_wait_for_vblank
,
380 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
381 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
384 .blit
= &r100_copy_blit
,
385 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
386 .dma
= &r200_copy_dma
,
387 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
388 .copy
= &r100_copy_blit
,
389 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
392 .set_reg
= r100_set_surface_reg
,
393 .clear_reg
= r100_clear_surface_reg
,
396 .init
= &r100_hpd_init
,
397 .fini
= &r100_hpd_fini
,
398 .sense
= &r100_hpd_sense
,
399 .set_polarity
= &r100_hpd_set_polarity
,
402 .misc
= &r100_pm_misc
,
403 .prepare
= &r100_pm_prepare
,
404 .finish
= &r100_pm_finish
,
405 .init_profile
= &r100_pm_init_profile
,
406 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
407 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
408 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
409 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
410 .set_memory_clock
= NULL
,
411 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
412 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
413 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
416 .page_flip
= &r100_page_flip
,
417 .page_flip_pending
= &r100_page_flip_pending
,
421 static struct radeon_asic r300_asic_pcie
= {
424 .suspend
= &r300_suspend
,
425 .resume
= &r300_resume
,
426 .vga_set_state
= &r100_vga_set_state
,
427 .asic_reset
= &r300_asic_reset
,
428 .mmio_hdp_flush
= NULL
,
429 .gui_idle
= &r100_gui_idle
,
430 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
432 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
433 .get_page_entry
= &rv370_pcie_gart_get_page_entry
,
434 .set_page
= &rv370_pcie_gart_set_page
,
437 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
440 .set
= &r100_irq_set
,
441 .process
= &r100_irq_process
,
444 .bandwidth_update
= &r100_bandwidth_update
,
445 .get_vblank_counter
= &r100_get_vblank_counter
,
446 .wait_for_vblank
= &r100_wait_for_vblank
,
447 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
448 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
451 .blit
= &r100_copy_blit
,
452 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
453 .dma
= &r200_copy_dma
,
454 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
455 .copy
= &r100_copy_blit
,
456 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
459 .set_reg
= r100_set_surface_reg
,
460 .clear_reg
= r100_clear_surface_reg
,
463 .init
= &r100_hpd_init
,
464 .fini
= &r100_hpd_fini
,
465 .sense
= &r100_hpd_sense
,
466 .set_polarity
= &r100_hpd_set_polarity
,
469 .misc
= &r100_pm_misc
,
470 .prepare
= &r100_pm_prepare
,
471 .finish
= &r100_pm_finish
,
472 .init_profile
= &r100_pm_init_profile
,
473 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
474 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
475 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
476 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
477 .set_memory_clock
= NULL
,
478 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
479 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
480 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
483 .page_flip
= &r100_page_flip
,
484 .page_flip_pending
= &r100_page_flip_pending
,
488 static struct radeon_asic r420_asic
= {
491 .suspend
= &r420_suspend
,
492 .resume
= &r420_resume
,
493 .vga_set_state
= &r100_vga_set_state
,
494 .asic_reset
= &r300_asic_reset
,
495 .mmio_hdp_flush
= NULL
,
496 .gui_idle
= &r100_gui_idle
,
497 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
499 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
500 .get_page_entry
= &rv370_pcie_gart_get_page_entry
,
501 .set_page
= &rv370_pcie_gart_set_page
,
504 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
507 .set
= &r100_irq_set
,
508 .process
= &r100_irq_process
,
511 .bandwidth_update
= &r100_bandwidth_update
,
512 .get_vblank_counter
= &r100_get_vblank_counter
,
513 .wait_for_vblank
= &r100_wait_for_vblank
,
514 .set_backlight_level
= &atombios_set_backlight_level
,
515 .get_backlight_level
= &atombios_get_backlight_level
,
518 .blit
= &r100_copy_blit
,
519 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
520 .dma
= &r200_copy_dma
,
521 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
522 .copy
= &r100_copy_blit
,
523 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
526 .set_reg
= r100_set_surface_reg
,
527 .clear_reg
= r100_clear_surface_reg
,
530 .init
= &r100_hpd_init
,
531 .fini
= &r100_hpd_fini
,
532 .sense
= &r100_hpd_sense
,
533 .set_polarity
= &r100_hpd_set_polarity
,
536 .misc
= &r100_pm_misc
,
537 .prepare
= &r100_pm_prepare
,
538 .finish
= &r100_pm_finish
,
539 .init_profile
= &r420_pm_init_profile
,
540 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
541 .get_engine_clock
= &radeon_atom_get_engine_clock
,
542 .set_engine_clock
= &radeon_atom_set_engine_clock
,
543 .get_memory_clock
= &radeon_atom_get_memory_clock
,
544 .set_memory_clock
= &radeon_atom_set_memory_clock
,
545 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
546 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
547 .set_clock_gating
= &radeon_atom_set_clock_gating
,
550 .page_flip
= &r100_page_flip
,
551 .page_flip_pending
= &r100_page_flip_pending
,
555 static struct radeon_asic rs400_asic
= {
558 .suspend
= &rs400_suspend
,
559 .resume
= &rs400_resume
,
560 .vga_set_state
= &r100_vga_set_state
,
561 .asic_reset
= &r300_asic_reset
,
562 .mmio_hdp_flush
= NULL
,
563 .gui_idle
= &r100_gui_idle
,
564 .mc_wait_for_idle
= &rs400_mc_wait_for_idle
,
566 .tlb_flush
= &rs400_gart_tlb_flush
,
567 .get_page_entry
= &rs400_gart_get_page_entry
,
568 .set_page
= &rs400_gart_set_page
,
571 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
574 .set
= &r100_irq_set
,
575 .process
= &r100_irq_process
,
578 .bandwidth_update
= &r100_bandwidth_update
,
579 .get_vblank_counter
= &r100_get_vblank_counter
,
580 .wait_for_vblank
= &r100_wait_for_vblank
,
581 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
582 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
585 .blit
= &r100_copy_blit
,
586 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
587 .dma
= &r200_copy_dma
,
588 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
589 .copy
= &r100_copy_blit
,
590 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
593 .set_reg
= r100_set_surface_reg
,
594 .clear_reg
= r100_clear_surface_reg
,
597 .init
= &r100_hpd_init
,
598 .fini
= &r100_hpd_fini
,
599 .sense
= &r100_hpd_sense
,
600 .set_polarity
= &r100_hpd_set_polarity
,
603 .misc
= &r100_pm_misc
,
604 .prepare
= &r100_pm_prepare
,
605 .finish
= &r100_pm_finish
,
606 .init_profile
= &r100_pm_init_profile
,
607 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
608 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
609 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
610 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
611 .set_memory_clock
= NULL
,
612 .get_pcie_lanes
= NULL
,
613 .set_pcie_lanes
= NULL
,
614 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
617 .page_flip
= &r100_page_flip
,
618 .page_flip_pending
= &r100_page_flip_pending
,
622 static struct radeon_asic rs600_asic
= {
625 .suspend
= &rs600_suspend
,
626 .resume
= &rs600_resume
,
627 .vga_set_state
= &r100_vga_set_state
,
628 .asic_reset
= &rs600_asic_reset
,
629 .mmio_hdp_flush
= NULL
,
630 .gui_idle
= &r100_gui_idle
,
631 .mc_wait_for_idle
= &rs600_mc_wait_for_idle
,
633 .tlb_flush
= &rs600_gart_tlb_flush
,
634 .get_page_entry
= &rs600_gart_get_page_entry
,
635 .set_page
= &rs600_gart_set_page
,
638 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
641 .set
= &rs600_irq_set
,
642 .process
= &rs600_irq_process
,
645 .bandwidth_update
= &rs600_bandwidth_update
,
646 .get_vblank_counter
= &rs600_get_vblank_counter
,
647 .wait_for_vblank
= &avivo_wait_for_vblank
,
648 .set_backlight_level
= &atombios_set_backlight_level
,
649 .get_backlight_level
= &atombios_get_backlight_level
,
652 .blit
= &r100_copy_blit
,
653 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
654 .dma
= &r200_copy_dma
,
655 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
656 .copy
= &r100_copy_blit
,
657 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
660 .set_reg
= r100_set_surface_reg
,
661 .clear_reg
= r100_clear_surface_reg
,
664 .init
= &rs600_hpd_init
,
665 .fini
= &rs600_hpd_fini
,
666 .sense
= &rs600_hpd_sense
,
667 .set_polarity
= &rs600_hpd_set_polarity
,
670 .misc
= &rs600_pm_misc
,
671 .prepare
= &rs600_pm_prepare
,
672 .finish
= &rs600_pm_finish
,
673 .init_profile
= &r420_pm_init_profile
,
674 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
675 .get_engine_clock
= &radeon_atom_get_engine_clock
,
676 .set_engine_clock
= &radeon_atom_set_engine_clock
,
677 .get_memory_clock
= &radeon_atom_get_memory_clock
,
678 .set_memory_clock
= &radeon_atom_set_memory_clock
,
679 .get_pcie_lanes
= NULL
,
680 .set_pcie_lanes
= NULL
,
681 .set_clock_gating
= &radeon_atom_set_clock_gating
,
684 .page_flip
= &rs600_page_flip
,
685 .page_flip_pending
= &rs600_page_flip_pending
,
689 static struct radeon_asic rs690_asic
= {
692 .suspend
= &rs690_suspend
,
693 .resume
= &rs690_resume
,
694 .vga_set_state
= &r100_vga_set_state
,
695 .asic_reset
= &rs600_asic_reset
,
696 .mmio_hdp_flush
= NULL
,
697 .gui_idle
= &r100_gui_idle
,
698 .mc_wait_for_idle
= &rs690_mc_wait_for_idle
,
700 .tlb_flush
= &rs400_gart_tlb_flush
,
701 .get_page_entry
= &rs400_gart_get_page_entry
,
702 .set_page
= &rs400_gart_set_page
,
705 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
708 .set
= &rs600_irq_set
,
709 .process
= &rs600_irq_process
,
712 .get_vblank_counter
= &rs600_get_vblank_counter
,
713 .bandwidth_update
= &rs690_bandwidth_update
,
714 .wait_for_vblank
= &avivo_wait_for_vblank
,
715 .set_backlight_level
= &atombios_set_backlight_level
,
716 .get_backlight_level
= &atombios_get_backlight_level
,
719 .blit
= &r100_copy_blit
,
720 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
721 .dma
= &r200_copy_dma
,
722 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
723 .copy
= &r200_copy_dma
,
724 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
727 .set_reg
= r100_set_surface_reg
,
728 .clear_reg
= r100_clear_surface_reg
,
731 .init
= &rs600_hpd_init
,
732 .fini
= &rs600_hpd_fini
,
733 .sense
= &rs600_hpd_sense
,
734 .set_polarity
= &rs600_hpd_set_polarity
,
737 .misc
= &rs600_pm_misc
,
738 .prepare
= &rs600_pm_prepare
,
739 .finish
= &rs600_pm_finish
,
740 .init_profile
= &r420_pm_init_profile
,
741 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
742 .get_engine_clock
= &radeon_atom_get_engine_clock
,
743 .set_engine_clock
= &radeon_atom_set_engine_clock
,
744 .get_memory_clock
= &radeon_atom_get_memory_clock
,
745 .set_memory_clock
= &radeon_atom_set_memory_clock
,
746 .get_pcie_lanes
= NULL
,
747 .set_pcie_lanes
= NULL
,
748 .set_clock_gating
= &radeon_atom_set_clock_gating
,
751 .page_flip
= &rs600_page_flip
,
752 .page_flip_pending
= &rs600_page_flip_pending
,
756 static struct radeon_asic rv515_asic
= {
759 .suspend
= &rv515_suspend
,
760 .resume
= &rv515_resume
,
761 .vga_set_state
= &r100_vga_set_state
,
762 .asic_reset
= &rs600_asic_reset
,
763 .mmio_hdp_flush
= NULL
,
764 .gui_idle
= &r100_gui_idle
,
765 .mc_wait_for_idle
= &rv515_mc_wait_for_idle
,
767 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
768 .get_page_entry
= &rv370_pcie_gart_get_page_entry
,
769 .set_page
= &rv370_pcie_gart_set_page
,
772 [RADEON_RING_TYPE_GFX_INDEX
] = &rv515_gfx_ring
775 .set
= &rs600_irq_set
,
776 .process
= &rs600_irq_process
,
779 .get_vblank_counter
= &rs600_get_vblank_counter
,
780 .bandwidth_update
= &rv515_bandwidth_update
,
781 .wait_for_vblank
= &avivo_wait_for_vblank
,
782 .set_backlight_level
= &atombios_set_backlight_level
,
783 .get_backlight_level
= &atombios_get_backlight_level
,
786 .blit
= &r100_copy_blit
,
787 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
788 .dma
= &r200_copy_dma
,
789 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
790 .copy
= &r100_copy_blit
,
791 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
794 .set_reg
= r100_set_surface_reg
,
795 .clear_reg
= r100_clear_surface_reg
,
798 .init
= &rs600_hpd_init
,
799 .fini
= &rs600_hpd_fini
,
800 .sense
= &rs600_hpd_sense
,
801 .set_polarity
= &rs600_hpd_set_polarity
,
804 .misc
= &rs600_pm_misc
,
805 .prepare
= &rs600_pm_prepare
,
806 .finish
= &rs600_pm_finish
,
807 .init_profile
= &r420_pm_init_profile
,
808 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
809 .get_engine_clock
= &radeon_atom_get_engine_clock
,
810 .set_engine_clock
= &radeon_atom_set_engine_clock
,
811 .get_memory_clock
= &radeon_atom_get_memory_clock
,
812 .set_memory_clock
= &radeon_atom_set_memory_clock
,
813 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
814 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
815 .set_clock_gating
= &radeon_atom_set_clock_gating
,
818 .page_flip
= &rs600_page_flip
,
819 .page_flip_pending
= &rs600_page_flip_pending
,
823 static struct radeon_asic r520_asic
= {
826 .suspend
= &rv515_suspend
,
827 .resume
= &r520_resume
,
828 .vga_set_state
= &r100_vga_set_state
,
829 .asic_reset
= &rs600_asic_reset
,
830 .mmio_hdp_flush
= NULL
,
831 .gui_idle
= &r100_gui_idle
,
832 .mc_wait_for_idle
= &r520_mc_wait_for_idle
,
834 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
835 .get_page_entry
= &rv370_pcie_gart_get_page_entry
,
836 .set_page
= &rv370_pcie_gart_set_page
,
839 [RADEON_RING_TYPE_GFX_INDEX
] = &rv515_gfx_ring
842 .set
= &rs600_irq_set
,
843 .process
= &rs600_irq_process
,
846 .bandwidth_update
= &rv515_bandwidth_update
,
847 .get_vblank_counter
= &rs600_get_vblank_counter
,
848 .wait_for_vblank
= &avivo_wait_for_vblank
,
849 .set_backlight_level
= &atombios_set_backlight_level
,
850 .get_backlight_level
= &atombios_get_backlight_level
,
853 .blit
= &r100_copy_blit
,
854 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
855 .dma
= &r200_copy_dma
,
856 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
857 .copy
= &r100_copy_blit
,
858 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
861 .set_reg
= r100_set_surface_reg
,
862 .clear_reg
= r100_clear_surface_reg
,
865 .init
= &rs600_hpd_init
,
866 .fini
= &rs600_hpd_fini
,
867 .sense
= &rs600_hpd_sense
,
868 .set_polarity
= &rs600_hpd_set_polarity
,
871 .misc
= &rs600_pm_misc
,
872 .prepare
= &rs600_pm_prepare
,
873 .finish
= &rs600_pm_finish
,
874 .init_profile
= &r420_pm_init_profile
,
875 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
876 .get_engine_clock
= &radeon_atom_get_engine_clock
,
877 .set_engine_clock
= &radeon_atom_set_engine_clock
,
878 .get_memory_clock
= &radeon_atom_get_memory_clock
,
879 .set_memory_clock
= &radeon_atom_set_memory_clock
,
880 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
881 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
882 .set_clock_gating
= &radeon_atom_set_clock_gating
,
885 .page_flip
= &rs600_page_flip
,
886 .page_flip_pending
= &rs600_page_flip_pending
,
890 static struct radeon_asic_ring r600_gfx_ring
= {
891 .ib_execute
= &r600_ring_ib_execute
,
892 .emit_fence
= &r600_fence_ring_emit
,
893 .emit_semaphore
= &r600_semaphore_ring_emit
,
894 .cs_parse
= &r600_cs_parse
,
895 .ring_test
= &r600_ring_test
,
896 .ib_test
= &r600_ib_test
,
897 .is_lockup
= &r600_gfx_is_lockup
,
898 .get_rptr
= &r600_gfx_get_rptr
,
899 .get_wptr
= &r600_gfx_get_wptr
,
900 .set_wptr
= &r600_gfx_set_wptr
,
903 static struct radeon_asic_ring r600_dma_ring
= {
904 .ib_execute
= &r600_dma_ring_ib_execute
,
905 .emit_fence
= &r600_dma_fence_ring_emit
,
906 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
907 .cs_parse
= &r600_dma_cs_parse
,
908 .ring_test
= &r600_dma_ring_test
,
909 .ib_test
= &r600_dma_ib_test
,
910 .is_lockup
= &r600_dma_is_lockup
,
911 .get_rptr
= &r600_dma_get_rptr
,
912 .get_wptr
= &r600_dma_get_wptr
,
913 .set_wptr
= &r600_dma_set_wptr
,
916 static struct radeon_asic r600_asic
= {
919 .suspend
= &r600_suspend
,
920 .resume
= &r600_resume
,
921 .vga_set_state
= &r600_vga_set_state
,
922 .asic_reset
= &r600_asic_reset
,
923 .mmio_hdp_flush
= r600_mmio_hdp_flush
,
924 .gui_idle
= &r600_gui_idle
,
925 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
926 .get_xclk
= &r600_get_xclk
,
927 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
929 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
930 .get_page_entry
= &rs600_gart_get_page_entry
,
931 .set_page
= &rs600_gart_set_page
,
934 [RADEON_RING_TYPE_GFX_INDEX
] = &r600_gfx_ring
,
935 [R600_RING_TYPE_DMA_INDEX
] = &r600_dma_ring
,
938 .set
= &r600_irq_set
,
939 .process
= &r600_irq_process
,
942 .bandwidth_update
= &rv515_bandwidth_update
,
943 .get_vblank_counter
= &rs600_get_vblank_counter
,
944 .wait_for_vblank
= &avivo_wait_for_vblank
,
945 .set_backlight_level
= &atombios_set_backlight_level
,
946 .get_backlight_level
= &atombios_get_backlight_level
,
949 .blit
= &r600_copy_cpdma
,
950 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
951 .dma
= &r600_copy_dma
,
952 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
953 .copy
= &r600_copy_cpdma
,
954 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
957 .set_reg
= r600_set_surface_reg
,
958 .clear_reg
= r600_clear_surface_reg
,
961 .init
= &r600_hpd_init
,
962 .fini
= &r600_hpd_fini
,
963 .sense
= &r600_hpd_sense
,
964 .set_polarity
= &r600_hpd_set_polarity
,
967 .misc
= &r600_pm_misc
,
968 .prepare
= &rs600_pm_prepare
,
969 .finish
= &rs600_pm_finish
,
970 .init_profile
= &r600_pm_init_profile
,
971 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
972 .get_engine_clock
= &radeon_atom_get_engine_clock
,
973 .set_engine_clock
= &radeon_atom_set_engine_clock
,
974 .get_memory_clock
= &radeon_atom_get_memory_clock
,
975 .set_memory_clock
= &radeon_atom_set_memory_clock
,
976 .get_pcie_lanes
= &r600_get_pcie_lanes
,
977 .set_pcie_lanes
= &r600_set_pcie_lanes
,
978 .set_clock_gating
= NULL
,
979 .get_temperature
= &rv6xx_get_temp
,
982 .page_flip
= &rs600_page_flip
,
983 .page_flip_pending
= &rs600_page_flip_pending
,
987 static struct radeon_asic_ring rv6xx_uvd_ring
= {
988 .ib_execute
= &uvd_v1_0_ib_execute
,
989 .emit_fence
= &uvd_v1_0_fence_emit
,
990 .emit_semaphore
= &uvd_v1_0_semaphore_emit
,
991 .cs_parse
= &radeon_uvd_cs_parse
,
992 .ring_test
= &uvd_v1_0_ring_test
,
993 .ib_test
= &uvd_v1_0_ib_test
,
994 .is_lockup
= &radeon_ring_test_lockup
,
995 .get_rptr
= &uvd_v1_0_get_rptr
,
996 .get_wptr
= &uvd_v1_0_get_wptr
,
997 .set_wptr
= &uvd_v1_0_set_wptr
,
1000 static struct radeon_asic rv6xx_asic
= {
1003 .suspend
= &r600_suspend
,
1004 .resume
= &r600_resume
,
1005 .vga_set_state
= &r600_vga_set_state
,
1006 .asic_reset
= &r600_asic_reset
,
1007 .mmio_hdp_flush
= r600_mmio_hdp_flush
,
1008 .gui_idle
= &r600_gui_idle
,
1009 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1010 .get_xclk
= &r600_get_xclk
,
1011 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1013 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1014 .get_page_entry
= &rs600_gart_get_page_entry
,
1015 .set_page
= &rs600_gart_set_page
,
1018 [RADEON_RING_TYPE_GFX_INDEX
] = &r600_gfx_ring
,
1019 [R600_RING_TYPE_DMA_INDEX
] = &r600_dma_ring
,
1020 [R600_RING_TYPE_UVD_INDEX
] = &rv6xx_uvd_ring
,
1023 .set
= &r600_irq_set
,
1024 .process
= &r600_irq_process
,
1027 .bandwidth_update
= &rv515_bandwidth_update
,
1028 .get_vblank_counter
= &rs600_get_vblank_counter
,
1029 .wait_for_vblank
= &avivo_wait_for_vblank
,
1030 .set_backlight_level
= &atombios_set_backlight_level
,
1031 .get_backlight_level
= &atombios_get_backlight_level
,
1034 .blit
= &r600_copy_cpdma
,
1035 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1036 .dma
= &r600_copy_dma
,
1037 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1038 .copy
= &r600_copy_cpdma
,
1039 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1042 .set_reg
= r600_set_surface_reg
,
1043 .clear_reg
= r600_clear_surface_reg
,
1046 .init
= &r600_hpd_init
,
1047 .fini
= &r600_hpd_fini
,
1048 .sense
= &r600_hpd_sense
,
1049 .set_polarity
= &r600_hpd_set_polarity
,
1052 .misc
= &r600_pm_misc
,
1053 .prepare
= &rs600_pm_prepare
,
1054 .finish
= &rs600_pm_finish
,
1055 .init_profile
= &r600_pm_init_profile
,
1056 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1057 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1058 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1059 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1060 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1061 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1062 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1063 .set_clock_gating
= NULL
,
1064 .get_temperature
= &rv6xx_get_temp
,
1065 .set_uvd_clocks
= &r600_set_uvd_clocks
,
1068 .init
= &rv6xx_dpm_init
,
1069 .setup_asic
= &rv6xx_setup_asic
,
1070 .enable
= &rv6xx_dpm_enable
,
1071 .late_enable
= &r600_dpm_late_enable
,
1072 .disable
= &rv6xx_dpm_disable
,
1073 .pre_set_power_state
= &r600_dpm_pre_set_power_state
,
1074 .set_power_state
= &rv6xx_dpm_set_power_state
,
1075 .post_set_power_state
= &r600_dpm_post_set_power_state
,
1076 .display_configuration_changed
= &rv6xx_dpm_display_configuration_changed
,
1077 .fini
= &rv6xx_dpm_fini
,
1078 .get_sclk
= &rv6xx_dpm_get_sclk
,
1079 .get_mclk
= &rv6xx_dpm_get_mclk
,
1080 .print_power_state
= &rv6xx_dpm_print_power_state
,
1081 .debugfs_print_current_performance_level
= &rv6xx_dpm_debugfs_print_current_performance_level
,
1082 .force_performance_level
= &rv6xx_dpm_force_performance_level
,
1083 .get_current_sclk
= &rv6xx_dpm_get_current_sclk
,
1084 .get_current_mclk
= &rv6xx_dpm_get_current_mclk
,
1087 .page_flip
= &rs600_page_flip
,
1088 .page_flip_pending
= &rs600_page_flip_pending
,
1092 static struct radeon_asic rs780_asic
= {
1095 .suspend
= &r600_suspend
,
1096 .resume
= &r600_resume
,
1097 .vga_set_state
= &r600_vga_set_state
,
1098 .asic_reset
= &r600_asic_reset
,
1099 .mmio_hdp_flush
= r600_mmio_hdp_flush
,
1100 .gui_idle
= &r600_gui_idle
,
1101 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1102 .get_xclk
= &r600_get_xclk
,
1103 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1105 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1106 .get_page_entry
= &rs600_gart_get_page_entry
,
1107 .set_page
= &rs600_gart_set_page
,
1110 [RADEON_RING_TYPE_GFX_INDEX
] = &r600_gfx_ring
,
1111 [R600_RING_TYPE_DMA_INDEX
] = &r600_dma_ring
,
1112 [R600_RING_TYPE_UVD_INDEX
] = &rv6xx_uvd_ring
,
1115 .set
= &r600_irq_set
,
1116 .process
= &r600_irq_process
,
1119 .bandwidth_update
= &rs690_bandwidth_update
,
1120 .get_vblank_counter
= &rs600_get_vblank_counter
,
1121 .wait_for_vblank
= &avivo_wait_for_vblank
,
1122 .set_backlight_level
= &atombios_set_backlight_level
,
1123 .get_backlight_level
= &atombios_get_backlight_level
,
1126 .blit
= &r600_copy_cpdma
,
1127 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1128 .dma
= &r600_copy_dma
,
1129 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1130 .copy
= &r600_copy_cpdma
,
1131 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1134 .set_reg
= r600_set_surface_reg
,
1135 .clear_reg
= r600_clear_surface_reg
,
1138 .init
= &r600_hpd_init
,
1139 .fini
= &r600_hpd_fini
,
1140 .sense
= &r600_hpd_sense
,
1141 .set_polarity
= &r600_hpd_set_polarity
,
1144 .misc
= &r600_pm_misc
,
1145 .prepare
= &rs600_pm_prepare
,
1146 .finish
= &rs600_pm_finish
,
1147 .init_profile
= &rs780_pm_init_profile
,
1148 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1149 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1150 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1151 .get_memory_clock
= NULL
,
1152 .set_memory_clock
= NULL
,
1153 .get_pcie_lanes
= NULL
,
1154 .set_pcie_lanes
= NULL
,
1155 .set_clock_gating
= NULL
,
1156 .get_temperature
= &rv6xx_get_temp
,
1157 .set_uvd_clocks
= &r600_set_uvd_clocks
,
1160 .init
= &rs780_dpm_init
,
1161 .setup_asic
= &rs780_dpm_setup_asic
,
1162 .enable
= &rs780_dpm_enable
,
1163 .late_enable
= &r600_dpm_late_enable
,
1164 .disable
= &rs780_dpm_disable
,
1165 .pre_set_power_state
= &r600_dpm_pre_set_power_state
,
1166 .set_power_state
= &rs780_dpm_set_power_state
,
1167 .post_set_power_state
= &r600_dpm_post_set_power_state
,
1168 .display_configuration_changed
= &rs780_dpm_display_configuration_changed
,
1169 .fini
= &rs780_dpm_fini
,
1170 .get_sclk
= &rs780_dpm_get_sclk
,
1171 .get_mclk
= &rs780_dpm_get_mclk
,
1172 .print_power_state
= &rs780_dpm_print_power_state
,
1173 .debugfs_print_current_performance_level
= &rs780_dpm_debugfs_print_current_performance_level
,
1174 .force_performance_level
= &rs780_dpm_force_performance_level
,
1175 .get_current_sclk
= &rs780_dpm_get_current_sclk
,
1176 .get_current_mclk
= &rs780_dpm_get_current_mclk
,
1179 .page_flip
= &rs600_page_flip
,
1180 .page_flip_pending
= &rs600_page_flip_pending
,
1184 static struct radeon_asic_ring rv770_uvd_ring
= {
1185 .ib_execute
= &uvd_v1_0_ib_execute
,
1186 .emit_fence
= &uvd_v2_2_fence_emit
,
1187 .emit_semaphore
= &uvd_v1_0_semaphore_emit
,
1188 .cs_parse
= &radeon_uvd_cs_parse
,
1189 .ring_test
= &uvd_v1_0_ring_test
,
1190 .ib_test
= &uvd_v1_0_ib_test
,
1191 .is_lockup
= &radeon_ring_test_lockup
,
1192 .get_rptr
= &uvd_v1_0_get_rptr
,
1193 .get_wptr
= &uvd_v1_0_get_wptr
,
1194 .set_wptr
= &uvd_v1_0_set_wptr
,
1197 static struct radeon_asic rv770_asic
= {
1198 .init
= &rv770_init
,
1199 .fini
= &rv770_fini
,
1200 .suspend
= &rv770_suspend
,
1201 .resume
= &rv770_resume
,
1202 .asic_reset
= &r600_asic_reset
,
1203 .vga_set_state
= &r600_vga_set_state
,
1204 .mmio_hdp_flush
= r600_mmio_hdp_flush
,
1205 .gui_idle
= &r600_gui_idle
,
1206 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1207 .get_xclk
= &rv770_get_xclk
,
1208 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1210 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1211 .get_page_entry
= &rs600_gart_get_page_entry
,
1212 .set_page
= &rs600_gart_set_page
,
1215 [RADEON_RING_TYPE_GFX_INDEX
] = &r600_gfx_ring
,
1216 [R600_RING_TYPE_DMA_INDEX
] = &r600_dma_ring
,
1217 [R600_RING_TYPE_UVD_INDEX
] = &rv770_uvd_ring
,
1220 .set
= &r600_irq_set
,
1221 .process
= &r600_irq_process
,
1224 .bandwidth_update
= &rv515_bandwidth_update
,
1225 .get_vblank_counter
= &rs600_get_vblank_counter
,
1226 .wait_for_vblank
= &avivo_wait_for_vblank
,
1227 .set_backlight_level
= &atombios_set_backlight_level
,
1228 .get_backlight_level
= &atombios_get_backlight_level
,
1231 .blit
= &r600_copy_cpdma
,
1232 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1233 .dma
= &rv770_copy_dma
,
1234 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1235 .copy
= &rv770_copy_dma
,
1236 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1239 .set_reg
= r600_set_surface_reg
,
1240 .clear_reg
= r600_clear_surface_reg
,
1243 .init
= &r600_hpd_init
,
1244 .fini
= &r600_hpd_fini
,
1245 .sense
= &r600_hpd_sense
,
1246 .set_polarity
= &r600_hpd_set_polarity
,
1249 .misc
= &rv770_pm_misc
,
1250 .prepare
= &rs600_pm_prepare
,
1251 .finish
= &rs600_pm_finish
,
1252 .init_profile
= &r600_pm_init_profile
,
1253 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1254 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1255 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1256 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1257 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1258 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1259 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1260 .set_clock_gating
= &radeon_atom_set_clock_gating
,
1261 .set_uvd_clocks
= &rv770_set_uvd_clocks
,
1262 .get_temperature
= &rv770_get_temp
,
1265 .init
= &rv770_dpm_init
,
1266 .setup_asic
= &rv770_dpm_setup_asic
,
1267 .enable
= &rv770_dpm_enable
,
1268 .late_enable
= &rv770_dpm_late_enable
,
1269 .disable
= &rv770_dpm_disable
,
1270 .pre_set_power_state
= &r600_dpm_pre_set_power_state
,
1271 .set_power_state
= &rv770_dpm_set_power_state
,
1272 .post_set_power_state
= &r600_dpm_post_set_power_state
,
1273 .display_configuration_changed
= &rv770_dpm_display_configuration_changed
,
1274 .fini
= &rv770_dpm_fini
,
1275 .get_sclk
= &rv770_dpm_get_sclk
,
1276 .get_mclk
= &rv770_dpm_get_mclk
,
1277 .print_power_state
= &rv770_dpm_print_power_state
,
1278 .debugfs_print_current_performance_level
= &rv770_dpm_debugfs_print_current_performance_level
,
1279 .force_performance_level
= &rv770_dpm_force_performance_level
,
1280 .vblank_too_short
= &rv770_dpm_vblank_too_short
,
1281 .get_current_sclk
= &rv770_dpm_get_current_sclk
,
1282 .get_current_mclk
= &rv770_dpm_get_current_mclk
,
1285 .page_flip
= &rv770_page_flip
,
1286 .page_flip_pending
= &rv770_page_flip_pending
,
1290 static struct radeon_asic_ring evergreen_gfx_ring
= {
1291 .ib_execute
= &evergreen_ring_ib_execute
,
1292 .emit_fence
= &r600_fence_ring_emit
,
1293 .emit_semaphore
= &r600_semaphore_ring_emit
,
1294 .cs_parse
= &evergreen_cs_parse
,
1295 .ring_test
= &r600_ring_test
,
1296 .ib_test
= &r600_ib_test
,
1297 .is_lockup
= &evergreen_gfx_is_lockup
,
1298 .get_rptr
= &r600_gfx_get_rptr
,
1299 .get_wptr
= &r600_gfx_get_wptr
,
1300 .set_wptr
= &r600_gfx_set_wptr
,
1303 static struct radeon_asic_ring evergreen_dma_ring
= {
1304 .ib_execute
= &evergreen_dma_ring_ib_execute
,
1305 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1306 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1307 .cs_parse
= &evergreen_dma_cs_parse
,
1308 .ring_test
= &r600_dma_ring_test
,
1309 .ib_test
= &r600_dma_ib_test
,
1310 .is_lockup
= &evergreen_dma_is_lockup
,
1311 .get_rptr
= &r600_dma_get_rptr
,
1312 .get_wptr
= &r600_dma_get_wptr
,
1313 .set_wptr
= &r600_dma_set_wptr
,
1316 static struct radeon_asic evergreen_asic
= {
1317 .init
= &evergreen_init
,
1318 .fini
= &evergreen_fini
,
1319 .suspend
= &evergreen_suspend
,
1320 .resume
= &evergreen_resume
,
1321 .asic_reset
= &evergreen_asic_reset
,
1322 .vga_set_state
= &r600_vga_set_state
,
1323 .mmio_hdp_flush
= r600_mmio_hdp_flush
,
1324 .gui_idle
= &r600_gui_idle
,
1325 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1326 .get_xclk
= &rv770_get_xclk
,
1327 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1329 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1330 .get_page_entry
= &rs600_gart_get_page_entry
,
1331 .set_page
= &rs600_gart_set_page
,
1334 [RADEON_RING_TYPE_GFX_INDEX
] = &evergreen_gfx_ring
,
1335 [R600_RING_TYPE_DMA_INDEX
] = &evergreen_dma_ring
,
1336 [R600_RING_TYPE_UVD_INDEX
] = &rv770_uvd_ring
,
1339 .set
= &evergreen_irq_set
,
1340 .process
= &evergreen_irq_process
,
1343 .bandwidth_update
= &evergreen_bandwidth_update
,
1344 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1345 .wait_for_vblank
= &dce4_wait_for_vblank
,
1346 .set_backlight_level
= &atombios_set_backlight_level
,
1347 .get_backlight_level
= &atombios_get_backlight_level
,
1350 .blit
= &r600_copy_cpdma
,
1351 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1352 .dma
= &evergreen_copy_dma
,
1353 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1354 .copy
= &evergreen_copy_dma
,
1355 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1358 .set_reg
= r600_set_surface_reg
,
1359 .clear_reg
= r600_clear_surface_reg
,
1362 .init
= &evergreen_hpd_init
,
1363 .fini
= &evergreen_hpd_fini
,
1364 .sense
= &evergreen_hpd_sense
,
1365 .set_polarity
= &evergreen_hpd_set_polarity
,
1368 .misc
= &evergreen_pm_misc
,
1369 .prepare
= &evergreen_pm_prepare
,
1370 .finish
= &evergreen_pm_finish
,
1371 .init_profile
= &r600_pm_init_profile
,
1372 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1373 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1374 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1375 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1376 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1377 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1378 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1379 .set_clock_gating
= NULL
,
1380 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1381 .get_temperature
= &evergreen_get_temp
,
1384 .init
= &cypress_dpm_init
,
1385 .setup_asic
= &cypress_dpm_setup_asic
,
1386 .enable
= &cypress_dpm_enable
,
1387 .late_enable
= &rv770_dpm_late_enable
,
1388 .disable
= &cypress_dpm_disable
,
1389 .pre_set_power_state
= &r600_dpm_pre_set_power_state
,
1390 .set_power_state
= &cypress_dpm_set_power_state
,
1391 .post_set_power_state
= &r600_dpm_post_set_power_state
,
1392 .display_configuration_changed
= &cypress_dpm_display_configuration_changed
,
1393 .fini
= &cypress_dpm_fini
,
1394 .get_sclk
= &rv770_dpm_get_sclk
,
1395 .get_mclk
= &rv770_dpm_get_mclk
,
1396 .print_power_state
= &rv770_dpm_print_power_state
,
1397 .debugfs_print_current_performance_level
= &rv770_dpm_debugfs_print_current_performance_level
,
1398 .force_performance_level
= &rv770_dpm_force_performance_level
,
1399 .vblank_too_short
= &cypress_dpm_vblank_too_short
,
1400 .get_current_sclk
= &rv770_dpm_get_current_sclk
,
1401 .get_current_mclk
= &rv770_dpm_get_current_mclk
,
1404 .page_flip
= &evergreen_page_flip
,
1405 .page_flip_pending
= &evergreen_page_flip_pending
,
1409 static struct radeon_asic sumo_asic
= {
1410 .init
= &evergreen_init
,
1411 .fini
= &evergreen_fini
,
1412 .suspend
= &evergreen_suspend
,
1413 .resume
= &evergreen_resume
,
1414 .asic_reset
= &evergreen_asic_reset
,
1415 .vga_set_state
= &r600_vga_set_state
,
1416 .mmio_hdp_flush
= r600_mmio_hdp_flush
,
1417 .gui_idle
= &r600_gui_idle
,
1418 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1419 .get_xclk
= &r600_get_xclk
,
1420 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1422 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1423 .get_page_entry
= &rs600_gart_get_page_entry
,
1424 .set_page
= &rs600_gart_set_page
,
1427 [RADEON_RING_TYPE_GFX_INDEX
] = &evergreen_gfx_ring
,
1428 [R600_RING_TYPE_DMA_INDEX
] = &evergreen_dma_ring
,
1429 [R600_RING_TYPE_UVD_INDEX
] = &rv770_uvd_ring
,
1432 .set
= &evergreen_irq_set
,
1433 .process
= &evergreen_irq_process
,
1436 .bandwidth_update
= &evergreen_bandwidth_update
,
1437 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1438 .wait_for_vblank
= &dce4_wait_for_vblank
,
1439 .set_backlight_level
= &atombios_set_backlight_level
,
1440 .get_backlight_level
= &atombios_get_backlight_level
,
1443 .blit
= &r600_copy_cpdma
,
1444 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1445 .dma
= &evergreen_copy_dma
,
1446 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1447 .copy
= &evergreen_copy_dma
,
1448 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1451 .set_reg
= r600_set_surface_reg
,
1452 .clear_reg
= r600_clear_surface_reg
,
1455 .init
= &evergreen_hpd_init
,
1456 .fini
= &evergreen_hpd_fini
,
1457 .sense
= &evergreen_hpd_sense
,
1458 .set_polarity
= &evergreen_hpd_set_polarity
,
1461 .misc
= &evergreen_pm_misc
,
1462 .prepare
= &evergreen_pm_prepare
,
1463 .finish
= &evergreen_pm_finish
,
1464 .init_profile
= &sumo_pm_init_profile
,
1465 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1466 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1467 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1468 .get_memory_clock
= NULL
,
1469 .set_memory_clock
= NULL
,
1470 .get_pcie_lanes
= NULL
,
1471 .set_pcie_lanes
= NULL
,
1472 .set_clock_gating
= NULL
,
1473 .set_uvd_clocks
= &sumo_set_uvd_clocks
,
1474 .get_temperature
= &sumo_get_temp
,
1477 .init
= &sumo_dpm_init
,
1478 .setup_asic
= &sumo_dpm_setup_asic
,
1479 .enable
= &sumo_dpm_enable
,
1480 .late_enable
= &sumo_dpm_late_enable
,
1481 .disable
= &sumo_dpm_disable
,
1482 .pre_set_power_state
= &sumo_dpm_pre_set_power_state
,
1483 .set_power_state
= &sumo_dpm_set_power_state
,
1484 .post_set_power_state
= &sumo_dpm_post_set_power_state
,
1485 .display_configuration_changed
= &sumo_dpm_display_configuration_changed
,
1486 .fini
= &sumo_dpm_fini
,
1487 .get_sclk
= &sumo_dpm_get_sclk
,
1488 .get_mclk
= &sumo_dpm_get_mclk
,
1489 .print_power_state
= &sumo_dpm_print_power_state
,
1490 .debugfs_print_current_performance_level
= &sumo_dpm_debugfs_print_current_performance_level
,
1491 .force_performance_level
= &sumo_dpm_force_performance_level
,
1494 .page_flip
= &evergreen_page_flip
,
1495 .page_flip_pending
= &evergreen_page_flip_pending
,
1499 static struct radeon_asic btc_asic
= {
1500 .init
= &evergreen_init
,
1501 .fini
= &evergreen_fini
,
1502 .suspend
= &evergreen_suspend
,
1503 .resume
= &evergreen_resume
,
1504 .asic_reset
= &evergreen_asic_reset
,
1505 .vga_set_state
= &r600_vga_set_state
,
1506 .mmio_hdp_flush
= r600_mmio_hdp_flush
,
1507 .gui_idle
= &r600_gui_idle
,
1508 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1509 .get_xclk
= &rv770_get_xclk
,
1510 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1512 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1513 .get_page_entry
= &rs600_gart_get_page_entry
,
1514 .set_page
= &rs600_gart_set_page
,
1517 [RADEON_RING_TYPE_GFX_INDEX
] = &evergreen_gfx_ring
,
1518 [R600_RING_TYPE_DMA_INDEX
] = &evergreen_dma_ring
,
1519 [R600_RING_TYPE_UVD_INDEX
] = &rv770_uvd_ring
,
1522 .set
= &evergreen_irq_set
,
1523 .process
= &evergreen_irq_process
,
1526 .bandwidth_update
= &evergreen_bandwidth_update
,
1527 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1528 .wait_for_vblank
= &dce4_wait_for_vblank
,
1529 .set_backlight_level
= &atombios_set_backlight_level
,
1530 .get_backlight_level
= &atombios_get_backlight_level
,
1533 .blit
= &r600_copy_cpdma
,
1534 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1535 .dma
= &evergreen_copy_dma
,
1536 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1537 .copy
= &evergreen_copy_dma
,
1538 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1541 .set_reg
= r600_set_surface_reg
,
1542 .clear_reg
= r600_clear_surface_reg
,
1545 .init
= &evergreen_hpd_init
,
1546 .fini
= &evergreen_hpd_fini
,
1547 .sense
= &evergreen_hpd_sense
,
1548 .set_polarity
= &evergreen_hpd_set_polarity
,
1551 .misc
= &evergreen_pm_misc
,
1552 .prepare
= &evergreen_pm_prepare
,
1553 .finish
= &evergreen_pm_finish
,
1554 .init_profile
= &btc_pm_init_profile
,
1555 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1556 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1557 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1558 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1559 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1560 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1561 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1562 .set_clock_gating
= NULL
,
1563 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1564 .get_temperature
= &evergreen_get_temp
,
1567 .init
= &btc_dpm_init
,
1568 .setup_asic
= &btc_dpm_setup_asic
,
1569 .enable
= &btc_dpm_enable
,
1570 .late_enable
= &rv770_dpm_late_enable
,
1571 .disable
= &btc_dpm_disable
,
1572 .pre_set_power_state
= &btc_dpm_pre_set_power_state
,
1573 .set_power_state
= &btc_dpm_set_power_state
,
1574 .post_set_power_state
= &btc_dpm_post_set_power_state
,
1575 .display_configuration_changed
= &cypress_dpm_display_configuration_changed
,
1576 .fini
= &btc_dpm_fini
,
1577 .get_sclk
= &btc_dpm_get_sclk
,
1578 .get_mclk
= &btc_dpm_get_mclk
,
1579 .print_power_state
= &rv770_dpm_print_power_state
,
1580 .debugfs_print_current_performance_level
= &btc_dpm_debugfs_print_current_performance_level
,
1581 .force_performance_level
= &rv770_dpm_force_performance_level
,
1582 .vblank_too_short
= &btc_dpm_vblank_too_short
,
1585 .page_flip
= &evergreen_page_flip
,
1586 .page_flip_pending
= &evergreen_page_flip_pending
,
1590 static struct radeon_asic_ring cayman_gfx_ring
= {
1591 .ib_execute
= &cayman_ring_ib_execute
,
1592 .ib_parse
= &evergreen_ib_parse
,
1593 .emit_fence
= &cayman_fence_ring_emit
,
1594 .emit_semaphore
= &r600_semaphore_ring_emit
,
1595 .cs_parse
= &evergreen_cs_parse
,
1596 .ring_test
= &r600_ring_test
,
1597 .ib_test
= &r600_ib_test
,
1598 .is_lockup
= &cayman_gfx_is_lockup
,
1599 .vm_flush
= &cayman_vm_flush
,
1600 .get_rptr
= &cayman_gfx_get_rptr
,
1601 .get_wptr
= &cayman_gfx_get_wptr
,
1602 .set_wptr
= &cayman_gfx_set_wptr
,
1605 static struct radeon_asic_ring cayman_dma_ring
= {
1606 .ib_execute
= &cayman_dma_ring_ib_execute
,
1607 .ib_parse
= &evergreen_dma_ib_parse
,
1608 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1609 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1610 .cs_parse
= &evergreen_dma_cs_parse
,
1611 .ring_test
= &r600_dma_ring_test
,
1612 .ib_test
= &r600_dma_ib_test
,
1613 .is_lockup
= &cayman_dma_is_lockup
,
1614 .vm_flush
= &cayman_dma_vm_flush
,
1615 .get_rptr
= &cayman_dma_get_rptr
,
1616 .get_wptr
= &cayman_dma_get_wptr
,
1617 .set_wptr
= &cayman_dma_set_wptr
1620 static struct radeon_asic_ring cayman_uvd_ring
= {
1621 .ib_execute
= &uvd_v1_0_ib_execute
,
1622 .emit_fence
= &uvd_v2_2_fence_emit
,
1623 .emit_semaphore
= &uvd_v3_1_semaphore_emit
,
1624 .cs_parse
= &radeon_uvd_cs_parse
,
1625 .ring_test
= &uvd_v1_0_ring_test
,
1626 .ib_test
= &uvd_v1_0_ib_test
,
1627 .is_lockup
= &radeon_ring_test_lockup
,
1628 .get_rptr
= &uvd_v1_0_get_rptr
,
1629 .get_wptr
= &uvd_v1_0_get_wptr
,
1630 .set_wptr
= &uvd_v1_0_set_wptr
,
1633 static struct radeon_asic cayman_asic
= {
1634 .init
= &cayman_init
,
1635 .fini
= &cayman_fini
,
1636 .suspend
= &cayman_suspend
,
1637 .resume
= &cayman_resume
,
1638 .asic_reset
= &cayman_asic_reset
,
1639 .vga_set_state
= &r600_vga_set_state
,
1640 .mmio_hdp_flush
= r600_mmio_hdp_flush
,
1641 .gui_idle
= &r600_gui_idle
,
1642 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1643 .get_xclk
= &rv770_get_xclk
,
1644 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1646 .tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1647 .get_page_entry
= &rs600_gart_get_page_entry
,
1648 .set_page
= &rs600_gart_set_page
,
1651 .init
= &cayman_vm_init
,
1652 .fini
= &cayman_vm_fini
,
1653 .copy_pages
= &cayman_dma_vm_copy_pages
,
1654 .write_pages
= &cayman_dma_vm_write_pages
,
1655 .set_pages
= &cayman_dma_vm_set_pages
,
1656 .pad_ib
= &cayman_dma_vm_pad_ib
,
1659 [RADEON_RING_TYPE_GFX_INDEX
] = &cayman_gfx_ring
,
1660 [CAYMAN_RING_TYPE_CP1_INDEX
] = &cayman_gfx_ring
,
1661 [CAYMAN_RING_TYPE_CP2_INDEX
] = &cayman_gfx_ring
,
1662 [R600_RING_TYPE_DMA_INDEX
] = &cayman_dma_ring
,
1663 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &cayman_dma_ring
,
1664 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
1667 .set
= &evergreen_irq_set
,
1668 .process
= &evergreen_irq_process
,
1671 .bandwidth_update
= &evergreen_bandwidth_update
,
1672 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1673 .wait_for_vblank
= &dce4_wait_for_vblank
,
1674 .set_backlight_level
= &atombios_set_backlight_level
,
1675 .get_backlight_level
= &atombios_get_backlight_level
,
1678 .blit
= &r600_copy_cpdma
,
1679 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1680 .dma
= &evergreen_copy_dma
,
1681 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1682 .copy
= &evergreen_copy_dma
,
1683 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1686 .set_reg
= r600_set_surface_reg
,
1687 .clear_reg
= r600_clear_surface_reg
,
1690 .init
= &evergreen_hpd_init
,
1691 .fini
= &evergreen_hpd_fini
,
1692 .sense
= &evergreen_hpd_sense
,
1693 .set_polarity
= &evergreen_hpd_set_polarity
,
1696 .misc
= &evergreen_pm_misc
,
1697 .prepare
= &evergreen_pm_prepare
,
1698 .finish
= &evergreen_pm_finish
,
1699 .init_profile
= &btc_pm_init_profile
,
1700 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1701 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1702 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1703 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1704 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1705 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1706 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1707 .set_clock_gating
= NULL
,
1708 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1709 .get_temperature
= &evergreen_get_temp
,
1712 .init
= &ni_dpm_init
,
1713 .setup_asic
= &ni_dpm_setup_asic
,
1714 .enable
= &ni_dpm_enable
,
1715 .late_enable
= &rv770_dpm_late_enable
,
1716 .disable
= &ni_dpm_disable
,
1717 .pre_set_power_state
= &ni_dpm_pre_set_power_state
,
1718 .set_power_state
= &ni_dpm_set_power_state
,
1719 .post_set_power_state
= &ni_dpm_post_set_power_state
,
1720 .display_configuration_changed
= &cypress_dpm_display_configuration_changed
,
1721 .fini
= &ni_dpm_fini
,
1722 .get_sclk
= &ni_dpm_get_sclk
,
1723 .get_mclk
= &ni_dpm_get_mclk
,
1724 .print_power_state
= &ni_dpm_print_power_state
,
1725 .debugfs_print_current_performance_level
= &ni_dpm_debugfs_print_current_performance_level
,
1726 .force_performance_level
= &ni_dpm_force_performance_level
,
1727 .vblank_too_short
= &ni_dpm_vblank_too_short
,
1730 .page_flip
= &evergreen_page_flip
,
1731 .page_flip_pending
= &evergreen_page_flip_pending
,
1735 static struct radeon_asic trinity_asic
= {
1736 .init
= &cayman_init
,
1737 .fini
= &cayman_fini
,
1738 .suspend
= &cayman_suspend
,
1739 .resume
= &cayman_resume
,
1740 .asic_reset
= &cayman_asic_reset
,
1741 .vga_set_state
= &r600_vga_set_state
,
1742 .mmio_hdp_flush
= r600_mmio_hdp_flush
,
1743 .gui_idle
= &r600_gui_idle
,
1744 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1745 .get_xclk
= &r600_get_xclk
,
1746 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1748 .tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1749 .get_page_entry
= &rs600_gart_get_page_entry
,
1750 .set_page
= &rs600_gart_set_page
,
1753 .init
= &cayman_vm_init
,
1754 .fini
= &cayman_vm_fini
,
1755 .copy_pages
= &cayman_dma_vm_copy_pages
,
1756 .write_pages
= &cayman_dma_vm_write_pages
,
1757 .set_pages
= &cayman_dma_vm_set_pages
,
1758 .pad_ib
= &cayman_dma_vm_pad_ib
,
1761 [RADEON_RING_TYPE_GFX_INDEX
] = &cayman_gfx_ring
,
1762 [CAYMAN_RING_TYPE_CP1_INDEX
] = &cayman_gfx_ring
,
1763 [CAYMAN_RING_TYPE_CP2_INDEX
] = &cayman_gfx_ring
,
1764 [R600_RING_TYPE_DMA_INDEX
] = &cayman_dma_ring
,
1765 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &cayman_dma_ring
,
1766 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
1769 .set
= &evergreen_irq_set
,
1770 .process
= &evergreen_irq_process
,
1773 .bandwidth_update
= &dce6_bandwidth_update
,
1774 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1775 .wait_for_vblank
= &dce4_wait_for_vblank
,
1776 .set_backlight_level
= &atombios_set_backlight_level
,
1777 .get_backlight_level
= &atombios_get_backlight_level
,
1780 .blit
= &r600_copy_cpdma
,
1781 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1782 .dma
= &evergreen_copy_dma
,
1783 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1784 .copy
= &evergreen_copy_dma
,
1785 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1788 .set_reg
= r600_set_surface_reg
,
1789 .clear_reg
= r600_clear_surface_reg
,
1792 .init
= &evergreen_hpd_init
,
1793 .fini
= &evergreen_hpd_fini
,
1794 .sense
= &evergreen_hpd_sense
,
1795 .set_polarity
= &evergreen_hpd_set_polarity
,
1798 .misc
= &evergreen_pm_misc
,
1799 .prepare
= &evergreen_pm_prepare
,
1800 .finish
= &evergreen_pm_finish
,
1801 .init_profile
= &sumo_pm_init_profile
,
1802 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1803 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1804 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1805 .get_memory_clock
= NULL
,
1806 .set_memory_clock
= NULL
,
1807 .get_pcie_lanes
= NULL
,
1808 .set_pcie_lanes
= NULL
,
1809 .set_clock_gating
= NULL
,
1810 .set_uvd_clocks
= &sumo_set_uvd_clocks
,
1811 .get_temperature
= &tn_get_temp
,
1814 .init
= &trinity_dpm_init
,
1815 .setup_asic
= &trinity_dpm_setup_asic
,
1816 .enable
= &trinity_dpm_enable
,
1817 .late_enable
= &trinity_dpm_late_enable
,
1818 .disable
= &trinity_dpm_disable
,
1819 .pre_set_power_state
= &trinity_dpm_pre_set_power_state
,
1820 .set_power_state
= &trinity_dpm_set_power_state
,
1821 .post_set_power_state
= &trinity_dpm_post_set_power_state
,
1822 .display_configuration_changed
= &trinity_dpm_display_configuration_changed
,
1823 .fini
= &trinity_dpm_fini
,
1824 .get_sclk
= &trinity_dpm_get_sclk
,
1825 .get_mclk
= &trinity_dpm_get_mclk
,
1826 .print_power_state
= &trinity_dpm_print_power_state
,
1827 .debugfs_print_current_performance_level
= &trinity_dpm_debugfs_print_current_performance_level
,
1828 .force_performance_level
= &trinity_dpm_force_performance_level
,
1829 .enable_bapm
= &trinity_dpm_enable_bapm
,
1832 .page_flip
= &evergreen_page_flip
,
1833 .page_flip_pending
= &evergreen_page_flip_pending
,
1837 static struct radeon_asic_ring si_gfx_ring
= {
1838 .ib_execute
= &si_ring_ib_execute
,
1839 .ib_parse
= &si_ib_parse
,
1840 .emit_fence
= &si_fence_ring_emit
,
1841 .emit_semaphore
= &r600_semaphore_ring_emit
,
1843 .ring_test
= &r600_ring_test
,
1844 .ib_test
= &r600_ib_test
,
1845 .is_lockup
= &si_gfx_is_lockup
,
1846 .vm_flush
= &si_vm_flush
,
1847 .get_rptr
= &cayman_gfx_get_rptr
,
1848 .get_wptr
= &cayman_gfx_get_wptr
,
1849 .set_wptr
= &cayman_gfx_set_wptr
,
1852 static struct radeon_asic_ring si_dma_ring
= {
1853 .ib_execute
= &cayman_dma_ring_ib_execute
,
1854 .ib_parse
= &evergreen_dma_ib_parse
,
1855 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1856 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1858 .ring_test
= &r600_dma_ring_test
,
1859 .ib_test
= &r600_dma_ib_test
,
1860 .is_lockup
= &si_dma_is_lockup
,
1861 .vm_flush
= &si_dma_vm_flush
,
1862 .get_rptr
= &cayman_dma_get_rptr
,
1863 .get_wptr
= &cayman_dma_get_wptr
,
1864 .set_wptr
= &cayman_dma_set_wptr
,
1867 static struct radeon_asic si_asic
= {
1870 .suspend
= &si_suspend
,
1871 .resume
= &si_resume
,
1872 .asic_reset
= &si_asic_reset
,
1873 .vga_set_state
= &r600_vga_set_state
,
1874 .mmio_hdp_flush
= r600_mmio_hdp_flush
,
1875 .gui_idle
= &r600_gui_idle
,
1876 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1877 .get_xclk
= &si_get_xclk
,
1878 .get_gpu_clock_counter
= &si_get_gpu_clock_counter
,
1880 .tlb_flush
= &si_pcie_gart_tlb_flush
,
1881 .get_page_entry
= &rs600_gart_get_page_entry
,
1882 .set_page
= &rs600_gart_set_page
,
1885 .init
= &si_vm_init
,
1886 .fini
= &si_vm_fini
,
1887 .copy_pages
= &si_dma_vm_copy_pages
,
1888 .write_pages
= &si_dma_vm_write_pages
,
1889 .set_pages
= &si_dma_vm_set_pages
,
1890 .pad_ib
= &cayman_dma_vm_pad_ib
,
1893 [RADEON_RING_TYPE_GFX_INDEX
] = &si_gfx_ring
,
1894 [CAYMAN_RING_TYPE_CP1_INDEX
] = &si_gfx_ring
,
1895 [CAYMAN_RING_TYPE_CP2_INDEX
] = &si_gfx_ring
,
1896 [R600_RING_TYPE_DMA_INDEX
] = &si_dma_ring
,
1897 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &si_dma_ring
,
1898 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
1902 .process
= &si_irq_process
,
1905 .bandwidth_update
= &dce6_bandwidth_update
,
1906 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1907 .wait_for_vblank
= &dce4_wait_for_vblank
,
1908 .set_backlight_level
= &atombios_set_backlight_level
,
1909 .get_backlight_level
= &atombios_get_backlight_level
,
1912 .blit
= &r600_copy_cpdma
,
1913 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1914 .dma
= &si_copy_dma
,
1915 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1916 .copy
= &si_copy_dma
,
1917 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1920 .set_reg
= r600_set_surface_reg
,
1921 .clear_reg
= r600_clear_surface_reg
,
1924 .init
= &evergreen_hpd_init
,
1925 .fini
= &evergreen_hpd_fini
,
1926 .sense
= &evergreen_hpd_sense
,
1927 .set_polarity
= &evergreen_hpd_set_polarity
,
1930 .misc
= &evergreen_pm_misc
,
1931 .prepare
= &evergreen_pm_prepare
,
1932 .finish
= &evergreen_pm_finish
,
1933 .init_profile
= &sumo_pm_init_profile
,
1934 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1935 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1936 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1937 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1938 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1939 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1940 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1941 .set_clock_gating
= NULL
,
1942 .set_uvd_clocks
= &si_set_uvd_clocks
,
1943 .get_temperature
= &si_get_temp
,
1946 .init
= &si_dpm_init
,
1947 .setup_asic
= &si_dpm_setup_asic
,
1948 .enable
= &si_dpm_enable
,
1949 .late_enable
= &si_dpm_late_enable
,
1950 .disable
= &si_dpm_disable
,
1951 .pre_set_power_state
= &si_dpm_pre_set_power_state
,
1952 .set_power_state
= &si_dpm_set_power_state
,
1953 .post_set_power_state
= &si_dpm_post_set_power_state
,
1954 .display_configuration_changed
= &si_dpm_display_configuration_changed
,
1955 .fini
= &si_dpm_fini
,
1956 .get_sclk
= &ni_dpm_get_sclk
,
1957 .get_mclk
= &ni_dpm_get_mclk
,
1958 .print_power_state
= &ni_dpm_print_power_state
,
1959 .debugfs_print_current_performance_level
= &si_dpm_debugfs_print_current_performance_level
,
1960 .force_performance_level
= &si_dpm_force_performance_level
,
1961 .vblank_too_short
= &ni_dpm_vblank_too_short
,
1962 .fan_ctrl_set_mode
= &si_fan_ctrl_set_mode
,
1963 .fan_ctrl_get_mode
= &si_fan_ctrl_get_mode
,
1964 .get_fan_speed_percent
= &si_fan_ctrl_get_fan_speed_percent
,
1965 .set_fan_speed_percent
= &si_fan_ctrl_set_fan_speed_percent
,
1968 .page_flip
= &evergreen_page_flip
,
1969 .page_flip_pending
= &evergreen_page_flip_pending
,
1973 static struct radeon_asic_ring ci_gfx_ring
= {
1974 .ib_execute
= &cik_ring_ib_execute
,
1975 .ib_parse
= &cik_ib_parse
,
1976 .emit_fence
= &cik_fence_gfx_ring_emit
,
1977 .emit_semaphore
= &cik_semaphore_ring_emit
,
1979 .ring_test
= &cik_ring_test
,
1980 .ib_test
= &cik_ib_test
,
1981 .is_lockup
= &cik_gfx_is_lockup
,
1982 .vm_flush
= &cik_vm_flush
,
1983 .get_rptr
= &cik_gfx_get_rptr
,
1984 .get_wptr
= &cik_gfx_get_wptr
,
1985 .set_wptr
= &cik_gfx_set_wptr
,
1988 static struct radeon_asic_ring ci_cp_ring
= {
1989 .ib_execute
= &cik_ring_ib_execute
,
1990 .ib_parse
= &cik_ib_parse
,
1991 .emit_fence
= &cik_fence_compute_ring_emit
,
1992 .emit_semaphore
= &cik_semaphore_ring_emit
,
1994 .ring_test
= &cik_ring_test
,
1995 .ib_test
= &cik_ib_test
,
1996 .is_lockup
= &cik_gfx_is_lockup
,
1997 .vm_flush
= &cik_vm_flush
,
1998 .get_rptr
= &cik_compute_get_rptr
,
1999 .get_wptr
= &cik_compute_get_wptr
,
2000 .set_wptr
= &cik_compute_set_wptr
,
2003 static struct radeon_asic_ring ci_dma_ring
= {
2004 .ib_execute
= &cik_sdma_ring_ib_execute
,
2005 .ib_parse
= &cik_ib_parse
,
2006 .emit_fence
= &cik_sdma_fence_ring_emit
,
2007 .emit_semaphore
= &cik_sdma_semaphore_ring_emit
,
2009 .ring_test
= &cik_sdma_ring_test
,
2010 .ib_test
= &cik_sdma_ib_test
,
2011 .is_lockup
= &cik_sdma_is_lockup
,
2012 .vm_flush
= &cik_dma_vm_flush
,
2013 .get_rptr
= &cik_sdma_get_rptr
,
2014 .get_wptr
= &cik_sdma_get_wptr
,
2015 .set_wptr
= &cik_sdma_set_wptr
,
2018 static struct radeon_asic_ring ci_vce_ring
= {
2019 .ib_execute
= &radeon_vce_ib_execute
,
2020 .emit_fence
= &radeon_vce_fence_emit
,
2021 .emit_semaphore
= &radeon_vce_semaphore_emit
,
2022 .cs_parse
= &radeon_vce_cs_parse
,
2023 .ring_test
= &radeon_vce_ring_test
,
2024 .ib_test
= &radeon_vce_ib_test
,
2025 .is_lockup
= &radeon_ring_test_lockup
,
2026 .get_rptr
= &vce_v1_0_get_rptr
,
2027 .get_wptr
= &vce_v1_0_get_wptr
,
2028 .set_wptr
= &vce_v1_0_set_wptr
,
2031 static struct radeon_asic ci_asic
= {
2034 .suspend
= &cik_suspend
,
2035 .resume
= &cik_resume
,
2036 .asic_reset
= &cik_asic_reset
,
2037 .vga_set_state
= &r600_vga_set_state
,
2038 .mmio_hdp_flush
= &r600_mmio_hdp_flush
,
2039 .gui_idle
= &r600_gui_idle
,
2040 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
2041 .get_xclk
= &cik_get_xclk
,
2042 .get_gpu_clock_counter
= &cik_get_gpu_clock_counter
,
2044 .tlb_flush
= &cik_pcie_gart_tlb_flush
,
2045 .get_page_entry
= &rs600_gart_get_page_entry
,
2046 .set_page
= &rs600_gart_set_page
,
2049 .init
= &cik_vm_init
,
2050 .fini
= &cik_vm_fini
,
2051 .copy_pages
= &cik_sdma_vm_copy_pages
,
2052 .write_pages
= &cik_sdma_vm_write_pages
,
2053 .set_pages
= &cik_sdma_vm_set_pages
,
2054 .pad_ib
= &cik_sdma_vm_pad_ib
,
2057 [RADEON_RING_TYPE_GFX_INDEX
] = &ci_gfx_ring
,
2058 [CAYMAN_RING_TYPE_CP1_INDEX
] = &ci_cp_ring
,
2059 [CAYMAN_RING_TYPE_CP2_INDEX
] = &ci_cp_ring
,
2060 [R600_RING_TYPE_DMA_INDEX
] = &ci_dma_ring
,
2061 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &ci_dma_ring
,
2062 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
2063 [TN_RING_TYPE_VCE1_INDEX
] = &ci_vce_ring
,
2064 [TN_RING_TYPE_VCE2_INDEX
] = &ci_vce_ring
,
2067 .set
= &cik_irq_set
,
2068 .process
= &cik_irq_process
,
2071 .bandwidth_update
= &dce8_bandwidth_update
,
2072 .get_vblank_counter
= &evergreen_get_vblank_counter
,
2073 .wait_for_vblank
= &dce4_wait_for_vblank
,
2074 .set_backlight_level
= &atombios_set_backlight_level
,
2075 .get_backlight_level
= &atombios_get_backlight_level
,
2078 .blit
= &cik_copy_cpdma
,
2079 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
2080 .dma
= &cik_copy_dma
,
2081 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2082 .copy
= &cik_copy_dma
,
2083 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2086 .set_reg
= r600_set_surface_reg
,
2087 .clear_reg
= r600_clear_surface_reg
,
2090 .init
= &evergreen_hpd_init
,
2091 .fini
= &evergreen_hpd_fini
,
2092 .sense
= &evergreen_hpd_sense
,
2093 .set_polarity
= &evergreen_hpd_set_polarity
,
2096 .misc
= &evergreen_pm_misc
,
2097 .prepare
= &evergreen_pm_prepare
,
2098 .finish
= &evergreen_pm_finish
,
2099 .init_profile
= &sumo_pm_init_profile
,
2100 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
2101 .get_engine_clock
= &radeon_atom_get_engine_clock
,
2102 .set_engine_clock
= &radeon_atom_set_engine_clock
,
2103 .get_memory_clock
= &radeon_atom_get_memory_clock
,
2104 .set_memory_clock
= &radeon_atom_set_memory_clock
,
2105 .get_pcie_lanes
= NULL
,
2106 .set_pcie_lanes
= NULL
,
2107 .set_clock_gating
= NULL
,
2108 .set_uvd_clocks
= &cik_set_uvd_clocks
,
2109 .set_vce_clocks
= &cik_set_vce_clocks
,
2110 .get_temperature
= &ci_get_temp
,
2113 .init
= &ci_dpm_init
,
2114 .setup_asic
= &ci_dpm_setup_asic
,
2115 .enable
= &ci_dpm_enable
,
2116 .late_enable
= &ci_dpm_late_enable
,
2117 .disable
= &ci_dpm_disable
,
2118 .pre_set_power_state
= &ci_dpm_pre_set_power_state
,
2119 .set_power_state
= &ci_dpm_set_power_state
,
2120 .post_set_power_state
= &ci_dpm_post_set_power_state
,
2121 .display_configuration_changed
= &ci_dpm_display_configuration_changed
,
2122 .fini
= &ci_dpm_fini
,
2123 .get_sclk
= &ci_dpm_get_sclk
,
2124 .get_mclk
= &ci_dpm_get_mclk
,
2125 .print_power_state
= &ci_dpm_print_power_state
,
2126 .debugfs_print_current_performance_level
= &ci_dpm_debugfs_print_current_performance_level
,
2127 .force_performance_level
= &ci_dpm_force_performance_level
,
2128 .vblank_too_short
= &ci_dpm_vblank_too_short
,
2129 .powergate_uvd
= &ci_dpm_powergate_uvd
,
2130 .fan_ctrl_set_mode
= &ci_fan_ctrl_set_mode
,
2131 .fan_ctrl_get_mode
= &ci_fan_ctrl_get_mode
,
2132 .get_fan_speed_percent
= &ci_fan_ctrl_get_fan_speed_percent
,
2133 .set_fan_speed_percent
= &ci_fan_ctrl_set_fan_speed_percent
,
2136 .page_flip
= &evergreen_page_flip
,
2137 .page_flip_pending
= &evergreen_page_flip_pending
,
2141 static struct radeon_asic kv_asic
= {
2144 .suspend
= &cik_suspend
,
2145 .resume
= &cik_resume
,
2146 .asic_reset
= &cik_asic_reset
,
2147 .vga_set_state
= &r600_vga_set_state
,
2148 .mmio_hdp_flush
= &r600_mmio_hdp_flush
,
2149 .gui_idle
= &r600_gui_idle
,
2150 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
2151 .get_xclk
= &cik_get_xclk
,
2152 .get_gpu_clock_counter
= &cik_get_gpu_clock_counter
,
2154 .tlb_flush
= &cik_pcie_gart_tlb_flush
,
2155 .get_page_entry
= &rs600_gart_get_page_entry
,
2156 .set_page
= &rs600_gart_set_page
,
2159 .init
= &cik_vm_init
,
2160 .fini
= &cik_vm_fini
,
2161 .copy_pages
= &cik_sdma_vm_copy_pages
,
2162 .write_pages
= &cik_sdma_vm_write_pages
,
2163 .set_pages
= &cik_sdma_vm_set_pages
,
2164 .pad_ib
= &cik_sdma_vm_pad_ib
,
2167 [RADEON_RING_TYPE_GFX_INDEX
] = &ci_gfx_ring
,
2168 [CAYMAN_RING_TYPE_CP1_INDEX
] = &ci_cp_ring
,
2169 [CAYMAN_RING_TYPE_CP2_INDEX
] = &ci_cp_ring
,
2170 [R600_RING_TYPE_DMA_INDEX
] = &ci_dma_ring
,
2171 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &ci_dma_ring
,
2172 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
2173 [TN_RING_TYPE_VCE1_INDEX
] = &ci_vce_ring
,
2174 [TN_RING_TYPE_VCE2_INDEX
] = &ci_vce_ring
,
2177 .set
= &cik_irq_set
,
2178 .process
= &cik_irq_process
,
2181 .bandwidth_update
= &dce8_bandwidth_update
,
2182 .get_vblank_counter
= &evergreen_get_vblank_counter
,
2183 .wait_for_vblank
= &dce4_wait_for_vblank
,
2184 .set_backlight_level
= &atombios_set_backlight_level
,
2185 .get_backlight_level
= &atombios_get_backlight_level
,
2188 .blit
= &cik_copy_cpdma
,
2189 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
2190 .dma
= &cik_copy_dma
,
2191 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2192 .copy
= &cik_copy_dma
,
2193 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2196 .set_reg
= r600_set_surface_reg
,
2197 .clear_reg
= r600_clear_surface_reg
,
2200 .init
= &evergreen_hpd_init
,
2201 .fini
= &evergreen_hpd_fini
,
2202 .sense
= &evergreen_hpd_sense
,
2203 .set_polarity
= &evergreen_hpd_set_polarity
,
2206 .misc
= &evergreen_pm_misc
,
2207 .prepare
= &evergreen_pm_prepare
,
2208 .finish
= &evergreen_pm_finish
,
2209 .init_profile
= &sumo_pm_init_profile
,
2210 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
2211 .get_engine_clock
= &radeon_atom_get_engine_clock
,
2212 .set_engine_clock
= &radeon_atom_set_engine_clock
,
2213 .get_memory_clock
= &radeon_atom_get_memory_clock
,
2214 .set_memory_clock
= &radeon_atom_set_memory_clock
,
2215 .get_pcie_lanes
= NULL
,
2216 .set_pcie_lanes
= NULL
,
2217 .set_clock_gating
= NULL
,
2218 .set_uvd_clocks
= &cik_set_uvd_clocks
,
2219 .set_vce_clocks
= &cik_set_vce_clocks
,
2220 .get_temperature
= &kv_get_temp
,
2223 .init
= &kv_dpm_init
,
2224 .setup_asic
= &kv_dpm_setup_asic
,
2225 .enable
= &kv_dpm_enable
,
2226 .late_enable
= &kv_dpm_late_enable
,
2227 .disable
= &kv_dpm_disable
,
2228 .pre_set_power_state
= &kv_dpm_pre_set_power_state
,
2229 .set_power_state
= &kv_dpm_set_power_state
,
2230 .post_set_power_state
= &kv_dpm_post_set_power_state
,
2231 .display_configuration_changed
= &kv_dpm_display_configuration_changed
,
2232 .fini
= &kv_dpm_fini
,
2233 .get_sclk
= &kv_dpm_get_sclk
,
2234 .get_mclk
= &kv_dpm_get_mclk
,
2235 .print_power_state
= &kv_dpm_print_power_state
,
2236 .debugfs_print_current_performance_level
= &kv_dpm_debugfs_print_current_performance_level
,
2237 .force_performance_level
= &kv_dpm_force_performance_level
,
2238 .powergate_uvd
= &kv_dpm_powergate_uvd
,
2239 .enable_bapm
= &kv_dpm_enable_bapm
,
2242 .page_flip
= &evergreen_page_flip
,
2243 .page_flip_pending
= &evergreen_page_flip_pending
,
2248 * radeon_asic_init - register asic specific callbacks
2250 * @rdev: radeon device pointer
2252 * Registers the appropriate asic specific callbacks for each
2253 * chip family. Also sets other asics specific info like the number
2254 * of crtcs and the register aperture accessors (all asics).
2255 * Returns 0 for success.
2257 int radeon_asic_init(struct radeon_device
*rdev
)
2259 radeon_register_accessor_init(rdev
);
2261 /* set the number of crtcs */
2262 if (rdev
->flags
& RADEON_SINGLE_CRTC
)
2267 rdev
->has_uvd
= false;
2269 switch (rdev
->family
) {
2275 rdev
->asic
= &r100_asic
;
2281 rdev
->asic
= &r200_asic
;
2287 if (rdev
->flags
& RADEON_IS_PCIE
)
2288 rdev
->asic
= &r300_asic_pcie
;
2290 rdev
->asic
= &r300_asic
;
2295 rdev
->asic
= &r420_asic
;
2297 if (rdev
->bios
== NULL
) {
2298 rdev
->asic
->pm
.get_engine_clock
= &radeon_legacy_get_engine_clock
;
2299 rdev
->asic
->pm
.set_engine_clock
= &radeon_legacy_set_engine_clock
;
2300 rdev
->asic
->pm
.get_memory_clock
= &radeon_legacy_get_memory_clock
;
2301 rdev
->asic
->pm
.set_memory_clock
= NULL
;
2302 rdev
->asic
->display
.set_backlight_level
= &radeon_legacy_set_backlight_level
;
2307 rdev
->asic
= &rs400_asic
;
2310 rdev
->asic
= &rs600_asic
;
2314 rdev
->asic
= &rs690_asic
;
2317 rdev
->asic
= &rv515_asic
;
2324 rdev
->asic
= &r520_asic
;
2327 rdev
->asic
= &r600_asic
;
2334 rdev
->asic
= &rv6xx_asic
;
2335 rdev
->has_uvd
= true;
2339 rdev
->asic
= &rs780_asic
;
2340 /* 760G/780V/880V don't have UVD */
2341 if ((rdev
->pdev
->device
== 0x9616)||
2342 (rdev
->pdev
->device
== 0x9611)||
2343 (rdev
->pdev
->device
== 0x9613)||
2344 (rdev
->pdev
->device
== 0x9711)||
2345 (rdev
->pdev
->device
== 0x9713))
2346 rdev
->has_uvd
= false;
2348 rdev
->has_uvd
= true;
2354 rdev
->asic
= &rv770_asic
;
2355 rdev
->has_uvd
= true;
2363 if (rdev
->family
== CHIP_CEDAR
)
2367 rdev
->asic
= &evergreen_asic
;
2368 rdev
->has_uvd
= true;
2373 rdev
->asic
= &sumo_asic
;
2374 rdev
->has_uvd
= true;
2380 if (rdev
->family
== CHIP_CAICOS
)
2384 rdev
->asic
= &btc_asic
;
2385 rdev
->has_uvd
= true;
2388 rdev
->asic
= &cayman_asic
;
2391 rdev
->has_uvd
= true;
2394 rdev
->asic
= &trinity_asic
;
2397 rdev
->has_uvd
= true;
2404 rdev
->asic
= &si_asic
;
2406 if (rdev
->family
== CHIP_HAINAN
)
2408 else if (rdev
->family
== CHIP_OLAND
)
2412 if (rdev
->family
== CHIP_HAINAN
)
2413 rdev
->has_uvd
= false;
2415 rdev
->has_uvd
= true;
2416 switch (rdev
->family
) {
2419 RADEON_CG_SUPPORT_GFX_MGCG
|
2420 RADEON_CG_SUPPORT_GFX_MGLS
|
2421 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2422 RADEON_CG_SUPPORT_GFX_CGLS
|
2423 RADEON_CG_SUPPORT_GFX_CGTS
|
2424 RADEON_CG_SUPPORT_GFX_CP_LS
|
2425 RADEON_CG_SUPPORT_MC_MGCG
|
2426 RADEON_CG_SUPPORT_SDMA_MGCG
|
2427 RADEON_CG_SUPPORT_BIF_LS
|
2428 RADEON_CG_SUPPORT_VCE_MGCG
|
2429 RADEON_CG_SUPPORT_UVD_MGCG
|
2430 RADEON_CG_SUPPORT_HDP_LS
|
2431 RADEON_CG_SUPPORT_HDP_MGCG
;
2436 RADEON_CG_SUPPORT_GFX_MGCG
|
2437 RADEON_CG_SUPPORT_GFX_MGLS
|
2438 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2439 RADEON_CG_SUPPORT_GFX_CGLS
|
2440 RADEON_CG_SUPPORT_GFX_CGTS
|
2441 RADEON_CG_SUPPORT_GFX_CP_LS
|
2442 RADEON_CG_SUPPORT_GFX_RLC_LS
|
2443 RADEON_CG_SUPPORT_MC_LS
|
2444 RADEON_CG_SUPPORT_MC_MGCG
|
2445 RADEON_CG_SUPPORT_SDMA_MGCG
|
2446 RADEON_CG_SUPPORT_BIF_LS
|
2447 RADEON_CG_SUPPORT_VCE_MGCG
|
2448 RADEON_CG_SUPPORT_UVD_MGCG
|
2449 RADEON_CG_SUPPORT_HDP_LS
|
2450 RADEON_CG_SUPPORT_HDP_MGCG
;
2455 RADEON_CG_SUPPORT_GFX_MGCG
|
2456 RADEON_CG_SUPPORT_GFX_MGLS
|
2457 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2458 RADEON_CG_SUPPORT_GFX_CGLS
|
2459 RADEON_CG_SUPPORT_GFX_CGTS
|
2460 RADEON_CG_SUPPORT_GFX_CP_LS
|
2461 RADEON_CG_SUPPORT_GFX_RLC_LS
|
2462 RADEON_CG_SUPPORT_MC_LS
|
2463 RADEON_CG_SUPPORT_MC_MGCG
|
2464 RADEON_CG_SUPPORT_SDMA_MGCG
|
2465 RADEON_CG_SUPPORT_BIF_LS
|
2466 RADEON_CG_SUPPORT_VCE_MGCG
|
2467 RADEON_CG_SUPPORT_UVD_MGCG
|
2468 RADEON_CG_SUPPORT_HDP_LS
|
2469 RADEON_CG_SUPPORT_HDP_MGCG
;
2470 rdev
->pg_flags
= 0 |
2471 /*RADEON_PG_SUPPORT_GFX_PG | */
2472 RADEON_PG_SUPPORT_SDMA
;
2476 RADEON_CG_SUPPORT_GFX_MGCG
|
2477 RADEON_CG_SUPPORT_GFX_MGLS
|
2478 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2479 RADEON_CG_SUPPORT_GFX_CGLS
|
2480 RADEON_CG_SUPPORT_GFX_CGTS
|
2481 RADEON_CG_SUPPORT_GFX_CP_LS
|
2482 RADEON_CG_SUPPORT_GFX_RLC_LS
|
2483 RADEON_CG_SUPPORT_MC_LS
|
2484 RADEON_CG_SUPPORT_MC_MGCG
|
2485 RADEON_CG_SUPPORT_SDMA_MGCG
|
2486 RADEON_CG_SUPPORT_BIF_LS
|
2487 RADEON_CG_SUPPORT_UVD_MGCG
|
2488 RADEON_CG_SUPPORT_HDP_LS
|
2489 RADEON_CG_SUPPORT_HDP_MGCG
;
2494 RADEON_CG_SUPPORT_GFX_MGCG
|
2495 RADEON_CG_SUPPORT_GFX_MGLS
|
2496 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2497 RADEON_CG_SUPPORT_GFX_CGLS
|
2498 RADEON_CG_SUPPORT_GFX_CGTS
|
2499 RADEON_CG_SUPPORT_GFX_CP_LS
|
2500 RADEON_CG_SUPPORT_GFX_RLC_LS
|
2501 RADEON_CG_SUPPORT_MC_LS
|
2502 RADEON_CG_SUPPORT_MC_MGCG
|
2503 RADEON_CG_SUPPORT_SDMA_MGCG
|
2504 RADEON_CG_SUPPORT_BIF_LS
|
2505 RADEON_CG_SUPPORT_HDP_LS
|
2506 RADEON_CG_SUPPORT_HDP_MGCG
;
2517 rdev
->asic
= &ci_asic
;
2519 rdev
->has_uvd
= true;
2520 if (rdev
->family
== CHIP_BONAIRE
) {
2522 RADEON_CG_SUPPORT_GFX_MGCG
|
2523 RADEON_CG_SUPPORT_GFX_MGLS
|
2524 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2525 RADEON_CG_SUPPORT_GFX_CGLS
|
2526 RADEON_CG_SUPPORT_GFX_CGTS
|
2527 RADEON_CG_SUPPORT_GFX_CGTS_LS
|
2528 RADEON_CG_SUPPORT_GFX_CP_LS
|
2529 RADEON_CG_SUPPORT_MC_LS
|
2530 RADEON_CG_SUPPORT_MC_MGCG
|
2531 RADEON_CG_SUPPORT_SDMA_MGCG
|
2532 RADEON_CG_SUPPORT_SDMA_LS
|
2533 RADEON_CG_SUPPORT_BIF_LS
|
2534 RADEON_CG_SUPPORT_VCE_MGCG
|
2535 RADEON_CG_SUPPORT_UVD_MGCG
|
2536 RADEON_CG_SUPPORT_HDP_LS
|
2537 RADEON_CG_SUPPORT_HDP_MGCG
;
2541 RADEON_CG_SUPPORT_GFX_MGCG
|
2542 RADEON_CG_SUPPORT_GFX_MGLS
|
2543 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2544 RADEON_CG_SUPPORT_GFX_CGLS
|
2545 RADEON_CG_SUPPORT_GFX_CGTS
|
2546 RADEON_CG_SUPPORT_GFX_CP_LS
|
2547 RADEON_CG_SUPPORT_MC_LS
|
2548 RADEON_CG_SUPPORT_MC_MGCG
|
2549 RADEON_CG_SUPPORT_SDMA_MGCG
|
2550 RADEON_CG_SUPPORT_SDMA_LS
|
2551 RADEON_CG_SUPPORT_BIF_LS
|
2552 RADEON_CG_SUPPORT_VCE_MGCG
|
2553 RADEON_CG_SUPPORT_UVD_MGCG
|
2554 RADEON_CG_SUPPORT_HDP_LS
|
2555 RADEON_CG_SUPPORT_HDP_MGCG
;
2562 rdev
->asic
= &kv_asic
;
2564 if (rdev
->family
== CHIP_KAVERI
) {
2567 RADEON_CG_SUPPORT_GFX_MGCG
|
2568 RADEON_CG_SUPPORT_GFX_MGLS
|
2569 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2570 RADEON_CG_SUPPORT_GFX_CGLS
|
2571 RADEON_CG_SUPPORT_GFX_CGTS
|
2572 RADEON_CG_SUPPORT_GFX_CGTS_LS
|
2573 RADEON_CG_SUPPORT_GFX_CP_LS
|
2574 RADEON_CG_SUPPORT_SDMA_MGCG
|
2575 RADEON_CG_SUPPORT_SDMA_LS
|
2576 RADEON_CG_SUPPORT_BIF_LS
|
2577 RADEON_CG_SUPPORT_VCE_MGCG
|
2578 RADEON_CG_SUPPORT_UVD_MGCG
|
2579 RADEON_CG_SUPPORT_HDP_LS
|
2580 RADEON_CG_SUPPORT_HDP_MGCG
;
2582 /*RADEON_PG_SUPPORT_GFX_PG |
2583 RADEON_PG_SUPPORT_GFX_SMG |
2584 RADEON_PG_SUPPORT_GFX_DMG |
2585 RADEON_PG_SUPPORT_UVD |
2586 RADEON_PG_SUPPORT_VCE |
2587 RADEON_PG_SUPPORT_CP |
2588 RADEON_PG_SUPPORT_GDS |
2589 RADEON_PG_SUPPORT_RLC_SMU_HS |
2590 RADEON_PG_SUPPORT_ACP |
2591 RADEON_PG_SUPPORT_SAMU;*/
2595 RADEON_CG_SUPPORT_GFX_MGCG
|
2596 RADEON_CG_SUPPORT_GFX_MGLS
|
2597 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2598 RADEON_CG_SUPPORT_GFX_CGLS
|
2599 RADEON_CG_SUPPORT_GFX_CGTS
|
2600 RADEON_CG_SUPPORT_GFX_CGTS_LS
|
2601 RADEON_CG_SUPPORT_GFX_CP_LS
|
2602 RADEON_CG_SUPPORT_SDMA_MGCG
|
2603 RADEON_CG_SUPPORT_SDMA_LS
|
2604 RADEON_CG_SUPPORT_BIF_LS
|
2605 RADEON_CG_SUPPORT_VCE_MGCG
|
2606 RADEON_CG_SUPPORT_UVD_MGCG
|
2607 RADEON_CG_SUPPORT_HDP_LS
|
2608 RADEON_CG_SUPPORT_HDP_MGCG
;
2610 /*RADEON_PG_SUPPORT_GFX_PG |
2611 RADEON_PG_SUPPORT_GFX_SMG |
2612 RADEON_PG_SUPPORT_UVD |
2613 RADEON_PG_SUPPORT_VCE |
2614 RADEON_PG_SUPPORT_CP |
2615 RADEON_PG_SUPPORT_GDS |
2616 RADEON_PG_SUPPORT_RLC_SMU_HS |
2617 RADEON_PG_SUPPORT_SAMU;*/
2619 rdev
->has_uvd
= true;
2622 /* FIXME: not supported yet */
2626 if (rdev
->flags
& RADEON_IS_IGP
) {
2627 rdev
->asic
->pm
.get_memory_clock
= NULL
;
2628 rdev
->asic
->pm
.set_memory_clock
= NULL
;