2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/console.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
37 #include "radeon_asic.h"
41 * Registers accessors functions.
44 * radeon_invalid_rreg - dummy reg read function
46 * @rdev: radeon device pointer
47 * @reg: offset of register
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
53 static uint32_t radeon_invalid_rreg(struct radeon_device
*rdev
, uint32_t reg
)
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
61 * radeon_invalid_wreg - dummy reg write function
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
70 static void radeon_invalid_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
78 * radeon_register_accessor_init - sets up the register accessor callbacks
80 * @rdev: radeon device pointer
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
85 static void radeon_register_accessor_init(struct radeon_device
*rdev
)
87 rdev
->mc_rreg
= &radeon_invalid_rreg
;
88 rdev
->mc_wreg
= &radeon_invalid_wreg
;
89 rdev
->pll_rreg
= &radeon_invalid_rreg
;
90 rdev
->pll_wreg
= &radeon_invalid_wreg
;
91 rdev
->pciep_rreg
= &radeon_invalid_rreg
;
92 rdev
->pciep_wreg
= &radeon_invalid_wreg
;
94 /* Don't change order as we are overridding accessor. */
95 if (rdev
->family
< CHIP_RV515
) {
96 rdev
->pcie_reg_mask
= 0xff;
98 rdev
->pcie_reg_mask
= 0x7ff;
100 /* FIXME: not sure here */
101 if (rdev
->family
<= CHIP_R580
) {
102 rdev
->pll_rreg
= &r100_pll_rreg
;
103 rdev
->pll_wreg
= &r100_pll_wreg
;
105 if (rdev
->family
>= CHIP_R420
) {
106 rdev
->mc_rreg
= &r420_mc_rreg
;
107 rdev
->mc_wreg
= &r420_mc_wreg
;
109 if (rdev
->family
>= CHIP_RV515
) {
110 rdev
->mc_rreg
= &rv515_mc_rreg
;
111 rdev
->mc_wreg
= &rv515_mc_wreg
;
113 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
114 rdev
->mc_rreg
= &rs400_mc_rreg
;
115 rdev
->mc_wreg
= &rs400_mc_wreg
;
117 if (rdev
->family
== CHIP_RS690
|| rdev
->family
== CHIP_RS740
) {
118 rdev
->mc_rreg
= &rs690_mc_rreg
;
119 rdev
->mc_wreg
= &rs690_mc_wreg
;
121 if (rdev
->family
== CHIP_RS600
) {
122 rdev
->mc_rreg
= &rs600_mc_rreg
;
123 rdev
->mc_wreg
= &rs600_mc_wreg
;
125 if (rdev
->family
== CHIP_RS780
|| rdev
->family
== CHIP_RS880
) {
126 rdev
->mc_rreg
= &rs780_mc_rreg
;
127 rdev
->mc_wreg
= &rs780_mc_wreg
;
130 if (rdev
->family
>= CHIP_BONAIRE
) {
131 rdev
->pciep_rreg
= &cik_pciep_rreg
;
132 rdev
->pciep_wreg
= &cik_pciep_wreg
;
133 } else if (rdev
->family
>= CHIP_R600
) {
134 rdev
->pciep_rreg
= &r600_pciep_rreg
;
135 rdev
->pciep_wreg
= &r600_pciep_wreg
;
140 /* helper to disable agp */
142 * radeon_agp_disable - AGP disable helper function
144 * @rdev: radeon device pointer
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
149 void radeon_agp_disable(struct radeon_device
*rdev
)
151 rdev
->flags
&= ~RADEON_IS_AGP
;
152 if (rdev
->family
>= CHIP_R600
) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev
->flags
|= RADEON_IS_PCIE
;
155 } else if (rdev
->family
>= CHIP_RV515
||
156 rdev
->family
== CHIP_RV380
||
157 rdev
->family
== CHIP_RV410
||
158 rdev
->family
== CHIP_R423
) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev
->flags
|= RADEON_IS_PCIE
;
161 rdev
->asic
->gart
.tlb_flush
= &rv370_pcie_gart_tlb_flush
;
162 rdev
->asic
->gart
.set_page
= &rv370_pcie_gart_set_page
;
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev
->flags
|= RADEON_IS_PCI
;
166 rdev
->asic
->gart
.tlb_flush
= &r100_pci_gart_tlb_flush
;
167 rdev
->asic
->gart
.set_page
= &r100_pci_gart_set_page
;
169 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
175 static struct radeon_asic r100_asic
= {
178 .suspend
= &r100_suspend
,
179 .resume
= &r100_resume
,
180 .vga_set_state
= &r100_vga_set_state
,
181 .asic_reset
= &r100_asic_reset
,
182 .ioctl_wait_idle
= NULL
,
183 .gui_idle
= &r100_gui_idle
,
184 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
186 .tlb_flush
= &r100_pci_gart_tlb_flush
,
187 .set_page
= &r100_pci_gart_set_page
,
190 [RADEON_RING_TYPE_GFX_INDEX
] = {
191 .ib_execute
= &r100_ring_ib_execute
,
192 .emit_fence
= &r100_fence_ring_emit
,
193 .emit_semaphore
= &r100_semaphore_ring_emit
,
194 .cs_parse
= &r100_cs_parse
,
195 .ring_start
= &r100_ring_start
,
196 .ring_test
= &r100_ring_test
,
197 .ib_test
= &r100_ib_test
,
198 .is_lockup
= &r100_gpu_is_lockup
,
199 .get_rptr
= &radeon_ring_generic_get_rptr
,
200 .get_wptr
= &radeon_ring_generic_get_wptr
,
201 .set_wptr
= &radeon_ring_generic_set_wptr
,
205 .set
= &r100_irq_set
,
206 .process
= &r100_irq_process
,
209 .bandwidth_update
= &r100_bandwidth_update
,
210 .get_vblank_counter
= &r100_get_vblank_counter
,
211 .wait_for_vblank
= &r100_wait_for_vblank
,
212 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
213 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
216 .blit
= &r100_copy_blit
,
217 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
219 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
220 .copy
= &r100_copy_blit
,
221 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
224 .set_reg
= r100_set_surface_reg
,
225 .clear_reg
= r100_clear_surface_reg
,
228 .init
= &r100_hpd_init
,
229 .fini
= &r100_hpd_fini
,
230 .sense
= &r100_hpd_sense
,
231 .set_polarity
= &r100_hpd_set_polarity
,
234 .misc
= &r100_pm_misc
,
235 .prepare
= &r100_pm_prepare
,
236 .finish
= &r100_pm_finish
,
237 .init_profile
= &r100_pm_init_profile
,
238 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
239 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
240 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
241 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
242 .set_memory_clock
= NULL
,
243 .get_pcie_lanes
= NULL
,
244 .set_pcie_lanes
= NULL
,
245 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
248 .pre_page_flip
= &r100_pre_page_flip
,
249 .page_flip
= &r100_page_flip
,
250 .post_page_flip
= &r100_post_page_flip
,
254 static struct radeon_asic r200_asic
= {
257 .suspend
= &r100_suspend
,
258 .resume
= &r100_resume
,
259 .vga_set_state
= &r100_vga_set_state
,
260 .asic_reset
= &r100_asic_reset
,
261 .ioctl_wait_idle
= NULL
,
262 .gui_idle
= &r100_gui_idle
,
263 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
265 .tlb_flush
= &r100_pci_gart_tlb_flush
,
266 .set_page
= &r100_pci_gart_set_page
,
269 [RADEON_RING_TYPE_GFX_INDEX
] = {
270 .ib_execute
= &r100_ring_ib_execute
,
271 .emit_fence
= &r100_fence_ring_emit
,
272 .emit_semaphore
= &r100_semaphore_ring_emit
,
273 .cs_parse
= &r100_cs_parse
,
274 .ring_start
= &r100_ring_start
,
275 .ring_test
= &r100_ring_test
,
276 .ib_test
= &r100_ib_test
,
277 .is_lockup
= &r100_gpu_is_lockup
,
278 .get_rptr
= &radeon_ring_generic_get_rptr
,
279 .get_wptr
= &radeon_ring_generic_get_wptr
,
280 .set_wptr
= &radeon_ring_generic_set_wptr
,
284 .set
= &r100_irq_set
,
285 .process
= &r100_irq_process
,
288 .bandwidth_update
= &r100_bandwidth_update
,
289 .get_vblank_counter
= &r100_get_vblank_counter
,
290 .wait_for_vblank
= &r100_wait_for_vblank
,
291 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
292 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
295 .blit
= &r100_copy_blit
,
296 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
297 .dma
= &r200_copy_dma
,
298 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
299 .copy
= &r100_copy_blit
,
300 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
303 .set_reg
= r100_set_surface_reg
,
304 .clear_reg
= r100_clear_surface_reg
,
307 .init
= &r100_hpd_init
,
308 .fini
= &r100_hpd_fini
,
309 .sense
= &r100_hpd_sense
,
310 .set_polarity
= &r100_hpd_set_polarity
,
313 .misc
= &r100_pm_misc
,
314 .prepare
= &r100_pm_prepare
,
315 .finish
= &r100_pm_finish
,
316 .init_profile
= &r100_pm_init_profile
,
317 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
318 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
319 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
320 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
321 .set_memory_clock
= NULL
,
322 .get_pcie_lanes
= NULL
,
323 .set_pcie_lanes
= NULL
,
324 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
327 .pre_page_flip
= &r100_pre_page_flip
,
328 .page_flip
= &r100_page_flip
,
329 .post_page_flip
= &r100_post_page_flip
,
333 static struct radeon_asic r300_asic
= {
336 .suspend
= &r300_suspend
,
337 .resume
= &r300_resume
,
338 .vga_set_state
= &r100_vga_set_state
,
339 .asic_reset
= &r300_asic_reset
,
340 .ioctl_wait_idle
= NULL
,
341 .gui_idle
= &r100_gui_idle
,
342 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
344 .tlb_flush
= &r100_pci_gart_tlb_flush
,
345 .set_page
= &r100_pci_gart_set_page
,
348 [RADEON_RING_TYPE_GFX_INDEX
] = {
349 .ib_execute
= &r100_ring_ib_execute
,
350 .emit_fence
= &r300_fence_ring_emit
,
351 .emit_semaphore
= &r100_semaphore_ring_emit
,
352 .cs_parse
= &r300_cs_parse
,
353 .ring_start
= &r300_ring_start
,
354 .ring_test
= &r100_ring_test
,
355 .ib_test
= &r100_ib_test
,
356 .is_lockup
= &r100_gpu_is_lockup
,
357 .get_rptr
= &radeon_ring_generic_get_rptr
,
358 .get_wptr
= &radeon_ring_generic_get_wptr
,
359 .set_wptr
= &radeon_ring_generic_set_wptr
,
363 .set
= &r100_irq_set
,
364 .process
= &r100_irq_process
,
367 .bandwidth_update
= &r100_bandwidth_update
,
368 .get_vblank_counter
= &r100_get_vblank_counter
,
369 .wait_for_vblank
= &r100_wait_for_vblank
,
370 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
371 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
374 .blit
= &r100_copy_blit
,
375 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
376 .dma
= &r200_copy_dma
,
377 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
378 .copy
= &r100_copy_blit
,
379 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
382 .set_reg
= r100_set_surface_reg
,
383 .clear_reg
= r100_clear_surface_reg
,
386 .init
= &r100_hpd_init
,
387 .fini
= &r100_hpd_fini
,
388 .sense
= &r100_hpd_sense
,
389 .set_polarity
= &r100_hpd_set_polarity
,
392 .misc
= &r100_pm_misc
,
393 .prepare
= &r100_pm_prepare
,
394 .finish
= &r100_pm_finish
,
395 .init_profile
= &r100_pm_init_profile
,
396 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
397 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
398 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
399 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
400 .set_memory_clock
= NULL
,
401 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
402 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
403 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
406 .pre_page_flip
= &r100_pre_page_flip
,
407 .page_flip
= &r100_page_flip
,
408 .post_page_flip
= &r100_post_page_flip
,
412 static struct radeon_asic r300_asic_pcie
= {
415 .suspend
= &r300_suspend
,
416 .resume
= &r300_resume
,
417 .vga_set_state
= &r100_vga_set_state
,
418 .asic_reset
= &r300_asic_reset
,
419 .ioctl_wait_idle
= NULL
,
420 .gui_idle
= &r100_gui_idle
,
421 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
423 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
424 .set_page
= &rv370_pcie_gart_set_page
,
427 [RADEON_RING_TYPE_GFX_INDEX
] = {
428 .ib_execute
= &r100_ring_ib_execute
,
429 .emit_fence
= &r300_fence_ring_emit
,
430 .emit_semaphore
= &r100_semaphore_ring_emit
,
431 .cs_parse
= &r300_cs_parse
,
432 .ring_start
= &r300_ring_start
,
433 .ring_test
= &r100_ring_test
,
434 .ib_test
= &r100_ib_test
,
435 .is_lockup
= &r100_gpu_is_lockup
,
436 .get_rptr
= &radeon_ring_generic_get_rptr
,
437 .get_wptr
= &radeon_ring_generic_get_wptr
,
438 .set_wptr
= &radeon_ring_generic_set_wptr
,
442 .set
= &r100_irq_set
,
443 .process
= &r100_irq_process
,
446 .bandwidth_update
= &r100_bandwidth_update
,
447 .get_vblank_counter
= &r100_get_vblank_counter
,
448 .wait_for_vblank
= &r100_wait_for_vblank
,
449 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
450 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
453 .blit
= &r100_copy_blit
,
454 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
455 .dma
= &r200_copy_dma
,
456 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
457 .copy
= &r100_copy_blit
,
458 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
461 .set_reg
= r100_set_surface_reg
,
462 .clear_reg
= r100_clear_surface_reg
,
465 .init
= &r100_hpd_init
,
466 .fini
= &r100_hpd_fini
,
467 .sense
= &r100_hpd_sense
,
468 .set_polarity
= &r100_hpd_set_polarity
,
471 .misc
= &r100_pm_misc
,
472 .prepare
= &r100_pm_prepare
,
473 .finish
= &r100_pm_finish
,
474 .init_profile
= &r100_pm_init_profile
,
475 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
476 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
477 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
478 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
479 .set_memory_clock
= NULL
,
480 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
481 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
482 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
485 .pre_page_flip
= &r100_pre_page_flip
,
486 .page_flip
= &r100_page_flip
,
487 .post_page_flip
= &r100_post_page_flip
,
491 static struct radeon_asic r420_asic
= {
494 .suspend
= &r420_suspend
,
495 .resume
= &r420_resume
,
496 .vga_set_state
= &r100_vga_set_state
,
497 .asic_reset
= &r300_asic_reset
,
498 .ioctl_wait_idle
= NULL
,
499 .gui_idle
= &r100_gui_idle
,
500 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
502 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
503 .set_page
= &rv370_pcie_gart_set_page
,
506 [RADEON_RING_TYPE_GFX_INDEX
] = {
507 .ib_execute
= &r100_ring_ib_execute
,
508 .emit_fence
= &r300_fence_ring_emit
,
509 .emit_semaphore
= &r100_semaphore_ring_emit
,
510 .cs_parse
= &r300_cs_parse
,
511 .ring_start
= &r300_ring_start
,
512 .ring_test
= &r100_ring_test
,
513 .ib_test
= &r100_ib_test
,
514 .is_lockup
= &r100_gpu_is_lockup
,
515 .get_rptr
= &radeon_ring_generic_get_rptr
,
516 .get_wptr
= &radeon_ring_generic_get_wptr
,
517 .set_wptr
= &radeon_ring_generic_set_wptr
,
521 .set
= &r100_irq_set
,
522 .process
= &r100_irq_process
,
525 .bandwidth_update
= &r100_bandwidth_update
,
526 .get_vblank_counter
= &r100_get_vblank_counter
,
527 .wait_for_vblank
= &r100_wait_for_vblank
,
528 .set_backlight_level
= &atombios_set_backlight_level
,
529 .get_backlight_level
= &atombios_get_backlight_level
,
532 .blit
= &r100_copy_blit
,
533 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
534 .dma
= &r200_copy_dma
,
535 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
536 .copy
= &r100_copy_blit
,
537 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
540 .set_reg
= r100_set_surface_reg
,
541 .clear_reg
= r100_clear_surface_reg
,
544 .init
= &r100_hpd_init
,
545 .fini
= &r100_hpd_fini
,
546 .sense
= &r100_hpd_sense
,
547 .set_polarity
= &r100_hpd_set_polarity
,
550 .misc
= &r100_pm_misc
,
551 .prepare
= &r100_pm_prepare
,
552 .finish
= &r100_pm_finish
,
553 .init_profile
= &r420_pm_init_profile
,
554 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
555 .get_engine_clock
= &radeon_atom_get_engine_clock
,
556 .set_engine_clock
= &radeon_atom_set_engine_clock
,
557 .get_memory_clock
= &radeon_atom_get_memory_clock
,
558 .set_memory_clock
= &radeon_atom_set_memory_clock
,
559 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
560 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
561 .set_clock_gating
= &radeon_atom_set_clock_gating
,
564 .pre_page_flip
= &r100_pre_page_flip
,
565 .page_flip
= &r100_page_flip
,
566 .post_page_flip
= &r100_post_page_flip
,
570 static struct radeon_asic rs400_asic
= {
573 .suspend
= &rs400_suspend
,
574 .resume
= &rs400_resume
,
575 .vga_set_state
= &r100_vga_set_state
,
576 .asic_reset
= &r300_asic_reset
,
577 .ioctl_wait_idle
= NULL
,
578 .gui_idle
= &r100_gui_idle
,
579 .mc_wait_for_idle
= &rs400_mc_wait_for_idle
,
581 .tlb_flush
= &rs400_gart_tlb_flush
,
582 .set_page
= &rs400_gart_set_page
,
585 [RADEON_RING_TYPE_GFX_INDEX
] = {
586 .ib_execute
= &r100_ring_ib_execute
,
587 .emit_fence
= &r300_fence_ring_emit
,
588 .emit_semaphore
= &r100_semaphore_ring_emit
,
589 .cs_parse
= &r300_cs_parse
,
590 .ring_start
= &r300_ring_start
,
591 .ring_test
= &r100_ring_test
,
592 .ib_test
= &r100_ib_test
,
593 .is_lockup
= &r100_gpu_is_lockup
,
594 .get_rptr
= &radeon_ring_generic_get_rptr
,
595 .get_wptr
= &radeon_ring_generic_get_wptr
,
596 .set_wptr
= &radeon_ring_generic_set_wptr
,
600 .set
= &r100_irq_set
,
601 .process
= &r100_irq_process
,
604 .bandwidth_update
= &r100_bandwidth_update
,
605 .get_vblank_counter
= &r100_get_vblank_counter
,
606 .wait_for_vblank
= &r100_wait_for_vblank
,
607 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
608 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
611 .blit
= &r100_copy_blit
,
612 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
613 .dma
= &r200_copy_dma
,
614 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
615 .copy
= &r100_copy_blit
,
616 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
619 .set_reg
= r100_set_surface_reg
,
620 .clear_reg
= r100_clear_surface_reg
,
623 .init
= &r100_hpd_init
,
624 .fini
= &r100_hpd_fini
,
625 .sense
= &r100_hpd_sense
,
626 .set_polarity
= &r100_hpd_set_polarity
,
629 .misc
= &r100_pm_misc
,
630 .prepare
= &r100_pm_prepare
,
631 .finish
= &r100_pm_finish
,
632 .init_profile
= &r100_pm_init_profile
,
633 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
634 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
635 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
636 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
637 .set_memory_clock
= NULL
,
638 .get_pcie_lanes
= NULL
,
639 .set_pcie_lanes
= NULL
,
640 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
643 .pre_page_flip
= &r100_pre_page_flip
,
644 .page_flip
= &r100_page_flip
,
645 .post_page_flip
= &r100_post_page_flip
,
649 static struct radeon_asic rs600_asic
= {
652 .suspend
= &rs600_suspend
,
653 .resume
= &rs600_resume
,
654 .vga_set_state
= &r100_vga_set_state
,
655 .asic_reset
= &rs600_asic_reset
,
656 .ioctl_wait_idle
= NULL
,
657 .gui_idle
= &r100_gui_idle
,
658 .mc_wait_for_idle
= &rs600_mc_wait_for_idle
,
660 .tlb_flush
= &rs600_gart_tlb_flush
,
661 .set_page
= &rs600_gart_set_page
,
664 [RADEON_RING_TYPE_GFX_INDEX
] = {
665 .ib_execute
= &r100_ring_ib_execute
,
666 .emit_fence
= &r300_fence_ring_emit
,
667 .emit_semaphore
= &r100_semaphore_ring_emit
,
668 .cs_parse
= &r300_cs_parse
,
669 .ring_start
= &r300_ring_start
,
670 .ring_test
= &r100_ring_test
,
671 .ib_test
= &r100_ib_test
,
672 .is_lockup
= &r100_gpu_is_lockup
,
673 .get_rptr
= &radeon_ring_generic_get_rptr
,
674 .get_wptr
= &radeon_ring_generic_get_wptr
,
675 .set_wptr
= &radeon_ring_generic_set_wptr
,
679 .set
= &rs600_irq_set
,
680 .process
= &rs600_irq_process
,
683 .bandwidth_update
= &rs600_bandwidth_update
,
684 .get_vblank_counter
= &rs600_get_vblank_counter
,
685 .wait_for_vblank
= &avivo_wait_for_vblank
,
686 .set_backlight_level
= &atombios_set_backlight_level
,
687 .get_backlight_level
= &atombios_get_backlight_level
,
688 .hdmi_enable
= &r600_hdmi_enable
,
689 .hdmi_setmode
= &r600_hdmi_setmode
,
692 .blit
= &r100_copy_blit
,
693 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
694 .dma
= &r200_copy_dma
,
695 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
696 .copy
= &r100_copy_blit
,
697 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
700 .set_reg
= r100_set_surface_reg
,
701 .clear_reg
= r100_clear_surface_reg
,
704 .init
= &rs600_hpd_init
,
705 .fini
= &rs600_hpd_fini
,
706 .sense
= &rs600_hpd_sense
,
707 .set_polarity
= &rs600_hpd_set_polarity
,
710 .misc
= &rs600_pm_misc
,
711 .prepare
= &rs600_pm_prepare
,
712 .finish
= &rs600_pm_finish
,
713 .init_profile
= &r420_pm_init_profile
,
714 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
715 .get_engine_clock
= &radeon_atom_get_engine_clock
,
716 .set_engine_clock
= &radeon_atom_set_engine_clock
,
717 .get_memory_clock
= &radeon_atom_get_memory_clock
,
718 .set_memory_clock
= &radeon_atom_set_memory_clock
,
719 .get_pcie_lanes
= NULL
,
720 .set_pcie_lanes
= NULL
,
721 .set_clock_gating
= &radeon_atom_set_clock_gating
,
724 .pre_page_flip
= &rs600_pre_page_flip
,
725 .page_flip
= &rs600_page_flip
,
726 .post_page_flip
= &rs600_post_page_flip
,
730 static struct radeon_asic rs690_asic
= {
733 .suspend
= &rs690_suspend
,
734 .resume
= &rs690_resume
,
735 .vga_set_state
= &r100_vga_set_state
,
736 .asic_reset
= &rs600_asic_reset
,
737 .ioctl_wait_idle
= NULL
,
738 .gui_idle
= &r100_gui_idle
,
739 .mc_wait_for_idle
= &rs690_mc_wait_for_idle
,
741 .tlb_flush
= &rs400_gart_tlb_flush
,
742 .set_page
= &rs400_gart_set_page
,
745 [RADEON_RING_TYPE_GFX_INDEX
] = {
746 .ib_execute
= &r100_ring_ib_execute
,
747 .emit_fence
= &r300_fence_ring_emit
,
748 .emit_semaphore
= &r100_semaphore_ring_emit
,
749 .cs_parse
= &r300_cs_parse
,
750 .ring_start
= &r300_ring_start
,
751 .ring_test
= &r100_ring_test
,
752 .ib_test
= &r100_ib_test
,
753 .is_lockup
= &r100_gpu_is_lockup
,
754 .get_rptr
= &radeon_ring_generic_get_rptr
,
755 .get_wptr
= &radeon_ring_generic_get_wptr
,
756 .set_wptr
= &radeon_ring_generic_set_wptr
,
760 .set
= &rs600_irq_set
,
761 .process
= &rs600_irq_process
,
764 .get_vblank_counter
= &rs600_get_vblank_counter
,
765 .bandwidth_update
= &rs690_bandwidth_update
,
766 .wait_for_vblank
= &avivo_wait_for_vblank
,
767 .set_backlight_level
= &atombios_set_backlight_level
,
768 .get_backlight_level
= &atombios_get_backlight_level
,
769 .hdmi_enable
= &r600_hdmi_enable
,
770 .hdmi_setmode
= &r600_hdmi_setmode
,
773 .blit
= &r100_copy_blit
,
774 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
775 .dma
= &r200_copy_dma
,
776 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
777 .copy
= &r200_copy_dma
,
778 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
781 .set_reg
= r100_set_surface_reg
,
782 .clear_reg
= r100_clear_surface_reg
,
785 .init
= &rs600_hpd_init
,
786 .fini
= &rs600_hpd_fini
,
787 .sense
= &rs600_hpd_sense
,
788 .set_polarity
= &rs600_hpd_set_polarity
,
791 .misc
= &rs600_pm_misc
,
792 .prepare
= &rs600_pm_prepare
,
793 .finish
= &rs600_pm_finish
,
794 .init_profile
= &r420_pm_init_profile
,
795 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
796 .get_engine_clock
= &radeon_atom_get_engine_clock
,
797 .set_engine_clock
= &radeon_atom_set_engine_clock
,
798 .get_memory_clock
= &radeon_atom_get_memory_clock
,
799 .set_memory_clock
= &radeon_atom_set_memory_clock
,
800 .get_pcie_lanes
= NULL
,
801 .set_pcie_lanes
= NULL
,
802 .set_clock_gating
= &radeon_atom_set_clock_gating
,
805 .pre_page_flip
= &rs600_pre_page_flip
,
806 .page_flip
= &rs600_page_flip
,
807 .post_page_flip
= &rs600_post_page_flip
,
811 static struct radeon_asic rv515_asic
= {
814 .suspend
= &rv515_suspend
,
815 .resume
= &rv515_resume
,
816 .vga_set_state
= &r100_vga_set_state
,
817 .asic_reset
= &rs600_asic_reset
,
818 .ioctl_wait_idle
= NULL
,
819 .gui_idle
= &r100_gui_idle
,
820 .mc_wait_for_idle
= &rv515_mc_wait_for_idle
,
822 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
823 .set_page
= &rv370_pcie_gart_set_page
,
826 [RADEON_RING_TYPE_GFX_INDEX
] = {
827 .ib_execute
= &r100_ring_ib_execute
,
828 .emit_fence
= &r300_fence_ring_emit
,
829 .emit_semaphore
= &r100_semaphore_ring_emit
,
830 .cs_parse
= &r300_cs_parse
,
831 .ring_start
= &rv515_ring_start
,
832 .ring_test
= &r100_ring_test
,
833 .ib_test
= &r100_ib_test
,
834 .is_lockup
= &r100_gpu_is_lockup
,
835 .get_rptr
= &radeon_ring_generic_get_rptr
,
836 .get_wptr
= &radeon_ring_generic_get_wptr
,
837 .set_wptr
= &radeon_ring_generic_set_wptr
,
841 .set
= &rs600_irq_set
,
842 .process
= &rs600_irq_process
,
845 .get_vblank_counter
= &rs600_get_vblank_counter
,
846 .bandwidth_update
= &rv515_bandwidth_update
,
847 .wait_for_vblank
= &avivo_wait_for_vblank
,
848 .set_backlight_level
= &atombios_set_backlight_level
,
849 .get_backlight_level
= &atombios_get_backlight_level
,
852 .blit
= &r100_copy_blit
,
853 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
854 .dma
= &r200_copy_dma
,
855 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
856 .copy
= &r100_copy_blit
,
857 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
860 .set_reg
= r100_set_surface_reg
,
861 .clear_reg
= r100_clear_surface_reg
,
864 .init
= &rs600_hpd_init
,
865 .fini
= &rs600_hpd_fini
,
866 .sense
= &rs600_hpd_sense
,
867 .set_polarity
= &rs600_hpd_set_polarity
,
870 .misc
= &rs600_pm_misc
,
871 .prepare
= &rs600_pm_prepare
,
872 .finish
= &rs600_pm_finish
,
873 .init_profile
= &r420_pm_init_profile
,
874 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
875 .get_engine_clock
= &radeon_atom_get_engine_clock
,
876 .set_engine_clock
= &radeon_atom_set_engine_clock
,
877 .get_memory_clock
= &radeon_atom_get_memory_clock
,
878 .set_memory_clock
= &radeon_atom_set_memory_clock
,
879 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
880 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
881 .set_clock_gating
= &radeon_atom_set_clock_gating
,
884 .pre_page_flip
= &rs600_pre_page_flip
,
885 .page_flip
= &rs600_page_flip
,
886 .post_page_flip
= &rs600_post_page_flip
,
890 static struct radeon_asic r520_asic
= {
893 .suspend
= &rv515_suspend
,
894 .resume
= &r520_resume
,
895 .vga_set_state
= &r100_vga_set_state
,
896 .asic_reset
= &rs600_asic_reset
,
897 .ioctl_wait_idle
= NULL
,
898 .gui_idle
= &r100_gui_idle
,
899 .mc_wait_for_idle
= &r520_mc_wait_for_idle
,
901 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
902 .set_page
= &rv370_pcie_gart_set_page
,
905 [RADEON_RING_TYPE_GFX_INDEX
] = {
906 .ib_execute
= &r100_ring_ib_execute
,
907 .emit_fence
= &r300_fence_ring_emit
,
908 .emit_semaphore
= &r100_semaphore_ring_emit
,
909 .cs_parse
= &r300_cs_parse
,
910 .ring_start
= &rv515_ring_start
,
911 .ring_test
= &r100_ring_test
,
912 .ib_test
= &r100_ib_test
,
913 .is_lockup
= &r100_gpu_is_lockup
,
914 .get_rptr
= &radeon_ring_generic_get_rptr
,
915 .get_wptr
= &radeon_ring_generic_get_wptr
,
916 .set_wptr
= &radeon_ring_generic_set_wptr
,
920 .set
= &rs600_irq_set
,
921 .process
= &rs600_irq_process
,
924 .bandwidth_update
= &rv515_bandwidth_update
,
925 .get_vblank_counter
= &rs600_get_vblank_counter
,
926 .wait_for_vblank
= &avivo_wait_for_vblank
,
927 .set_backlight_level
= &atombios_set_backlight_level
,
928 .get_backlight_level
= &atombios_get_backlight_level
,
931 .blit
= &r100_copy_blit
,
932 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
933 .dma
= &r200_copy_dma
,
934 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
935 .copy
= &r100_copy_blit
,
936 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
939 .set_reg
= r100_set_surface_reg
,
940 .clear_reg
= r100_clear_surface_reg
,
943 .init
= &rs600_hpd_init
,
944 .fini
= &rs600_hpd_fini
,
945 .sense
= &rs600_hpd_sense
,
946 .set_polarity
= &rs600_hpd_set_polarity
,
949 .misc
= &rs600_pm_misc
,
950 .prepare
= &rs600_pm_prepare
,
951 .finish
= &rs600_pm_finish
,
952 .init_profile
= &r420_pm_init_profile
,
953 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
954 .get_engine_clock
= &radeon_atom_get_engine_clock
,
955 .set_engine_clock
= &radeon_atom_set_engine_clock
,
956 .get_memory_clock
= &radeon_atom_get_memory_clock
,
957 .set_memory_clock
= &radeon_atom_set_memory_clock
,
958 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
959 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
960 .set_clock_gating
= &radeon_atom_set_clock_gating
,
963 .pre_page_flip
= &rs600_pre_page_flip
,
964 .page_flip
= &rs600_page_flip
,
965 .post_page_flip
= &rs600_post_page_flip
,
969 static struct radeon_asic r600_asic
= {
972 .suspend
= &r600_suspend
,
973 .resume
= &r600_resume
,
974 .vga_set_state
= &r600_vga_set_state
,
975 .asic_reset
= &r600_asic_reset
,
976 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
977 .gui_idle
= &r600_gui_idle
,
978 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
979 .get_xclk
= &r600_get_xclk
,
980 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
982 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
983 .set_page
= &rs600_gart_set_page
,
986 [RADEON_RING_TYPE_GFX_INDEX
] = {
987 .ib_execute
= &r600_ring_ib_execute
,
988 .emit_fence
= &r600_fence_ring_emit
,
989 .emit_semaphore
= &r600_semaphore_ring_emit
,
990 .cs_parse
= &r600_cs_parse
,
991 .ring_test
= &r600_ring_test
,
992 .ib_test
= &r600_ib_test
,
993 .is_lockup
= &r600_gfx_is_lockup
,
994 .get_rptr
= &radeon_ring_generic_get_rptr
,
995 .get_wptr
= &radeon_ring_generic_get_wptr
,
996 .set_wptr
= &radeon_ring_generic_set_wptr
,
998 [R600_RING_TYPE_DMA_INDEX
] = {
999 .ib_execute
= &r600_dma_ring_ib_execute
,
1000 .emit_fence
= &r600_dma_fence_ring_emit
,
1001 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1002 .cs_parse
= &r600_dma_cs_parse
,
1003 .ring_test
= &r600_dma_ring_test
,
1004 .ib_test
= &r600_dma_ib_test
,
1005 .is_lockup
= &r600_dma_is_lockup
,
1006 .get_rptr
= &radeon_ring_generic_get_rptr
,
1007 .get_wptr
= &radeon_ring_generic_get_wptr
,
1008 .set_wptr
= &radeon_ring_generic_set_wptr
,
1012 .set
= &r600_irq_set
,
1013 .process
= &r600_irq_process
,
1016 .bandwidth_update
= &rv515_bandwidth_update
,
1017 .get_vblank_counter
= &rs600_get_vblank_counter
,
1018 .wait_for_vblank
= &avivo_wait_for_vblank
,
1019 .set_backlight_level
= &atombios_set_backlight_level
,
1020 .get_backlight_level
= &atombios_get_backlight_level
,
1021 .hdmi_enable
= &r600_hdmi_enable
,
1022 .hdmi_setmode
= &r600_hdmi_setmode
,
1025 .blit
= &r600_copy_blit
,
1026 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1027 .dma
= &r600_copy_dma
,
1028 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1029 .copy
= &r600_copy_dma
,
1030 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1033 .set_reg
= r600_set_surface_reg
,
1034 .clear_reg
= r600_clear_surface_reg
,
1037 .init
= &r600_hpd_init
,
1038 .fini
= &r600_hpd_fini
,
1039 .sense
= &r600_hpd_sense
,
1040 .set_polarity
= &r600_hpd_set_polarity
,
1043 .misc
= &r600_pm_misc
,
1044 .prepare
= &rs600_pm_prepare
,
1045 .finish
= &rs600_pm_finish
,
1046 .init_profile
= &r600_pm_init_profile
,
1047 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1048 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1049 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1050 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1051 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1052 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1053 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1054 .set_clock_gating
= NULL
,
1055 .get_temperature
= &rv6xx_get_temp
,
1058 .pre_page_flip
= &rs600_pre_page_flip
,
1059 .page_flip
= &rs600_page_flip
,
1060 .post_page_flip
= &rs600_post_page_flip
,
1064 static struct radeon_asic rs780_asic
= {
1067 .suspend
= &r600_suspend
,
1068 .resume
= &r600_resume
,
1069 .vga_set_state
= &r600_vga_set_state
,
1070 .asic_reset
= &r600_asic_reset
,
1071 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1072 .gui_idle
= &r600_gui_idle
,
1073 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1074 .get_xclk
= &r600_get_xclk
,
1075 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1077 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1078 .set_page
= &rs600_gart_set_page
,
1081 [RADEON_RING_TYPE_GFX_INDEX
] = {
1082 .ib_execute
= &r600_ring_ib_execute
,
1083 .emit_fence
= &r600_fence_ring_emit
,
1084 .emit_semaphore
= &r600_semaphore_ring_emit
,
1085 .cs_parse
= &r600_cs_parse
,
1086 .ring_test
= &r600_ring_test
,
1087 .ib_test
= &r600_ib_test
,
1088 .is_lockup
= &r600_gfx_is_lockup
,
1089 .get_rptr
= &radeon_ring_generic_get_rptr
,
1090 .get_wptr
= &radeon_ring_generic_get_wptr
,
1091 .set_wptr
= &radeon_ring_generic_set_wptr
,
1093 [R600_RING_TYPE_DMA_INDEX
] = {
1094 .ib_execute
= &r600_dma_ring_ib_execute
,
1095 .emit_fence
= &r600_dma_fence_ring_emit
,
1096 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1097 .cs_parse
= &r600_dma_cs_parse
,
1098 .ring_test
= &r600_dma_ring_test
,
1099 .ib_test
= &r600_dma_ib_test
,
1100 .is_lockup
= &r600_dma_is_lockup
,
1101 .get_rptr
= &radeon_ring_generic_get_rptr
,
1102 .get_wptr
= &radeon_ring_generic_get_wptr
,
1103 .set_wptr
= &radeon_ring_generic_set_wptr
,
1107 .set
= &r600_irq_set
,
1108 .process
= &r600_irq_process
,
1111 .bandwidth_update
= &rs690_bandwidth_update
,
1112 .get_vblank_counter
= &rs600_get_vblank_counter
,
1113 .wait_for_vblank
= &avivo_wait_for_vblank
,
1114 .set_backlight_level
= &atombios_set_backlight_level
,
1115 .get_backlight_level
= &atombios_get_backlight_level
,
1116 .hdmi_enable
= &r600_hdmi_enable
,
1117 .hdmi_setmode
= &r600_hdmi_setmode
,
1120 .blit
= &r600_copy_blit
,
1121 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1122 .dma
= &r600_copy_dma
,
1123 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1124 .copy
= &r600_copy_dma
,
1125 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1128 .set_reg
= r600_set_surface_reg
,
1129 .clear_reg
= r600_clear_surface_reg
,
1132 .init
= &r600_hpd_init
,
1133 .fini
= &r600_hpd_fini
,
1134 .sense
= &r600_hpd_sense
,
1135 .set_polarity
= &r600_hpd_set_polarity
,
1138 .misc
= &r600_pm_misc
,
1139 .prepare
= &rs600_pm_prepare
,
1140 .finish
= &rs600_pm_finish
,
1141 .init_profile
= &rs780_pm_init_profile
,
1142 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1143 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1144 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1145 .get_memory_clock
= NULL
,
1146 .set_memory_clock
= NULL
,
1147 .get_pcie_lanes
= NULL
,
1148 .set_pcie_lanes
= NULL
,
1149 .set_clock_gating
= NULL
,
1150 .get_temperature
= &rv6xx_get_temp
,
1153 .pre_page_flip
= &rs600_pre_page_flip
,
1154 .page_flip
= &rs600_page_flip
,
1155 .post_page_flip
= &rs600_post_page_flip
,
1159 static struct radeon_asic rv770_asic
= {
1160 .init
= &rv770_init
,
1161 .fini
= &rv770_fini
,
1162 .suspend
= &rv770_suspend
,
1163 .resume
= &rv770_resume
,
1164 .asic_reset
= &r600_asic_reset
,
1165 .vga_set_state
= &r600_vga_set_state
,
1166 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1167 .gui_idle
= &r600_gui_idle
,
1168 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1169 .get_xclk
= &rv770_get_xclk
,
1170 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1172 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1173 .set_page
= &rs600_gart_set_page
,
1176 [RADEON_RING_TYPE_GFX_INDEX
] = {
1177 .ib_execute
= &r600_ring_ib_execute
,
1178 .emit_fence
= &r600_fence_ring_emit
,
1179 .emit_semaphore
= &r600_semaphore_ring_emit
,
1180 .cs_parse
= &r600_cs_parse
,
1181 .ring_test
= &r600_ring_test
,
1182 .ib_test
= &r600_ib_test
,
1183 .is_lockup
= &r600_gfx_is_lockup
,
1184 .get_rptr
= &radeon_ring_generic_get_rptr
,
1185 .get_wptr
= &radeon_ring_generic_get_wptr
,
1186 .set_wptr
= &radeon_ring_generic_set_wptr
,
1188 [R600_RING_TYPE_DMA_INDEX
] = {
1189 .ib_execute
= &r600_dma_ring_ib_execute
,
1190 .emit_fence
= &r600_dma_fence_ring_emit
,
1191 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1192 .cs_parse
= &r600_dma_cs_parse
,
1193 .ring_test
= &r600_dma_ring_test
,
1194 .ib_test
= &r600_dma_ib_test
,
1195 .is_lockup
= &r600_dma_is_lockup
,
1196 .get_rptr
= &radeon_ring_generic_get_rptr
,
1197 .get_wptr
= &radeon_ring_generic_get_wptr
,
1198 .set_wptr
= &radeon_ring_generic_set_wptr
,
1200 [R600_RING_TYPE_UVD_INDEX
] = {
1201 .ib_execute
= &r600_uvd_ib_execute
,
1202 .emit_fence
= &r600_uvd_fence_emit
,
1203 .emit_semaphore
= &r600_uvd_semaphore_emit
,
1204 .cs_parse
= &radeon_uvd_cs_parse
,
1205 .ring_test
= &r600_uvd_ring_test
,
1206 .ib_test
= &r600_uvd_ib_test
,
1207 .is_lockup
= &radeon_ring_test_lockup
,
1208 .get_rptr
= &radeon_ring_generic_get_rptr
,
1209 .get_wptr
= &radeon_ring_generic_get_wptr
,
1210 .set_wptr
= &radeon_ring_generic_set_wptr
,
1214 .set
= &r600_irq_set
,
1215 .process
= &r600_irq_process
,
1218 .bandwidth_update
= &rv515_bandwidth_update
,
1219 .get_vblank_counter
= &rs600_get_vblank_counter
,
1220 .wait_for_vblank
= &avivo_wait_for_vblank
,
1221 .set_backlight_level
= &atombios_set_backlight_level
,
1222 .get_backlight_level
= &atombios_get_backlight_level
,
1223 .hdmi_enable
= &r600_hdmi_enable
,
1224 .hdmi_setmode
= &r600_hdmi_setmode
,
1227 .blit
= &r600_copy_blit
,
1228 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1229 .dma
= &rv770_copy_dma
,
1230 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1231 .copy
= &rv770_copy_dma
,
1232 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1235 .set_reg
= r600_set_surface_reg
,
1236 .clear_reg
= r600_clear_surface_reg
,
1239 .init
= &r600_hpd_init
,
1240 .fini
= &r600_hpd_fini
,
1241 .sense
= &r600_hpd_sense
,
1242 .set_polarity
= &r600_hpd_set_polarity
,
1245 .misc
= &rv770_pm_misc
,
1246 .prepare
= &rs600_pm_prepare
,
1247 .finish
= &rs600_pm_finish
,
1248 .init_profile
= &r600_pm_init_profile
,
1249 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1250 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1251 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1252 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1253 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1254 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1255 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1256 .set_clock_gating
= &radeon_atom_set_clock_gating
,
1257 .set_uvd_clocks
= &rv770_set_uvd_clocks
,
1258 .get_temperature
= &rv770_get_temp
,
1261 .pre_page_flip
= &rs600_pre_page_flip
,
1262 .page_flip
= &rv770_page_flip
,
1263 .post_page_flip
= &rs600_post_page_flip
,
1267 static struct radeon_asic evergreen_asic
= {
1268 .init
= &evergreen_init
,
1269 .fini
= &evergreen_fini
,
1270 .suspend
= &evergreen_suspend
,
1271 .resume
= &evergreen_resume
,
1272 .asic_reset
= &evergreen_asic_reset
,
1273 .vga_set_state
= &r600_vga_set_state
,
1274 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1275 .gui_idle
= &r600_gui_idle
,
1276 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1277 .get_xclk
= &rv770_get_xclk
,
1278 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1280 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1281 .set_page
= &rs600_gart_set_page
,
1284 [RADEON_RING_TYPE_GFX_INDEX
] = {
1285 .ib_execute
= &evergreen_ring_ib_execute
,
1286 .emit_fence
= &r600_fence_ring_emit
,
1287 .emit_semaphore
= &r600_semaphore_ring_emit
,
1288 .cs_parse
= &evergreen_cs_parse
,
1289 .ring_test
= &r600_ring_test
,
1290 .ib_test
= &r600_ib_test
,
1291 .is_lockup
= &evergreen_gfx_is_lockup
,
1292 .get_rptr
= &radeon_ring_generic_get_rptr
,
1293 .get_wptr
= &radeon_ring_generic_get_wptr
,
1294 .set_wptr
= &radeon_ring_generic_set_wptr
,
1296 [R600_RING_TYPE_DMA_INDEX
] = {
1297 .ib_execute
= &evergreen_dma_ring_ib_execute
,
1298 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1299 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1300 .cs_parse
= &evergreen_dma_cs_parse
,
1301 .ring_test
= &r600_dma_ring_test
,
1302 .ib_test
= &r600_dma_ib_test
,
1303 .is_lockup
= &evergreen_dma_is_lockup
,
1304 .get_rptr
= &radeon_ring_generic_get_rptr
,
1305 .get_wptr
= &radeon_ring_generic_get_wptr
,
1306 .set_wptr
= &radeon_ring_generic_set_wptr
,
1308 [R600_RING_TYPE_UVD_INDEX
] = {
1309 .ib_execute
= &r600_uvd_ib_execute
,
1310 .emit_fence
= &r600_uvd_fence_emit
,
1311 .emit_semaphore
= &r600_uvd_semaphore_emit
,
1312 .cs_parse
= &radeon_uvd_cs_parse
,
1313 .ring_test
= &r600_uvd_ring_test
,
1314 .ib_test
= &r600_uvd_ib_test
,
1315 .is_lockup
= &radeon_ring_test_lockup
,
1316 .get_rptr
= &radeon_ring_generic_get_rptr
,
1317 .get_wptr
= &radeon_ring_generic_get_wptr
,
1318 .set_wptr
= &radeon_ring_generic_set_wptr
,
1322 .set
= &evergreen_irq_set
,
1323 .process
= &evergreen_irq_process
,
1326 .bandwidth_update
= &evergreen_bandwidth_update
,
1327 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1328 .wait_for_vblank
= &dce4_wait_for_vblank
,
1329 .set_backlight_level
= &atombios_set_backlight_level
,
1330 .get_backlight_level
= &atombios_get_backlight_level
,
1331 .hdmi_enable
= &evergreen_hdmi_enable
,
1332 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1335 .blit
= &r600_copy_blit
,
1336 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1337 .dma
= &evergreen_copy_dma
,
1338 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1339 .copy
= &evergreen_copy_dma
,
1340 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1343 .set_reg
= r600_set_surface_reg
,
1344 .clear_reg
= r600_clear_surface_reg
,
1347 .init
= &evergreen_hpd_init
,
1348 .fini
= &evergreen_hpd_fini
,
1349 .sense
= &evergreen_hpd_sense
,
1350 .set_polarity
= &evergreen_hpd_set_polarity
,
1353 .misc
= &evergreen_pm_misc
,
1354 .prepare
= &evergreen_pm_prepare
,
1355 .finish
= &evergreen_pm_finish
,
1356 .init_profile
= &r600_pm_init_profile
,
1357 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1358 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1359 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1360 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1361 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1362 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1363 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1364 .set_clock_gating
= NULL
,
1365 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1366 .get_temperature
= &evergreen_get_temp
,
1369 .pre_page_flip
= &evergreen_pre_page_flip
,
1370 .page_flip
= &evergreen_page_flip
,
1371 .post_page_flip
= &evergreen_post_page_flip
,
1375 static struct radeon_asic sumo_asic
= {
1376 .init
= &evergreen_init
,
1377 .fini
= &evergreen_fini
,
1378 .suspend
= &evergreen_suspend
,
1379 .resume
= &evergreen_resume
,
1380 .asic_reset
= &evergreen_asic_reset
,
1381 .vga_set_state
= &r600_vga_set_state
,
1382 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1383 .gui_idle
= &r600_gui_idle
,
1384 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1385 .get_xclk
= &r600_get_xclk
,
1386 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1388 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1389 .set_page
= &rs600_gart_set_page
,
1392 [RADEON_RING_TYPE_GFX_INDEX
] = {
1393 .ib_execute
= &evergreen_ring_ib_execute
,
1394 .emit_fence
= &r600_fence_ring_emit
,
1395 .emit_semaphore
= &r600_semaphore_ring_emit
,
1396 .cs_parse
= &evergreen_cs_parse
,
1397 .ring_test
= &r600_ring_test
,
1398 .ib_test
= &r600_ib_test
,
1399 .is_lockup
= &evergreen_gfx_is_lockup
,
1400 .get_rptr
= &radeon_ring_generic_get_rptr
,
1401 .get_wptr
= &radeon_ring_generic_get_wptr
,
1402 .set_wptr
= &radeon_ring_generic_set_wptr
,
1404 [R600_RING_TYPE_DMA_INDEX
] = {
1405 .ib_execute
= &evergreen_dma_ring_ib_execute
,
1406 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1407 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1408 .cs_parse
= &evergreen_dma_cs_parse
,
1409 .ring_test
= &r600_dma_ring_test
,
1410 .ib_test
= &r600_dma_ib_test
,
1411 .is_lockup
= &evergreen_dma_is_lockup
,
1412 .get_rptr
= &radeon_ring_generic_get_rptr
,
1413 .get_wptr
= &radeon_ring_generic_get_wptr
,
1414 .set_wptr
= &radeon_ring_generic_set_wptr
,
1416 [R600_RING_TYPE_UVD_INDEX
] = {
1417 .ib_execute
= &r600_uvd_ib_execute
,
1418 .emit_fence
= &r600_uvd_fence_emit
,
1419 .emit_semaphore
= &r600_uvd_semaphore_emit
,
1420 .cs_parse
= &radeon_uvd_cs_parse
,
1421 .ring_test
= &r600_uvd_ring_test
,
1422 .ib_test
= &r600_uvd_ib_test
,
1423 .is_lockup
= &radeon_ring_test_lockup
,
1424 .get_rptr
= &radeon_ring_generic_get_rptr
,
1425 .get_wptr
= &radeon_ring_generic_get_wptr
,
1426 .set_wptr
= &radeon_ring_generic_set_wptr
,
1430 .set
= &evergreen_irq_set
,
1431 .process
= &evergreen_irq_process
,
1434 .bandwidth_update
= &evergreen_bandwidth_update
,
1435 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1436 .wait_for_vblank
= &dce4_wait_for_vblank
,
1437 .set_backlight_level
= &atombios_set_backlight_level
,
1438 .get_backlight_level
= &atombios_get_backlight_level
,
1439 .hdmi_enable
= &evergreen_hdmi_enable
,
1440 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1443 .blit
= &r600_copy_blit
,
1444 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1445 .dma
= &evergreen_copy_dma
,
1446 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1447 .copy
= &evergreen_copy_dma
,
1448 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1451 .set_reg
= r600_set_surface_reg
,
1452 .clear_reg
= r600_clear_surface_reg
,
1455 .init
= &evergreen_hpd_init
,
1456 .fini
= &evergreen_hpd_fini
,
1457 .sense
= &evergreen_hpd_sense
,
1458 .set_polarity
= &evergreen_hpd_set_polarity
,
1461 .misc
= &evergreen_pm_misc
,
1462 .prepare
= &evergreen_pm_prepare
,
1463 .finish
= &evergreen_pm_finish
,
1464 .init_profile
= &sumo_pm_init_profile
,
1465 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1466 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1467 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1468 .get_memory_clock
= NULL
,
1469 .set_memory_clock
= NULL
,
1470 .get_pcie_lanes
= NULL
,
1471 .set_pcie_lanes
= NULL
,
1472 .set_clock_gating
= NULL
,
1473 .set_uvd_clocks
= &sumo_set_uvd_clocks
,
1474 .get_temperature
= &sumo_get_temp
,
1477 .pre_page_flip
= &evergreen_pre_page_flip
,
1478 .page_flip
= &evergreen_page_flip
,
1479 .post_page_flip
= &evergreen_post_page_flip
,
1483 static struct radeon_asic btc_asic
= {
1484 .init
= &evergreen_init
,
1485 .fini
= &evergreen_fini
,
1486 .suspend
= &evergreen_suspend
,
1487 .resume
= &evergreen_resume
,
1488 .asic_reset
= &evergreen_asic_reset
,
1489 .vga_set_state
= &r600_vga_set_state
,
1490 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1491 .gui_idle
= &r600_gui_idle
,
1492 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1493 .get_xclk
= &rv770_get_xclk
,
1494 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1496 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1497 .set_page
= &rs600_gart_set_page
,
1500 [RADEON_RING_TYPE_GFX_INDEX
] = {
1501 .ib_execute
= &evergreen_ring_ib_execute
,
1502 .emit_fence
= &r600_fence_ring_emit
,
1503 .emit_semaphore
= &r600_semaphore_ring_emit
,
1504 .cs_parse
= &evergreen_cs_parse
,
1505 .ring_test
= &r600_ring_test
,
1506 .ib_test
= &r600_ib_test
,
1507 .is_lockup
= &evergreen_gfx_is_lockup
,
1508 .get_rptr
= &radeon_ring_generic_get_rptr
,
1509 .get_wptr
= &radeon_ring_generic_get_wptr
,
1510 .set_wptr
= &radeon_ring_generic_set_wptr
,
1512 [R600_RING_TYPE_DMA_INDEX
] = {
1513 .ib_execute
= &evergreen_dma_ring_ib_execute
,
1514 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1515 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1516 .cs_parse
= &evergreen_dma_cs_parse
,
1517 .ring_test
= &r600_dma_ring_test
,
1518 .ib_test
= &r600_dma_ib_test
,
1519 .is_lockup
= &evergreen_dma_is_lockup
,
1520 .get_rptr
= &radeon_ring_generic_get_rptr
,
1521 .get_wptr
= &radeon_ring_generic_get_wptr
,
1522 .set_wptr
= &radeon_ring_generic_set_wptr
,
1524 [R600_RING_TYPE_UVD_INDEX
] = {
1525 .ib_execute
= &r600_uvd_ib_execute
,
1526 .emit_fence
= &r600_uvd_fence_emit
,
1527 .emit_semaphore
= &r600_uvd_semaphore_emit
,
1528 .cs_parse
= &radeon_uvd_cs_parse
,
1529 .ring_test
= &r600_uvd_ring_test
,
1530 .ib_test
= &r600_uvd_ib_test
,
1531 .is_lockup
= &radeon_ring_test_lockup
,
1532 .get_rptr
= &radeon_ring_generic_get_rptr
,
1533 .get_wptr
= &radeon_ring_generic_get_wptr
,
1534 .set_wptr
= &radeon_ring_generic_set_wptr
,
1538 .set
= &evergreen_irq_set
,
1539 .process
= &evergreen_irq_process
,
1542 .bandwidth_update
= &evergreen_bandwidth_update
,
1543 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1544 .wait_for_vblank
= &dce4_wait_for_vblank
,
1545 .set_backlight_level
= &atombios_set_backlight_level
,
1546 .get_backlight_level
= &atombios_get_backlight_level
,
1547 .hdmi_enable
= &evergreen_hdmi_enable
,
1548 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1551 .blit
= &r600_copy_blit
,
1552 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1553 .dma
= &evergreen_copy_dma
,
1554 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1555 .copy
= &evergreen_copy_dma
,
1556 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1559 .set_reg
= r600_set_surface_reg
,
1560 .clear_reg
= r600_clear_surface_reg
,
1563 .init
= &evergreen_hpd_init
,
1564 .fini
= &evergreen_hpd_fini
,
1565 .sense
= &evergreen_hpd_sense
,
1566 .set_polarity
= &evergreen_hpd_set_polarity
,
1569 .misc
= &evergreen_pm_misc
,
1570 .prepare
= &evergreen_pm_prepare
,
1571 .finish
= &evergreen_pm_finish
,
1572 .init_profile
= &btc_pm_init_profile
,
1573 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1574 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1575 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1576 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1577 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1578 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1579 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1580 .set_clock_gating
= NULL
,
1581 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1582 .get_temperature
= &evergreen_get_temp
,
1585 .pre_page_flip
= &evergreen_pre_page_flip
,
1586 .page_flip
= &evergreen_page_flip
,
1587 .post_page_flip
= &evergreen_post_page_flip
,
1591 static struct radeon_asic cayman_asic
= {
1592 .init
= &cayman_init
,
1593 .fini
= &cayman_fini
,
1594 .suspend
= &cayman_suspend
,
1595 .resume
= &cayman_resume
,
1596 .asic_reset
= &cayman_asic_reset
,
1597 .vga_set_state
= &r600_vga_set_state
,
1598 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1599 .gui_idle
= &r600_gui_idle
,
1600 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1601 .get_xclk
= &rv770_get_xclk
,
1602 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1604 .tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1605 .set_page
= &rs600_gart_set_page
,
1608 .init
= &cayman_vm_init
,
1609 .fini
= &cayman_vm_fini
,
1610 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1611 .set_page
= &cayman_vm_set_page
,
1614 [RADEON_RING_TYPE_GFX_INDEX
] = {
1615 .ib_execute
= &cayman_ring_ib_execute
,
1616 .ib_parse
= &evergreen_ib_parse
,
1617 .emit_fence
= &cayman_fence_ring_emit
,
1618 .emit_semaphore
= &r600_semaphore_ring_emit
,
1619 .cs_parse
= &evergreen_cs_parse
,
1620 .ring_test
= &r600_ring_test
,
1621 .ib_test
= &r600_ib_test
,
1622 .is_lockup
= &cayman_gfx_is_lockup
,
1623 .vm_flush
= &cayman_vm_flush
,
1624 .get_rptr
= &radeon_ring_generic_get_rptr
,
1625 .get_wptr
= &radeon_ring_generic_get_wptr
,
1626 .set_wptr
= &radeon_ring_generic_set_wptr
,
1628 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
1629 .ib_execute
= &cayman_ring_ib_execute
,
1630 .ib_parse
= &evergreen_ib_parse
,
1631 .emit_fence
= &cayman_fence_ring_emit
,
1632 .emit_semaphore
= &r600_semaphore_ring_emit
,
1633 .cs_parse
= &evergreen_cs_parse
,
1634 .ring_test
= &r600_ring_test
,
1635 .ib_test
= &r600_ib_test
,
1636 .is_lockup
= &cayman_gfx_is_lockup
,
1637 .vm_flush
= &cayman_vm_flush
,
1638 .get_rptr
= &radeon_ring_generic_get_rptr
,
1639 .get_wptr
= &radeon_ring_generic_get_wptr
,
1640 .set_wptr
= &radeon_ring_generic_set_wptr
,
1642 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
1643 .ib_execute
= &cayman_ring_ib_execute
,
1644 .ib_parse
= &evergreen_ib_parse
,
1645 .emit_fence
= &cayman_fence_ring_emit
,
1646 .emit_semaphore
= &r600_semaphore_ring_emit
,
1647 .cs_parse
= &evergreen_cs_parse
,
1648 .ring_test
= &r600_ring_test
,
1649 .ib_test
= &r600_ib_test
,
1650 .is_lockup
= &cayman_gfx_is_lockup
,
1651 .vm_flush
= &cayman_vm_flush
,
1652 .get_rptr
= &radeon_ring_generic_get_rptr
,
1653 .get_wptr
= &radeon_ring_generic_get_wptr
,
1654 .set_wptr
= &radeon_ring_generic_set_wptr
,
1656 [R600_RING_TYPE_DMA_INDEX
] = {
1657 .ib_execute
= &cayman_dma_ring_ib_execute
,
1658 .ib_parse
= &evergreen_dma_ib_parse
,
1659 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1660 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1661 .cs_parse
= &evergreen_dma_cs_parse
,
1662 .ring_test
= &r600_dma_ring_test
,
1663 .ib_test
= &r600_dma_ib_test
,
1664 .is_lockup
= &cayman_dma_is_lockup
,
1665 .vm_flush
= &cayman_dma_vm_flush
,
1666 .get_rptr
= &radeon_ring_generic_get_rptr
,
1667 .get_wptr
= &radeon_ring_generic_get_wptr
,
1668 .set_wptr
= &radeon_ring_generic_set_wptr
,
1670 [CAYMAN_RING_TYPE_DMA1_INDEX
] = {
1671 .ib_execute
= &cayman_dma_ring_ib_execute
,
1672 .ib_parse
= &evergreen_dma_ib_parse
,
1673 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1674 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1675 .cs_parse
= &evergreen_dma_cs_parse
,
1676 .ring_test
= &r600_dma_ring_test
,
1677 .ib_test
= &r600_dma_ib_test
,
1678 .is_lockup
= &cayman_dma_is_lockup
,
1679 .vm_flush
= &cayman_dma_vm_flush
,
1680 .get_rptr
= &radeon_ring_generic_get_rptr
,
1681 .get_wptr
= &radeon_ring_generic_get_wptr
,
1682 .set_wptr
= &radeon_ring_generic_set_wptr
,
1684 [R600_RING_TYPE_UVD_INDEX
] = {
1685 .ib_execute
= &r600_uvd_ib_execute
,
1686 .emit_fence
= &r600_uvd_fence_emit
,
1687 .emit_semaphore
= &cayman_uvd_semaphore_emit
,
1688 .cs_parse
= &radeon_uvd_cs_parse
,
1689 .ring_test
= &r600_uvd_ring_test
,
1690 .ib_test
= &r600_uvd_ib_test
,
1691 .is_lockup
= &radeon_ring_test_lockup
,
1692 .get_rptr
= &radeon_ring_generic_get_rptr
,
1693 .get_wptr
= &radeon_ring_generic_get_wptr
,
1694 .set_wptr
= &radeon_ring_generic_set_wptr
,
1698 .set
= &evergreen_irq_set
,
1699 .process
= &evergreen_irq_process
,
1702 .bandwidth_update
= &evergreen_bandwidth_update
,
1703 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1704 .wait_for_vblank
= &dce4_wait_for_vblank
,
1705 .set_backlight_level
= &atombios_set_backlight_level
,
1706 .get_backlight_level
= &atombios_get_backlight_level
,
1707 .hdmi_enable
= &evergreen_hdmi_enable
,
1708 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1711 .blit
= &r600_copy_blit
,
1712 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1713 .dma
= &evergreen_copy_dma
,
1714 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1715 .copy
= &evergreen_copy_dma
,
1716 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1719 .set_reg
= r600_set_surface_reg
,
1720 .clear_reg
= r600_clear_surface_reg
,
1723 .init
= &evergreen_hpd_init
,
1724 .fini
= &evergreen_hpd_fini
,
1725 .sense
= &evergreen_hpd_sense
,
1726 .set_polarity
= &evergreen_hpd_set_polarity
,
1729 .misc
= &evergreen_pm_misc
,
1730 .prepare
= &evergreen_pm_prepare
,
1731 .finish
= &evergreen_pm_finish
,
1732 .init_profile
= &btc_pm_init_profile
,
1733 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1734 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1735 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1736 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1737 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1738 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1739 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1740 .set_clock_gating
= NULL
,
1741 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1742 .get_temperature
= &evergreen_get_temp
,
1745 .pre_page_flip
= &evergreen_pre_page_flip
,
1746 .page_flip
= &evergreen_page_flip
,
1747 .post_page_flip
= &evergreen_post_page_flip
,
1751 static struct radeon_asic trinity_asic
= {
1752 .init
= &cayman_init
,
1753 .fini
= &cayman_fini
,
1754 .suspend
= &cayman_suspend
,
1755 .resume
= &cayman_resume
,
1756 .asic_reset
= &cayman_asic_reset
,
1757 .vga_set_state
= &r600_vga_set_state
,
1758 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1759 .gui_idle
= &r600_gui_idle
,
1760 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1761 .get_xclk
= &r600_get_xclk
,
1762 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1764 .tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1765 .set_page
= &rs600_gart_set_page
,
1768 .init
= &cayman_vm_init
,
1769 .fini
= &cayman_vm_fini
,
1770 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1771 .set_page
= &cayman_vm_set_page
,
1774 [RADEON_RING_TYPE_GFX_INDEX
] = {
1775 .ib_execute
= &cayman_ring_ib_execute
,
1776 .ib_parse
= &evergreen_ib_parse
,
1777 .emit_fence
= &cayman_fence_ring_emit
,
1778 .emit_semaphore
= &r600_semaphore_ring_emit
,
1779 .cs_parse
= &evergreen_cs_parse
,
1780 .ring_test
= &r600_ring_test
,
1781 .ib_test
= &r600_ib_test
,
1782 .is_lockup
= &cayman_gfx_is_lockup
,
1783 .vm_flush
= &cayman_vm_flush
,
1784 .get_rptr
= &radeon_ring_generic_get_rptr
,
1785 .get_wptr
= &radeon_ring_generic_get_wptr
,
1786 .set_wptr
= &radeon_ring_generic_set_wptr
,
1788 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
1789 .ib_execute
= &cayman_ring_ib_execute
,
1790 .ib_parse
= &evergreen_ib_parse
,
1791 .emit_fence
= &cayman_fence_ring_emit
,
1792 .emit_semaphore
= &r600_semaphore_ring_emit
,
1793 .cs_parse
= &evergreen_cs_parse
,
1794 .ring_test
= &r600_ring_test
,
1795 .ib_test
= &r600_ib_test
,
1796 .is_lockup
= &cayman_gfx_is_lockup
,
1797 .vm_flush
= &cayman_vm_flush
,
1798 .get_rptr
= &radeon_ring_generic_get_rptr
,
1799 .get_wptr
= &radeon_ring_generic_get_wptr
,
1800 .set_wptr
= &radeon_ring_generic_set_wptr
,
1802 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
1803 .ib_execute
= &cayman_ring_ib_execute
,
1804 .ib_parse
= &evergreen_ib_parse
,
1805 .emit_fence
= &cayman_fence_ring_emit
,
1806 .emit_semaphore
= &r600_semaphore_ring_emit
,
1807 .cs_parse
= &evergreen_cs_parse
,
1808 .ring_test
= &r600_ring_test
,
1809 .ib_test
= &r600_ib_test
,
1810 .is_lockup
= &cayman_gfx_is_lockup
,
1811 .vm_flush
= &cayman_vm_flush
,
1812 .get_rptr
= &radeon_ring_generic_get_rptr
,
1813 .get_wptr
= &radeon_ring_generic_get_wptr
,
1814 .set_wptr
= &radeon_ring_generic_set_wptr
,
1816 [R600_RING_TYPE_DMA_INDEX
] = {
1817 .ib_execute
= &cayman_dma_ring_ib_execute
,
1818 .ib_parse
= &evergreen_dma_ib_parse
,
1819 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1820 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1821 .cs_parse
= &evergreen_dma_cs_parse
,
1822 .ring_test
= &r600_dma_ring_test
,
1823 .ib_test
= &r600_dma_ib_test
,
1824 .is_lockup
= &cayman_dma_is_lockup
,
1825 .vm_flush
= &cayman_dma_vm_flush
,
1826 .get_rptr
= &radeon_ring_generic_get_rptr
,
1827 .get_wptr
= &radeon_ring_generic_get_wptr
,
1828 .set_wptr
= &radeon_ring_generic_set_wptr
,
1830 [CAYMAN_RING_TYPE_DMA1_INDEX
] = {
1831 .ib_execute
= &cayman_dma_ring_ib_execute
,
1832 .ib_parse
= &evergreen_dma_ib_parse
,
1833 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1834 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1835 .cs_parse
= &evergreen_dma_cs_parse
,
1836 .ring_test
= &r600_dma_ring_test
,
1837 .ib_test
= &r600_dma_ib_test
,
1838 .is_lockup
= &cayman_dma_is_lockup
,
1839 .vm_flush
= &cayman_dma_vm_flush
,
1840 .get_rptr
= &radeon_ring_generic_get_rptr
,
1841 .get_wptr
= &radeon_ring_generic_get_wptr
,
1842 .set_wptr
= &radeon_ring_generic_set_wptr
,
1844 [R600_RING_TYPE_UVD_INDEX
] = {
1845 .ib_execute
= &r600_uvd_ib_execute
,
1846 .emit_fence
= &r600_uvd_fence_emit
,
1847 .emit_semaphore
= &cayman_uvd_semaphore_emit
,
1848 .cs_parse
= &radeon_uvd_cs_parse
,
1849 .ring_test
= &r600_uvd_ring_test
,
1850 .ib_test
= &r600_uvd_ib_test
,
1851 .is_lockup
= &radeon_ring_test_lockup
,
1852 .get_rptr
= &radeon_ring_generic_get_rptr
,
1853 .get_wptr
= &radeon_ring_generic_get_wptr
,
1854 .set_wptr
= &radeon_ring_generic_set_wptr
,
1858 .set
= &evergreen_irq_set
,
1859 .process
= &evergreen_irq_process
,
1862 .bandwidth_update
= &dce6_bandwidth_update
,
1863 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1864 .wait_for_vblank
= &dce4_wait_for_vblank
,
1865 .set_backlight_level
= &atombios_set_backlight_level
,
1866 .get_backlight_level
= &atombios_get_backlight_level
,
1869 .blit
= &r600_copy_blit
,
1870 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1871 .dma
= &evergreen_copy_dma
,
1872 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1873 .copy
= &evergreen_copy_dma
,
1874 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1877 .set_reg
= r600_set_surface_reg
,
1878 .clear_reg
= r600_clear_surface_reg
,
1881 .init
= &evergreen_hpd_init
,
1882 .fini
= &evergreen_hpd_fini
,
1883 .sense
= &evergreen_hpd_sense
,
1884 .set_polarity
= &evergreen_hpd_set_polarity
,
1887 .misc
= &evergreen_pm_misc
,
1888 .prepare
= &evergreen_pm_prepare
,
1889 .finish
= &evergreen_pm_finish
,
1890 .init_profile
= &sumo_pm_init_profile
,
1891 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1892 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1893 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1894 .get_memory_clock
= NULL
,
1895 .set_memory_clock
= NULL
,
1896 .get_pcie_lanes
= NULL
,
1897 .set_pcie_lanes
= NULL
,
1898 .set_clock_gating
= NULL
,
1899 .set_uvd_clocks
= &sumo_set_uvd_clocks
,
1900 .get_temperature
= &tn_get_temp
,
1903 .pre_page_flip
= &evergreen_pre_page_flip
,
1904 .page_flip
= &evergreen_page_flip
,
1905 .post_page_flip
= &evergreen_post_page_flip
,
1909 static struct radeon_asic si_asic
= {
1912 .suspend
= &si_suspend
,
1913 .resume
= &si_resume
,
1914 .asic_reset
= &si_asic_reset
,
1915 .vga_set_state
= &r600_vga_set_state
,
1916 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1917 .gui_idle
= &r600_gui_idle
,
1918 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1919 .get_xclk
= &si_get_xclk
,
1920 .get_gpu_clock_counter
= &si_get_gpu_clock_counter
,
1922 .tlb_flush
= &si_pcie_gart_tlb_flush
,
1923 .set_page
= &rs600_gart_set_page
,
1926 .init
= &si_vm_init
,
1927 .fini
= &si_vm_fini
,
1928 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1929 .set_page
= &si_vm_set_page
,
1932 [RADEON_RING_TYPE_GFX_INDEX
] = {
1933 .ib_execute
= &si_ring_ib_execute
,
1934 .ib_parse
= &si_ib_parse
,
1935 .emit_fence
= &si_fence_ring_emit
,
1936 .emit_semaphore
= &r600_semaphore_ring_emit
,
1938 .ring_test
= &r600_ring_test
,
1939 .ib_test
= &r600_ib_test
,
1940 .is_lockup
= &si_gfx_is_lockup
,
1941 .vm_flush
= &si_vm_flush
,
1942 .get_rptr
= &radeon_ring_generic_get_rptr
,
1943 .get_wptr
= &radeon_ring_generic_get_wptr
,
1944 .set_wptr
= &radeon_ring_generic_set_wptr
,
1946 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
1947 .ib_execute
= &si_ring_ib_execute
,
1948 .ib_parse
= &si_ib_parse
,
1949 .emit_fence
= &si_fence_ring_emit
,
1950 .emit_semaphore
= &r600_semaphore_ring_emit
,
1952 .ring_test
= &r600_ring_test
,
1953 .ib_test
= &r600_ib_test
,
1954 .is_lockup
= &si_gfx_is_lockup
,
1955 .vm_flush
= &si_vm_flush
,
1956 .get_rptr
= &radeon_ring_generic_get_rptr
,
1957 .get_wptr
= &radeon_ring_generic_get_wptr
,
1958 .set_wptr
= &radeon_ring_generic_set_wptr
,
1960 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
1961 .ib_execute
= &si_ring_ib_execute
,
1962 .ib_parse
= &si_ib_parse
,
1963 .emit_fence
= &si_fence_ring_emit
,
1964 .emit_semaphore
= &r600_semaphore_ring_emit
,
1966 .ring_test
= &r600_ring_test
,
1967 .ib_test
= &r600_ib_test
,
1968 .is_lockup
= &si_gfx_is_lockup
,
1969 .vm_flush
= &si_vm_flush
,
1970 .get_rptr
= &radeon_ring_generic_get_rptr
,
1971 .get_wptr
= &radeon_ring_generic_get_wptr
,
1972 .set_wptr
= &radeon_ring_generic_set_wptr
,
1974 [R600_RING_TYPE_DMA_INDEX
] = {
1975 .ib_execute
= &cayman_dma_ring_ib_execute
,
1976 .ib_parse
= &evergreen_dma_ib_parse
,
1977 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1978 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1980 .ring_test
= &r600_dma_ring_test
,
1981 .ib_test
= &r600_dma_ib_test
,
1982 .is_lockup
= &si_dma_is_lockup
,
1983 .vm_flush
= &si_dma_vm_flush
,
1984 .get_rptr
= &radeon_ring_generic_get_rptr
,
1985 .get_wptr
= &radeon_ring_generic_get_wptr
,
1986 .set_wptr
= &radeon_ring_generic_set_wptr
,
1988 [CAYMAN_RING_TYPE_DMA1_INDEX
] = {
1989 .ib_execute
= &cayman_dma_ring_ib_execute
,
1990 .ib_parse
= &evergreen_dma_ib_parse
,
1991 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1992 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1994 .ring_test
= &r600_dma_ring_test
,
1995 .ib_test
= &r600_dma_ib_test
,
1996 .is_lockup
= &si_dma_is_lockup
,
1997 .vm_flush
= &si_dma_vm_flush
,
1998 .get_rptr
= &radeon_ring_generic_get_rptr
,
1999 .get_wptr
= &radeon_ring_generic_get_wptr
,
2000 .set_wptr
= &radeon_ring_generic_set_wptr
,
2002 [R600_RING_TYPE_UVD_INDEX
] = {
2003 .ib_execute
= &r600_uvd_ib_execute
,
2004 .emit_fence
= &r600_uvd_fence_emit
,
2005 .emit_semaphore
= &cayman_uvd_semaphore_emit
,
2006 .cs_parse
= &radeon_uvd_cs_parse
,
2007 .ring_test
= &r600_uvd_ring_test
,
2008 .ib_test
= &r600_uvd_ib_test
,
2009 .is_lockup
= &radeon_ring_test_lockup
,
2010 .get_rptr
= &radeon_ring_generic_get_rptr
,
2011 .get_wptr
= &radeon_ring_generic_get_wptr
,
2012 .set_wptr
= &radeon_ring_generic_set_wptr
,
2017 .process
= &si_irq_process
,
2020 .bandwidth_update
= &dce6_bandwidth_update
,
2021 .get_vblank_counter
= &evergreen_get_vblank_counter
,
2022 .wait_for_vblank
= &dce4_wait_for_vblank
,
2023 .set_backlight_level
= &atombios_set_backlight_level
,
2024 .get_backlight_level
= &atombios_get_backlight_level
,
2028 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
2029 .dma
= &si_copy_dma
,
2030 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2031 .copy
= &si_copy_dma
,
2032 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2035 .set_reg
= r600_set_surface_reg
,
2036 .clear_reg
= r600_clear_surface_reg
,
2039 .init
= &evergreen_hpd_init
,
2040 .fini
= &evergreen_hpd_fini
,
2041 .sense
= &evergreen_hpd_sense
,
2042 .set_polarity
= &evergreen_hpd_set_polarity
,
2045 .misc
= &evergreen_pm_misc
,
2046 .prepare
= &evergreen_pm_prepare
,
2047 .finish
= &evergreen_pm_finish
,
2048 .init_profile
= &sumo_pm_init_profile
,
2049 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
2050 .get_engine_clock
= &radeon_atom_get_engine_clock
,
2051 .set_engine_clock
= &radeon_atom_set_engine_clock
,
2052 .get_memory_clock
= &radeon_atom_get_memory_clock
,
2053 .set_memory_clock
= &radeon_atom_set_memory_clock
,
2054 .get_pcie_lanes
= &r600_get_pcie_lanes
,
2055 .set_pcie_lanes
= &r600_set_pcie_lanes
,
2056 .set_clock_gating
= NULL
,
2057 .set_uvd_clocks
= &si_set_uvd_clocks
,
2058 .get_temperature
= &si_get_temp
,
2061 .pre_page_flip
= &evergreen_pre_page_flip
,
2062 .page_flip
= &evergreen_page_flip
,
2063 .post_page_flip
= &evergreen_post_page_flip
,
2067 static struct radeon_asic ci_asic
= {
2070 .suspend
= &cik_suspend
,
2071 .resume
= &cik_resume
,
2072 .asic_reset
= &cik_asic_reset
,
2073 .vga_set_state
= &r600_vga_set_state
,
2074 .ioctl_wait_idle
= NULL
,
2075 .gui_idle
= &r600_gui_idle
,
2076 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
2077 .get_xclk
= &cik_get_xclk
,
2078 .get_gpu_clock_counter
= &cik_get_gpu_clock_counter
,
2080 .tlb_flush
= &cik_pcie_gart_tlb_flush
,
2081 .set_page
= &rs600_gart_set_page
,
2084 .init
= &cik_vm_init
,
2085 .fini
= &cik_vm_fini
,
2086 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2087 .set_page
= &cik_vm_set_page
,
2090 [RADEON_RING_TYPE_GFX_INDEX
] = {
2091 .ib_execute
= &cik_ring_ib_execute
,
2092 .ib_parse
= &cik_ib_parse
,
2093 .emit_fence
= &cik_fence_gfx_ring_emit
,
2094 .emit_semaphore
= &cik_semaphore_ring_emit
,
2096 .ring_test
= &cik_ring_test
,
2097 .ib_test
= &cik_ib_test
,
2098 .is_lockup
= &cik_gfx_is_lockup
,
2099 .vm_flush
= &cik_vm_flush
,
2100 .get_rptr
= &radeon_ring_generic_get_rptr
,
2101 .get_wptr
= &radeon_ring_generic_get_wptr
,
2102 .set_wptr
= &radeon_ring_generic_set_wptr
,
2104 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
2105 .ib_execute
= &cik_ring_ib_execute
,
2106 .ib_parse
= &cik_ib_parse
,
2107 .emit_fence
= &cik_fence_compute_ring_emit
,
2108 .emit_semaphore
= &cik_semaphore_ring_emit
,
2110 .ring_test
= &cik_ring_test
,
2111 .ib_test
= &cik_ib_test
,
2112 .is_lockup
= &cik_gfx_is_lockup
,
2113 .vm_flush
= &cik_vm_flush
,
2114 .get_rptr
= &cik_compute_ring_get_rptr
,
2115 .get_wptr
= &cik_compute_ring_get_wptr
,
2116 .set_wptr
= &cik_compute_ring_set_wptr
,
2118 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
2119 .ib_execute
= &cik_ring_ib_execute
,
2120 .ib_parse
= &cik_ib_parse
,
2121 .emit_fence
= &cik_fence_compute_ring_emit
,
2122 .emit_semaphore
= &cik_semaphore_ring_emit
,
2124 .ring_test
= &cik_ring_test
,
2125 .ib_test
= &cik_ib_test
,
2126 .is_lockup
= &cik_gfx_is_lockup
,
2127 .vm_flush
= &cik_vm_flush
,
2128 .get_rptr
= &cik_compute_ring_get_rptr
,
2129 .get_wptr
= &cik_compute_ring_get_wptr
,
2130 .set_wptr
= &cik_compute_ring_set_wptr
,
2132 [R600_RING_TYPE_DMA_INDEX
] = {
2133 .ib_execute
= &cik_sdma_ring_ib_execute
,
2134 .ib_parse
= &cik_ib_parse
,
2135 .emit_fence
= &cik_sdma_fence_ring_emit
,
2136 .emit_semaphore
= &cik_sdma_semaphore_ring_emit
,
2138 .ring_test
= &cik_sdma_ring_test
,
2139 .ib_test
= &cik_sdma_ib_test
,
2140 .is_lockup
= &cik_sdma_is_lockup
,
2141 .vm_flush
= &cik_dma_vm_flush
,
2142 .get_rptr
= &radeon_ring_generic_get_rptr
,
2143 .get_wptr
= &radeon_ring_generic_get_wptr
,
2144 .set_wptr
= &radeon_ring_generic_set_wptr
,
2146 [CAYMAN_RING_TYPE_DMA1_INDEX
] = {
2147 .ib_execute
= &cik_sdma_ring_ib_execute
,
2148 .ib_parse
= &cik_ib_parse
,
2149 .emit_fence
= &cik_sdma_fence_ring_emit
,
2150 .emit_semaphore
= &cik_sdma_semaphore_ring_emit
,
2152 .ring_test
= &cik_sdma_ring_test
,
2153 .ib_test
= &cik_sdma_ib_test
,
2154 .is_lockup
= &cik_sdma_is_lockup
,
2155 .vm_flush
= &cik_dma_vm_flush
,
2156 .get_rptr
= &radeon_ring_generic_get_rptr
,
2157 .get_wptr
= &radeon_ring_generic_get_wptr
,
2158 .set_wptr
= &radeon_ring_generic_set_wptr
,
2160 [R600_RING_TYPE_UVD_INDEX
] = {
2161 .ib_execute
= &r600_uvd_ib_execute
,
2162 .emit_fence
= &r600_uvd_fence_emit
,
2163 .emit_semaphore
= &cayman_uvd_semaphore_emit
,
2164 .cs_parse
= &radeon_uvd_cs_parse
,
2165 .ring_test
= &r600_uvd_ring_test
,
2166 .ib_test
= &r600_uvd_ib_test
,
2167 .is_lockup
= &radeon_ring_test_lockup
,
2168 .get_rptr
= &radeon_ring_generic_get_rptr
,
2169 .get_wptr
= &radeon_ring_generic_get_wptr
,
2170 .set_wptr
= &radeon_ring_generic_set_wptr
,
2174 .set
= &cik_irq_set
,
2175 .process
= &cik_irq_process
,
2178 .bandwidth_update
= &dce8_bandwidth_update
,
2179 .get_vblank_counter
= &evergreen_get_vblank_counter
,
2180 .wait_for_vblank
= &dce4_wait_for_vblank
,
2184 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
2185 .dma
= &cik_copy_dma
,
2186 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2187 .copy
= &cik_copy_dma
,
2188 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2191 .set_reg
= r600_set_surface_reg
,
2192 .clear_reg
= r600_clear_surface_reg
,
2195 .init
= &evergreen_hpd_init
,
2196 .fini
= &evergreen_hpd_fini
,
2197 .sense
= &evergreen_hpd_sense
,
2198 .set_polarity
= &evergreen_hpd_set_polarity
,
2201 .misc
= &evergreen_pm_misc
,
2202 .prepare
= &evergreen_pm_prepare
,
2203 .finish
= &evergreen_pm_finish
,
2204 .init_profile
= &sumo_pm_init_profile
,
2205 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
2206 .get_engine_clock
= &radeon_atom_get_engine_clock
,
2207 .set_engine_clock
= &radeon_atom_set_engine_clock
,
2208 .get_memory_clock
= &radeon_atom_get_memory_clock
,
2209 .set_memory_clock
= &radeon_atom_set_memory_clock
,
2210 .get_pcie_lanes
= NULL
,
2211 .set_pcie_lanes
= NULL
,
2212 .set_clock_gating
= NULL
,
2213 .set_uvd_clocks
= &cik_set_uvd_clocks
,
2216 .pre_page_flip
= &evergreen_pre_page_flip
,
2217 .page_flip
= &evergreen_page_flip
,
2218 .post_page_flip
= &evergreen_post_page_flip
,
2222 static struct radeon_asic kv_asic
= {
2225 .suspend
= &cik_suspend
,
2226 .resume
= &cik_resume
,
2227 .asic_reset
= &cik_asic_reset
,
2228 .vga_set_state
= &r600_vga_set_state
,
2229 .ioctl_wait_idle
= NULL
,
2230 .gui_idle
= &r600_gui_idle
,
2231 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
2232 .get_xclk
= &cik_get_xclk
,
2233 .get_gpu_clock_counter
= &cik_get_gpu_clock_counter
,
2235 .tlb_flush
= &cik_pcie_gart_tlb_flush
,
2236 .set_page
= &rs600_gart_set_page
,
2239 .init
= &cik_vm_init
,
2240 .fini
= &cik_vm_fini
,
2241 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2242 .set_page
= &cik_vm_set_page
,
2245 [RADEON_RING_TYPE_GFX_INDEX
] = {
2246 .ib_execute
= &cik_ring_ib_execute
,
2247 .ib_parse
= &cik_ib_parse
,
2248 .emit_fence
= &cik_fence_gfx_ring_emit
,
2249 .emit_semaphore
= &cik_semaphore_ring_emit
,
2251 .ring_test
= &cik_ring_test
,
2252 .ib_test
= &cik_ib_test
,
2253 .is_lockup
= &cik_gfx_is_lockup
,
2254 .vm_flush
= &cik_vm_flush
,
2255 .get_rptr
= &radeon_ring_generic_get_rptr
,
2256 .get_wptr
= &radeon_ring_generic_get_wptr
,
2257 .set_wptr
= &radeon_ring_generic_set_wptr
,
2259 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
2260 .ib_execute
= &cik_ring_ib_execute
,
2261 .ib_parse
= &cik_ib_parse
,
2262 .emit_fence
= &cik_fence_compute_ring_emit
,
2263 .emit_semaphore
= &cik_semaphore_ring_emit
,
2265 .ring_test
= &cik_ring_test
,
2266 .ib_test
= &cik_ib_test
,
2267 .is_lockup
= &cik_gfx_is_lockup
,
2268 .vm_flush
= &cik_vm_flush
,
2269 .get_rptr
= &cik_compute_ring_get_rptr
,
2270 .get_wptr
= &cik_compute_ring_get_wptr
,
2271 .set_wptr
= &cik_compute_ring_set_wptr
,
2273 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
2274 .ib_execute
= &cik_ring_ib_execute
,
2275 .ib_parse
= &cik_ib_parse
,
2276 .emit_fence
= &cik_fence_compute_ring_emit
,
2277 .emit_semaphore
= &cik_semaphore_ring_emit
,
2279 .ring_test
= &cik_ring_test
,
2280 .ib_test
= &cik_ib_test
,
2281 .is_lockup
= &cik_gfx_is_lockup
,
2282 .vm_flush
= &cik_vm_flush
,
2283 .get_rptr
= &cik_compute_ring_get_rptr
,
2284 .get_wptr
= &cik_compute_ring_get_wptr
,
2285 .set_wptr
= &cik_compute_ring_set_wptr
,
2287 [R600_RING_TYPE_DMA_INDEX
] = {
2288 .ib_execute
= &cik_sdma_ring_ib_execute
,
2289 .ib_parse
= &cik_ib_parse
,
2290 .emit_fence
= &cik_sdma_fence_ring_emit
,
2291 .emit_semaphore
= &cik_sdma_semaphore_ring_emit
,
2293 .ring_test
= &cik_sdma_ring_test
,
2294 .ib_test
= &cik_sdma_ib_test
,
2295 .is_lockup
= &cik_sdma_is_lockup
,
2296 .vm_flush
= &cik_dma_vm_flush
,
2297 .get_rptr
= &radeon_ring_generic_get_rptr
,
2298 .get_wptr
= &radeon_ring_generic_get_wptr
,
2299 .set_wptr
= &radeon_ring_generic_set_wptr
,
2301 [CAYMAN_RING_TYPE_DMA1_INDEX
] = {
2302 .ib_execute
= &cik_sdma_ring_ib_execute
,
2303 .ib_parse
= &cik_ib_parse
,
2304 .emit_fence
= &cik_sdma_fence_ring_emit
,
2305 .emit_semaphore
= &cik_sdma_semaphore_ring_emit
,
2307 .ring_test
= &cik_sdma_ring_test
,
2308 .ib_test
= &cik_sdma_ib_test
,
2309 .is_lockup
= &cik_sdma_is_lockup
,
2310 .vm_flush
= &cik_dma_vm_flush
,
2311 .get_rptr
= &radeon_ring_generic_get_rptr
,
2312 .get_wptr
= &radeon_ring_generic_get_wptr
,
2313 .set_wptr
= &radeon_ring_generic_set_wptr
,
2315 [R600_RING_TYPE_UVD_INDEX
] = {
2316 .ib_execute
= &r600_uvd_ib_execute
,
2317 .emit_fence
= &r600_uvd_fence_emit
,
2318 .emit_semaphore
= &cayman_uvd_semaphore_emit
,
2319 .cs_parse
= &radeon_uvd_cs_parse
,
2320 .ring_test
= &r600_uvd_ring_test
,
2321 .ib_test
= &r600_uvd_ib_test
,
2322 .is_lockup
= &radeon_ring_test_lockup
,
2323 .get_rptr
= &radeon_ring_generic_get_rptr
,
2324 .get_wptr
= &radeon_ring_generic_get_wptr
,
2325 .set_wptr
= &radeon_ring_generic_set_wptr
,
2329 .set
= &cik_irq_set
,
2330 .process
= &cik_irq_process
,
2333 .bandwidth_update
= &dce8_bandwidth_update
,
2334 .get_vblank_counter
= &evergreen_get_vblank_counter
,
2335 .wait_for_vblank
= &dce4_wait_for_vblank
,
2339 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
2340 .dma
= &cik_copy_dma
,
2341 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2342 .copy
= &cik_copy_dma
,
2343 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2346 .set_reg
= r600_set_surface_reg
,
2347 .clear_reg
= r600_clear_surface_reg
,
2350 .init
= &evergreen_hpd_init
,
2351 .fini
= &evergreen_hpd_fini
,
2352 .sense
= &evergreen_hpd_sense
,
2353 .set_polarity
= &evergreen_hpd_set_polarity
,
2356 .misc
= &evergreen_pm_misc
,
2357 .prepare
= &evergreen_pm_prepare
,
2358 .finish
= &evergreen_pm_finish
,
2359 .init_profile
= &sumo_pm_init_profile
,
2360 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
2361 .get_engine_clock
= &radeon_atom_get_engine_clock
,
2362 .set_engine_clock
= &radeon_atom_set_engine_clock
,
2363 .get_memory_clock
= &radeon_atom_get_memory_clock
,
2364 .set_memory_clock
= &radeon_atom_set_memory_clock
,
2365 .get_pcie_lanes
= NULL
,
2366 .set_pcie_lanes
= NULL
,
2367 .set_clock_gating
= NULL
,
2368 .set_uvd_clocks
= &cik_set_uvd_clocks
,
2371 .pre_page_flip
= &evergreen_pre_page_flip
,
2372 .page_flip
= &evergreen_page_flip
,
2373 .post_page_flip
= &evergreen_post_page_flip
,
2378 * radeon_asic_init - register asic specific callbacks
2380 * @rdev: radeon device pointer
2382 * Registers the appropriate asic specific callbacks for each
2383 * chip family. Also sets other asics specific info like the number
2384 * of crtcs and the register aperture accessors (all asics).
2385 * Returns 0 for success.
2387 int radeon_asic_init(struct radeon_device
*rdev
)
2389 radeon_register_accessor_init(rdev
);
2391 /* set the number of crtcs */
2392 if (rdev
->flags
& RADEON_SINGLE_CRTC
)
2397 rdev
->has_uvd
= false;
2399 switch (rdev
->family
) {
2405 rdev
->asic
= &r100_asic
;
2411 rdev
->asic
= &r200_asic
;
2417 if (rdev
->flags
& RADEON_IS_PCIE
)
2418 rdev
->asic
= &r300_asic_pcie
;
2420 rdev
->asic
= &r300_asic
;
2425 rdev
->asic
= &r420_asic
;
2427 if (rdev
->bios
== NULL
) {
2428 rdev
->asic
->pm
.get_engine_clock
= &radeon_legacy_get_engine_clock
;
2429 rdev
->asic
->pm
.set_engine_clock
= &radeon_legacy_set_engine_clock
;
2430 rdev
->asic
->pm
.get_memory_clock
= &radeon_legacy_get_memory_clock
;
2431 rdev
->asic
->pm
.set_memory_clock
= NULL
;
2432 rdev
->asic
->display
.set_backlight_level
= &radeon_legacy_set_backlight_level
;
2437 rdev
->asic
= &rs400_asic
;
2440 rdev
->asic
= &rs600_asic
;
2444 rdev
->asic
= &rs690_asic
;
2447 rdev
->asic
= &rv515_asic
;
2454 rdev
->asic
= &r520_asic
;
2462 rdev
->asic
= &r600_asic
;
2463 if (rdev
->family
== CHIP_R600
)
2464 rdev
->has_uvd
= false;
2466 rdev
->has_uvd
= true;
2470 rdev
->asic
= &rs780_asic
;
2471 rdev
->has_uvd
= true;
2477 rdev
->asic
= &rv770_asic
;
2478 rdev
->has_uvd
= true;
2486 if (rdev
->family
== CHIP_CEDAR
)
2490 rdev
->asic
= &evergreen_asic
;
2491 rdev
->has_uvd
= true;
2496 rdev
->asic
= &sumo_asic
;
2497 rdev
->has_uvd
= true;
2503 if (rdev
->family
== CHIP_CAICOS
)
2507 rdev
->asic
= &btc_asic
;
2508 rdev
->has_uvd
= true;
2511 rdev
->asic
= &cayman_asic
;
2514 rdev
->has_uvd
= true;
2517 rdev
->asic
= &trinity_asic
;
2520 rdev
->has_uvd
= true;
2527 rdev
->asic
= &si_asic
;
2529 if (rdev
->family
== CHIP_HAINAN
)
2531 else if (rdev
->family
== CHIP_OLAND
)
2535 if (rdev
->family
== CHIP_HAINAN
)
2536 rdev
->has_uvd
= false;
2538 rdev
->has_uvd
= true;
2541 rdev
->asic
= &ci_asic
;
2546 rdev
->asic
= &kv_asic
;
2548 if (rdev
->family
== CHIP_KAVERI
)
2554 /* FIXME: not supported yet */
2558 if (rdev
->flags
& RADEON_IS_IGP
) {
2559 rdev
->asic
->pm
.get_memory_clock
= NULL
;
2560 rdev
->asic
->pm
.set_memory_clock
= NULL
;