2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/console.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
37 #include "radeon_asic.h"
41 * Registers accessors functions.
44 * radeon_invalid_rreg - dummy reg read function
46 * @rdev: radeon device pointer
47 * @reg: offset of register
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
53 static uint32_t radeon_invalid_rreg(struct radeon_device
*rdev
, uint32_t reg
)
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
61 * radeon_invalid_wreg - dummy reg write function
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
70 static void radeon_invalid_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
78 * radeon_register_accessor_init - sets up the register accessor callbacks
80 * @rdev: radeon device pointer
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
85 static void radeon_register_accessor_init(struct radeon_device
*rdev
)
87 rdev
->mc_rreg
= &radeon_invalid_rreg
;
88 rdev
->mc_wreg
= &radeon_invalid_wreg
;
89 rdev
->pll_rreg
= &radeon_invalid_rreg
;
90 rdev
->pll_wreg
= &radeon_invalid_wreg
;
91 rdev
->pciep_rreg
= &radeon_invalid_rreg
;
92 rdev
->pciep_wreg
= &radeon_invalid_wreg
;
94 /* Don't change order as we are overridding accessor. */
95 if (rdev
->family
< CHIP_RV515
) {
96 rdev
->pcie_reg_mask
= 0xff;
98 rdev
->pcie_reg_mask
= 0x7ff;
100 /* FIXME: not sure here */
101 if (rdev
->family
<= CHIP_R580
) {
102 rdev
->pll_rreg
= &r100_pll_rreg
;
103 rdev
->pll_wreg
= &r100_pll_wreg
;
105 if (rdev
->family
>= CHIP_R420
) {
106 rdev
->mc_rreg
= &r420_mc_rreg
;
107 rdev
->mc_wreg
= &r420_mc_wreg
;
109 if (rdev
->family
>= CHIP_RV515
) {
110 rdev
->mc_rreg
= &rv515_mc_rreg
;
111 rdev
->mc_wreg
= &rv515_mc_wreg
;
113 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
114 rdev
->mc_rreg
= &rs400_mc_rreg
;
115 rdev
->mc_wreg
= &rs400_mc_wreg
;
117 if (rdev
->family
== CHIP_RS690
|| rdev
->family
== CHIP_RS740
) {
118 rdev
->mc_rreg
= &rs690_mc_rreg
;
119 rdev
->mc_wreg
= &rs690_mc_wreg
;
121 if (rdev
->family
== CHIP_RS600
) {
122 rdev
->mc_rreg
= &rs600_mc_rreg
;
123 rdev
->mc_wreg
= &rs600_mc_wreg
;
125 if (rdev
->family
== CHIP_RS780
|| rdev
->family
== CHIP_RS880
) {
126 rdev
->mc_rreg
= &rs780_mc_rreg
;
127 rdev
->mc_wreg
= &rs780_mc_wreg
;
130 if (rdev
->family
>= CHIP_BONAIRE
) {
131 rdev
->pciep_rreg
= &cik_pciep_rreg
;
132 rdev
->pciep_wreg
= &cik_pciep_wreg
;
133 } else if (rdev
->family
>= CHIP_R600
) {
134 rdev
->pciep_rreg
= &r600_pciep_rreg
;
135 rdev
->pciep_wreg
= &r600_pciep_wreg
;
140 /* helper to disable agp */
142 * radeon_agp_disable - AGP disable helper function
144 * @rdev: radeon device pointer
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
149 void radeon_agp_disable(struct radeon_device
*rdev
)
151 rdev
->flags
&= ~RADEON_IS_AGP
;
152 if (rdev
->family
>= CHIP_R600
) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev
->flags
|= RADEON_IS_PCIE
;
155 } else if (rdev
->family
>= CHIP_RV515
||
156 rdev
->family
== CHIP_RV380
||
157 rdev
->family
== CHIP_RV410
||
158 rdev
->family
== CHIP_R423
) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev
->flags
|= RADEON_IS_PCIE
;
161 rdev
->asic
->gart
.tlb_flush
= &rv370_pcie_gart_tlb_flush
;
162 rdev
->asic
->gart
.set_page
= &rv370_pcie_gart_set_page
;
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev
->flags
|= RADEON_IS_PCI
;
166 rdev
->asic
->gart
.tlb_flush
= &r100_pci_gart_tlb_flush
;
167 rdev
->asic
->gart
.set_page
= &r100_pci_gart_set_page
;
169 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
175 static struct radeon_asic r100_asic
= {
178 .suspend
= &r100_suspend
,
179 .resume
= &r100_resume
,
180 .vga_set_state
= &r100_vga_set_state
,
181 .asic_reset
= &r100_asic_reset
,
182 .ioctl_wait_idle
= NULL
,
183 .gui_idle
= &r100_gui_idle
,
184 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
186 .tlb_flush
= &r100_pci_gart_tlb_flush
,
187 .set_page
= &r100_pci_gart_set_page
,
190 [RADEON_RING_TYPE_GFX_INDEX
] = {
191 .ib_execute
= &r100_ring_ib_execute
,
192 .emit_fence
= &r100_fence_ring_emit
,
193 .emit_semaphore
= &r100_semaphore_ring_emit
,
194 .cs_parse
= &r100_cs_parse
,
195 .ring_start
= &r100_ring_start
,
196 .ring_test
= &r100_ring_test
,
197 .ib_test
= &r100_ib_test
,
198 .is_lockup
= &r100_gpu_is_lockup
,
199 .get_rptr
= &radeon_ring_generic_get_rptr
,
200 .get_wptr
= &radeon_ring_generic_get_wptr
,
201 .set_wptr
= &radeon_ring_generic_set_wptr
,
205 .set
= &r100_irq_set
,
206 .process
= &r100_irq_process
,
209 .bandwidth_update
= &r100_bandwidth_update
,
210 .get_vblank_counter
= &r100_get_vblank_counter
,
211 .wait_for_vblank
= &r100_wait_for_vblank
,
212 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
213 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
216 .blit
= &r100_copy_blit
,
217 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
219 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
220 .copy
= &r100_copy_blit
,
221 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
224 .set_reg
= r100_set_surface_reg
,
225 .clear_reg
= r100_clear_surface_reg
,
228 .init
= &r100_hpd_init
,
229 .fini
= &r100_hpd_fini
,
230 .sense
= &r100_hpd_sense
,
231 .set_polarity
= &r100_hpd_set_polarity
,
234 .misc
= &r100_pm_misc
,
235 .prepare
= &r100_pm_prepare
,
236 .finish
= &r100_pm_finish
,
237 .init_profile
= &r100_pm_init_profile
,
238 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
239 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
240 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
241 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
242 .set_memory_clock
= NULL
,
243 .get_pcie_lanes
= NULL
,
244 .set_pcie_lanes
= NULL
,
245 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
248 .pre_page_flip
= &r100_pre_page_flip
,
249 .page_flip
= &r100_page_flip
,
250 .post_page_flip
= &r100_post_page_flip
,
254 static struct radeon_asic r200_asic
= {
257 .suspend
= &r100_suspend
,
258 .resume
= &r100_resume
,
259 .vga_set_state
= &r100_vga_set_state
,
260 .asic_reset
= &r100_asic_reset
,
261 .ioctl_wait_idle
= NULL
,
262 .gui_idle
= &r100_gui_idle
,
263 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
265 .tlb_flush
= &r100_pci_gart_tlb_flush
,
266 .set_page
= &r100_pci_gart_set_page
,
269 [RADEON_RING_TYPE_GFX_INDEX
] = {
270 .ib_execute
= &r100_ring_ib_execute
,
271 .emit_fence
= &r100_fence_ring_emit
,
272 .emit_semaphore
= &r100_semaphore_ring_emit
,
273 .cs_parse
= &r100_cs_parse
,
274 .ring_start
= &r100_ring_start
,
275 .ring_test
= &r100_ring_test
,
276 .ib_test
= &r100_ib_test
,
277 .is_lockup
= &r100_gpu_is_lockup
,
278 .get_rptr
= &radeon_ring_generic_get_rptr
,
279 .get_wptr
= &radeon_ring_generic_get_wptr
,
280 .set_wptr
= &radeon_ring_generic_set_wptr
,
284 .set
= &r100_irq_set
,
285 .process
= &r100_irq_process
,
288 .bandwidth_update
= &r100_bandwidth_update
,
289 .get_vblank_counter
= &r100_get_vblank_counter
,
290 .wait_for_vblank
= &r100_wait_for_vblank
,
291 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
292 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
295 .blit
= &r100_copy_blit
,
296 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
297 .dma
= &r200_copy_dma
,
298 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
299 .copy
= &r100_copy_blit
,
300 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
303 .set_reg
= r100_set_surface_reg
,
304 .clear_reg
= r100_clear_surface_reg
,
307 .init
= &r100_hpd_init
,
308 .fini
= &r100_hpd_fini
,
309 .sense
= &r100_hpd_sense
,
310 .set_polarity
= &r100_hpd_set_polarity
,
313 .misc
= &r100_pm_misc
,
314 .prepare
= &r100_pm_prepare
,
315 .finish
= &r100_pm_finish
,
316 .init_profile
= &r100_pm_init_profile
,
317 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
318 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
319 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
320 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
321 .set_memory_clock
= NULL
,
322 .get_pcie_lanes
= NULL
,
323 .set_pcie_lanes
= NULL
,
324 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
327 .pre_page_flip
= &r100_pre_page_flip
,
328 .page_flip
= &r100_page_flip
,
329 .post_page_flip
= &r100_post_page_flip
,
333 static struct radeon_asic r300_asic
= {
336 .suspend
= &r300_suspend
,
337 .resume
= &r300_resume
,
338 .vga_set_state
= &r100_vga_set_state
,
339 .asic_reset
= &r300_asic_reset
,
340 .ioctl_wait_idle
= NULL
,
341 .gui_idle
= &r100_gui_idle
,
342 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
344 .tlb_flush
= &r100_pci_gart_tlb_flush
,
345 .set_page
= &r100_pci_gart_set_page
,
348 [RADEON_RING_TYPE_GFX_INDEX
] = {
349 .ib_execute
= &r100_ring_ib_execute
,
350 .emit_fence
= &r300_fence_ring_emit
,
351 .emit_semaphore
= &r100_semaphore_ring_emit
,
352 .cs_parse
= &r300_cs_parse
,
353 .ring_start
= &r300_ring_start
,
354 .ring_test
= &r100_ring_test
,
355 .ib_test
= &r100_ib_test
,
356 .is_lockup
= &r100_gpu_is_lockup
,
357 .get_rptr
= &radeon_ring_generic_get_rptr
,
358 .get_wptr
= &radeon_ring_generic_get_wptr
,
359 .set_wptr
= &radeon_ring_generic_set_wptr
,
363 .set
= &r100_irq_set
,
364 .process
= &r100_irq_process
,
367 .bandwidth_update
= &r100_bandwidth_update
,
368 .get_vblank_counter
= &r100_get_vblank_counter
,
369 .wait_for_vblank
= &r100_wait_for_vblank
,
370 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
371 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
374 .blit
= &r100_copy_blit
,
375 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
376 .dma
= &r200_copy_dma
,
377 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
378 .copy
= &r100_copy_blit
,
379 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
382 .set_reg
= r100_set_surface_reg
,
383 .clear_reg
= r100_clear_surface_reg
,
386 .init
= &r100_hpd_init
,
387 .fini
= &r100_hpd_fini
,
388 .sense
= &r100_hpd_sense
,
389 .set_polarity
= &r100_hpd_set_polarity
,
392 .misc
= &r100_pm_misc
,
393 .prepare
= &r100_pm_prepare
,
394 .finish
= &r100_pm_finish
,
395 .init_profile
= &r100_pm_init_profile
,
396 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
397 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
398 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
399 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
400 .set_memory_clock
= NULL
,
401 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
402 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
403 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
406 .pre_page_flip
= &r100_pre_page_flip
,
407 .page_flip
= &r100_page_flip
,
408 .post_page_flip
= &r100_post_page_flip
,
412 static struct radeon_asic r300_asic_pcie
= {
415 .suspend
= &r300_suspend
,
416 .resume
= &r300_resume
,
417 .vga_set_state
= &r100_vga_set_state
,
418 .asic_reset
= &r300_asic_reset
,
419 .ioctl_wait_idle
= NULL
,
420 .gui_idle
= &r100_gui_idle
,
421 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
423 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
424 .set_page
= &rv370_pcie_gart_set_page
,
427 [RADEON_RING_TYPE_GFX_INDEX
] = {
428 .ib_execute
= &r100_ring_ib_execute
,
429 .emit_fence
= &r300_fence_ring_emit
,
430 .emit_semaphore
= &r100_semaphore_ring_emit
,
431 .cs_parse
= &r300_cs_parse
,
432 .ring_start
= &r300_ring_start
,
433 .ring_test
= &r100_ring_test
,
434 .ib_test
= &r100_ib_test
,
435 .is_lockup
= &r100_gpu_is_lockup
,
436 .get_rptr
= &radeon_ring_generic_get_rptr
,
437 .get_wptr
= &radeon_ring_generic_get_wptr
,
438 .set_wptr
= &radeon_ring_generic_set_wptr
,
442 .set
= &r100_irq_set
,
443 .process
= &r100_irq_process
,
446 .bandwidth_update
= &r100_bandwidth_update
,
447 .get_vblank_counter
= &r100_get_vblank_counter
,
448 .wait_for_vblank
= &r100_wait_for_vblank
,
449 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
450 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
453 .blit
= &r100_copy_blit
,
454 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
455 .dma
= &r200_copy_dma
,
456 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
457 .copy
= &r100_copy_blit
,
458 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
461 .set_reg
= r100_set_surface_reg
,
462 .clear_reg
= r100_clear_surface_reg
,
465 .init
= &r100_hpd_init
,
466 .fini
= &r100_hpd_fini
,
467 .sense
= &r100_hpd_sense
,
468 .set_polarity
= &r100_hpd_set_polarity
,
471 .misc
= &r100_pm_misc
,
472 .prepare
= &r100_pm_prepare
,
473 .finish
= &r100_pm_finish
,
474 .init_profile
= &r100_pm_init_profile
,
475 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
476 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
477 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
478 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
479 .set_memory_clock
= NULL
,
480 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
481 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
482 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
485 .pre_page_flip
= &r100_pre_page_flip
,
486 .page_flip
= &r100_page_flip
,
487 .post_page_flip
= &r100_post_page_flip
,
491 static struct radeon_asic r420_asic
= {
494 .suspend
= &r420_suspend
,
495 .resume
= &r420_resume
,
496 .vga_set_state
= &r100_vga_set_state
,
497 .asic_reset
= &r300_asic_reset
,
498 .ioctl_wait_idle
= NULL
,
499 .gui_idle
= &r100_gui_idle
,
500 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
502 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
503 .set_page
= &rv370_pcie_gart_set_page
,
506 [RADEON_RING_TYPE_GFX_INDEX
] = {
507 .ib_execute
= &r100_ring_ib_execute
,
508 .emit_fence
= &r300_fence_ring_emit
,
509 .emit_semaphore
= &r100_semaphore_ring_emit
,
510 .cs_parse
= &r300_cs_parse
,
511 .ring_start
= &r300_ring_start
,
512 .ring_test
= &r100_ring_test
,
513 .ib_test
= &r100_ib_test
,
514 .is_lockup
= &r100_gpu_is_lockup
,
515 .get_rptr
= &radeon_ring_generic_get_rptr
,
516 .get_wptr
= &radeon_ring_generic_get_wptr
,
517 .set_wptr
= &radeon_ring_generic_set_wptr
,
521 .set
= &r100_irq_set
,
522 .process
= &r100_irq_process
,
525 .bandwidth_update
= &r100_bandwidth_update
,
526 .get_vblank_counter
= &r100_get_vblank_counter
,
527 .wait_for_vblank
= &r100_wait_for_vblank
,
528 .set_backlight_level
= &atombios_set_backlight_level
,
529 .get_backlight_level
= &atombios_get_backlight_level
,
532 .blit
= &r100_copy_blit
,
533 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
534 .dma
= &r200_copy_dma
,
535 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
536 .copy
= &r100_copy_blit
,
537 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
540 .set_reg
= r100_set_surface_reg
,
541 .clear_reg
= r100_clear_surface_reg
,
544 .init
= &r100_hpd_init
,
545 .fini
= &r100_hpd_fini
,
546 .sense
= &r100_hpd_sense
,
547 .set_polarity
= &r100_hpd_set_polarity
,
550 .misc
= &r100_pm_misc
,
551 .prepare
= &r100_pm_prepare
,
552 .finish
= &r100_pm_finish
,
553 .init_profile
= &r420_pm_init_profile
,
554 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
555 .get_engine_clock
= &radeon_atom_get_engine_clock
,
556 .set_engine_clock
= &radeon_atom_set_engine_clock
,
557 .get_memory_clock
= &radeon_atom_get_memory_clock
,
558 .set_memory_clock
= &radeon_atom_set_memory_clock
,
559 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
560 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
561 .set_clock_gating
= &radeon_atom_set_clock_gating
,
564 .pre_page_flip
= &r100_pre_page_flip
,
565 .page_flip
= &r100_page_flip
,
566 .post_page_flip
= &r100_post_page_flip
,
570 static struct radeon_asic rs400_asic
= {
573 .suspend
= &rs400_suspend
,
574 .resume
= &rs400_resume
,
575 .vga_set_state
= &r100_vga_set_state
,
576 .asic_reset
= &r300_asic_reset
,
577 .ioctl_wait_idle
= NULL
,
578 .gui_idle
= &r100_gui_idle
,
579 .mc_wait_for_idle
= &rs400_mc_wait_for_idle
,
581 .tlb_flush
= &rs400_gart_tlb_flush
,
582 .set_page
= &rs400_gart_set_page
,
585 [RADEON_RING_TYPE_GFX_INDEX
] = {
586 .ib_execute
= &r100_ring_ib_execute
,
587 .emit_fence
= &r300_fence_ring_emit
,
588 .emit_semaphore
= &r100_semaphore_ring_emit
,
589 .cs_parse
= &r300_cs_parse
,
590 .ring_start
= &r300_ring_start
,
591 .ring_test
= &r100_ring_test
,
592 .ib_test
= &r100_ib_test
,
593 .is_lockup
= &r100_gpu_is_lockup
,
594 .get_rptr
= &radeon_ring_generic_get_rptr
,
595 .get_wptr
= &radeon_ring_generic_get_wptr
,
596 .set_wptr
= &radeon_ring_generic_set_wptr
,
600 .set
= &r100_irq_set
,
601 .process
= &r100_irq_process
,
604 .bandwidth_update
= &r100_bandwidth_update
,
605 .get_vblank_counter
= &r100_get_vblank_counter
,
606 .wait_for_vblank
= &r100_wait_for_vblank
,
607 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
608 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
611 .blit
= &r100_copy_blit
,
612 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
613 .dma
= &r200_copy_dma
,
614 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
615 .copy
= &r100_copy_blit
,
616 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
619 .set_reg
= r100_set_surface_reg
,
620 .clear_reg
= r100_clear_surface_reg
,
623 .init
= &r100_hpd_init
,
624 .fini
= &r100_hpd_fini
,
625 .sense
= &r100_hpd_sense
,
626 .set_polarity
= &r100_hpd_set_polarity
,
629 .misc
= &r100_pm_misc
,
630 .prepare
= &r100_pm_prepare
,
631 .finish
= &r100_pm_finish
,
632 .init_profile
= &r100_pm_init_profile
,
633 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
634 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
635 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
636 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
637 .set_memory_clock
= NULL
,
638 .get_pcie_lanes
= NULL
,
639 .set_pcie_lanes
= NULL
,
640 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
643 .pre_page_flip
= &r100_pre_page_flip
,
644 .page_flip
= &r100_page_flip
,
645 .post_page_flip
= &r100_post_page_flip
,
649 static struct radeon_asic rs600_asic
= {
652 .suspend
= &rs600_suspend
,
653 .resume
= &rs600_resume
,
654 .vga_set_state
= &r100_vga_set_state
,
655 .asic_reset
= &rs600_asic_reset
,
656 .ioctl_wait_idle
= NULL
,
657 .gui_idle
= &r100_gui_idle
,
658 .mc_wait_for_idle
= &rs600_mc_wait_for_idle
,
660 .tlb_flush
= &rs600_gart_tlb_flush
,
661 .set_page
= &rs600_gart_set_page
,
664 [RADEON_RING_TYPE_GFX_INDEX
] = {
665 .ib_execute
= &r100_ring_ib_execute
,
666 .emit_fence
= &r300_fence_ring_emit
,
667 .emit_semaphore
= &r100_semaphore_ring_emit
,
668 .cs_parse
= &r300_cs_parse
,
669 .ring_start
= &r300_ring_start
,
670 .ring_test
= &r100_ring_test
,
671 .ib_test
= &r100_ib_test
,
672 .is_lockup
= &r100_gpu_is_lockup
,
673 .get_rptr
= &radeon_ring_generic_get_rptr
,
674 .get_wptr
= &radeon_ring_generic_get_wptr
,
675 .set_wptr
= &radeon_ring_generic_set_wptr
,
679 .set
= &rs600_irq_set
,
680 .process
= &rs600_irq_process
,
683 .bandwidth_update
= &rs600_bandwidth_update
,
684 .get_vblank_counter
= &rs600_get_vblank_counter
,
685 .wait_for_vblank
= &avivo_wait_for_vblank
,
686 .set_backlight_level
= &atombios_set_backlight_level
,
687 .get_backlight_level
= &atombios_get_backlight_level
,
688 .hdmi_enable
= &r600_hdmi_enable
,
689 .hdmi_setmode
= &r600_hdmi_setmode
,
692 .blit
= &r100_copy_blit
,
693 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
694 .dma
= &r200_copy_dma
,
695 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
696 .copy
= &r100_copy_blit
,
697 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
700 .set_reg
= r100_set_surface_reg
,
701 .clear_reg
= r100_clear_surface_reg
,
704 .init
= &rs600_hpd_init
,
705 .fini
= &rs600_hpd_fini
,
706 .sense
= &rs600_hpd_sense
,
707 .set_polarity
= &rs600_hpd_set_polarity
,
710 .misc
= &rs600_pm_misc
,
711 .prepare
= &rs600_pm_prepare
,
712 .finish
= &rs600_pm_finish
,
713 .init_profile
= &r420_pm_init_profile
,
714 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
715 .get_engine_clock
= &radeon_atom_get_engine_clock
,
716 .set_engine_clock
= &radeon_atom_set_engine_clock
,
717 .get_memory_clock
= &radeon_atom_get_memory_clock
,
718 .set_memory_clock
= &radeon_atom_set_memory_clock
,
719 .get_pcie_lanes
= NULL
,
720 .set_pcie_lanes
= NULL
,
721 .set_clock_gating
= &radeon_atom_set_clock_gating
,
724 .pre_page_flip
= &rs600_pre_page_flip
,
725 .page_flip
= &rs600_page_flip
,
726 .post_page_flip
= &rs600_post_page_flip
,
730 static struct radeon_asic rs690_asic
= {
733 .suspend
= &rs690_suspend
,
734 .resume
= &rs690_resume
,
735 .vga_set_state
= &r100_vga_set_state
,
736 .asic_reset
= &rs600_asic_reset
,
737 .ioctl_wait_idle
= NULL
,
738 .gui_idle
= &r100_gui_idle
,
739 .mc_wait_for_idle
= &rs690_mc_wait_for_idle
,
741 .tlb_flush
= &rs400_gart_tlb_flush
,
742 .set_page
= &rs400_gart_set_page
,
745 [RADEON_RING_TYPE_GFX_INDEX
] = {
746 .ib_execute
= &r100_ring_ib_execute
,
747 .emit_fence
= &r300_fence_ring_emit
,
748 .emit_semaphore
= &r100_semaphore_ring_emit
,
749 .cs_parse
= &r300_cs_parse
,
750 .ring_start
= &r300_ring_start
,
751 .ring_test
= &r100_ring_test
,
752 .ib_test
= &r100_ib_test
,
753 .is_lockup
= &r100_gpu_is_lockup
,
754 .get_rptr
= &radeon_ring_generic_get_rptr
,
755 .get_wptr
= &radeon_ring_generic_get_wptr
,
756 .set_wptr
= &radeon_ring_generic_set_wptr
,
760 .set
= &rs600_irq_set
,
761 .process
= &rs600_irq_process
,
764 .get_vblank_counter
= &rs600_get_vblank_counter
,
765 .bandwidth_update
= &rs690_bandwidth_update
,
766 .wait_for_vblank
= &avivo_wait_for_vblank
,
767 .set_backlight_level
= &atombios_set_backlight_level
,
768 .get_backlight_level
= &atombios_get_backlight_level
,
769 .hdmi_enable
= &r600_hdmi_enable
,
770 .hdmi_setmode
= &r600_hdmi_setmode
,
773 .blit
= &r100_copy_blit
,
774 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
775 .dma
= &r200_copy_dma
,
776 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
777 .copy
= &r200_copy_dma
,
778 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
781 .set_reg
= r100_set_surface_reg
,
782 .clear_reg
= r100_clear_surface_reg
,
785 .init
= &rs600_hpd_init
,
786 .fini
= &rs600_hpd_fini
,
787 .sense
= &rs600_hpd_sense
,
788 .set_polarity
= &rs600_hpd_set_polarity
,
791 .misc
= &rs600_pm_misc
,
792 .prepare
= &rs600_pm_prepare
,
793 .finish
= &rs600_pm_finish
,
794 .init_profile
= &r420_pm_init_profile
,
795 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
796 .get_engine_clock
= &radeon_atom_get_engine_clock
,
797 .set_engine_clock
= &radeon_atom_set_engine_clock
,
798 .get_memory_clock
= &radeon_atom_get_memory_clock
,
799 .set_memory_clock
= &radeon_atom_set_memory_clock
,
800 .get_pcie_lanes
= NULL
,
801 .set_pcie_lanes
= NULL
,
802 .set_clock_gating
= &radeon_atom_set_clock_gating
,
805 .pre_page_flip
= &rs600_pre_page_flip
,
806 .page_flip
= &rs600_page_flip
,
807 .post_page_flip
= &rs600_post_page_flip
,
811 static struct radeon_asic rv515_asic
= {
814 .suspend
= &rv515_suspend
,
815 .resume
= &rv515_resume
,
816 .vga_set_state
= &r100_vga_set_state
,
817 .asic_reset
= &rs600_asic_reset
,
818 .ioctl_wait_idle
= NULL
,
819 .gui_idle
= &r100_gui_idle
,
820 .mc_wait_for_idle
= &rv515_mc_wait_for_idle
,
822 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
823 .set_page
= &rv370_pcie_gart_set_page
,
826 [RADEON_RING_TYPE_GFX_INDEX
] = {
827 .ib_execute
= &r100_ring_ib_execute
,
828 .emit_fence
= &r300_fence_ring_emit
,
829 .emit_semaphore
= &r100_semaphore_ring_emit
,
830 .cs_parse
= &r300_cs_parse
,
831 .ring_start
= &rv515_ring_start
,
832 .ring_test
= &r100_ring_test
,
833 .ib_test
= &r100_ib_test
,
834 .is_lockup
= &r100_gpu_is_lockup
,
835 .get_rptr
= &radeon_ring_generic_get_rptr
,
836 .get_wptr
= &radeon_ring_generic_get_wptr
,
837 .set_wptr
= &radeon_ring_generic_set_wptr
,
841 .set
= &rs600_irq_set
,
842 .process
= &rs600_irq_process
,
845 .get_vblank_counter
= &rs600_get_vblank_counter
,
846 .bandwidth_update
= &rv515_bandwidth_update
,
847 .wait_for_vblank
= &avivo_wait_for_vblank
,
848 .set_backlight_level
= &atombios_set_backlight_level
,
849 .get_backlight_level
= &atombios_get_backlight_level
,
852 .blit
= &r100_copy_blit
,
853 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
854 .dma
= &r200_copy_dma
,
855 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
856 .copy
= &r100_copy_blit
,
857 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
860 .set_reg
= r100_set_surface_reg
,
861 .clear_reg
= r100_clear_surface_reg
,
864 .init
= &rs600_hpd_init
,
865 .fini
= &rs600_hpd_fini
,
866 .sense
= &rs600_hpd_sense
,
867 .set_polarity
= &rs600_hpd_set_polarity
,
870 .misc
= &rs600_pm_misc
,
871 .prepare
= &rs600_pm_prepare
,
872 .finish
= &rs600_pm_finish
,
873 .init_profile
= &r420_pm_init_profile
,
874 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
875 .get_engine_clock
= &radeon_atom_get_engine_clock
,
876 .set_engine_clock
= &radeon_atom_set_engine_clock
,
877 .get_memory_clock
= &radeon_atom_get_memory_clock
,
878 .set_memory_clock
= &radeon_atom_set_memory_clock
,
879 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
880 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
881 .set_clock_gating
= &radeon_atom_set_clock_gating
,
884 .pre_page_flip
= &rs600_pre_page_flip
,
885 .page_flip
= &rs600_page_flip
,
886 .post_page_flip
= &rs600_post_page_flip
,
890 static struct radeon_asic r520_asic
= {
893 .suspend
= &rv515_suspend
,
894 .resume
= &r520_resume
,
895 .vga_set_state
= &r100_vga_set_state
,
896 .asic_reset
= &rs600_asic_reset
,
897 .ioctl_wait_idle
= NULL
,
898 .gui_idle
= &r100_gui_idle
,
899 .mc_wait_for_idle
= &r520_mc_wait_for_idle
,
901 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
902 .set_page
= &rv370_pcie_gart_set_page
,
905 [RADEON_RING_TYPE_GFX_INDEX
] = {
906 .ib_execute
= &r100_ring_ib_execute
,
907 .emit_fence
= &r300_fence_ring_emit
,
908 .emit_semaphore
= &r100_semaphore_ring_emit
,
909 .cs_parse
= &r300_cs_parse
,
910 .ring_start
= &rv515_ring_start
,
911 .ring_test
= &r100_ring_test
,
912 .ib_test
= &r100_ib_test
,
913 .is_lockup
= &r100_gpu_is_lockup
,
914 .get_rptr
= &radeon_ring_generic_get_rptr
,
915 .get_wptr
= &radeon_ring_generic_get_wptr
,
916 .set_wptr
= &radeon_ring_generic_set_wptr
,
920 .set
= &rs600_irq_set
,
921 .process
= &rs600_irq_process
,
924 .bandwidth_update
= &rv515_bandwidth_update
,
925 .get_vblank_counter
= &rs600_get_vblank_counter
,
926 .wait_for_vblank
= &avivo_wait_for_vblank
,
927 .set_backlight_level
= &atombios_set_backlight_level
,
928 .get_backlight_level
= &atombios_get_backlight_level
,
931 .blit
= &r100_copy_blit
,
932 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
933 .dma
= &r200_copy_dma
,
934 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
935 .copy
= &r100_copy_blit
,
936 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
939 .set_reg
= r100_set_surface_reg
,
940 .clear_reg
= r100_clear_surface_reg
,
943 .init
= &rs600_hpd_init
,
944 .fini
= &rs600_hpd_fini
,
945 .sense
= &rs600_hpd_sense
,
946 .set_polarity
= &rs600_hpd_set_polarity
,
949 .misc
= &rs600_pm_misc
,
950 .prepare
= &rs600_pm_prepare
,
951 .finish
= &rs600_pm_finish
,
952 .init_profile
= &r420_pm_init_profile
,
953 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
954 .get_engine_clock
= &radeon_atom_get_engine_clock
,
955 .set_engine_clock
= &radeon_atom_set_engine_clock
,
956 .get_memory_clock
= &radeon_atom_get_memory_clock
,
957 .set_memory_clock
= &radeon_atom_set_memory_clock
,
958 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
959 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
960 .set_clock_gating
= &radeon_atom_set_clock_gating
,
963 .pre_page_flip
= &rs600_pre_page_flip
,
964 .page_flip
= &rs600_page_flip
,
965 .post_page_flip
= &rs600_post_page_flip
,
969 static struct radeon_asic r600_asic
= {
972 .suspend
= &r600_suspend
,
973 .resume
= &r600_resume
,
974 .vga_set_state
= &r600_vga_set_state
,
975 .asic_reset
= &r600_asic_reset
,
976 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
977 .gui_idle
= &r600_gui_idle
,
978 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
979 .get_xclk
= &r600_get_xclk
,
980 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
982 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
983 .set_page
= &rs600_gart_set_page
,
986 [RADEON_RING_TYPE_GFX_INDEX
] = {
987 .ib_execute
= &r600_ring_ib_execute
,
988 .emit_fence
= &r600_fence_ring_emit
,
989 .emit_semaphore
= &r600_semaphore_ring_emit
,
990 .cs_parse
= &r600_cs_parse
,
991 .ring_test
= &r600_ring_test
,
992 .ib_test
= &r600_ib_test
,
993 .is_lockup
= &r600_gfx_is_lockup
,
994 .get_rptr
= &radeon_ring_generic_get_rptr
,
995 .get_wptr
= &radeon_ring_generic_get_wptr
,
996 .set_wptr
= &radeon_ring_generic_set_wptr
,
998 [R600_RING_TYPE_DMA_INDEX
] = {
999 .ib_execute
= &r600_dma_ring_ib_execute
,
1000 .emit_fence
= &r600_dma_fence_ring_emit
,
1001 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1002 .cs_parse
= &r600_dma_cs_parse
,
1003 .ring_test
= &r600_dma_ring_test
,
1004 .ib_test
= &r600_dma_ib_test
,
1005 .is_lockup
= &r600_dma_is_lockup
,
1006 .get_rptr
= &radeon_ring_generic_get_rptr
,
1007 .get_wptr
= &radeon_ring_generic_get_wptr
,
1008 .set_wptr
= &radeon_ring_generic_set_wptr
,
1012 .set
= &r600_irq_set
,
1013 .process
= &r600_irq_process
,
1016 .bandwidth_update
= &rv515_bandwidth_update
,
1017 .get_vblank_counter
= &rs600_get_vblank_counter
,
1018 .wait_for_vblank
= &avivo_wait_for_vblank
,
1019 .set_backlight_level
= &atombios_set_backlight_level
,
1020 .get_backlight_level
= &atombios_get_backlight_level
,
1021 .hdmi_enable
= &r600_hdmi_enable
,
1022 .hdmi_setmode
= &r600_hdmi_setmode
,
1025 .blit
= &r600_copy_blit
,
1026 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1027 .dma
= &r600_copy_dma
,
1028 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1029 .copy
= &r600_copy_dma
,
1030 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1033 .set_reg
= r600_set_surface_reg
,
1034 .clear_reg
= r600_clear_surface_reg
,
1037 .init
= &r600_hpd_init
,
1038 .fini
= &r600_hpd_fini
,
1039 .sense
= &r600_hpd_sense
,
1040 .set_polarity
= &r600_hpd_set_polarity
,
1043 .misc
= &r600_pm_misc
,
1044 .prepare
= &rs600_pm_prepare
,
1045 .finish
= &rs600_pm_finish
,
1046 .init_profile
= &r600_pm_init_profile
,
1047 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1048 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1049 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1050 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1051 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1052 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1053 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1054 .set_clock_gating
= NULL
,
1055 .get_temperature
= &rv6xx_get_temp
,
1058 .pre_page_flip
= &rs600_pre_page_flip
,
1059 .page_flip
= &rs600_page_flip
,
1060 .post_page_flip
= &rs600_post_page_flip
,
1064 static struct radeon_asic rv6xx_asic
= {
1067 .suspend
= &r600_suspend
,
1068 .resume
= &r600_resume
,
1069 .vga_set_state
= &r600_vga_set_state
,
1070 .asic_reset
= &r600_asic_reset
,
1071 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1072 .gui_idle
= &r600_gui_idle
,
1073 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1074 .get_xclk
= &r600_get_xclk
,
1075 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1077 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1078 .set_page
= &rs600_gart_set_page
,
1081 [RADEON_RING_TYPE_GFX_INDEX
] = {
1082 .ib_execute
= &r600_ring_ib_execute
,
1083 .emit_fence
= &r600_fence_ring_emit
,
1084 .emit_semaphore
= &r600_semaphore_ring_emit
,
1085 .cs_parse
= &r600_cs_parse
,
1086 .ring_test
= &r600_ring_test
,
1087 .ib_test
= &r600_ib_test
,
1088 .is_lockup
= &r600_gfx_is_lockup
,
1089 .get_rptr
= &radeon_ring_generic_get_rptr
,
1090 .get_wptr
= &radeon_ring_generic_get_wptr
,
1091 .set_wptr
= &radeon_ring_generic_set_wptr
,
1093 [R600_RING_TYPE_DMA_INDEX
] = {
1094 .ib_execute
= &r600_dma_ring_ib_execute
,
1095 .emit_fence
= &r600_dma_fence_ring_emit
,
1096 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1097 .cs_parse
= &r600_dma_cs_parse
,
1098 .ring_test
= &r600_dma_ring_test
,
1099 .ib_test
= &r600_dma_ib_test
,
1100 .is_lockup
= &r600_dma_is_lockup
,
1101 .get_rptr
= &radeon_ring_generic_get_rptr
,
1102 .get_wptr
= &radeon_ring_generic_get_wptr
,
1103 .set_wptr
= &radeon_ring_generic_set_wptr
,
1107 .set
= &r600_irq_set
,
1108 .process
= &r600_irq_process
,
1111 .bandwidth_update
= &rv515_bandwidth_update
,
1112 .get_vblank_counter
= &rs600_get_vblank_counter
,
1113 .wait_for_vblank
= &avivo_wait_for_vblank
,
1114 .set_backlight_level
= &atombios_set_backlight_level
,
1115 .get_backlight_level
= &atombios_get_backlight_level
,
1118 .blit
= &r600_copy_blit
,
1119 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1120 .dma
= &r600_copy_dma
,
1121 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1122 .copy
= &r600_copy_dma
,
1123 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1126 .set_reg
= r600_set_surface_reg
,
1127 .clear_reg
= r600_clear_surface_reg
,
1130 .init
= &r600_hpd_init
,
1131 .fini
= &r600_hpd_fini
,
1132 .sense
= &r600_hpd_sense
,
1133 .set_polarity
= &r600_hpd_set_polarity
,
1136 .misc
= &r600_pm_misc
,
1137 .prepare
= &rs600_pm_prepare
,
1138 .finish
= &rs600_pm_finish
,
1139 .init_profile
= &r600_pm_init_profile
,
1140 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1141 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1142 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1143 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1144 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1145 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1146 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1147 .set_clock_gating
= NULL
,
1148 .get_temperature
= &rv6xx_get_temp
,
1151 .pre_page_flip
= &rs600_pre_page_flip
,
1152 .page_flip
= &rs600_page_flip
,
1153 .post_page_flip
= &rs600_post_page_flip
,
1157 static struct radeon_asic rs780_asic
= {
1160 .suspend
= &r600_suspend
,
1161 .resume
= &r600_resume
,
1162 .vga_set_state
= &r600_vga_set_state
,
1163 .asic_reset
= &r600_asic_reset
,
1164 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1165 .gui_idle
= &r600_gui_idle
,
1166 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1167 .get_xclk
= &r600_get_xclk
,
1168 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1170 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1171 .set_page
= &rs600_gart_set_page
,
1174 [RADEON_RING_TYPE_GFX_INDEX
] = {
1175 .ib_execute
= &r600_ring_ib_execute
,
1176 .emit_fence
= &r600_fence_ring_emit
,
1177 .emit_semaphore
= &r600_semaphore_ring_emit
,
1178 .cs_parse
= &r600_cs_parse
,
1179 .ring_test
= &r600_ring_test
,
1180 .ib_test
= &r600_ib_test
,
1181 .is_lockup
= &r600_gfx_is_lockup
,
1182 .get_rptr
= &radeon_ring_generic_get_rptr
,
1183 .get_wptr
= &radeon_ring_generic_get_wptr
,
1184 .set_wptr
= &radeon_ring_generic_set_wptr
,
1186 [R600_RING_TYPE_DMA_INDEX
] = {
1187 .ib_execute
= &r600_dma_ring_ib_execute
,
1188 .emit_fence
= &r600_dma_fence_ring_emit
,
1189 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1190 .cs_parse
= &r600_dma_cs_parse
,
1191 .ring_test
= &r600_dma_ring_test
,
1192 .ib_test
= &r600_dma_ib_test
,
1193 .is_lockup
= &r600_dma_is_lockup
,
1194 .get_rptr
= &radeon_ring_generic_get_rptr
,
1195 .get_wptr
= &radeon_ring_generic_get_wptr
,
1196 .set_wptr
= &radeon_ring_generic_set_wptr
,
1200 .set
= &r600_irq_set
,
1201 .process
= &r600_irq_process
,
1204 .bandwidth_update
= &rs690_bandwidth_update
,
1205 .get_vblank_counter
= &rs600_get_vblank_counter
,
1206 .wait_for_vblank
= &avivo_wait_for_vblank
,
1207 .set_backlight_level
= &atombios_set_backlight_level
,
1208 .get_backlight_level
= &atombios_get_backlight_level
,
1209 .hdmi_enable
= &r600_hdmi_enable
,
1210 .hdmi_setmode
= &r600_hdmi_setmode
,
1213 .blit
= &r600_copy_blit
,
1214 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1215 .dma
= &r600_copy_dma
,
1216 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1217 .copy
= &r600_copy_dma
,
1218 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1221 .set_reg
= r600_set_surface_reg
,
1222 .clear_reg
= r600_clear_surface_reg
,
1225 .init
= &r600_hpd_init
,
1226 .fini
= &r600_hpd_fini
,
1227 .sense
= &r600_hpd_sense
,
1228 .set_polarity
= &r600_hpd_set_polarity
,
1231 .misc
= &r600_pm_misc
,
1232 .prepare
= &rs600_pm_prepare
,
1233 .finish
= &rs600_pm_finish
,
1234 .init_profile
= &rs780_pm_init_profile
,
1235 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1236 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1237 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1238 .get_memory_clock
= NULL
,
1239 .set_memory_clock
= NULL
,
1240 .get_pcie_lanes
= NULL
,
1241 .set_pcie_lanes
= NULL
,
1242 .set_clock_gating
= NULL
,
1243 .get_temperature
= &rv6xx_get_temp
,
1246 .init
= &rs780_dpm_init
,
1247 .setup_asic
= &rs780_dpm_setup_asic
,
1248 .enable
= &rs780_dpm_enable
,
1249 .disable
= &rs780_dpm_disable
,
1250 .set_power_state
= &rs780_dpm_set_power_state
,
1251 .display_configuration_changed
= &rs780_dpm_display_configuration_changed
,
1252 .fini
= &rs780_dpm_fini
,
1253 .get_sclk
= &rs780_dpm_get_sclk
,
1254 .get_mclk
= &rs780_dpm_get_mclk
,
1255 .print_power_state
= &rs780_dpm_print_power_state
,
1258 .pre_page_flip
= &rs600_pre_page_flip
,
1259 .page_flip
= &rs600_page_flip
,
1260 .post_page_flip
= &rs600_post_page_flip
,
1264 static struct radeon_asic rv770_asic
= {
1265 .init
= &rv770_init
,
1266 .fini
= &rv770_fini
,
1267 .suspend
= &rv770_suspend
,
1268 .resume
= &rv770_resume
,
1269 .asic_reset
= &r600_asic_reset
,
1270 .vga_set_state
= &r600_vga_set_state
,
1271 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1272 .gui_idle
= &r600_gui_idle
,
1273 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1274 .get_xclk
= &rv770_get_xclk
,
1275 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1277 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1278 .set_page
= &rs600_gart_set_page
,
1281 [RADEON_RING_TYPE_GFX_INDEX
] = {
1282 .ib_execute
= &r600_ring_ib_execute
,
1283 .emit_fence
= &r600_fence_ring_emit
,
1284 .emit_semaphore
= &r600_semaphore_ring_emit
,
1285 .cs_parse
= &r600_cs_parse
,
1286 .ring_test
= &r600_ring_test
,
1287 .ib_test
= &r600_ib_test
,
1288 .is_lockup
= &r600_gfx_is_lockup
,
1289 .get_rptr
= &radeon_ring_generic_get_rptr
,
1290 .get_wptr
= &radeon_ring_generic_get_wptr
,
1291 .set_wptr
= &radeon_ring_generic_set_wptr
,
1293 [R600_RING_TYPE_DMA_INDEX
] = {
1294 .ib_execute
= &r600_dma_ring_ib_execute
,
1295 .emit_fence
= &r600_dma_fence_ring_emit
,
1296 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1297 .cs_parse
= &r600_dma_cs_parse
,
1298 .ring_test
= &r600_dma_ring_test
,
1299 .ib_test
= &r600_dma_ib_test
,
1300 .is_lockup
= &r600_dma_is_lockup
,
1301 .get_rptr
= &radeon_ring_generic_get_rptr
,
1302 .get_wptr
= &radeon_ring_generic_get_wptr
,
1303 .set_wptr
= &radeon_ring_generic_set_wptr
,
1305 [R600_RING_TYPE_UVD_INDEX
] = {
1306 .ib_execute
= &r600_uvd_ib_execute
,
1307 .emit_fence
= &r600_uvd_fence_emit
,
1308 .emit_semaphore
= &r600_uvd_semaphore_emit
,
1309 .cs_parse
= &radeon_uvd_cs_parse
,
1310 .ring_test
= &r600_uvd_ring_test
,
1311 .ib_test
= &r600_uvd_ib_test
,
1312 .is_lockup
= &radeon_ring_test_lockup
,
1313 .get_rptr
= &radeon_ring_generic_get_rptr
,
1314 .get_wptr
= &radeon_ring_generic_get_wptr
,
1315 .set_wptr
= &radeon_ring_generic_set_wptr
,
1319 .set
= &r600_irq_set
,
1320 .process
= &r600_irq_process
,
1323 .bandwidth_update
= &rv515_bandwidth_update
,
1324 .get_vblank_counter
= &rs600_get_vblank_counter
,
1325 .wait_for_vblank
= &avivo_wait_for_vblank
,
1326 .set_backlight_level
= &atombios_set_backlight_level
,
1327 .get_backlight_level
= &atombios_get_backlight_level
,
1328 .hdmi_enable
= &r600_hdmi_enable
,
1329 .hdmi_setmode
= &r600_hdmi_setmode
,
1332 .blit
= &r600_copy_blit
,
1333 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1334 .dma
= &rv770_copy_dma
,
1335 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1336 .copy
= &rv770_copy_dma
,
1337 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1340 .set_reg
= r600_set_surface_reg
,
1341 .clear_reg
= r600_clear_surface_reg
,
1344 .init
= &r600_hpd_init
,
1345 .fini
= &r600_hpd_fini
,
1346 .sense
= &r600_hpd_sense
,
1347 .set_polarity
= &r600_hpd_set_polarity
,
1350 .misc
= &rv770_pm_misc
,
1351 .prepare
= &rs600_pm_prepare
,
1352 .finish
= &rs600_pm_finish
,
1353 .init_profile
= &r600_pm_init_profile
,
1354 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1355 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1356 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1357 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1358 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1359 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1360 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1361 .set_clock_gating
= &radeon_atom_set_clock_gating
,
1362 .set_uvd_clocks
= &rv770_set_uvd_clocks
,
1363 .get_temperature
= &rv770_get_temp
,
1366 .pre_page_flip
= &rs600_pre_page_flip
,
1367 .page_flip
= &rv770_page_flip
,
1368 .post_page_flip
= &rs600_post_page_flip
,
1372 static struct radeon_asic evergreen_asic
= {
1373 .init
= &evergreen_init
,
1374 .fini
= &evergreen_fini
,
1375 .suspend
= &evergreen_suspend
,
1376 .resume
= &evergreen_resume
,
1377 .asic_reset
= &evergreen_asic_reset
,
1378 .vga_set_state
= &r600_vga_set_state
,
1379 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1380 .gui_idle
= &r600_gui_idle
,
1381 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1382 .get_xclk
= &rv770_get_xclk
,
1383 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1385 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1386 .set_page
= &rs600_gart_set_page
,
1389 [RADEON_RING_TYPE_GFX_INDEX
] = {
1390 .ib_execute
= &evergreen_ring_ib_execute
,
1391 .emit_fence
= &r600_fence_ring_emit
,
1392 .emit_semaphore
= &r600_semaphore_ring_emit
,
1393 .cs_parse
= &evergreen_cs_parse
,
1394 .ring_test
= &r600_ring_test
,
1395 .ib_test
= &r600_ib_test
,
1396 .is_lockup
= &evergreen_gfx_is_lockup
,
1397 .get_rptr
= &radeon_ring_generic_get_rptr
,
1398 .get_wptr
= &radeon_ring_generic_get_wptr
,
1399 .set_wptr
= &radeon_ring_generic_set_wptr
,
1401 [R600_RING_TYPE_DMA_INDEX
] = {
1402 .ib_execute
= &evergreen_dma_ring_ib_execute
,
1403 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1404 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1405 .cs_parse
= &evergreen_dma_cs_parse
,
1406 .ring_test
= &r600_dma_ring_test
,
1407 .ib_test
= &r600_dma_ib_test
,
1408 .is_lockup
= &evergreen_dma_is_lockup
,
1409 .get_rptr
= &radeon_ring_generic_get_rptr
,
1410 .get_wptr
= &radeon_ring_generic_get_wptr
,
1411 .set_wptr
= &radeon_ring_generic_set_wptr
,
1413 [R600_RING_TYPE_UVD_INDEX
] = {
1414 .ib_execute
= &r600_uvd_ib_execute
,
1415 .emit_fence
= &r600_uvd_fence_emit
,
1416 .emit_semaphore
= &r600_uvd_semaphore_emit
,
1417 .cs_parse
= &radeon_uvd_cs_parse
,
1418 .ring_test
= &r600_uvd_ring_test
,
1419 .ib_test
= &r600_uvd_ib_test
,
1420 .is_lockup
= &radeon_ring_test_lockup
,
1421 .get_rptr
= &radeon_ring_generic_get_rptr
,
1422 .get_wptr
= &radeon_ring_generic_get_wptr
,
1423 .set_wptr
= &radeon_ring_generic_set_wptr
,
1427 .set
= &evergreen_irq_set
,
1428 .process
= &evergreen_irq_process
,
1431 .bandwidth_update
= &evergreen_bandwidth_update
,
1432 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1433 .wait_for_vblank
= &dce4_wait_for_vblank
,
1434 .set_backlight_level
= &atombios_set_backlight_level
,
1435 .get_backlight_level
= &atombios_get_backlight_level
,
1436 .hdmi_enable
= &evergreen_hdmi_enable
,
1437 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1440 .blit
= &r600_copy_blit
,
1441 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1442 .dma
= &evergreen_copy_dma
,
1443 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1444 .copy
= &evergreen_copy_dma
,
1445 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1448 .set_reg
= r600_set_surface_reg
,
1449 .clear_reg
= r600_clear_surface_reg
,
1452 .init
= &evergreen_hpd_init
,
1453 .fini
= &evergreen_hpd_fini
,
1454 .sense
= &evergreen_hpd_sense
,
1455 .set_polarity
= &evergreen_hpd_set_polarity
,
1458 .misc
= &evergreen_pm_misc
,
1459 .prepare
= &evergreen_pm_prepare
,
1460 .finish
= &evergreen_pm_finish
,
1461 .init_profile
= &r600_pm_init_profile
,
1462 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1463 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1464 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1465 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1466 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1467 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1468 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1469 .set_clock_gating
= NULL
,
1470 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1471 .get_temperature
= &evergreen_get_temp
,
1474 .pre_page_flip
= &evergreen_pre_page_flip
,
1475 .page_flip
= &evergreen_page_flip
,
1476 .post_page_flip
= &evergreen_post_page_flip
,
1480 static struct radeon_asic sumo_asic
= {
1481 .init
= &evergreen_init
,
1482 .fini
= &evergreen_fini
,
1483 .suspend
= &evergreen_suspend
,
1484 .resume
= &evergreen_resume
,
1485 .asic_reset
= &evergreen_asic_reset
,
1486 .vga_set_state
= &r600_vga_set_state
,
1487 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1488 .gui_idle
= &r600_gui_idle
,
1489 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1490 .get_xclk
= &r600_get_xclk
,
1491 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1493 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1494 .set_page
= &rs600_gart_set_page
,
1497 [RADEON_RING_TYPE_GFX_INDEX
] = {
1498 .ib_execute
= &evergreen_ring_ib_execute
,
1499 .emit_fence
= &r600_fence_ring_emit
,
1500 .emit_semaphore
= &r600_semaphore_ring_emit
,
1501 .cs_parse
= &evergreen_cs_parse
,
1502 .ring_test
= &r600_ring_test
,
1503 .ib_test
= &r600_ib_test
,
1504 .is_lockup
= &evergreen_gfx_is_lockup
,
1505 .get_rptr
= &radeon_ring_generic_get_rptr
,
1506 .get_wptr
= &radeon_ring_generic_get_wptr
,
1507 .set_wptr
= &radeon_ring_generic_set_wptr
,
1509 [R600_RING_TYPE_DMA_INDEX
] = {
1510 .ib_execute
= &evergreen_dma_ring_ib_execute
,
1511 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1512 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1513 .cs_parse
= &evergreen_dma_cs_parse
,
1514 .ring_test
= &r600_dma_ring_test
,
1515 .ib_test
= &r600_dma_ib_test
,
1516 .is_lockup
= &evergreen_dma_is_lockup
,
1517 .get_rptr
= &radeon_ring_generic_get_rptr
,
1518 .get_wptr
= &radeon_ring_generic_get_wptr
,
1519 .set_wptr
= &radeon_ring_generic_set_wptr
,
1521 [R600_RING_TYPE_UVD_INDEX
] = {
1522 .ib_execute
= &r600_uvd_ib_execute
,
1523 .emit_fence
= &r600_uvd_fence_emit
,
1524 .emit_semaphore
= &r600_uvd_semaphore_emit
,
1525 .cs_parse
= &radeon_uvd_cs_parse
,
1526 .ring_test
= &r600_uvd_ring_test
,
1527 .ib_test
= &r600_uvd_ib_test
,
1528 .is_lockup
= &radeon_ring_test_lockup
,
1529 .get_rptr
= &radeon_ring_generic_get_rptr
,
1530 .get_wptr
= &radeon_ring_generic_get_wptr
,
1531 .set_wptr
= &radeon_ring_generic_set_wptr
,
1535 .set
= &evergreen_irq_set
,
1536 .process
= &evergreen_irq_process
,
1539 .bandwidth_update
= &evergreen_bandwidth_update
,
1540 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1541 .wait_for_vblank
= &dce4_wait_for_vblank
,
1542 .set_backlight_level
= &atombios_set_backlight_level
,
1543 .get_backlight_level
= &atombios_get_backlight_level
,
1544 .hdmi_enable
= &evergreen_hdmi_enable
,
1545 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1548 .blit
= &r600_copy_blit
,
1549 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1550 .dma
= &evergreen_copy_dma
,
1551 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1552 .copy
= &evergreen_copy_dma
,
1553 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1556 .set_reg
= r600_set_surface_reg
,
1557 .clear_reg
= r600_clear_surface_reg
,
1560 .init
= &evergreen_hpd_init
,
1561 .fini
= &evergreen_hpd_fini
,
1562 .sense
= &evergreen_hpd_sense
,
1563 .set_polarity
= &evergreen_hpd_set_polarity
,
1566 .misc
= &evergreen_pm_misc
,
1567 .prepare
= &evergreen_pm_prepare
,
1568 .finish
= &evergreen_pm_finish
,
1569 .init_profile
= &sumo_pm_init_profile
,
1570 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1571 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1572 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1573 .get_memory_clock
= NULL
,
1574 .set_memory_clock
= NULL
,
1575 .get_pcie_lanes
= NULL
,
1576 .set_pcie_lanes
= NULL
,
1577 .set_clock_gating
= NULL
,
1578 .set_uvd_clocks
= &sumo_set_uvd_clocks
,
1579 .get_temperature
= &sumo_get_temp
,
1582 .pre_page_flip
= &evergreen_pre_page_flip
,
1583 .page_flip
= &evergreen_page_flip
,
1584 .post_page_flip
= &evergreen_post_page_flip
,
1588 static struct radeon_asic btc_asic
= {
1589 .init
= &evergreen_init
,
1590 .fini
= &evergreen_fini
,
1591 .suspend
= &evergreen_suspend
,
1592 .resume
= &evergreen_resume
,
1593 .asic_reset
= &evergreen_asic_reset
,
1594 .vga_set_state
= &r600_vga_set_state
,
1595 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1596 .gui_idle
= &r600_gui_idle
,
1597 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1598 .get_xclk
= &rv770_get_xclk
,
1599 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1601 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1602 .set_page
= &rs600_gart_set_page
,
1605 [RADEON_RING_TYPE_GFX_INDEX
] = {
1606 .ib_execute
= &evergreen_ring_ib_execute
,
1607 .emit_fence
= &r600_fence_ring_emit
,
1608 .emit_semaphore
= &r600_semaphore_ring_emit
,
1609 .cs_parse
= &evergreen_cs_parse
,
1610 .ring_test
= &r600_ring_test
,
1611 .ib_test
= &r600_ib_test
,
1612 .is_lockup
= &evergreen_gfx_is_lockup
,
1613 .get_rptr
= &radeon_ring_generic_get_rptr
,
1614 .get_wptr
= &radeon_ring_generic_get_wptr
,
1615 .set_wptr
= &radeon_ring_generic_set_wptr
,
1617 [R600_RING_TYPE_DMA_INDEX
] = {
1618 .ib_execute
= &evergreen_dma_ring_ib_execute
,
1619 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1620 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1621 .cs_parse
= &evergreen_dma_cs_parse
,
1622 .ring_test
= &r600_dma_ring_test
,
1623 .ib_test
= &r600_dma_ib_test
,
1624 .is_lockup
= &evergreen_dma_is_lockup
,
1625 .get_rptr
= &radeon_ring_generic_get_rptr
,
1626 .get_wptr
= &radeon_ring_generic_get_wptr
,
1627 .set_wptr
= &radeon_ring_generic_set_wptr
,
1629 [R600_RING_TYPE_UVD_INDEX
] = {
1630 .ib_execute
= &r600_uvd_ib_execute
,
1631 .emit_fence
= &r600_uvd_fence_emit
,
1632 .emit_semaphore
= &r600_uvd_semaphore_emit
,
1633 .cs_parse
= &radeon_uvd_cs_parse
,
1634 .ring_test
= &r600_uvd_ring_test
,
1635 .ib_test
= &r600_uvd_ib_test
,
1636 .is_lockup
= &radeon_ring_test_lockup
,
1637 .get_rptr
= &radeon_ring_generic_get_rptr
,
1638 .get_wptr
= &radeon_ring_generic_get_wptr
,
1639 .set_wptr
= &radeon_ring_generic_set_wptr
,
1643 .set
= &evergreen_irq_set
,
1644 .process
= &evergreen_irq_process
,
1647 .bandwidth_update
= &evergreen_bandwidth_update
,
1648 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1649 .wait_for_vblank
= &dce4_wait_for_vblank
,
1650 .set_backlight_level
= &atombios_set_backlight_level
,
1651 .get_backlight_level
= &atombios_get_backlight_level
,
1652 .hdmi_enable
= &evergreen_hdmi_enable
,
1653 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1656 .blit
= &r600_copy_blit
,
1657 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1658 .dma
= &evergreen_copy_dma
,
1659 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1660 .copy
= &evergreen_copy_dma
,
1661 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1664 .set_reg
= r600_set_surface_reg
,
1665 .clear_reg
= r600_clear_surface_reg
,
1668 .init
= &evergreen_hpd_init
,
1669 .fini
= &evergreen_hpd_fini
,
1670 .sense
= &evergreen_hpd_sense
,
1671 .set_polarity
= &evergreen_hpd_set_polarity
,
1674 .misc
= &evergreen_pm_misc
,
1675 .prepare
= &evergreen_pm_prepare
,
1676 .finish
= &evergreen_pm_finish
,
1677 .init_profile
= &btc_pm_init_profile
,
1678 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1679 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1680 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1681 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1682 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1683 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1684 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1685 .set_clock_gating
= NULL
,
1686 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1687 .get_temperature
= &evergreen_get_temp
,
1690 .pre_page_flip
= &evergreen_pre_page_flip
,
1691 .page_flip
= &evergreen_page_flip
,
1692 .post_page_flip
= &evergreen_post_page_flip
,
1696 static struct radeon_asic cayman_asic
= {
1697 .init
= &cayman_init
,
1698 .fini
= &cayman_fini
,
1699 .suspend
= &cayman_suspend
,
1700 .resume
= &cayman_resume
,
1701 .asic_reset
= &cayman_asic_reset
,
1702 .vga_set_state
= &r600_vga_set_state
,
1703 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1704 .gui_idle
= &r600_gui_idle
,
1705 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1706 .get_xclk
= &rv770_get_xclk
,
1707 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1709 .tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1710 .set_page
= &rs600_gart_set_page
,
1713 .init
= &cayman_vm_init
,
1714 .fini
= &cayman_vm_fini
,
1715 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1716 .set_page
= &cayman_vm_set_page
,
1719 [RADEON_RING_TYPE_GFX_INDEX
] = {
1720 .ib_execute
= &cayman_ring_ib_execute
,
1721 .ib_parse
= &evergreen_ib_parse
,
1722 .emit_fence
= &cayman_fence_ring_emit
,
1723 .emit_semaphore
= &r600_semaphore_ring_emit
,
1724 .cs_parse
= &evergreen_cs_parse
,
1725 .ring_test
= &r600_ring_test
,
1726 .ib_test
= &r600_ib_test
,
1727 .is_lockup
= &cayman_gfx_is_lockup
,
1728 .vm_flush
= &cayman_vm_flush
,
1729 .get_rptr
= &radeon_ring_generic_get_rptr
,
1730 .get_wptr
= &radeon_ring_generic_get_wptr
,
1731 .set_wptr
= &radeon_ring_generic_set_wptr
,
1733 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
1734 .ib_execute
= &cayman_ring_ib_execute
,
1735 .ib_parse
= &evergreen_ib_parse
,
1736 .emit_fence
= &cayman_fence_ring_emit
,
1737 .emit_semaphore
= &r600_semaphore_ring_emit
,
1738 .cs_parse
= &evergreen_cs_parse
,
1739 .ring_test
= &r600_ring_test
,
1740 .ib_test
= &r600_ib_test
,
1741 .is_lockup
= &cayman_gfx_is_lockup
,
1742 .vm_flush
= &cayman_vm_flush
,
1743 .get_rptr
= &radeon_ring_generic_get_rptr
,
1744 .get_wptr
= &radeon_ring_generic_get_wptr
,
1745 .set_wptr
= &radeon_ring_generic_set_wptr
,
1747 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
1748 .ib_execute
= &cayman_ring_ib_execute
,
1749 .ib_parse
= &evergreen_ib_parse
,
1750 .emit_fence
= &cayman_fence_ring_emit
,
1751 .emit_semaphore
= &r600_semaphore_ring_emit
,
1752 .cs_parse
= &evergreen_cs_parse
,
1753 .ring_test
= &r600_ring_test
,
1754 .ib_test
= &r600_ib_test
,
1755 .is_lockup
= &cayman_gfx_is_lockup
,
1756 .vm_flush
= &cayman_vm_flush
,
1757 .get_rptr
= &radeon_ring_generic_get_rptr
,
1758 .get_wptr
= &radeon_ring_generic_get_wptr
,
1759 .set_wptr
= &radeon_ring_generic_set_wptr
,
1761 [R600_RING_TYPE_DMA_INDEX
] = {
1762 .ib_execute
= &cayman_dma_ring_ib_execute
,
1763 .ib_parse
= &evergreen_dma_ib_parse
,
1764 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1765 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1766 .cs_parse
= &evergreen_dma_cs_parse
,
1767 .ring_test
= &r600_dma_ring_test
,
1768 .ib_test
= &r600_dma_ib_test
,
1769 .is_lockup
= &cayman_dma_is_lockup
,
1770 .vm_flush
= &cayman_dma_vm_flush
,
1771 .get_rptr
= &radeon_ring_generic_get_rptr
,
1772 .get_wptr
= &radeon_ring_generic_get_wptr
,
1773 .set_wptr
= &radeon_ring_generic_set_wptr
,
1775 [CAYMAN_RING_TYPE_DMA1_INDEX
] = {
1776 .ib_execute
= &cayman_dma_ring_ib_execute
,
1777 .ib_parse
= &evergreen_dma_ib_parse
,
1778 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1779 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1780 .cs_parse
= &evergreen_dma_cs_parse
,
1781 .ring_test
= &r600_dma_ring_test
,
1782 .ib_test
= &r600_dma_ib_test
,
1783 .is_lockup
= &cayman_dma_is_lockup
,
1784 .vm_flush
= &cayman_dma_vm_flush
,
1785 .get_rptr
= &radeon_ring_generic_get_rptr
,
1786 .get_wptr
= &radeon_ring_generic_get_wptr
,
1787 .set_wptr
= &radeon_ring_generic_set_wptr
,
1789 [R600_RING_TYPE_UVD_INDEX
] = {
1790 .ib_execute
= &r600_uvd_ib_execute
,
1791 .emit_fence
= &r600_uvd_fence_emit
,
1792 .emit_semaphore
= &cayman_uvd_semaphore_emit
,
1793 .cs_parse
= &radeon_uvd_cs_parse
,
1794 .ring_test
= &r600_uvd_ring_test
,
1795 .ib_test
= &r600_uvd_ib_test
,
1796 .is_lockup
= &radeon_ring_test_lockup
,
1797 .get_rptr
= &radeon_ring_generic_get_rptr
,
1798 .get_wptr
= &radeon_ring_generic_get_wptr
,
1799 .set_wptr
= &radeon_ring_generic_set_wptr
,
1803 .set
= &evergreen_irq_set
,
1804 .process
= &evergreen_irq_process
,
1807 .bandwidth_update
= &evergreen_bandwidth_update
,
1808 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1809 .wait_for_vblank
= &dce4_wait_for_vblank
,
1810 .set_backlight_level
= &atombios_set_backlight_level
,
1811 .get_backlight_level
= &atombios_get_backlight_level
,
1812 .hdmi_enable
= &evergreen_hdmi_enable
,
1813 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1816 .blit
= &r600_copy_blit
,
1817 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1818 .dma
= &evergreen_copy_dma
,
1819 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1820 .copy
= &evergreen_copy_dma
,
1821 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1824 .set_reg
= r600_set_surface_reg
,
1825 .clear_reg
= r600_clear_surface_reg
,
1828 .init
= &evergreen_hpd_init
,
1829 .fini
= &evergreen_hpd_fini
,
1830 .sense
= &evergreen_hpd_sense
,
1831 .set_polarity
= &evergreen_hpd_set_polarity
,
1834 .misc
= &evergreen_pm_misc
,
1835 .prepare
= &evergreen_pm_prepare
,
1836 .finish
= &evergreen_pm_finish
,
1837 .init_profile
= &btc_pm_init_profile
,
1838 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1839 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1840 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1841 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1842 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1843 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1844 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1845 .set_clock_gating
= NULL
,
1846 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1847 .get_temperature
= &evergreen_get_temp
,
1850 .pre_page_flip
= &evergreen_pre_page_flip
,
1851 .page_flip
= &evergreen_page_flip
,
1852 .post_page_flip
= &evergreen_post_page_flip
,
1856 static struct radeon_asic trinity_asic
= {
1857 .init
= &cayman_init
,
1858 .fini
= &cayman_fini
,
1859 .suspend
= &cayman_suspend
,
1860 .resume
= &cayman_resume
,
1861 .asic_reset
= &cayman_asic_reset
,
1862 .vga_set_state
= &r600_vga_set_state
,
1863 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1864 .gui_idle
= &r600_gui_idle
,
1865 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1866 .get_xclk
= &r600_get_xclk
,
1867 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1869 .tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1870 .set_page
= &rs600_gart_set_page
,
1873 .init
= &cayman_vm_init
,
1874 .fini
= &cayman_vm_fini
,
1875 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1876 .set_page
= &cayman_vm_set_page
,
1879 [RADEON_RING_TYPE_GFX_INDEX
] = {
1880 .ib_execute
= &cayman_ring_ib_execute
,
1881 .ib_parse
= &evergreen_ib_parse
,
1882 .emit_fence
= &cayman_fence_ring_emit
,
1883 .emit_semaphore
= &r600_semaphore_ring_emit
,
1884 .cs_parse
= &evergreen_cs_parse
,
1885 .ring_test
= &r600_ring_test
,
1886 .ib_test
= &r600_ib_test
,
1887 .is_lockup
= &cayman_gfx_is_lockup
,
1888 .vm_flush
= &cayman_vm_flush
,
1889 .get_rptr
= &radeon_ring_generic_get_rptr
,
1890 .get_wptr
= &radeon_ring_generic_get_wptr
,
1891 .set_wptr
= &radeon_ring_generic_set_wptr
,
1893 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
1894 .ib_execute
= &cayman_ring_ib_execute
,
1895 .ib_parse
= &evergreen_ib_parse
,
1896 .emit_fence
= &cayman_fence_ring_emit
,
1897 .emit_semaphore
= &r600_semaphore_ring_emit
,
1898 .cs_parse
= &evergreen_cs_parse
,
1899 .ring_test
= &r600_ring_test
,
1900 .ib_test
= &r600_ib_test
,
1901 .is_lockup
= &cayman_gfx_is_lockup
,
1902 .vm_flush
= &cayman_vm_flush
,
1903 .get_rptr
= &radeon_ring_generic_get_rptr
,
1904 .get_wptr
= &radeon_ring_generic_get_wptr
,
1905 .set_wptr
= &radeon_ring_generic_set_wptr
,
1907 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
1908 .ib_execute
= &cayman_ring_ib_execute
,
1909 .ib_parse
= &evergreen_ib_parse
,
1910 .emit_fence
= &cayman_fence_ring_emit
,
1911 .emit_semaphore
= &r600_semaphore_ring_emit
,
1912 .cs_parse
= &evergreen_cs_parse
,
1913 .ring_test
= &r600_ring_test
,
1914 .ib_test
= &r600_ib_test
,
1915 .is_lockup
= &cayman_gfx_is_lockup
,
1916 .vm_flush
= &cayman_vm_flush
,
1917 .get_rptr
= &radeon_ring_generic_get_rptr
,
1918 .get_wptr
= &radeon_ring_generic_get_wptr
,
1919 .set_wptr
= &radeon_ring_generic_set_wptr
,
1921 [R600_RING_TYPE_DMA_INDEX
] = {
1922 .ib_execute
= &cayman_dma_ring_ib_execute
,
1923 .ib_parse
= &evergreen_dma_ib_parse
,
1924 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1925 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1926 .cs_parse
= &evergreen_dma_cs_parse
,
1927 .ring_test
= &r600_dma_ring_test
,
1928 .ib_test
= &r600_dma_ib_test
,
1929 .is_lockup
= &cayman_dma_is_lockup
,
1930 .vm_flush
= &cayman_dma_vm_flush
,
1931 .get_rptr
= &radeon_ring_generic_get_rptr
,
1932 .get_wptr
= &radeon_ring_generic_get_wptr
,
1933 .set_wptr
= &radeon_ring_generic_set_wptr
,
1935 [CAYMAN_RING_TYPE_DMA1_INDEX
] = {
1936 .ib_execute
= &cayman_dma_ring_ib_execute
,
1937 .ib_parse
= &evergreen_dma_ib_parse
,
1938 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1939 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1940 .cs_parse
= &evergreen_dma_cs_parse
,
1941 .ring_test
= &r600_dma_ring_test
,
1942 .ib_test
= &r600_dma_ib_test
,
1943 .is_lockup
= &cayman_dma_is_lockup
,
1944 .vm_flush
= &cayman_dma_vm_flush
,
1945 .get_rptr
= &radeon_ring_generic_get_rptr
,
1946 .get_wptr
= &radeon_ring_generic_get_wptr
,
1947 .set_wptr
= &radeon_ring_generic_set_wptr
,
1949 [R600_RING_TYPE_UVD_INDEX
] = {
1950 .ib_execute
= &r600_uvd_ib_execute
,
1951 .emit_fence
= &r600_uvd_fence_emit
,
1952 .emit_semaphore
= &cayman_uvd_semaphore_emit
,
1953 .cs_parse
= &radeon_uvd_cs_parse
,
1954 .ring_test
= &r600_uvd_ring_test
,
1955 .ib_test
= &r600_uvd_ib_test
,
1956 .is_lockup
= &radeon_ring_test_lockup
,
1957 .get_rptr
= &radeon_ring_generic_get_rptr
,
1958 .get_wptr
= &radeon_ring_generic_get_wptr
,
1959 .set_wptr
= &radeon_ring_generic_set_wptr
,
1963 .set
= &evergreen_irq_set
,
1964 .process
= &evergreen_irq_process
,
1967 .bandwidth_update
= &dce6_bandwidth_update
,
1968 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1969 .wait_for_vblank
= &dce4_wait_for_vblank
,
1970 .set_backlight_level
= &atombios_set_backlight_level
,
1971 .get_backlight_level
= &atombios_get_backlight_level
,
1974 .blit
= &r600_copy_blit
,
1975 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1976 .dma
= &evergreen_copy_dma
,
1977 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1978 .copy
= &evergreen_copy_dma
,
1979 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1982 .set_reg
= r600_set_surface_reg
,
1983 .clear_reg
= r600_clear_surface_reg
,
1986 .init
= &evergreen_hpd_init
,
1987 .fini
= &evergreen_hpd_fini
,
1988 .sense
= &evergreen_hpd_sense
,
1989 .set_polarity
= &evergreen_hpd_set_polarity
,
1992 .misc
= &evergreen_pm_misc
,
1993 .prepare
= &evergreen_pm_prepare
,
1994 .finish
= &evergreen_pm_finish
,
1995 .init_profile
= &sumo_pm_init_profile
,
1996 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1997 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1998 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1999 .get_memory_clock
= NULL
,
2000 .set_memory_clock
= NULL
,
2001 .get_pcie_lanes
= NULL
,
2002 .set_pcie_lanes
= NULL
,
2003 .set_clock_gating
= NULL
,
2004 .set_uvd_clocks
= &sumo_set_uvd_clocks
,
2005 .get_temperature
= &tn_get_temp
,
2008 .pre_page_flip
= &evergreen_pre_page_flip
,
2009 .page_flip
= &evergreen_page_flip
,
2010 .post_page_flip
= &evergreen_post_page_flip
,
2014 static struct radeon_asic si_asic
= {
2017 .suspend
= &si_suspend
,
2018 .resume
= &si_resume
,
2019 .asic_reset
= &si_asic_reset
,
2020 .vga_set_state
= &r600_vga_set_state
,
2021 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
2022 .gui_idle
= &r600_gui_idle
,
2023 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
2024 .get_xclk
= &si_get_xclk
,
2025 .get_gpu_clock_counter
= &si_get_gpu_clock_counter
,
2027 .tlb_flush
= &si_pcie_gart_tlb_flush
,
2028 .set_page
= &rs600_gart_set_page
,
2031 .init
= &si_vm_init
,
2032 .fini
= &si_vm_fini
,
2033 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2034 .set_page
= &si_vm_set_page
,
2037 [RADEON_RING_TYPE_GFX_INDEX
] = {
2038 .ib_execute
= &si_ring_ib_execute
,
2039 .ib_parse
= &si_ib_parse
,
2040 .emit_fence
= &si_fence_ring_emit
,
2041 .emit_semaphore
= &r600_semaphore_ring_emit
,
2043 .ring_test
= &r600_ring_test
,
2044 .ib_test
= &r600_ib_test
,
2045 .is_lockup
= &si_gfx_is_lockup
,
2046 .vm_flush
= &si_vm_flush
,
2047 .get_rptr
= &radeon_ring_generic_get_rptr
,
2048 .get_wptr
= &radeon_ring_generic_get_wptr
,
2049 .set_wptr
= &radeon_ring_generic_set_wptr
,
2051 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
2052 .ib_execute
= &si_ring_ib_execute
,
2053 .ib_parse
= &si_ib_parse
,
2054 .emit_fence
= &si_fence_ring_emit
,
2055 .emit_semaphore
= &r600_semaphore_ring_emit
,
2057 .ring_test
= &r600_ring_test
,
2058 .ib_test
= &r600_ib_test
,
2059 .is_lockup
= &si_gfx_is_lockup
,
2060 .vm_flush
= &si_vm_flush
,
2061 .get_rptr
= &radeon_ring_generic_get_rptr
,
2062 .get_wptr
= &radeon_ring_generic_get_wptr
,
2063 .set_wptr
= &radeon_ring_generic_set_wptr
,
2065 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
2066 .ib_execute
= &si_ring_ib_execute
,
2067 .ib_parse
= &si_ib_parse
,
2068 .emit_fence
= &si_fence_ring_emit
,
2069 .emit_semaphore
= &r600_semaphore_ring_emit
,
2071 .ring_test
= &r600_ring_test
,
2072 .ib_test
= &r600_ib_test
,
2073 .is_lockup
= &si_gfx_is_lockup
,
2074 .vm_flush
= &si_vm_flush
,
2075 .get_rptr
= &radeon_ring_generic_get_rptr
,
2076 .get_wptr
= &radeon_ring_generic_get_wptr
,
2077 .set_wptr
= &radeon_ring_generic_set_wptr
,
2079 [R600_RING_TYPE_DMA_INDEX
] = {
2080 .ib_execute
= &cayman_dma_ring_ib_execute
,
2081 .ib_parse
= &evergreen_dma_ib_parse
,
2082 .emit_fence
= &evergreen_dma_fence_ring_emit
,
2083 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
2085 .ring_test
= &r600_dma_ring_test
,
2086 .ib_test
= &r600_dma_ib_test
,
2087 .is_lockup
= &si_dma_is_lockup
,
2088 .vm_flush
= &si_dma_vm_flush
,
2089 .get_rptr
= &radeon_ring_generic_get_rptr
,
2090 .get_wptr
= &radeon_ring_generic_get_wptr
,
2091 .set_wptr
= &radeon_ring_generic_set_wptr
,
2093 [CAYMAN_RING_TYPE_DMA1_INDEX
] = {
2094 .ib_execute
= &cayman_dma_ring_ib_execute
,
2095 .ib_parse
= &evergreen_dma_ib_parse
,
2096 .emit_fence
= &evergreen_dma_fence_ring_emit
,
2097 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
2099 .ring_test
= &r600_dma_ring_test
,
2100 .ib_test
= &r600_dma_ib_test
,
2101 .is_lockup
= &si_dma_is_lockup
,
2102 .vm_flush
= &si_dma_vm_flush
,
2103 .get_rptr
= &radeon_ring_generic_get_rptr
,
2104 .get_wptr
= &radeon_ring_generic_get_wptr
,
2105 .set_wptr
= &radeon_ring_generic_set_wptr
,
2107 [R600_RING_TYPE_UVD_INDEX
] = {
2108 .ib_execute
= &r600_uvd_ib_execute
,
2109 .emit_fence
= &r600_uvd_fence_emit
,
2110 .emit_semaphore
= &cayman_uvd_semaphore_emit
,
2111 .cs_parse
= &radeon_uvd_cs_parse
,
2112 .ring_test
= &r600_uvd_ring_test
,
2113 .ib_test
= &r600_uvd_ib_test
,
2114 .is_lockup
= &radeon_ring_test_lockup
,
2115 .get_rptr
= &radeon_ring_generic_get_rptr
,
2116 .get_wptr
= &radeon_ring_generic_get_wptr
,
2117 .set_wptr
= &radeon_ring_generic_set_wptr
,
2122 .process
= &si_irq_process
,
2125 .bandwidth_update
= &dce6_bandwidth_update
,
2126 .get_vblank_counter
= &evergreen_get_vblank_counter
,
2127 .wait_for_vblank
= &dce4_wait_for_vblank
,
2128 .set_backlight_level
= &atombios_set_backlight_level
,
2129 .get_backlight_level
= &atombios_get_backlight_level
,
2133 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
2134 .dma
= &si_copy_dma
,
2135 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2136 .copy
= &si_copy_dma
,
2137 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2140 .set_reg
= r600_set_surface_reg
,
2141 .clear_reg
= r600_clear_surface_reg
,
2144 .init
= &evergreen_hpd_init
,
2145 .fini
= &evergreen_hpd_fini
,
2146 .sense
= &evergreen_hpd_sense
,
2147 .set_polarity
= &evergreen_hpd_set_polarity
,
2150 .misc
= &evergreen_pm_misc
,
2151 .prepare
= &evergreen_pm_prepare
,
2152 .finish
= &evergreen_pm_finish
,
2153 .init_profile
= &sumo_pm_init_profile
,
2154 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
2155 .get_engine_clock
= &radeon_atom_get_engine_clock
,
2156 .set_engine_clock
= &radeon_atom_set_engine_clock
,
2157 .get_memory_clock
= &radeon_atom_get_memory_clock
,
2158 .set_memory_clock
= &radeon_atom_set_memory_clock
,
2159 .get_pcie_lanes
= &r600_get_pcie_lanes
,
2160 .set_pcie_lanes
= &r600_set_pcie_lanes
,
2161 .set_clock_gating
= NULL
,
2162 .set_uvd_clocks
= &si_set_uvd_clocks
,
2163 .get_temperature
= &si_get_temp
,
2166 .pre_page_flip
= &evergreen_pre_page_flip
,
2167 .page_flip
= &evergreen_page_flip
,
2168 .post_page_flip
= &evergreen_post_page_flip
,
2172 static struct radeon_asic ci_asic
= {
2175 .suspend
= &cik_suspend
,
2176 .resume
= &cik_resume
,
2177 .asic_reset
= &cik_asic_reset
,
2178 .vga_set_state
= &r600_vga_set_state
,
2179 .ioctl_wait_idle
= NULL
,
2180 .gui_idle
= &r600_gui_idle
,
2181 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
2182 .get_xclk
= &cik_get_xclk
,
2183 .get_gpu_clock_counter
= &cik_get_gpu_clock_counter
,
2185 .tlb_flush
= &cik_pcie_gart_tlb_flush
,
2186 .set_page
= &rs600_gart_set_page
,
2189 .init
= &cik_vm_init
,
2190 .fini
= &cik_vm_fini
,
2191 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2192 .set_page
= &cik_vm_set_page
,
2195 [RADEON_RING_TYPE_GFX_INDEX
] = {
2196 .ib_execute
= &cik_ring_ib_execute
,
2197 .ib_parse
= &cik_ib_parse
,
2198 .emit_fence
= &cik_fence_gfx_ring_emit
,
2199 .emit_semaphore
= &cik_semaphore_ring_emit
,
2201 .ring_test
= &cik_ring_test
,
2202 .ib_test
= &cik_ib_test
,
2203 .is_lockup
= &cik_gfx_is_lockup
,
2204 .vm_flush
= &cik_vm_flush
,
2205 .get_rptr
= &radeon_ring_generic_get_rptr
,
2206 .get_wptr
= &radeon_ring_generic_get_wptr
,
2207 .set_wptr
= &radeon_ring_generic_set_wptr
,
2209 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
2210 .ib_execute
= &cik_ring_ib_execute
,
2211 .ib_parse
= &cik_ib_parse
,
2212 .emit_fence
= &cik_fence_compute_ring_emit
,
2213 .emit_semaphore
= &cik_semaphore_ring_emit
,
2215 .ring_test
= &cik_ring_test
,
2216 .ib_test
= &cik_ib_test
,
2217 .is_lockup
= &cik_gfx_is_lockup
,
2218 .vm_flush
= &cik_vm_flush
,
2219 .get_rptr
= &cik_compute_ring_get_rptr
,
2220 .get_wptr
= &cik_compute_ring_get_wptr
,
2221 .set_wptr
= &cik_compute_ring_set_wptr
,
2223 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
2224 .ib_execute
= &cik_ring_ib_execute
,
2225 .ib_parse
= &cik_ib_parse
,
2226 .emit_fence
= &cik_fence_compute_ring_emit
,
2227 .emit_semaphore
= &cik_semaphore_ring_emit
,
2229 .ring_test
= &cik_ring_test
,
2230 .ib_test
= &cik_ib_test
,
2231 .is_lockup
= &cik_gfx_is_lockup
,
2232 .vm_flush
= &cik_vm_flush
,
2233 .get_rptr
= &cik_compute_ring_get_rptr
,
2234 .get_wptr
= &cik_compute_ring_get_wptr
,
2235 .set_wptr
= &cik_compute_ring_set_wptr
,
2237 [R600_RING_TYPE_DMA_INDEX
] = {
2238 .ib_execute
= &cik_sdma_ring_ib_execute
,
2239 .ib_parse
= &cik_ib_parse
,
2240 .emit_fence
= &cik_sdma_fence_ring_emit
,
2241 .emit_semaphore
= &cik_sdma_semaphore_ring_emit
,
2243 .ring_test
= &cik_sdma_ring_test
,
2244 .ib_test
= &cik_sdma_ib_test
,
2245 .is_lockup
= &cik_sdma_is_lockup
,
2246 .vm_flush
= &cik_dma_vm_flush
,
2247 .get_rptr
= &radeon_ring_generic_get_rptr
,
2248 .get_wptr
= &radeon_ring_generic_get_wptr
,
2249 .set_wptr
= &radeon_ring_generic_set_wptr
,
2251 [CAYMAN_RING_TYPE_DMA1_INDEX
] = {
2252 .ib_execute
= &cik_sdma_ring_ib_execute
,
2253 .ib_parse
= &cik_ib_parse
,
2254 .emit_fence
= &cik_sdma_fence_ring_emit
,
2255 .emit_semaphore
= &cik_sdma_semaphore_ring_emit
,
2257 .ring_test
= &cik_sdma_ring_test
,
2258 .ib_test
= &cik_sdma_ib_test
,
2259 .is_lockup
= &cik_sdma_is_lockup
,
2260 .vm_flush
= &cik_dma_vm_flush
,
2261 .get_rptr
= &radeon_ring_generic_get_rptr
,
2262 .get_wptr
= &radeon_ring_generic_get_wptr
,
2263 .set_wptr
= &radeon_ring_generic_set_wptr
,
2265 [R600_RING_TYPE_UVD_INDEX
] = {
2266 .ib_execute
= &r600_uvd_ib_execute
,
2267 .emit_fence
= &r600_uvd_fence_emit
,
2268 .emit_semaphore
= &cayman_uvd_semaphore_emit
,
2269 .cs_parse
= &radeon_uvd_cs_parse
,
2270 .ring_test
= &r600_uvd_ring_test
,
2271 .ib_test
= &r600_uvd_ib_test
,
2272 .is_lockup
= &radeon_ring_test_lockup
,
2273 .get_rptr
= &radeon_ring_generic_get_rptr
,
2274 .get_wptr
= &radeon_ring_generic_get_wptr
,
2275 .set_wptr
= &radeon_ring_generic_set_wptr
,
2279 .set
= &cik_irq_set
,
2280 .process
= &cik_irq_process
,
2283 .bandwidth_update
= &dce8_bandwidth_update
,
2284 .get_vblank_counter
= &evergreen_get_vblank_counter
,
2285 .wait_for_vblank
= &dce4_wait_for_vblank
,
2289 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
2290 .dma
= &cik_copy_dma
,
2291 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2292 .copy
= &cik_copy_dma
,
2293 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2296 .set_reg
= r600_set_surface_reg
,
2297 .clear_reg
= r600_clear_surface_reg
,
2300 .init
= &evergreen_hpd_init
,
2301 .fini
= &evergreen_hpd_fini
,
2302 .sense
= &evergreen_hpd_sense
,
2303 .set_polarity
= &evergreen_hpd_set_polarity
,
2306 .misc
= &evergreen_pm_misc
,
2307 .prepare
= &evergreen_pm_prepare
,
2308 .finish
= &evergreen_pm_finish
,
2309 .init_profile
= &sumo_pm_init_profile
,
2310 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
2311 .get_engine_clock
= &radeon_atom_get_engine_clock
,
2312 .set_engine_clock
= &radeon_atom_set_engine_clock
,
2313 .get_memory_clock
= &radeon_atom_get_memory_clock
,
2314 .set_memory_clock
= &radeon_atom_set_memory_clock
,
2315 .get_pcie_lanes
= NULL
,
2316 .set_pcie_lanes
= NULL
,
2317 .set_clock_gating
= NULL
,
2318 .set_uvd_clocks
= &cik_set_uvd_clocks
,
2321 .pre_page_flip
= &evergreen_pre_page_flip
,
2322 .page_flip
= &evergreen_page_flip
,
2323 .post_page_flip
= &evergreen_post_page_flip
,
2327 static struct radeon_asic kv_asic
= {
2330 .suspend
= &cik_suspend
,
2331 .resume
= &cik_resume
,
2332 .asic_reset
= &cik_asic_reset
,
2333 .vga_set_state
= &r600_vga_set_state
,
2334 .ioctl_wait_idle
= NULL
,
2335 .gui_idle
= &r600_gui_idle
,
2336 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
2337 .get_xclk
= &cik_get_xclk
,
2338 .get_gpu_clock_counter
= &cik_get_gpu_clock_counter
,
2340 .tlb_flush
= &cik_pcie_gart_tlb_flush
,
2341 .set_page
= &rs600_gart_set_page
,
2344 .init
= &cik_vm_init
,
2345 .fini
= &cik_vm_fini
,
2346 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2347 .set_page
= &cik_vm_set_page
,
2350 [RADEON_RING_TYPE_GFX_INDEX
] = {
2351 .ib_execute
= &cik_ring_ib_execute
,
2352 .ib_parse
= &cik_ib_parse
,
2353 .emit_fence
= &cik_fence_gfx_ring_emit
,
2354 .emit_semaphore
= &cik_semaphore_ring_emit
,
2356 .ring_test
= &cik_ring_test
,
2357 .ib_test
= &cik_ib_test
,
2358 .is_lockup
= &cik_gfx_is_lockup
,
2359 .vm_flush
= &cik_vm_flush
,
2360 .get_rptr
= &radeon_ring_generic_get_rptr
,
2361 .get_wptr
= &radeon_ring_generic_get_wptr
,
2362 .set_wptr
= &radeon_ring_generic_set_wptr
,
2364 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
2365 .ib_execute
= &cik_ring_ib_execute
,
2366 .ib_parse
= &cik_ib_parse
,
2367 .emit_fence
= &cik_fence_compute_ring_emit
,
2368 .emit_semaphore
= &cik_semaphore_ring_emit
,
2370 .ring_test
= &cik_ring_test
,
2371 .ib_test
= &cik_ib_test
,
2372 .is_lockup
= &cik_gfx_is_lockup
,
2373 .vm_flush
= &cik_vm_flush
,
2374 .get_rptr
= &cik_compute_ring_get_rptr
,
2375 .get_wptr
= &cik_compute_ring_get_wptr
,
2376 .set_wptr
= &cik_compute_ring_set_wptr
,
2378 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
2379 .ib_execute
= &cik_ring_ib_execute
,
2380 .ib_parse
= &cik_ib_parse
,
2381 .emit_fence
= &cik_fence_compute_ring_emit
,
2382 .emit_semaphore
= &cik_semaphore_ring_emit
,
2384 .ring_test
= &cik_ring_test
,
2385 .ib_test
= &cik_ib_test
,
2386 .is_lockup
= &cik_gfx_is_lockup
,
2387 .vm_flush
= &cik_vm_flush
,
2388 .get_rptr
= &cik_compute_ring_get_rptr
,
2389 .get_wptr
= &cik_compute_ring_get_wptr
,
2390 .set_wptr
= &cik_compute_ring_set_wptr
,
2392 [R600_RING_TYPE_DMA_INDEX
] = {
2393 .ib_execute
= &cik_sdma_ring_ib_execute
,
2394 .ib_parse
= &cik_ib_parse
,
2395 .emit_fence
= &cik_sdma_fence_ring_emit
,
2396 .emit_semaphore
= &cik_sdma_semaphore_ring_emit
,
2398 .ring_test
= &cik_sdma_ring_test
,
2399 .ib_test
= &cik_sdma_ib_test
,
2400 .is_lockup
= &cik_sdma_is_lockup
,
2401 .vm_flush
= &cik_dma_vm_flush
,
2402 .get_rptr
= &radeon_ring_generic_get_rptr
,
2403 .get_wptr
= &radeon_ring_generic_get_wptr
,
2404 .set_wptr
= &radeon_ring_generic_set_wptr
,
2406 [CAYMAN_RING_TYPE_DMA1_INDEX
] = {
2407 .ib_execute
= &cik_sdma_ring_ib_execute
,
2408 .ib_parse
= &cik_ib_parse
,
2409 .emit_fence
= &cik_sdma_fence_ring_emit
,
2410 .emit_semaphore
= &cik_sdma_semaphore_ring_emit
,
2412 .ring_test
= &cik_sdma_ring_test
,
2413 .ib_test
= &cik_sdma_ib_test
,
2414 .is_lockup
= &cik_sdma_is_lockup
,
2415 .vm_flush
= &cik_dma_vm_flush
,
2416 .get_rptr
= &radeon_ring_generic_get_rptr
,
2417 .get_wptr
= &radeon_ring_generic_get_wptr
,
2418 .set_wptr
= &radeon_ring_generic_set_wptr
,
2420 [R600_RING_TYPE_UVD_INDEX
] = {
2421 .ib_execute
= &r600_uvd_ib_execute
,
2422 .emit_fence
= &r600_uvd_fence_emit
,
2423 .emit_semaphore
= &cayman_uvd_semaphore_emit
,
2424 .cs_parse
= &radeon_uvd_cs_parse
,
2425 .ring_test
= &r600_uvd_ring_test
,
2426 .ib_test
= &r600_uvd_ib_test
,
2427 .is_lockup
= &radeon_ring_test_lockup
,
2428 .get_rptr
= &radeon_ring_generic_get_rptr
,
2429 .get_wptr
= &radeon_ring_generic_get_wptr
,
2430 .set_wptr
= &radeon_ring_generic_set_wptr
,
2434 .set
= &cik_irq_set
,
2435 .process
= &cik_irq_process
,
2438 .bandwidth_update
= &dce8_bandwidth_update
,
2439 .get_vblank_counter
= &evergreen_get_vblank_counter
,
2440 .wait_for_vblank
= &dce4_wait_for_vblank
,
2444 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
2445 .dma
= &cik_copy_dma
,
2446 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2447 .copy
= &cik_copy_dma
,
2448 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2451 .set_reg
= r600_set_surface_reg
,
2452 .clear_reg
= r600_clear_surface_reg
,
2455 .init
= &evergreen_hpd_init
,
2456 .fini
= &evergreen_hpd_fini
,
2457 .sense
= &evergreen_hpd_sense
,
2458 .set_polarity
= &evergreen_hpd_set_polarity
,
2461 .misc
= &evergreen_pm_misc
,
2462 .prepare
= &evergreen_pm_prepare
,
2463 .finish
= &evergreen_pm_finish
,
2464 .init_profile
= &sumo_pm_init_profile
,
2465 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
2466 .get_engine_clock
= &radeon_atom_get_engine_clock
,
2467 .set_engine_clock
= &radeon_atom_set_engine_clock
,
2468 .get_memory_clock
= &radeon_atom_get_memory_clock
,
2469 .set_memory_clock
= &radeon_atom_set_memory_clock
,
2470 .get_pcie_lanes
= NULL
,
2471 .set_pcie_lanes
= NULL
,
2472 .set_clock_gating
= NULL
,
2473 .set_uvd_clocks
= &cik_set_uvd_clocks
,
2476 .pre_page_flip
= &evergreen_pre_page_flip
,
2477 .page_flip
= &evergreen_page_flip
,
2478 .post_page_flip
= &evergreen_post_page_flip
,
2483 * radeon_asic_init - register asic specific callbacks
2485 * @rdev: radeon device pointer
2487 * Registers the appropriate asic specific callbacks for each
2488 * chip family. Also sets other asics specific info like the number
2489 * of crtcs and the register aperture accessors (all asics).
2490 * Returns 0 for success.
2492 int radeon_asic_init(struct radeon_device
*rdev
)
2494 radeon_register_accessor_init(rdev
);
2496 /* set the number of crtcs */
2497 if (rdev
->flags
& RADEON_SINGLE_CRTC
)
2502 rdev
->has_uvd
= false;
2504 switch (rdev
->family
) {
2510 rdev
->asic
= &r100_asic
;
2516 rdev
->asic
= &r200_asic
;
2522 if (rdev
->flags
& RADEON_IS_PCIE
)
2523 rdev
->asic
= &r300_asic_pcie
;
2525 rdev
->asic
= &r300_asic
;
2530 rdev
->asic
= &r420_asic
;
2532 if (rdev
->bios
== NULL
) {
2533 rdev
->asic
->pm
.get_engine_clock
= &radeon_legacy_get_engine_clock
;
2534 rdev
->asic
->pm
.set_engine_clock
= &radeon_legacy_set_engine_clock
;
2535 rdev
->asic
->pm
.get_memory_clock
= &radeon_legacy_get_memory_clock
;
2536 rdev
->asic
->pm
.set_memory_clock
= NULL
;
2537 rdev
->asic
->display
.set_backlight_level
= &radeon_legacy_set_backlight_level
;
2542 rdev
->asic
= &rs400_asic
;
2545 rdev
->asic
= &rs600_asic
;
2549 rdev
->asic
= &rs690_asic
;
2552 rdev
->asic
= &rv515_asic
;
2559 rdev
->asic
= &r520_asic
;
2562 rdev
->asic
= &r600_asic
;
2569 rdev
->asic
= &rv6xx_asic
;
2570 rdev
->has_uvd
= true;
2574 rdev
->asic
= &rs780_asic
;
2575 rdev
->has_uvd
= true;
2581 rdev
->asic
= &rv770_asic
;
2582 rdev
->has_uvd
= true;
2590 if (rdev
->family
== CHIP_CEDAR
)
2594 rdev
->asic
= &evergreen_asic
;
2595 rdev
->has_uvd
= true;
2600 rdev
->asic
= &sumo_asic
;
2601 rdev
->has_uvd
= true;
2607 if (rdev
->family
== CHIP_CAICOS
)
2611 rdev
->asic
= &btc_asic
;
2612 rdev
->has_uvd
= true;
2615 rdev
->asic
= &cayman_asic
;
2618 rdev
->has_uvd
= true;
2621 rdev
->asic
= &trinity_asic
;
2624 rdev
->has_uvd
= true;
2631 rdev
->asic
= &si_asic
;
2633 if (rdev
->family
== CHIP_HAINAN
)
2635 else if (rdev
->family
== CHIP_OLAND
)
2639 if (rdev
->family
== CHIP_HAINAN
)
2640 rdev
->has_uvd
= false;
2642 rdev
->has_uvd
= true;
2645 rdev
->asic
= &ci_asic
;
2650 rdev
->asic
= &kv_asic
;
2652 if (rdev
->family
== CHIP_KAVERI
)
2658 /* FIXME: not supported yet */
2662 if (rdev
->flags
& RADEON_IS_IGP
) {
2663 rdev
->asic
->pm
.get_memory_clock
= NULL
;
2664 rdev
->asic
->pm
.set_memory_clock
= NULL
;