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drm/radeon/kms: add dpm support for rv6xx (v3)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <linux/console.h>
30 #include <drm/drmP.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
36 #include "radeon.h"
37 #include "radeon_asic.h"
38 #include "atom.h"
39
40 /*
41 * Registers accessors functions.
42 */
43 /**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54 {
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58 }
59
60 /**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71 {
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75 }
76
77 /**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
85 static void radeon_register_accessor_init(struct radeon_device *rdev)
86 {
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137 }
138
139
140 /* helper to disable agp */
141 /**
142 * radeon_agp_disable - AGP disable helper function
143 *
144 * @rdev: radeon device pointer
145 *
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
148 */
149 void radeon_agp_disable(struct radeon_device *rdev)
150 {
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
163 } else {
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
168 }
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170 }
171
172 /*
173 * ASIC
174 */
175 static struct radeon_asic r100_asic = {
176 .init = &r100_init,
177 .fini = &r100_fini,
178 .suspend = &r100_suspend,
179 .resume = &r100_resume,
180 .vga_set_state = &r100_vga_set_state,
181 .asic_reset = &r100_asic_reset,
182 .ioctl_wait_idle = NULL,
183 .gui_idle = &r100_gui_idle,
184 .mc_wait_for_idle = &r100_mc_wait_for_idle,
185 .gart = {
186 .tlb_flush = &r100_pci_gart_tlb_flush,
187 .set_page = &r100_pci_gart_set_page,
188 },
189 .ring = {
190 [RADEON_RING_TYPE_GFX_INDEX] = {
191 .ib_execute = &r100_ring_ib_execute,
192 .emit_fence = &r100_fence_ring_emit,
193 .emit_semaphore = &r100_semaphore_ring_emit,
194 .cs_parse = &r100_cs_parse,
195 .ring_start = &r100_ring_start,
196 .ring_test = &r100_ring_test,
197 .ib_test = &r100_ib_test,
198 .is_lockup = &r100_gpu_is_lockup,
199 .get_rptr = &radeon_ring_generic_get_rptr,
200 .get_wptr = &radeon_ring_generic_get_wptr,
201 .set_wptr = &radeon_ring_generic_set_wptr,
202 }
203 },
204 .irq = {
205 .set = &r100_irq_set,
206 .process = &r100_irq_process,
207 },
208 .display = {
209 .bandwidth_update = &r100_bandwidth_update,
210 .get_vblank_counter = &r100_get_vblank_counter,
211 .wait_for_vblank = &r100_wait_for_vblank,
212 .set_backlight_level = &radeon_legacy_set_backlight_level,
213 .get_backlight_level = &radeon_legacy_get_backlight_level,
214 },
215 .copy = {
216 .blit = &r100_copy_blit,
217 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
218 .dma = NULL,
219 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
220 .copy = &r100_copy_blit,
221 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
222 },
223 .surface = {
224 .set_reg = r100_set_surface_reg,
225 .clear_reg = r100_clear_surface_reg,
226 },
227 .hpd = {
228 .init = &r100_hpd_init,
229 .fini = &r100_hpd_fini,
230 .sense = &r100_hpd_sense,
231 .set_polarity = &r100_hpd_set_polarity,
232 },
233 .pm = {
234 .misc = &r100_pm_misc,
235 .prepare = &r100_pm_prepare,
236 .finish = &r100_pm_finish,
237 .init_profile = &r100_pm_init_profile,
238 .get_dynpm_state = &r100_pm_get_dynpm_state,
239 .get_engine_clock = &radeon_legacy_get_engine_clock,
240 .set_engine_clock = &radeon_legacy_set_engine_clock,
241 .get_memory_clock = &radeon_legacy_get_memory_clock,
242 .set_memory_clock = NULL,
243 .get_pcie_lanes = NULL,
244 .set_pcie_lanes = NULL,
245 .set_clock_gating = &radeon_legacy_set_clock_gating,
246 },
247 .pflip = {
248 .pre_page_flip = &r100_pre_page_flip,
249 .page_flip = &r100_page_flip,
250 .post_page_flip = &r100_post_page_flip,
251 },
252 };
253
254 static struct radeon_asic r200_asic = {
255 .init = &r100_init,
256 .fini = &r100_fini,
257 .suspend = &r100_suspend,
258 .resume = &r100_resume,
259 .vga_set_state = &r100_vga_set_state,
260 .asic_reset = &r100_asic_reset,
261 .ioctl_wait_idle = NULL,
262 .gui_idle = &r100_gui_idle,
263 .mc_wait_for_idle = &r100_mc_wait_for_idle,
264 .gart = {
265 .tlb_flush = &r100_pci_gart_tlb_flush,
266 .set_page = &r100_pci_gart_set_page,
267 },
268 .ring = {
269 [RADEON_RING_TYPE_GFX_INDEX] = {
270 .ib_execute = &r100_ring_ib_execute,
271 .emit_fence = &r100_fence_ring_emit,
272 .emit_semaphore = &r100_semaphore_ring_emit,
273 .cs_parse = &r100_cs_parse,
274 .ring_start = &r100_ring_start,
275 .ring_test = &r100_ring_test,
276 .ib_test = &r100_ib_test,
277 .is_lockup = &r100_gpu_is_lockup,
278 .get_rptr = &radeon_ring_generic_get_rptr,
279 .get_wptr = &radeon_ring_generic_get_wptr,
280 .set_wptr = &radeon_ring_generic_set_wptr,
281 }
282 },
283 .irq = {
284 .set = &r100_irq_set,
285 .process = &r100_irq_process,
286 },
287 .display = {
288 .bandwidth_update = &r100_bandwidth_update,
289 .get_vblank_counter = &r100_get_vblank_counter,
290 .wait_for_vblank = &r100_wait_for_vblank,
291 .set_backlight_level = &radeon_legacy_set_backlight_level,
292 .get_backlight_level = &radeon_legacy_get_backlight_level,
293 },
294 .copy = {
295 .blit = &r100_copy_blit,
296 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
297 .dma = &r200_copy_dma,
298 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
299 .copy = &r100_copy_blit,
300 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
301 },
302 .surface = {
303 .set_reg = r100_set_surface_reg,
304 .clear_reg = r100_clear_surface_reg,
305 },
306 .hpd = {
307 .init = &r100_hpd_init,
308 .fini = &r100_hpd_fini,
309 .sense = &r100_hpd_sense,
310 .set_polarity = &r100_hpd_set_polarity,
311 },
312 .pm = {
313 .misc = &r100_pm_misc,
314 .prepare = &r100_pm_prepare,
315 .finish = &r100_pm_finish,
316 .init_profile = &r100_pm_init_profile,
317 .get_dynpm_state = &r100_pm_get_dynpm_state,
318 .get_engine_clock = &radeon_legacy_get_engine_clock,
319 .set_engine_clock = &radeon_legacy_set_engine_clock,
320 .get_memory_clock = &radeon_legacy_get_memory_clock,
321 .set_memory_clock = NULL,
322 .get_pcie_lanes = NULL,
323 .set_pcie_lanes = NULL,
324 .set_clock_gating = &radeon_legacy_set_clock_gating,
325 },
326 .pflip = {
327 .pre_page_flip = &r100_pre_page_flip,
328 .page_flip = &r100_page_flip,
329 .post_page_flip = &r100_post_page_flip,
330 },
331 };
332
333 static struct radeon_asic r300_asic = {
334 .init = &r300_init,
335 .fini = &r300_fini,
336 .suspend = &r300_suspend,
337 .resume = &r300_resume,
338 .vga_set_state = &r100_vga_set_state,
339 .asic_reset = &r300_asic_reset,
340 .ioctl_wait_idle = NULL,
341 .gui_idle = &r100_gui_idle,
342 .mc_wait_for_idle = &r300_mc_wait_for_idle,
343 .gart = {
344 .tlb_flush = &r100_pci_gart_tlb_flush,
345 .set_page = &r100_pci_gart_set_page,
346 },
347 .ring = {
348 [RADEON_RING_TYPE_GFX_INDEX] = {
349 .ib_execute = &r100_ring_ib_execute,
350 .emit_fence = &r300_fence_ring_emit,
351 .emit_semaphore = &r100_semaphore_ring_emit,
352 .cs_parse = &r300_cs_parse,
353 .ring_start = &r300_ring_start,
354 .ring_test = &r100_ring_test,
355 .ib_test = &r100_ib_test,
356 .is_lockup = &r100_gpu_is_lockup,
357 .get_rptr = &radeon_ring_generic_get_rptr,
358 .get_wptr = &radeon_ring_generic_get_wptr,
359 .set_wptr = &radeon_ring_generic_set_wptr,
360 }
361 },
362 .irq = {
363 .set = &r100_irq_set,
364 .process = &r100_irq_process,
365 },
366 .display = {
367 .bandwidth_update = &r100_bandwidth_update,
368 .get_vblank_counter = &r100_get_vblank_counter,
369 .wait_for_vblank = &r100_wait_for_vblank,
370 .set_backlight_level = &radeon_legacy_set_backlight_level,
371 .get_backlight_level = &radeon_legacy_get_backlight_level,
372 },
373 .copy = {
374 .blit = &r100_copy_blit,
375 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
376 .dma = &r200_copy_dma,
377 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
378 .copy = &r100_copy_blit,
379 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
380 },
381 .surface = {
382 .set_reg = r100_set_surface_reg,
383 .clear_reg = r100_clear_surface_reg,
384 },
385 .hpd = {
386 .init = &r100_hpd_init,
387 .fini = &r100_hpd_fini,
388 .sense = &r100_hpd_sense,
389 .set_polarity = &r100_hpd_set_polarity,
390 },
391 .pm = {
392 .misc = &r100_pm_misc,
393 .prepare = &r100_pm_prepare,
394 .finish = &r100_pm_finish,
395 .init_profile = &r100_pm_init_profile,
396 .get_dynpm_state = &r100_pm_get_dynpm_state,
397 .get_engine_clock = &radeon_legacy_get_engine_clock,
398 .set_engine_clock = &radeon_legacy_set_engine_clock,
399 .get_memory_clock = &radeon_legacy_get_memory_clock,
400 .set_memory_clock = NULL,
401 .get_pcie_lanes = &rv370_get_pcie_lanes,
402 .set_pcie_lanes = &rv370_set_pcie_lanes,
403 .set_clock_gating = &radeon_legacy_set_clock_gating,
404 },
405 .pflip = {
406 .pre_page_flip = &r100_pre_page_flip,
407 .page_flip = &r100_page_flip,
408 .post_page_flip = &r100_post_page_flip,
409 },
410 };
411
412 static struct radeon_asic r300_asic_pcie = {
413 .init = &r300_init,
414 .fini = &r300_fini,
415 .suspend = &r300_suspend,
416 .resume = &r300_resume,
417 .vga_set_state = &r100_vga_set_state,
418 .asic_reset = &r300_asic_reset,
419 .ioctl_wait_idle = NULL,
420 .gui_idle = &r100_gui_idle,
421 .mc_wait_for_idle = &r300_mc_wait_for_idle,
422 .gart = {
423 .tlb_flush = &rv370_pcie_gart_tlb_flush,
424 .set_page = &rv370_pcie_gart_set_page,
425 },
426 .ring = {
427 [RADEON_RING_TYPE_GFX_INDEX] = {
428 .ib_execute = &r100_ring_ib_execute,
429 .emit_fence = &r300_fence_ring_emit,
430 .emit_semaphore = &r100_semaphore_ring_emit,
431 .cs_parse = &r300_cs_parse,
432 .ring_start = &r300_ring_start,
433 .ring_test = &r100_ring_test,
434 .ib_test = &r100_ib_test,
435 .is_lockup = &r100_gpu_is_lockup,
436 .get_rptr = &radeon_ring_generic_get_rptr,
437 .get_wptr = &radeon_ring_generic_get_wptr,
438 .set_wptr = &radeon_ring_generic_set_wptr,
439 }
440 },
441 .irq = {
442 .set = &r100_irq_set,
443 .process = &r100_irq_process,
444 },
445 .display = {
446 .bandwidth_update = &r100_bandwidth_update,
447 .get_vblank_counter = &r100_get_vblank_counter,
448 .wait_for_vblank = &r100_wait_for_vblank,
449 .set_backlight_level = &radeon_legacy_set_backlight_level,
450 .get_backlight_level = &radeon_legacy_get_backlight_level,
451 },
452 .copy = {
453 .blit = &r100_copy_blit,
454 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
455 .dma = &r200_copy_dma,
456 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
457 .copy = &r100_copy_blit,
458 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
459 },
460 .surface = {
461 .set_reg = r100_set_surface_reg,
462 .clear_reg = r100_clear_surface_reg,
463 },
464 .hpd = {
465 .init = &r100_hpd_init,
466 .fini = &r100_hpd_fini,
467 .sense = &r100_hpd_sense,
468 .set_polarity = &r100_hpd_set_polarity,
469 },
470 .pm = {
471 .misc = &r100_pm_misc,
472 .prepare = &r100_pm_prepare,
473 .finish = &r100_pm_finish,
474 .init_profile = &r100_pm_init_profile,
475 .get_dynpm_state = &r100_pm_get_dynpm_state,
476 .get_engine_clock = &radeon_legacy_get_engine_clock,
477 .set_engine_clock = &radeon_legacy_set_engine_clock,
478 .get_memory_clock = &radeon_legacy_get_memory_clock,
479 .set_memory_clock = NULL,
480 .get_pcie_lanes = &rv370_get_pcie_lanes,
481 .set_pcie_lanes = &rv370_set_pcie_lanes,
482 .set_clock_gating = &radeon_legacy_set_clock_gating,
483 },
484 .pflip = {
485 .pre_page_flip = &r100_pre_page_flip,
486 .page_flip = &r100_page_flip,
487 .post_page_flip = &r100_post_page_flip,
488 },
489 };
490
491 static struct radeon_asic r420_asic = {
492 .init = &r420_init,
493 .fini = &r420_fini,
494 .suspend = &r420_suspend,
495 .resume = &r420_resume,
496 .vga_set_state = &r100_vga_set_state,
497 .asic_reset = &r300_asic_reset,
498 .ioctl_wait_idle = NULL,
499 .gui_idle = &r100_gui_idle,
500 .mc_wait_for_idle = &r300_mc_wait_for_idle,
501 .gart = {
502 .tlb_flush = &rv370_pcie_gart_tlb_flush,
503 .set_page = &rv370_pcie_gart_set_page,
504 },
505 .ring = {
506 [RADEON_RING_TYPE_GFX_INDEX] = {
507 .ib_execute = &r100_ring_ib_execute,
508 .emit_fence = &r300_fence_ring_emit,
509 .emit_semaphore = &r100_semaphore_ring_emit,
510 .cs_parse = &r300_cs_parse,
511 .ring_start = &r300_ring_start,
512 .ring_test = &r100_ring_test,
513 .ib_test = &r100_ib_test,
514 .is_lockup = &r100_gpu_is_lockup,
515 .get_rptr = &radeon_ring_generic_get_rptr,
516 .get_wptr = &radeon_ring_generic_get_wptr,
517 .set_wptr = &radeon_ring_generic_set_wptr,
518 }
519 },
520 .irq = {
521 .set = &r100_irq_set,
522 .process = &r100_irq_process,
523 },
524 .display = {
525 .bandwidth_update = &r100_bandwidth_update,
526 .get_vblank_counter = &r100_get_vblank_counter,
527 .wait_for_vblank = &r100_wait_for_vblank,
528 .set_backlight_level = &atombios_set_backlight_level,
529 .get_backlight_level = &atombios_get_backlight_level,
530 },
531 .copy = {
532 .blit = &r100_copy_blit,
533 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
534 .dma = &r200_copy_dma,
535 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
536 .copy = &r100_copy_blit,
537 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
538 },
539 .surface = {
540 .set_reg = r100_set_surface_reg,
541 .clear_reg = r100_clear_surface_reg,
542 },
543 .hpd = {
544 .init = &r100_hpd_init,
545 .fini = &r100_hpd_fini,
546 .sense = &r100_hpd_sense,
547 .set_polarity = &r100_hpd_set_polarity,
548 },
549 .pm = {
550 .misc = &r100_pm_misc,
551 .prepare = &r100_pm_prepare,
552 .finish = &r100_pm_finish,
553 .init_profile = &r420_pm_init_profile,
554 .get_dynpm_state = &r100_pm_get_dynpm_state,
555 .get_engine_clock = &radeon_atom_get_engine_clock,
556 .set_engine_clock = &radeon_atom_set_engine_clock,
557 .get_memory_clock = &radeon_atom_get_memory_clock,
558 .set_memory_clock = &radeon_atom_set_memory_clock,
559 .get_pcie_lanes = &rv370_get_pcie_lanes,
560 .set_pcie_lanes = &rv370_set_pcie_lanes,
561 .set_clock_gating = &radeon_atom_set_clock_gating,
562 },
563 .pflip = {
564 .pre_page_flip = &r100_pre_page_flip,
565 .page_flip = &r100_page_flip,
566 .post_page_flip = &r100_post_page_flip,
567 },
568 };
569
570 static struct radeon_asic rs400_asic = {
571 .init = &rs400_init,
572 .fini = &rs400_fini,
573 .suspend = &rs400_suspend,
574 .resume = &rs400_resume,
575 .vga_set_state = &r100_vga_set_state,
576 .asic_reset = &r300_asic_reset,
577 .ioctl_wait_idle = NULL,
578 .gui_idle = &r100_gui_idle,
579 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
580 .gart = {
581 .tlb_flush = &rs400_gart_tlb_flush,
582 .set_page = &rs400_gart_set_page,
583 },
584 .ring = {
585 [RADEON_RING_TYPE_GFX_INDEX] = {
586 .ib_execute = &r100_ring_ib_execute,
587 .emit_fence = &r300_fence_ring_emit,
588 .emit_semaphore = &r100_semaphore_ring_emit,
589 .cs_parse = &r300_cs_parse,
590 .ring_start = &r300_ring_start,
591 .ring_test = &r100_ring_test,
592 .ib_test = &r100_ib_test,
593 .is_lockup = &r100_gpu_is_lockup,
594 .get_rptr = &radeon_ring_generic_get_rptr,
595 .get_wptr = &radeon_ring_generic_get_wptr,
596 .set_wptr = &radeon_ring_generic_set_wptr,
597 }
598 },
599 .irq = {
600 .set = &r100_irq_set,
601 .process = &r100_irq_process,
602 },
603 .display = {
604 .bandwidth_update = &r100_bandwidth_update,
605 .get_vblank_counter = &r100_get_vblank_counter,
606 .wait_for_vblank = &r100_wait_for_vblank,
607 .set_backlight_level = &radeon_legacy_set_backlight_level,
608 .get_backlight_level = &radeon_legacy_get_backlight_level,
609 },
610 .copy = {
611 .blit = &r100_copy_blit,
612 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
613 .dma = &r200_copy_dma,
614 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
615 .copy = &r100_copy_blit,
616 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
617 },
618 .surface = {
619 .set_reg = r100_set_surface_reg,
620 .clear_reg = r100_clear_surface_reg,
621 },
622 .hpd = {
623 .init = &r100_hpd_init,
624 .fini = &r100_hpd_fini,
625 .sense = &r100_hpd_sense,
626 .set_polarity = &r100_hpd_set_polarity,
627 },
628 .pm = {
629 .misc = &r100_pm_misc,
630 .prepare = &r100_pm_prepare,
631 .finish = &r100_pm_finish,
632 .init_profile = &r100_pm_init_profile,
633 .get_dynpm_state = &r100_pm_get_dynpm_state,
634 .get_engine_clock = &radeon_legacy_get_engine_clock,
635 .set_engine_clock = &radeon_legacy_set_engine_clock,
636 .get_memory_clock = &radeon_legacy_get_memory_clock,
637 .set_memory_clock = NULL,
638 .get_pcie_lanes = NULL,
639 .set_pcie_lanes = NULL,
640 .set_clock_gating = &radeon_legacy_set_clock_gating,
641 },
642 .pflip = {
643 .pre_page_flip = &r100_pre_page_flip,
644 .page_flip = &r100_page_flip,
645 .post_page_flip = &r100_post_page_flip,
646 },
647 };
648
649 static struct radeon_asic rs600_asic = {
650 .init = &rs600_init,
651 .fini = &rs600_fini,
652 .suspend = &rs600_suspend,
653 .resume = &rs600_resume,
654 .vga_set_state = &r100_vga_set_state,
655 .asic_reset = &rs600_asic_reset,
656 .ioctl_wait_idle = NULL,
657 .gui_idle = &r100_gui_idle,
658 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
659 .gart = {
660 .tlb_flush = &rs600_gart_tlb_flush,
661 .set_page = &rs600_gart_set_page,
662 },
663 .ring = {
664 [RADEON_RING_TYPE_GFX_INDEX] = {
665 .ib_execute = &r100_ring_ib_execute,
666 .emit_fence = &r300_fence_ring_emit,
667 .emit_semaphore = &r100_semaphore_ring_emit,
668 .cs_parse = &r300_cs_parse,
669 .ring_start = &r300_ring_start,
670 .ring_test = &r100_ring_test,
671 .ib_test = &r100_ib_test,
672 .is_lockup = &r100_gpu_is_lockup,
673 .get_rptr = &radeon_ring_generic_get_rptr,
674 .get_wptr = &radeon_ring_generic_get_wptr,
675 .set_wptr = &radeon_ring_generic_set_wptr,
676 }
677 },
678 .irq = {
679 .set = &rs600_irq_set,
680 .process = &rs600_irq_process,
681 },
682 .display = {
683 .bandwidth_update = &rs600_bandwidth_update,
684 .get_vblank_counter = &rs600_get_vblank_counter,
685 .wait_for_vblank = &avivo_wait_for_vblank,
686 .set_backlight_level = &atombios_set_backlight_level,
687 .get_backlight_level = &atombios_get_backlight_level,
688 .hdmi_enable = &r600_hdmi_enable,
689 .hdmi_setmode = &r600_hdmi_setmode,
690 },
691 .copy = {
692 .blit = &r100_copy_blit,
693 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
694 .dma = &r200_copy_dma,
695 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
696 .copy = &r100_copy_blit,
697 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
698 },
699 .surface = {
700 .set_reg = r100_set_surface_reg,
701 .clear_reg = r100_clear_surface_reg,
702 },
703 .hpd = {
704 .init = &rs600_hpd_init,
705 .fini = &rs600_hpd_fini,
706 .sense = &rs600_hpd_sense,
707 .set_polarity = &rs600_hpd_set_polarity,
708 },
709 .pm = {
710 .misc = &rs600_pm_misc,
711 .prepare = &rs600_pm_prepare,
712 .finish = &rs600_pm_finish,
713 .init_profile = &r420_pm_init_profile,
714 .get_dynpm_state = &r100_pm_get_dynpm_state,
715 .get_engine_clock = &radeon_atom_get_engine_clock,
716 .set_engine_clock = &radeon_atom_set_engine_clock,
717 .get_memory_clock = &radeon_atom_get_memory_clock,
718 .set_memory_clock = &radeon_atom_set_memory_clock,
719 .get_pcie_lanes = NULL,
720 .set_pcie_lanes = NULL,
721 .set_clock_gating = &radeon_atom_set_clock_gating,
722 },
723 .pflip = {
724 .pre_page_flip = &rs600_pre_page_flip,
725 .page_flip = &rs600_page_flip,
726 .post_page_flip = &rs600_post_page_flip,
727 },
728 };
729
730 static struct radeon_asic rs690_asic = {
731 .init = &rs690_init,
732 .fini = &rs690_fini,
733 .suspend = &rs690_suspend,
734 .resume = &rs690_resume,
735 .vga_set_state = &r100_vga_set_state,
736 .asic_reset = &rs600_asic_reset,
737 .ioctl_wait_idle = NULL,
738 .gui_idle = &r100_gui_idle,
739 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
740 .gart = {
741 .tlb_flush = &rs400_gart_tlb_flush,
742 .set_page = &rs400_gart_set_page,
743 },
744 .ring = {
745 [RADEON_RING_TYPE_GFX_INDEX] = {
746 .ib_execute = &r100_ring_ib_execute,
747 .emit_fence = &r300_fence_ring_emit,
748 .emit_semaphore = &r100_semaphore_ring_emit,
749 .cs_parse = &r300_cs_parse,
750 .ring_start = &r300_ring_start,
751 .ring_test = &r100_ring_test,
752 .ib_test = &r100_ib_test,
753 .is_lockup = &r100_gpu_is_lockup,
754 .get_rptr = &radeon_ring_generic_get_rptr,
755 .get_wptr = &radeon_ring_generic_get_wptr,
756 .set_wptr = &radeon_ring_generic_set_wptr,
757 }
758 },
759 .irq = {
760 .set = &rs600_irq_set,
761 .process = &rs600_irq_process,
762 },
763 .display = {
764 .get_vblank_counter = &rs600_get_vblank_counter,
765 .bandwidth_update = &rs690_bandwidth_update,
766 .wait_for_vblank = &avivo_wait_for_vblank,
767 .set_backlight_level = &atombios_set_backlight_level,
768 .get_backlight_level = &atombios_get_backlight_level,
769 .hdmi_enable = &r600_hdmi_enable,
770 .hdmi_setmode = &r600_hdmi_setmode,
771 },
772 .copy = {
773 .blit = &r100_copy_blit,
774 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
775 .dma = &r200_copy_dma,
776 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
777 .copy = &r200_copy_dma,
778 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
779 },
780 .surface = {
781 .set_reg = r100_set_surface_reg,
782 .clear_reg = r100_clear_surface_reg,
783 },
784 .hpd = {
785 .init = &rs600_hpd_init,
786 .fini = &rs600_hpd_fini,
787 .sense = &rs600_hpd_sense,
788 .set_polarity = &rs600_hpd_set_polarity,
789 },
790 .pm = {
791 .misc = &rs600_pm_misc,
792 .prepare = &rs600_pm_prepare,
793 .finish = &rs600_pm_finish,
794 .init_profile = &r420_pm_init_profile,
795 .get_dynpm_state = &r100_pm_get_dynpm_state,
796 .get_engine_clock = &radeon_atom_get_engine_clock,
797 .set_engine_clock = &radeon_atom_set_engine_clock,
798 .get_memory_clock = &radeon_atom_get_memory_clock,
799 .set_memory_clock = &radeon_atom_set_memory_clock,
800 .get_pcie_lanes = NULL,
801 .set_pcie_lanes = NULL,
802 .set_clock_gating = &radeon_atom_set_clock_gating,
803 },
804 .pflip = {
805 .pre_page_flip = &rs600_pre_page_flip,
806 .page_flip = &rs600_page_flip,
807 .post_page_flip = &rs600_post_page_flip,
808 },
809 };
810
811 static struct radeon_asic rv515_asic = {
812 .init = &rv515_init,
813 .fini = &rv515_fini,
814 .suspend = &rv515_suspend,
815 .resume = &rv515_resume,
816 .vga_set_state = &r100_vga_set_state,
817 .asic_reset = &rs600_asic_reset,
818 .ioctl_wait_idle = NULL,
819 .gui_idle = &r100_gui_idle,
820 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
821 .gart = {
822 .tlb_flush = &rv370_pcie_gart_tlb_flush,
823 .set_page = &rv370_pcie_gart_set_page,
824 },
825 .ring = {
826 [RADEON_RING_TYPE_GFX_INDEX] = {
827 .ib_execute = &r100_ring_ib_execute,
828 .emit_fence = &r300_fence_ring_emit,
829 .emit_semaphore = &r100_semaphore_ring_emit,
830 .cs_parse = &r300_cs_parse,
831 .ring_start = &rv515_ring_start,
832 .ring_test = &r100_ring_test,
833 .ib_test = &r100_ib_test,
834 .is_lockup = &r100_gpu_is_lockup,
835 .get_rptr = &radeon_ring_generic_get_rptr,
836 .get_wptr = &radeon_ring_generic_get_wptr,
837 .set_wptr = &radeon_ring_generic_set_wptr,
838 }
839 },
840 .irq = {
841 .set = &rs600_irq_set,
842 .process = &rs600_irq_process,
843 },
844 .display = {
845 .get_vblank_counter = &rs600_get_vblank_counter,
846 .bandwidth_update = &rv515_bandwidth_update,
847 .wait_for_vblank = &avivo_wait_for_vblank,
848 .set_backlight_level = &atombios_set_backlight_level,
849 .get_backlight_level = &atombios_get_backlight_level,
850 },
851 .copy = {
852 .blit = &r100_copy_blit,
853 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
854 .dma = &r200_copy_dma,
855 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
856 .copy = &r100_copy_blit,
857 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
858 },
859 .surface = {
860 .set_reg = r100_set_surface_reg,
861 .clear_reg = r100_clear_surface_reg,
862 },
863 .hpd = {
864 .init = &rs600_hpd_init,
865 .fini = &rs600_hpd_fini,
866 .sense = &rs600_hpd_sense,
867 .set_polarity = &rs600_hpd_set_polarity,
868 },
869 .pm = {
870 .misc = &rs600_pm_misc,
871 .prepare = &rs600_pm_prepare,
872 .finish = &rs600_pm_finish,
873 .init_profile = &r420_pm_init_profile,
874 .get_dynpm_state = &r100_pm_get_dynpm_state,
875 .get_engine_clock = &radeon_atom_get_engine_clock,
876 .set_engine_clock = &radeon_atom_set_engine_clock,
877 .get_memory_clock = &radeon_atom_get_memory_clock,
878 .set_memory_clock = &radeon_atom_set_memory_clock,
879 .get_pcie_lanes = &rv370_get_pcie_lanes,
880 .set_pcie_lanes = &rv370_set_pcie_lanes,
881 .set_clock_gating = &radeon_atom_set_clock_gating,
882 },
883 .pflip = {
884 .pre_page_flip = &rs600_pre_page_flip,
885 .page_flip = &rs600_page_flip,
886 .post_page_flip = &rs600_post_page_flip,
887 },
888 };
889
890 static struct radeon_asic r520_asic = {
891 .init = &r520_init,
892 .fini = &rv515_fini,
893 .suspend = &rv515_suspend,
894 .resume = &r520_resume,
895 .vga_set_state = &r100_vga_set_state,
896 .asic_reset = &rs600_asic_reset,
897 .ioctl_wait_idle = NULL,
898 .gui_idle = &r100_gui_idle,
899 .mc_wait_for_idle = &r520_mc_wait_for_idle,
900 .gart = {
901 .tlb_flush = &rv370_pcie_gart_tlb_flush,
902 .set_page = &rv370_pcie_gart_set_page,
903 },
904 .ring = {
905 [RADEON_RING_TYPE_GFX_INDEX] = {
906 .ib_execute = &r100_ring_ib_execute,
907 .emit_fence = &r300_fence_ring_emit,
908 .emit_semaphore = &r100_semaphore_ring_emit,
909 .cs_parse = &r300_cs_parse,
910 .ring_start = &rv515_ring_start,
911 .ring_test = &r100_ring_test,
912 .ib_test = &r100_ib_test,
913 .is_lockup = &r100_gpu_is_lockup,
914 .get_rptr = &radeon_ring_generic_get_rptr,
915 .get_wptr = &radeon_ring_generic_get_wptr,
916 .set_wptr = &radeon_ring_generic_set_wptr,
917 }
918 },
919 .irq = {
920 .set = &rs600_irq_set,
921 .process = &rs600_irq_process,
922 },
923 .display = {
924 .bandwidth_update = &rv515_bandwidth_update,
925 .get_vblank_counter = &rs600_get_vblank_counter,
926 .wait_for_vblank = &avivo_wait_for_vblank,
927 .set_backlight_level = &atombios_set_backlight_level,
928 .get_backlight_level = &atombios_get_backlight_level,
929 },
930 .copy = {
931 .blit = &r100_copy_blit,
932 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
933 .dma = &r200_copy_dma,
934 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
935 .copy = &r100_copy_blit,
936 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
937 },
938 .surface = {
939 .set_reg = r100_set_surface_reg,
940 .clear_reg = r100_clear_surface_reg,
941 },
942 .hpd = {
943 .init = &rs600_hpd_init,
944 .fini = &rs600_hpd_fini,
945 .sense = &rs600_hpd_sense,
946 .set_polarity = &rs600_hpd_set_polarity,
947 },
948 .pm = {
949 .misc = &rs600_pm_misc,
950 .prepare = &rs600_pm_prepare,
951 .finish = &rs600_pm_finish,
952 .init_profile = &r420_pm_init_profile,
953 .get_dynpm_state = &r100_pm_get_dynpm_state,
954 .get_engine_clock = &radeon_atom_get_engine_clock,
955 .set_engine_clock = &radeon_atom_set_engine_clock,
956 .get_memory_clock = &radeon_atom_get_memory_clock,
957 .set_memory_clock = &radeon_atom_set_memory_clock,
958 .get_pcie_lanes = &rv370_get_pcie_lanes,
959 .set_pcie_lanes = &rv370_set_pcie_lanes,
960 .set_clock_gating = &radeon_atom_set_clock_gating,
961 },
962 .pflip = {
963 .pre_page_flip = &rs600_pre_page_flip,
964 .page_flip = &rs600_page_flip,
965 .post_page_flip = &rs600_post_page_flip,
966 },
967 };
968
969 static struct radeon_asic r600_asic = {
970 .init = &r600_init,
971 .fini = &r600_fini,
972 .suspend = &r600_suspend,
973 .resume = &r600_resume,
974 .vga_set_state = &r600_vga_set_state,
975 .asic_reset = &r600_asic_reset,
976 .ioctl_wait_idle = r600_ioctl_wait_idle,
977 .gui_idle = &r600_gui_idle,
978 .mc_wait_for_idle = &r600_mc_wait_for_idle,
979 .get_xclk = &r600_get_xclk,
980 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
981 .gart = {
982 .tlb_flush = &r600_pcie_gart_tlb_flush,
983 .set_page = &rs600_gart_set_page,
984 },
985 .ring = {
986 [RADEON_RING_TYPE_GFX_INDEX] = {
987 .ib_execute = &r600_ring_ib_execute,
988 .emit_fence = &r600_fence_ring_emit,
989 .emit_semaphore = &r600_semaphore_ring_emit,
990 .cs_parse = &r600_cs_parse,
991 .ring_test = &r600_ring_test,
992 .ib_test = &r600_ib_test,
993 .is_lockup = &r600_gfx_is_lockup,
994 .get_rptr = &radeon_ring_generic_get_rptr,
995 .get_wptr = &radeon_ring_generic_get_wptr,
996 .set_wptr = &radeon_ring_generic_set_wptr,
997 },
998 [R600_RING_TYPE_DMA_INDEX] = {
999 .ib_execute = &r600_dma_ring_ib_execute,
1000 .emit_fence = &r600_dma_fence_ring_emit,
1001 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1002 .cs_parse = &r600_dma_cs_parse,
1003 .ring_test = &r600_dma_ring_test,
1004 .ib_test = &r600_dma_ib_test,
1005 .is_lockup = &r600_dma_is_lockup,
1006 .get_rptr = &radeon_ring_generic_get_rptr,
1007 .get_wptr = &radeon_ring_generic_get_wptr,
1008 .set_wptr = &radeon_ring_generic_set_wptr,
1009 }
1010 },
1011 .irq = {
1012 .set = &r600_irq_set,
1013 .process = &r600_irq_process,
1014 },
1015 .display = {
1016 .bandwidth_update = &rv515_bandwidth_update,
1017 .get_vblank_counter = &rs600_get_vblank_counter,
1018 .wait_for_vblank = &avivo_wait_for_vblank,
1019 .set_backlight_level = &atombios_set_backlight_level,
1020 .get_backlight_level = &atombios_get_backlight_level,
1021 .hdmi_enable = &r600_hdmi_enable,
1022 .hdmi_setmode = &r600_hdmi_setmode,
1023 },
1024 .copy = {
1025 .blit = &r600_copy_blit,
1026 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1027 .dma = &r600_copy_dma,
1028 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1029 .copy = &r600_copy_dma,
1030 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1031 },
1032 .surface = {
1033 .set_reg = r600_set_surface_reg,
1034 .clear_reg = r600_clear_surface_reg,
1035 },
1036 .hpd = {
1037 .init = &r600_hpd_init,
1038 .fini = &r600_hpd_fini,
1039 .sense = &r600_hpd_sense,
1040 .set_polarity = &r600_hpd_set_polarity,
1041 },
1042 .pm = {
1043 .misc = &r600_pm_misc,
1044 .prepare = &rs600_pm_prepare,
1045 .finish = &rs600_pm_finish,
1046 .init_profile = &r600_pm_init_profile,
1047 .get_dynpm_state = &r600_pm_get_dynpm_state,
1048 .get_engine_clock = &radeon_atom_get_engine_clock,
1049 .set_engine_clock = &radeon_atom_set_engine_clock,
1050 .get_memory_clock = &radeon_atom_get_memory_clock,
1051 .set_memory_clock = &radeon_atom_set_memory_clock,
1052 .get_pcie_lanes = &r600_get_pcie_lanes,
1053 .set_pcie_lanes = &r600_set_pcie_lanes,
1054 .set_clock_gating = NULL,
1055 .get_temperature = &rv6xx_get_temp,
1056 },
1057 .pflip = {
1058 .pre_page_flip = &rs600_pre_page_flip,
1059 .page_flip = &rs600_page_flip,
1060 .post_page_flip = &rs600_post_page_flip,
1061 },
1062 };
1063
1064 static struct radeon_asic rv6xx_asic = {
1065 .init = &r600_init,
1066 .fini = &r600_fini,
1067 .suspend = &r600_suspend,
1068 .resume = &r600_resume,
1069 .vga_set_state = &r600_vga_set_state,
1070 .asic_reset = &r600_asic_reset,
1071 .ioctl_wait_idle = r600_ioctl_wait_idle,
1072 .gui_idle = &r600_gui_idle,
1073 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1074 .get_xclk = &r600_get_xclk,
1075 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1076 .gart = {
1077 .tlb_flush = &r600_pcie_gart_tlb_flush,
1078 .set_page = &rs600_gart_set_page,
1079 },
1080 .ring = {
1081 [RADEON_RING_TYPE_GFX_INDEX] = {
1082 .ib_execute = &r600_ring_ib_execute,
1083 .emit_fence = &r600_fence_ring_emit,
1084 .emit_semaphore = &r600_semaphore_ring_emit,
1085 .cs_parse = &r600_cs_parse,
1086 .ring_test = &r600_ring_test,
1087 .ib_test = &r600_ib_test,
1088 .is_lockup = &r600_gfx_is_lockup,
1089 .get_rptr = &radeon_ring_generic_get_rptr,
1090 .get_wptr = &radeon_ring_generic_get_wptr,
1091 .set_wptr = &radeon_ring_generic_set_wptr,
1092 },
1093 [R600_RING_TYPE_DMA_INDEX] = {
1094 .ib_execute = &r600_dma_ring_ib_execute,
1095 .emit_fence = &r600_dma_fence_ring_emit,
1096 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1097 .cs_parse = &r600_dma_cs_parse,
1098 .ring_test = &r600_dma_ring_test,
1099 .ib_test = &r600_dma_ib_test,
1100 .is_lockup = &r600_dma_is_lockup,
1101 .get_rptr = &radeon_ring_generic_get_rptr,
1102 .get_wptr = &radeon_ring_generic_get_wptr,
1103 .set_wptr = &radeon_ring_generic_set_wptr,
1104 }
1105 },
1106 .irq = {
1107 .set = &r600_irq_set,
1108 .process = &r600_irq_process,
1109 },
1110 .display = {
1111 .bandwidth_update = &rv515_bandwidth_update,
1112 .get_vblank_counter = &rs600_get_vblank_counter,
1113 .wait_for_vblank = &avivo_wait_for_vblank,
1114 .set_backlight_level = &atombios_set_backlight_level,
1115 .get_backlight_level = &atombios_get_backlight_level,
1116 },
1117 .copy = {
1118 .blit = &r600_copy_blit,
1119 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1120 .dma = &r600_copy_dma,
1121 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1122 .copy = &r600_copy_dma,
1123 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1124 },
1125 .surface = {
1126 .set_reg = r600_set_surface_reg,
1127 .clear_reg = r600_clear_surface_reg,
1128 },
1129 .hpd = {
1130 .init = &r600_hpd_init,
1131 .fini = &r600_hpd_fini,
1132 .sense = &r600_hpd_sense,
1133 .set_polarity = &r600_hpd_set_polarity,
1134 },
1135 .pm = {
1136 .misc = &r600_pm_misc,
1137 .prepare = &rs600_pm_prepare,
1138 .finish = &rs600_pm_finish,
1139 .init_profile = &r600_pm_init_profile,
1140 .get_dynpm_state = &r600_pm_get_dynpm_state,
1141 .get_engine_clock = &radeon_atom_get_engine_clock,
1142 .set_engine_clock = &radeon_atom_set_engine_clock,
1143 .get_memory_clock = &radeon_atom_get_memory_clock,
1144 .set_memory_clock = &radeon_atom_set_memory_clock,
1145 .get_pcie_lanes = &r600_get_pcie_lanes,
1146 .set_pcie_lanes = &r600_set_pcie_lanes,
1147 .set_clock_gating = NULL,
1148 .get_temperature = &rv6xx_get_temp,
1149 },
1150 .dpm = {
1151 .init = &rv6xx_dpm_init,
1152 .setup_asic = &rv6xx_setup_asic,
1153 .enable = &rv6xx_dpm_enable,
1154 .disable = &rv6xx_dpm_disable,
1155 .set_power_state = &rv6xx_dpm_set_power_state,
1156 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1157 .fini = &rv6xx_dpm_fini,
1158 .get_sclk = &rv6xx_dpm_get_sclk,
1159 .get_mclk = &rv6xx_dpm_get_mclk,
1160 .print_power_state = &rv6xx_dpm_print_power_state,
1161 },
1162 .pflip = {
1163 .pre_page_flip = &rs600_pre_page_flip,
1164 .page_flip = &rs600_page_flip,
1165 .post_page_flip = &rs600_post_page_flip,
1166 },
1167 };
1168
1169 static struct radeon_asic rs780_asic = {
1170 .init = &r600_init,
1171 .fini = &r600_fini,
1172 .suspend = &r600_suspend,
1173 .resume = &r600_resume,
1174 .vga_set_state = &r600_vga_set_state,
1175 .asic_reset = &r600_asic_reset,
1176 .ioctl_wait_idle = r600_ioctl_wait_idle,
1177 .gui_idle = &r600_gui_idle,
1178 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1179 .get_xclk = &r600_get_xclk,
1180 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1181 .gart = {
1182 .tlb_flush = &r600_pcie_gart_tlb_flush,
1183 .set_page = &rs600_gart_set_page,
1184 },
1185 .ring = {
1186 [RADEON_RING_TYPE_GFX_INDEX] = {
1187 .ib_execute = &r600_ring_ib_execute,
1188 .emit_fence = &r600_fence_ring_emit,
1189 .emit_semaphore = &r600_semaphore_ring_emit,
1190 .cs_parse = &r600_cs_parse,
1191 .ring_test = &r600_ring_test,
1192 .ib_test = &r600_ib_test,
1193 .is_lockup = &r600_gfx_is_lockup,
1194 .get_rptr = &radeon_ring_generic_get_rptr,
1195 .get_wptr = &radeon_ring_generic_get_wptr,
1196 .set_wptr = &radeon_ring_generic_set_wptr,
1197 },
1198 [R600_RING_TYPE_DMA_INDEX] = {
1199 .ib_execute = &r600_dma_ring_ib_execute,
1200 .emit_fence = &r600_dma_fence_ring_emit,
1201 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1202 .cs_parse = &r600_dma_cs_parse,
1203 .ring_test = &r600_dma_ring_test,
1204 .ib_test = &r600_dma_ib_test,
1205 .is_lockup = &r600_dma_is_lockup,
1206 .get_rptr = &radeon_ring_generic_get_rptr,
1207 .get_wptr = &radeon_ring_generic_get_wptr,
1208 .set_wptr = &radeon_ring_generic_set_wptr,
1209 }
1210 },
1211 .irq = {
1212 .set = &r600_irq_set,
1213 .process = &r600_irq_process,
1214 },
1215 .display = {
1216 .bandwidth_update = &rs690_bandwidth_update,
1217 .get_vblank_counter = &rs600_get_vblank_counter,
1218 .wait_for_vblank = &avivo_wait_for_vblank,
1219 .set_backlight_level = &atombios_set_backlight_level,
1220 .get_backlight_level = &atombios_get_backlight_level,
1221 .hdmi_enable = &r600_hdmi_enable,
1222 .hdmi_setmode = &r600_hdmi_setmode,
1223 },
1224 .copy = {
1225 .blit = &r600_copy_blit,
1226 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1227 .dma = &r600_copy_dma,
1228 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1229 .copy = &r600_copy_dma,
1230 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1231 },
1232 .surface = {
1233 .set_reg = r600_set_surface_reg,
1234 .clear_reg = r600_clear_surface_reg,
1235 },
1236 .hpd = {
1237 .init = &r600_hpd_init,
1238 .fini = &r600_hpd_fini,
1239 .sense = &r600_hpd_sense,
1240 .set_polarity = &r600_hpd_set_polarity,
1241 },
1242 .pm = {
1243 .misc = &r600_pm_misc,
1244 .prepare = &rs600_pm_prepare,
1245 .finish = &rs600_pm_finish,
1246 .init_profile = &rs780_pm_init_profile,
1247 .get_dynpm_state = &r600_pm_get_dynpm_state,
1248 .get_engine_clock = &radeon_atom_get_engine_clock,
1249 .set_engine_clock = &radeon_atom_set_engine_clock,
1250 .get_memory_clock = NULL,
1251 .set_memory_clock = NULL,
1252 .get_pcie_lanes = NULL,
1253 .set_pcie_lanes = NULL,
1254 .set_clock_gating = NULL,
1255 .get_temperature = &rv6xx_get_temp,
1256 },
1257 .dpm = {
1258 .init = &rs780_dpm_init,
1259 .setup_asic = &rs780_dpm_setup_asic,
1260 .enable = &rs780_dpm_enable,
1261 .disable = &rs780_dpm_disable,
1262 .set_power_state = &rs780_dpm_set_power_state,
1263 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1264 .fini = &rs780_dpm_fini,
1265 .get_sclk = &rs780_dpm_get_sclk,
1266 .get_mclk = &rs780_dpm_get_mclk,
1267 .print_power_state = &rs780_dpm_print_power_state,
1268 },
1269 .pflip = {
1270 .pre_page_flip = &rs600_pre_page_flip,
1271 .page_flip = &rs600_page_flip,
1272 .post_page_flip = &rs600_post_page_flip,
1273 },
1274 };
1275
1276 static struct radeon_asic rv770_asic = {
1277 .init = &rv770_init,
1278 .fini = &rv770_fini,
1279 .suspend = &rv770_suspend,
1280 .resume = &rv770_resume,
1281 .asic_reset = &r600_asic_reset,
1282 .vga_set_state = &r600_vga_set_state,
1283 .ioctl_wait_idle = r600_ioctl_wait_idle,
1284 .gui_idle = &r600_gui_idle,
1285 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1286 .get_xclk = &rv770_get_xclk,
1287 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1288 .gart = {
1289 .tlb_flush = &r600_pcie_gart_tlb_flush,
1290 .set_page = &rs600_gart_set_page,
1291 },
1292 .ring = {
1293 [RADEON_RING_TYPE_GFX_INDEX] = {
1294 .ib_execute = &r600_ring_ib_execute,
1295 .emit_fence = &r600_fence_ring_emit,
1296 .emit_semaphore = &r600_semaphore_ring_emit,
1297 .cs_parse = &r600_cs_parse,
1298 .ring_test = &r600_ring_test,
1299 .ib_test = &r600_ib_test,
1300 .is_lockup = &r600_gfx_is_lockup,
1301 .get_rptr = &radeon_ring_generic_get_rptr,
1302 .get_wptr = &radeon_ring_generic_get_wptr,
1303 .set_wptr = &radeon_ring_generic_set_wptr,
1304 },
1305 [R600_RING_TYPE_DMA_INDEX] = {
1306 .ib_execute = &r600_dma_ring_ib_execute,
1307 .emit_fence = &r600_dma_fence_ring_emit,
1308 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1309 .cs_parse = &r600_dma_cs_parse,
1310 .ring_test = &r600_dma_ring_test,
1311 .ib_test = &r600_dma_ib_test,
1312 .is_lockup = &r600_dma_is_lockup,
1313 .get_rptr = &radeon_ring_generic_get_rptr,
1314 .get_wptr = &radeon_ring_generic_get_wptr,
1315 .set_wptr = &radeon_ring_generic_set_wptr,
1316 },
1317 [R600_RING_TYPE_UVD_INDEX] = {
1318 .ib_execute = &r600_uvd_ib_execute,
1319 .emit_fence = &r600_uvd_fence_emit,
1320 .emit_semaphore = &r600_uvd_semaphore_emit,
1321 .cs_parse = &radeon_uvd_cs_parse,
1322 .ring_test = &r600_uvd_ring_test,
1323 .ib_test = &r600_uvd_ib_test,
1324 .is_lockup = &radeon_ring_test_lockup,
1325 .get_rptr = &radeon_ring_generic_get_rptr,
1326 .get_wptr = &radeon_ring_generic_get_wptr,
1327 .set_wptr = &radeon_ring_generic_set_wptr,
1328 }
1329 },
1330 .irq = {
1331 .set = &r600_irq_set,
1332 .process = &r600_irq_process,
1333 },
1334 .display = {
1335 .bandwidth_update = &rv515_bandwidth_update,
1336 .get_vblank_counter = &rs600_get_vblank_counter,
1337 .wait_for_vblank = &avivo_wait_for_vblank,
1338 .set_backlight_level = &atombios_set_backlight_level,
1339 .get_backlight_level = &atombios_get_backlight_level,
1340 .hdmi_enable = &r600_hdmi_enable,
1341 .hdmi_setmode = &r600_hdmi_setmode,
1342 },
1343 .copy = {
1344 .blit = &r600_copy_blit,
1345 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1346 .dma = &rv770_copy_dma,
1347 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1348 .copy = &rv770_copy_dma,
1349 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1350 },
1351 .surface = {
1352 .set_reg = r600_set_surface_reg,
1353 .clear_reg = r600_clear_surface_reg,
1354 },
1355 .hpd = {
1356 .init = &r600_hpd_init,
1357 .fini = &r600_hpd_fini,
1358 .sense = &r600_hpd_sense,
1359 .set_polarity = &r600_hpd_set_polarity,
1360 },
1361 .pm = {
1362 .misc = &rv770_pm_misc,
1363 .prepare = &rs600_pm_prepare,
1364 .finish = &rs600_pm_finish,
1365 .init_profile = &r600_pm_init_profile,
1366 .get_dynpm_state = &r600_pm_get_dynpm_state,
1367 .get_engine_clock = &radeon_atom_get_engine_clock,
1368 .set_engine_clock = &radeon_atom_set_engine_clock,
1369 .get_memory_clock = &radeon_atom_get_memory_clock,
1370 .set_memory_clock = &radeon_atom_set_memory_clock,
1371 .get_pcie_lanes = &r600_get_pcie_lanes,
1372 .set_pcie_lanes = &r600_set_pcie_lanes,
1373 .set_clock_gating = &radeon_atom_set_clock_gating,
1374 .set_uvd_clocks = &rv770_set_uvd_clocks,
1375 .get_temperature = &rv770_get_temp,
1376 },
1377 .pflip = {
1378 .pre_page_flip = &rs600_pre_page_flip,
1379 .page_flip = &rv770_page_flip,
1380 .post_page_flip = &rs600_post_page_flip,
1381 },
1382 };
1383
1384 static struct radeon_asic evergreen_asic = {
1385 .init = &evergreen_init,
1386 .fini = &evergreen_fini,
1387 .suspend = &evergreen_suspend,
1388 .resume = &evergreen_resume,
1389 .asic_reset = &evergreen_asic_reset,
1390 .vga_set_state = &r600_vga_set_state,
1391 .ioctl_wait_idle = r600_ioctl_wait_idle,
1392 .gui_idle = &r600_gui_idle,
1393 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1394 .get_xclk = &rv770_get_xclk,
1395 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1396 .gart = {
1397 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1398 .set_page = &rs600_gart_set_page,
1399 },
1400 .ring = {
1401 [RADEON_RING_TYPE_GFX_INDEX] = {
1402 .ib_execute = &evergreen_ring_ib_execute,
1403 .emit_fence = &r600_fence_ring_emit,
1404 .emit_semaphore = &r600_semaphore_ring_emit,
1405 .cs_parse = &evergreen_cs_parse,
1406 .ring_test = &r600_ring_test,
1407 .ib_test = &r600_ib_test,
1408 .is_lockup = &evergreen_gfx_is_lockup,
1409 .get_rptr = &radeon_ring_generic_get_rptr,
1410 .get_wptr = &radeon_ring_generic_get_wptr,
1411 .set_wptr = &radeon_ring_generic_set_wptr,
1412 },
1413 [R600_RING_TYPE_DMA_INDEX] = {
1414 .ib_execute = &evergreen_dma_ring_ib_execute,
1415 .emit_fence = &evergreen_dma_fence_ring_emit,
1416 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1417 .cs_parse = &evergreen_dma_cs_parse,
1418 .ring_test = &r600_dma_ring_test,
1419 .ib_test = &r600_dma_ib_test,
1420 .is_lockup = &evergreen_dma_is_lockup,
1421 .get_rptr = &radeon_ring_generic_get_rptr,
1422 .get_wptr = &radeon_ring_generic_get_wptr,
1423 .set_wptr = &radeon_ring_generic_set_wptr,
1424 },
1425 [R600_RING_TYPE_UVD_INDEX] = {
1426 .ib_execute = &r600_uvd_ib_execute,
1427 .emit_fence = &r600_uvd_fence_emit,
1428 .emit_semaphore = &r600_uvd_semaphore_emit,
1429 .cs_parse = &radeon_uvd_cs_parse,
1430 .ring_test = &r600_uvd_ring_test,
1431 .ib_test = &r600_uvd_ib_test,
1432 .is_lockup = &radeon_ring_test_lockup,
1433 .get_rptr = &radeon_ring_generic_get_rptr,
1434 .get_wptr = &radeon_ring_generic_get_wptr,
1435 .set_wptr = &radeon_ring_generic_set_wptr,
1436 }
1437 },
1438 .irq = {
1439 .set = &evergreen_irq_set,
1440 .process = &evergreen_irq_process,
1441 },
1442 .display = {
1443 .bandwidth_update = &evergreen_bandwidth_update,
1444 .get_vblank_counter = &evergreen_get_vblank_counter,
1445 .wait_for_vblank = &dce4_wait_for_vblank,
1446 .set_backlight_level = &atombios_set_backlight_level,
1447 .get_backlight_level = &atombios_get_backlight_level,
1448 .hdmi_enable = &evergreen_hdmi_enable,
1449 .hdmi_setmode = &evergreen_hdmi_setmode,
1450 },
1451 .copy = {
1452 .blit = &r600_copy_blit,
1453 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1454 .dma = &evergreen_copy_dma,
1455 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1456 .copy = &evergreen_copy_dma,
1457 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1458 },
1459 .surface = {
1460 .set_reg = r600_set_surface_reg,
1461 .clear_reg = r600_clear_surface_reg,
1462 },
1463 .hpd = {
1464 .init = &evergreen_hpd_init,
1465 .fini = &evergreen_hpd_fini,
1466 .sense = &evergreen_hpd_sense,
1467 .set_polarity = &evergreen_hpd_set_polarity,
1468 },
1469 .pm = {
1470 .misc = &evergreen_pm_misc,
1471 .prepare = &evergreen_pm_prepare,
1472 .finish = &evergreen_pm_finish,
1473 .init_profile = &r600_pm_init_profile,
1474 .get_dynpm_state = &r600_pm_get_dynpm_state,
1475 .get_engine_clock = &radeon_atom_get_engine_clock,
1476 .set_engine_clock = &radeon_atom_set_engine_clock,
1477 .get_memory_clock = &radeon_atom_get_memory_clock,
1478 .set_memory_clock = &radeon_atom_set_memory_clock,
1479 .get_pcie_lanes = &r600_get_pcie_lanes,
1480 .set_pcie_lanes = &r600_set_pcie_lanes,
1481 .set_clock_gating = NULL,
1482 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1483 .get_temperature = &evergreen_get_temp,
1484 },
1485 .pflip = {
1486 .pre_page_flip = &evergreen_pre_page_flip,
1487 .page_flip = &evergreen_page_flip,
1488 .post_page_flip = &evergreen_post_page_flip,
1489 },
1490 };
1491
1492 static struct radeon_asic sumo_asic = {
1493 .init = &evergreen_init,
1494 .fini = &evergreen_fini,
1495 .suspend = &evergreen_suspend,
1496 .resume = &evergreen_resume,
1497 .asic_reset = &evergreen_asic_reset,
1498 .vga_set_state = &r600_vga_set_state,
1499 .ioctl_wait_idle = r600_ioctl_wait_idle,
1500 .gui_idle = &r600_gui_idle,
1501 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1502 .get_xclk = &r600_get_xclk,
1503 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1504 .gart = {
1505 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1506 .set_page = &rs600_gart_set_page,
1507 },
1508 .ring = {
1509 [RADEON_RING_TYPE_GFX_INDEX] = {
1510 .ib_execute = &evergreen_ring_ib_execute,
1511 .emit_fence = &r600_fence_ring_emit,
1512 .emit_semaphore = &r600_semaphore_ring_emit,
1513 .cs_parse = &evergreen_cs_parse,
1514 .ring_test = &r600_ring_test,
1515 .ib_test = &r600_ib_test,
1516 .is_lockup = &evergreen_gfx_is_lockup,
1517 .get_rptr = &radeon_ring_generic_get_rptr,
1518 .get_wptr = &radeon_ring_generic_get_wptr,
1519 .set_wptr = &radeon_ring_generic_set_wptr,
1520 },
1521 [R600_RING_TYPE_DMA_INDEX] = {
1522 .ib_execute = &evergreen_dma_ring_ib_execute,
1523 .emit_fence = &evergreen_dma_fence_ring_emit,
1524 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1525 .cs_parse = &evergreen_dma_cs_parse,
1526 .ring_test = &r600_dma_ring_test,
1527 .ib_test = &r600_dma_ib_test,
1528 .is_lockup = &evergreen_dma_is_lockup,
1529 .get_rptr = &radeon_ring_generic_get_rptr,
1530 .get_wptr = &radeon_ring_generic_get_wptr,
1531 .set_wptr = &radeon_ring_generic_set_wptr,
1532 },
1533 [R600_RING_TYPE_UVD_INDEX] = {
1534 .ib_execute = &r600_uvd_ib_execute,
1535 .emit_fence = &r600_uvd_fence_emit,
1536 .emit_semaphore = &r600_uvd_semaphore_emit,
1537 .cs_parse = &radeon_uvd_cs_parse,
1538 .ring_test = &r600_uvd_ring_test,
1539 .ib_test = &r600_uvd_ib_test,
1540 .is_lockup = &radeon_ring_test_lockup,
1541 .get_rptr = &radeon_ring_generic_get_rptr,
1542 .get_wptr = &radeon_ring_generic_get_wptr,
1543 .set_wptr = &radeon_ring_generic_set_wptr,
1544 }
1545 },
1546 .irq = {
1547 .set = &evergreen_irq_set,
1548 .process = &evergreen_irq_process,
1549 },
1550 .display = {
1551 .bandwidth_update = &evergreen_bandwidth_update,
1552 .get_vblank_counter = &evergreen_get_vblank_counter,
1553 .wait_for_vblank = &dce4_wait_for_vblank,
1554 .set_backlight_level = &atombios_set_backlight_level,
1555 .get_backlight_level = &atombios_get_backlight_level,
1556 .hdmi_enable = &evergreen_hdmi_enable,
1557 .hdmi_setmode = &evergreen_hdmi_setmode,
1558 },
1559 .copy = {
1560 .blit = &r600_copy_blit,
1561 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1562 .dma = &evergreen_copy_dma,
1563 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1564 .copy = &evergreen_copy_dma,
1565 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1566 },
1567 .surface = {
1568 .set_reg = r600_set_surface_reg,
1569 .clear_reg = r600_clear_surface_reg,
1570 },
1571 .hpd = {
1572 .init = &evergreen_hpd_init,
1573 .fini = &evergreen_hpd_fini,
1574 .sense = &evergreen_hpd_sense,
1575 .set_polarity = &evergreen_hpd_set_polarity,
1576 },
1577 .pm = {
1578 .misc = &evergreen_pm_misc,
1579 .prepare = &evergreen_pm_prepare,
1580 .finish = &evergreen_pm_finish,
1581 .init_profile = &sumo_pm_init_profile,
1582 .get_dynpm_state = &r600_pm_get_dynpm_state,
1583 .get_engine_clock = &radeon_atom_get_engine_clock,
1584 .set_engine_clock = &radeon_atom_set_engine_clock,
1585 .get_memory_clock = NULL,
1586 .set_memory_clock = NULL,
1587 .get_pcie_lanes = NULL,
1588 .set_pcie_lanes = NULL,
1589 .set_clock_gating = NULL,
1590 .set_uvd_clocks = &sumo_set_uvd_clocks,
1591 .get_temperature = &sumo_get_temp,
1592 },
1593 .pflip = {
1594 .pre_page_flip = &evergreen_pre_page_flip,
1595 .page_flip = &evergreen_page_flip,
1596 .post_page_flip = &evergreen_post_page_flip,
1597 },
1598 };
1599
1600 static struct radeon_asic btc_asic = {
1601 .init = &evergreen_init,
1602 .fini = &evergreen_fini,
1603 .suspend = &evergreen_suspend,
1604 .resume = &evergreen_resume,
1605 .asic_reset = &evergreen_asic_reset,
1606 .vga_set_state = &r600_vga_set_state,
1607 .ioctl_wait_idle = r600_ioctl_wait_idle,
1608 .gui_idle = &r600_gui_idle,
1609 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1610 .get_xclk = &rv770_get_xclk,
1611 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1612 .gart = {
1613 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1614 .set_page = &rs600_gart_set_page,
1615 },
1616 .ring = {
1617 [RADEON_RING_TYPE_GFX_INDEX] = {
1618 .ib_execute = &evergreen_ring_ib_execute,
1619 .emit_fence = &r600_fence_ring_emit,
1620 .emit_semaphore = &r600_semaphore_ring_emit,
1621 .cs_parse = &evergreen_cs_parse,
1622 .ring_test = &r600_ring_test,
1623 .ib_test = &r600_ib_test,
1624 .is_lockup = &evergreen_gfx_is_lockup,
1625 .get_rptr = &radeon_ring_generic_get_rptr,
1626 .get_wptr = &radeon_ring_generic_get_wptr,
1627 .set_wptr = &radeon_ring_generic_set_wptr,
1628 },
1629 [R600_RING_TYPE_DMA_INDEX] = {
1630 .ib_execute = &evergreen_dma_ring_ib_execute,
1631 .emit_fence = &evergreen_dma_fence_ring_emit,
1632 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1633 .cs_parse = &evergreen_dma_cs_parse,
1634 .ring_test = &r600_dma_ring_test,
1635 .ib_test = &r600_dma_ib_test,
1636 .is_lockup = &evergreen_dma_is_lockup,
1637 .get_rptr = &radeon_ring_generic_get_rptr,
1638 .get_wptr = &radeon_ring_generic_get_wptr,
1639 .set_wptr = &radeon_ring_generic_set_wptr,
1640 },
1641 [R600_RING_TYPE_UVD_INDEX] = {
1642 .ib_execute = &r600_uvd_ib_execute,
1643 .emit_fence = &r600_uvd_fence_emit,
1644 .emit_semaphore = &r600_uvd_semaphore_emit,
1645 .cs_parse = &radeon_uvd_cs_parse,
1646 .ring_test = &r600_uvd_ring_test,
1647 .ib_test = &r600_uvd_ib_test,
1648 .is_lockup = &radeon_ring_test_lockup,
1649 .get_rptr = &radeon_ring_generic_get_rptr,
1650 .get_wptr = &radeon_ring_generic_get_wptr,
1651 .set_wptr = &radeon_ring_generic_set_wptr,
1652 }
1653 },
1654 .irq = {
1655 .set = &evergreen_irq_set,
1656 .process = &evergreen_irq_process,
1657 },
1658 .display = {
1659 .bandwidth_update = &evergreen_bandwidth_update,
1660 .get_vblank_counter = &evergreen_get_vblank_counter,
1661 .wait_for_vblank = &dce4_wait_for_vblank,
1662 .set_backlight_level = &atombios_set_backlight_level,
1663 .get_backlight_level = &atombios_get_backlight_level,
1664 .hdmi_enable = &evergreen_hdmi_enable,
1665 .hdmi_setmode = &evergreen_hdmi_setmode,
1666 },
1667 .copy = {
1668 .blit = &r600_copy_blit,
1669 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1670 .dma = &evergreen_copy_dma,
1671 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1672 .copy = &evergreen_copy_dma,
1673 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1674 },
1675 .surface = {
1676 .set_reg = r600_set_surface_reg,
1677 .clear_reg = r600_clear_surface_reg,
1678 },
1679 .hpd = {
1680 .init = &evergreen_hpd_init,
1681 .fini = &evergreen_hpd_fini,
1682 .sense = &evergreen_hpd_sense,
1683 .set_polarity = &evergreen_hpd_set_polarity,
1684 },
1685 .pm = {
1686 .misc = &evergreen_pm_misc,
1687 .prepare = &evergreen_pm_prepare,
1688 .finish = &evergreen_pm_finish,
1689 .init_profile = &btc_pm_init_profile,
1690 .get_dynpm_state = &r600_pm_get_dynpm_state,
1691 .get_engine_clock = &radeon_atom_get_engine_clock,
1692 .set_engine_clock = &radeon_atom_set_engine_clock,
1693 .get_memory_clock = &radeon_atom_get_memory_clock,
1694 .set_memory_clock = &radeon_atom_set_memory_clock,
1695 .get_pcie_lanes = &r600_get_pcie_lanes,
1696 .set_pcie_lanes = &r600_set_pcie_lanes,
1697 .set_clock_gating = NULL,
1698 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1699 .get_temperature = &evergreen_get_temp,
1700 },
1701 .pflip = {
1702 .pre_page_flip = &evergreen_pre_page_flip,
1703 .page_flip = &evergreen_page_flip,
1704 .post_page_flip = &evergreen_post_page_flip,
1705 },
1706 };
1707
1708 static struct radeon_asic cayman_asic = {
1709 .init = &cayman_init,
1710 .fini = &cayman_fini,
1711 .suspend = &cayman_suspend,
1712 .resume = &cayman_resume,
1713 .asic_reset = &cayman_asic_reset,
1714 .vga_set_state = &r600_vga_set_state,
1715 .ioctl_wait_idle = r600_ioctl_wait_idle,
1716 .gui_idle = &r600_gui_idle,
1717 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1718 .get_xclk = &rv770_get_xclk,
1719 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1720 .gart = {
1721 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1722 .set_page = &rs600_gart_set_page,
1723 },
1724 .vm = {
1725 .init = &cayman_vm_init,
1726 .fini = &cayman_vm_fini,
1727 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1728 .set_page = &cayman_vm_set_page,
1729 },
1730 .ring = {
1731 [RADEON_RING_TYPE_GFX_INDEX] = {
1732 .ib_execute = &cayman_ring_ib_execute,
1733 .ib_parse = &evergreen_ib_parse,
1734 .emit_fence = &cayman_fence_ring_emit,
1735 .emit_semaphore = &r600_semaphore_ring_emit,
1736 .cs_parse = &evergreen_cs_parse,
1737 .ring_test = &r600_ring_test,
1738 .ib_test = &r600_ib_test,
1739 .is_lockup = &cayman_gfx_is_lockup,
1740 .vm_flush = &cayman_vm_flush,
1741 .get_rptr = &radeon_ring_generic_get_rptr,
1742 .get_wptr = &radeon_ring_generic_get_wptr,
1743 .set_wptr = &radeon_ring_generic_set_wptr,
1744 },
1745 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1746 .ib_execute = &cayman_ring_ib_execute,
1747 .ib_parse = &evergreen_ib_parse,
1748 .emit_fence = &cayman_fence_ring_emit,
1749 .emit_semaphore = &r600_semaphore_ring_emit,
1750 .cs_parse = &evergreen_cs_parse,
1751 .ring_test = &r600_ring_test,
1752 .ib_test = &r600_ib_test,
1753 .is_lockup = &cayman_gfx_is_lockup,
1754 .vm_flush = &cayman_vm_flush,
1755 .get_rptr = &radeon_ring_generic_get_rptr,
1756 .get_wptr = &radeon_ring_generic_get_wptr,
1757 .set_wptr = &radeon_ring_generic_set_wptr,
1758 },
1759 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1760 .ib_execute = &cayman_ring_ib_execute,
1761 .ib_parse = &evergreen_ib_parse,
1762 .emit_fence = &cayman_fence_ring_emit,
1763 .emit_semaphore = &r600_semaphore_ring_emit,
1764 .cs_parse = &evergreen_cs_parse,
1765 .ring_test = &r600_ring_test,
1766 .ib_test = &r600_ib_test,
1767 .is_lockup = &cayman_gfx_is_lockup,
1768 .vm_flush = &cayman_vm_flush,
1769 .get_rptr = &radeon_ring_generic_get_rptr,
1770 .get_wptr = &radeon_ring_generic_get_wptr,
1771 .set_wptr = &radeon_ring_generic_set_wptr,
1772 },
1773 [R600_RING_TYPE_DMA_INDEX] = {
1774 .ib_execute = &cayman_dma_ring_ib_execute,
1775 .ib_parse = &evergreen_dma_ib_parse,
1776 .emit_fence = &evergreen_dma_fence_ring_emit,
1777 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1778 .cs_parse = &evergreen_dma_cs_parse,
1779 .ring_test = &r600_dma_ring_test,
1780 .ib_test = &r600_dma_ib_test,
1781 .is_lockup = &cayman_dma_is_lockup,
1782 .vm_flush = &cayman_dma_vm_flush,
1783 .get_rptr = &radeon_ring_generic_get_rptr,
1784 .get_wptr = &radeon_ring_generic_get_wptr,
1785 .set_wptr = &radeon_ring_generic_set_wptr,
1786 },
1787 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1788 .ib_execute = &cayman_dma_ring_ib_execute,
1789 .ib_parse = &evergreen_dma_ib_parse,
1790 .emit_fence = &evergreen_dma_fence_ring_emit,
1791 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1792 .cs_parse = &evergreen_dma_cs_parse,
1793 .ring_test = &r600_dma_ring_test,
1794 .ib_test = &r600_dma_ib_test,
1795 .is_lockup = &cayman_dma_is_lockup,
1796 .vm_flush = &cayman_dma_vm_flush,
1797 .get_rptr = &radeon_ring_generic_get_rptr,
1798 .get_wptr = &radeon_ring_generic_get_wptr,
1799 .set_wptr = &radeon_ring_generic_set_wptr,
1800 },
1801 [R600_RING_TYPE_UVD_INDEX] = {
1802 .ib_execute = &r600_uvd_ib_execute,
1803 .emit_fence = &r600_uvd_fence_emit,
1804 .emit_semaphore = &cayman_uvd_semaphore_emit,
1805 .cs_parse = &radeon_uvd_cs_parse,
1806 .ring_test = &r600_uvd_ring_test,
1807 .ib_test = &r600_uvd_ib_test,
1808 .is_lockup = &radeon_ring_test_lockup,
1809 .get_rptr = &radeon_ring_generic_get_rptr,
1810 .get_wptr = &radeon_ring_generic_get_wptr,
1811 .set_wptr = &radeon_ring_generic_set_wptr,
1812 }
1813 },
1814 .irq = {
1815 .set = &evergreen_irq_set,
1816 .process = &evergreen_irq_process,
1817 },
1818 .display = {
1819 .bandwidth_update = &evergreen_bandwidth_update,
1820 .get_vblank_counter = &evergreen_get_vblank_counter,
1821 .wait_for_vblank = &dce4_wait_for_vblank,
1822 .set_backlight_level = &atombios_set_backlight_level,
1823 .get_backlight_level = &atombios_get_backlight_level,
1824 .hdmi_enable = &evergreen_hdmi_enable,
1825 .hdmi_setmode = &evergreen_hdmi_setmode,
1826 },
1827 .copy = {
1828 .blit = &r600_copy_blit,
1829 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1830 .dma = &evergreen_copy_dma,
1831 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1832 .copy = &evergreen_copy_dma,
1833 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1834 },
1835 .surface = {
1836 .set_reg = r600_set_surface_reg,
1837 .clear_reg = r600_clear_surface_reg,
1838 },
1839 .hpd = {
1840 .init = &evergreen_hpd_init,
1841 .fini = &evergreen_hpd_fini,
1842 .sense = &evergreen_hpd_sense,
1843 .set_polarity = &evergreen_hpd_set_polarity,
1844 },
1845 .pm = {
1846 .misc = &evergreen_pm_misc,
1847 .prepare = &evergreen_pm_prepare,
1848 .finish = &evergreen_pm_finish,
1849 .init_profile = &btc_pm_init_profile,
1850 .get_dynpm_state = &r600_pm_get_dynpm_state,
1851 .get_engine_clock = &radeon_atom_get_engine_clock,
1852 .set_engine_clock = &radeon_atom_set_engine_clock,
1853 .get_memory_clock = &radeon_atom_get_memory_clock,
1854 .set_memory_clock = &radeon_atom_set_memory_clock,
1855 .get_pcie_lanes = &r600_get_pcie_lanes,
1856 .set_pcie_lanes = &r600_set_pcie_lanes,
1857 .set_clock_gating = NULL,
1858 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1859 .get_temperature = &evergreen_get_temp,
1860 },
1861 .pflip = {
1862 .pre_page_flip = &evergreen_pre_page_flip,
1863 .page_flip = &evergreen_page_flip,
1864 .post_page_flip = &evergreen_post_page_flip,
1865 },
1866 };
1867
1868 static struct radeon_asic trinity_asic = {
1869 .init = &cayman_init,
1870 .fini = &cayman_fini,
1871 .suspend = &cayman_suspend,
1872 .resume = &cayman_resume,
1873 .asic_reset = &cayman_asic_reset,
1874 .vga_set_state = &r600_vga_set_state,
1875 .ioctl_wait_idle = r600_ioctl_wait_idle,
1876 .gui_idle = &r600_gui_idle,
1877 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1878 .get_xclk = &r600_get_xclk,
1879 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1880 .gart = {
1881 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1882 .set_page = &rs600_gart_set_page,
1883 },
1884 .vm = {
1885 .init = &cayman_vm_init,
1886 .fini = &cayman_vm_fini,
1887 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1888 .set_page = &cayman_vm_set_page,
1889 },
1890 .ring = {
1891 [RADEON_RING_TYPE_GFX_INDEX] = {
1892 .ib_execute = &cayman_ring_ib_execute,
1893 .ib_parse = &evergreen_ib_parse,
1894 .emit_fence = &cayman_fence_ring_emit,
1895 .emit_semaphore = &r600_semaphore_ring_emit,
1896 .cs_parse = &evergreen_cs_parse,
1897 .ring_test = &r600_ring_test,
1898 .ib_test = &r600_ib_test,
1899 .is_lockup = &cayman_gfx_is_lockup,
1900 .vm_flush = &cayman_vm_flush,
1901 .get_rptr = &radeon_ring_generic_get_rptr,
1902 .get_wptr = &radeon_ring_generic_get_wptr,
1903 .set_wptr = &radeon_ring_generic_set_wptr,
1904 },
1905 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1906 .ib_execute = &cayman_ring_ib_execute,
1907 .ib_parse = &evergreen_ib_parse,
1908 .emit_fence = &cayman_fence_ring_emit,
1909 .emit_semaphore = &r600_semaphore_ring_emit,
1910 .cs_parse = &evergreen_cs_parse,
1911 .ring_test = &r600_ring_test,
1912 .ib_test = &r600_ib_test,
1913 .is_lockup = &cayman_gfx_is_lockup,
1914 .vm_flush = &cayman_vm_flush,
1915 .get_rptr = &radeon_ring_generic_get_rptr,
1916 .get_wptr = &radeon_ring_generic_get_wptr,
1917 .set_wptr = &radeon_ring_generic_set_wptr,
1918 },
1919 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1920 .ib_execute = &cayman_ring_ib_execute,
1921 .ib_parse = &evergreen_ib_parse,
1922 .emit_fence = &cayman_fence_ring_emit,
1923 .emit_semaphore = &r600_semaphore_ring_emit,
1924 .cs_parse = &evergreen_cs_parse,
1925 .ring_test = &r600_ring_test,
1926 .ib_test = &r600_ib_test,
1927 .is_lockup = &cayman_gfx_is_lockup,
1928 .vm_flush = &cayman_vm_flush,
1929 .get_rptr = &radeon_ring_generic_get_rptr,
1930 .get_wptr = &radeon_ring_generic_get_wptr,
1931 .set_wptr = &radeon_ring_generic_set_wptr,
1932 },
1933 [R600_RING_TYPE_DMA_INDEX] = {
1934 .ib_execute = &cayman_dma_ring_ib_execute,
1935 .ib_parse = &evergreen_dma_ib_parse,
1936 .emit_fence = &evergreen_dma_fence_ring_emit,
1937 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1938 .cs_parse = &evergreen_dma_cs_parse,
1939 .ring_test = &r600_dma_ring_test,
1940 .ib_test = &r600_dma_ib_test,
1941 .is_lockup = &cayman_dma_is_lockup,
1942 .vm_flush = &cayman_dma_vm_flush,
1943 .get_rptr = &radeon_ring_generic_get_rptr,
1944 .get_wptr = &radeon_ring_generic_get_wptr,
1945 .set_wptr = &radeon_ring_generic_set_wptr,
1946 },
1947 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1948 .ib_execute = &cayman_dma_ring_ib_execute,
1949 .ib_parse = &evergreen_dma_ib_parse,
1950 .emit_fence = &evergreen_dma_fence_ring_emit,
1951 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1952 .cs_parse = &evergreen_dma_cs_parse,
1953 .ring_test = &r600_dma_ring_test,
1954 .ib_test = &r600_dma_ib_test,
1955 .is_lockup = &cayman_dma_is_lockup,
1956 .vm_flush = &cayman_dma_vm_flush,
1957 .get_rptr = &radeon_ring_generic_get_rptr,
1958 .get_wptr = &radeon_ring_generic_get_wptr,
1959 .set_wptr = &radeon_ring_generic_set_wptr,
1960 },
1961 [R600_RING_TYPE_UVD_INDEX] = {
1962 .ib_execute = &r600_uvd_ib_execute,
1963 .emit_fence = &r600_uvd_fence_emit,
1964 .emit_semaphore = &cayman_uvd_semaphore_emit,
1965 .cs_parse = &radeon_uvd_cs_parse,
1966 .ring_test = &r600_uvd_ring_test,
1967 .ib_test = &r600_uvd_ib_test,
1968 .is_lockup = &radeon_ring_test_lockup,
1969 .get_rptr = &radeon_ring_generic_get_rptr,
1970 .get_wptr = &radeon_ring_generic_get_wptr,
1971 .set_wptr = &radeon_ring_generic_set_wptr,
1972 }
1973 },
1974 .irq = {
1975 .set = &evergreen_irq_set,
1976 .process = &evergreen_irq_process,
1977 },
1978 .display = {
1979 .bandwidth_update = &dce6_bandwidth_update,
1980 .get_vblank_counter = &evergreen_get_vblank_counter,
1981 .wait_for_vblank = &dce4_wait_for_vblank,
1982 .set_backlight_level = &atombios_set_backlight_level,
1983 .get_backlight_level = &atombios_get_backlight_level,
1984 },
1985 .copy = {
1986 .blit = &r600_copy_blit,
1987 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1988 .dma = &evergreen_copy_dma,
1989 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1990 .copy = &evergreen_copy_dma,
1991 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1992 },
1993 .surface = {
1994 .set_reg = r600_set_surface_reg,
1995 .clear_reg = r600_clear_surface_reg,
1996 },
1997 .hpd = {
1998 .init = &evergreen_hpd_init,
1999 .fini = &evergreen_hpd_fini,
2000 .sense = &evergreen_hpd_sense,
2001 .set_polarity = &evergreen_hpd_set_polarity,
2002 },
2003 .pm = {
2004 .misc = &evergreen_pm_misc,
2005 .prepare = &evergreen_pm_prepare,
2006 .finish = &evergreen_pm_finish,
2007 .init_profile = &sumo_pm_init_profile,
2008 .get_dynpm_state = &r600_pm_get_dynpm_state,
2009 .get_engine_clock = &radeon_atom_get_engine_clock,
2010 .set_engine_clock = &radeon_atom_set_engine_clock,
2011 .get_memory_clock = NULL,
2012 .set_memory_clock = NULL,
2013 .get_pcie_lanes = NULL,
2014 .set_pcie_lanes = NULL,
2015 .set_clock_gating = NULL,
2016 .set_uvd_clocks = &sumo_set_uvd_clocks,
2017 .get_temperature = &tn_get_temp,
2018 },
2019 .pflip = {
2020 .pre_page_flip = &evergreen_pre_page_flip,
2021 .page_flip = &evergreen_page_flip,
2022 .post_page_flip = &evergreen_post_page_flip,
2023 },
2024 };
2025
2026 static struct radeon_asic si_asic = {
2027 .init = &si_init,
2028 .fini = &si_fini,
2029 .suspend = &si_suspend,
2030 .resume = &si_resume,
2031 .asic_reset = &si_asic_reset,
2032 .vga_set_state = &r600_vga_set_state,
2033 .ioctl_wait_idle = r600_ioctl_wait_idle,
2034 .gui_idle = &r600_gui_idle,
2035 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2036 .get_xclk = &si_get_xclk,
2037 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
2038 .gart = {
2039 .tlb_flush = &si_pcie_gart_tlb_flush,
2040 .set_page = &rs600_gart_set_page,
2041 },
2042 .vm = {
2043 .init = &si_vm_init,
2044 .fini = &si_vm_fini,
2045 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2046 .set_page = &si_vm_set_page,
2047 },
2048 .ring = {
2049 [RADEON_RING_TYPE_GFX_INDEX] = {
2050 .ib_execute = &si_ring_ib_execute,
2051 .ib_parse = &si_ib_parse,
2052 .emit_fence = &si_fence_ring_emit,
2053 .emit_semaphore = &r600_semaphore_ring_emit,
2054 .cs_parse = NULL,
2055 .ring_test = &r600_ring_test,
2056 .ib_test = &r600_ib_test,
2057 .is_lockup = &si_gfx_is_lockup,
2058 .vm_flush = &si_vm_flush,
2059 .get_rptr = &radeon_ring_generic_get_rptr,
2060 .get_wptr = &radeon_ring_generic_get_wptr,
2061 .set_wptr = &radeon_ring_generic_set_wptr,
2062 },
2063 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2064 .ib_execute = &si_ring_ib_execute,
2065 .ib_parse = &si_ib_parse,
2066 .emit_fence = &si_fence_ring_emit,
2067 .emit_semaphore = &r600_semaphore_ring_emit,
2068 .cs_parse = NULL,
2069 .ring_test = &r600_ring_test,
2070 .ib_test = &r600_ib_test,
2071 .is_lockup = &si_gfx_is_lockup,
2072 .vm_flush = &si_vm_flush,
2073 .get_rptr = &radeon_ring_generic_get_rptr,
2074 .get_wptr = &radeon_ring_generic_get_wptr,
2075 .set_wptr = &radeon_ring_generic_set_wptr,
2076 },
2077 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2078 .ib_execute = &si_ring_ib_execute,
2079 .ib_parse = &si_ib_parse,
2080 .emit_fence = &si_fence_ring_emit,
2081 .emit_semaphore = &r600_semaphore_ring_emit,
2082 .cs_parse = NULL,
2083 .ring_test = &r600_ring_test,
2084 .ib_test = &r600_ib_test,
2085 .is_lockup = &si_gfx_is_lockup,
2086 .vm_flush = &si_vm_flush,
2087 .get_rptr = &radeon_ring_generic_get_rptr,
2088 .get_wptr = &radeon_ring_generic_get_wptr,
2089 .set_wptr = &radeon_ring_generic_set_wptr,
2090 },
2091 [R600_RING_TYPE_DMA_INDEX] = {
2092 .ib_execute = &cayman_dma_ring_ib_execute,
2093 .ib_parse = &evergreen_dma_ib_parse,
2094 .emit_fence = &evergreen_dma_fence_ring_emit,
2095 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2096 .cs_parse = NULL,
2097 .ring_test = &r600_dma_ring_test,
2098 .ib_test = &r600_dma_ib_test,
2099 .is_lockup = &si_dma_is_lockup,
2100 .vm_flush = &si_dma_vm_flush,
2101 .get_rptr = &radeon_ring_generic_get_rptr,
2102 .get_wptr = &radeon_ring_generic_get_wptr,
2103 .set_wptr = &radeon_ring_generic_set_wptr,
2104 },
2105 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2106 .ib_execute = &cayman_dma_ring_ib_execute,
2107 .ib_parse = &evergreen_dma_ib_parse,
2108 .emit_fence = &evergreen_dma_fence_ring_emit,
2109 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2110 .cs_parse = NULL,
2111 .ring_test = &r600_dma_ring_test,
2112 .ib_test = &r600_dma_ib_test,
2113 .is_lockup = &si_dma_is_lockup,
2114 .vm_flush = &si_dma_vm_flush,
2115 .get_rptr = &radeon_ring_generic_get_rptr,
2116 .get_wptr = &radeon_ring_generic_get_wptr,
2117 .set_wptr = &radeon_ring_generic_set_wptr,
2118 },
2119 [R600_RING_TYPE_UVD_INDEX] = {
2120 .ib_execute = &r600_uvd_ib_execute,
2121 .emit_fence = &r600_uvd_fence_emit,
2122 .emit_semaphore = &cayman_uvd_semaphore_emit,
2123 .cs_parse = &radeon_uvd_cs_parse,
2124 .ring_test = &r600_uvd_ring_test,
2125 .ib_test = &r600_uvd_ib_test,
2126 .is_lockup = &radeon_ring_test_lockup,
2127 .get_rptr = &radeon_ring_generic_get_rptr,
2128 .get_wptr = &radeon_ring_generic_get_wptr,
2129 .set_wptr = &radeon_ring_generic_set_wptr,
2130 }
2131 },
2132 .irq = {
2133 .set = &si_irq_set,
2134 .process = &si_irq_process,
2135 },
2136 .display = {
2137 .bandwidth_update = &dce6_bandwidth_update,
2138 .get_vblank_counter = &evergreen_get_vblank_counter,
2139 .wait_for_vblank = &dce4_wait_for_vblank,
2140 .set_backlight_level = &atombios_set_backlight_level,
2141 .get_backlight_level = &atombios_get_backlight_level,
2142 },
2143 .copy = {
2144 .blit = NULL,
2145 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2146 .dma = &si_copy_dma,
2147 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2148 .copy = &si_copy_dma,
2149 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2150 },
2151 .surface = {
2152 .set_reg = r600_set_surface_reg,
2153 .clear_reg = r600_clear_surface_reg,
2154 },
2155 .hpd = {
2156 .init = &evergreen_hpd_init,
2157 .fini = &evergreen_hpd_fini,
2158 .sense = &evergreen_hpd_sense,
2159 .set_polarity = &evergreen_hpd_set_polarity,
2160 },
2161 .pm = {
2162 .misc = &evergreen_pm_misc,
2163 .prepare = &evergreen_pm_prepare,
2164 .finish = &evergreen_pm_finish,
2165 .init_profile = &sumo_pm_init_profile,
2166 .get_dynpm_state = &r600_pm_get_dynpm_state,
2167 .get_engine_clock = &radeon_atom_get_engine_clock,
2168 .set_engine_clock = &radeon_atom_set_engine_clock,
2169 .get_memory_clock = &radeon_atom_get_memory_clock,
2170 .set_memory_clock = &radeon_atom_set_memory_clock,
2171 .get_pcie_lanes = &r600_get_pcie_lanes,
2172 .set_pcie_lanes = &r600_set_pcie_lanes,
2173 .set_clock_gating = NULL,
2174 .set_uvd_clocks = &si_set_uvd_clocks,
2175 .get_temperature = &si_get_temp,
2176 },
2177 .pflip = {
2178 .pre_page_flip = &evergreen_pre_page_flip,
2179 .page_flip = &evergreen_page_flip,
2180 .post_page_flip = &evergreen_post_page_flip,
2181 },
2182 };
2183
2184 static struct radeon_asic ci_asic = {
2185 .init = &cik_init,
2186 .fini = &cik_fini,
2187 .suspend = &cik_suspend,
2188 .resume = &cik_resume,
2189 .asic_reset = &cik_asic_reset,
2190 .vga_set_state = &r600_vga_set_state,
2191 .ioctl_wait_idle = NULL,
2192 .gui_idle = &r600_gui_idle,
2193 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2194 .get_xclk = &cik_get_xclk,
2195 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2196 .gart = {
2197 .tlb_flush = &cik_pcie_gart_tlb_flush,
2198 .set_page = &rs600_gart_set_page,
2199 },
2200 .vm = {
2201 .init = &cik_vm_init,
2202 .fini = &cik_vm_fini,
2203 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2204 .set_page = &cik_vm_set_page,
2205 },
2206 .ring = {
2207 [RADEON_RING_TYPE_GFX_INDEX] = {
2208 .ib_execute = &cik_ring_ib_execute,
2209 .ib_parse = &cik_ib_parse,
2210 .emit_fence = &cik_fence_gfx_ring_emit,
2211 .emit_semaphore = &cik_semaphore_ring_emit,
2212 .cs_parse = NULL,
2213 .ring_test = &cik_ring_test,
2214 .ib_test = &cik_ib_test,
2215 .is_lockup = &cik_gfx_is_lockup,
2216 .vm_flush = &cik_vm_flush,
2217 .get_rptr = &radeon_ring_generic_get_rptr,
2218 .get_wptr = &radeon_ring_generic_get_wptr,
2219 .set_wptr = &radeon_ring_generic_set_wptr,
2220 },
2221 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2222 .ib_execute = &cik_ring_ib_execute,
2223 .ib_parse = &cik_ib_parse,
2224 .emit_fence = &cik_fence_compute_ring_emit,
2225 .emit_semaphore = &cik_semaphore_ring_emit,
2226 .cs_parse = NULL,
2227 .ring_test = &cik_ring_test,
2228 .ib_test = &cik_ib_test,
2229 .is_lockup = &cik_gfx_is_lockup,
2230 .vm_flush = &cik_vm_flush,
2231 .get_rptr = &cik_compute_ring_get_rptr,
2232 .get_wptr = &cik_compute_ring_get_wptr,
2233 .set_wptr = &cik_compute_ring_set_wptr,
2234 },
2235 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2236 .ib_execute = &cik_ring_ib_execute,
2237 .ib_parse = &cik_ib_parse,
2238 .emit_fence = &cik_fence_compute_ring_emit,
2239 .emit_semaphore = &cik_semaphore_ring_emit,
2240 .cs_parse = NULL,
2241 .ring_test = &cik_ring_test,
2242 .ib_test = &cik_ib_test,
2243 .is_lockup = &cik_gfx_is_lockup,
2244 .vm_flush = &cik_vm_flush,
2245 .get_rptr = &cik_compute_ring_get_rptr,
2246 .get_wptr = &cik_compute_ring_get_wptr,
2247 .set_wptr = &cik_compute_ring_set_wptr,
2248 },
2249 [R600_RING_TYPE_DMA_INDEX] = {
2250 .ib_execute = &cik_sdma_ring_ib_execute,
2251 .ib_parse = &cik_ib_parse,
2252 .emit_fence = &cik_sdma_fence_ring_emit,
2253 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2254 .cs_parse = NULL,
2255 .ring_test = &cik_sdma_ring_test,
2256 .ib_test = &cik_sdma_ib_test,
2257 .is_lockup = &cik_sdma_is_lockup,
2258 .vm_flush = &cik_dma_vm_flush,
2259 .get_rptr = &radeon_ring_generic_get_rptr,
2260 .get_wptr = &radeon_ring_generic_get_wptr,
2261 .set_wptr = &radeon_ring_generic_set_wptr,
2262 },
2263 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2264 .ib_execute = &cik_sdma_ring_ib_execute,
2265 .ib_parse = &cik_ib_parse,
2266 .emit_fence = &cik_sdma_fence_ring_emit,
2267 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2268 .cs_parse = NULL,
2269 .ring_test = &cik_sdma_ring_test,
2270 .ib_test = &cik_sdma_ib_test,
2271 .is_lockup = &cik_sdma_is_lockup,
2272 .vm_flush = &cik_dma_vm_flush,
2273 .get_rptr = &radeon_ring_generic_get_rptr,
2274 .get_wptr = &radeon_ring_generic_get_wptr,
2275 .set_wptr = &radeon_ring_generic_set_wptr,
2276 },
2277 [R600_RING_TYPE_UVD_INDEX] = {
2278 .ib_execute = &r600_uvd_ib_execute,
2279 .emit_fence = &r600_uvd_fence_emit,
2280 .emit_semaphore = &cayman_uvd_semaphore_emit,
2281 .cs_parse = &radeon_uvd_cs_parse,
2282 .ring_test = &r600_uvd_ring_test,
2283 .ib_test = &r600_uvd_ib_test,
2284 .is_lockup = &radeon_ring_test_lockup,
2285 .get_rptr = &radeon_ring_generic_get_rptr,
2286 .get_wptr = &radeon_ring_generic_get_wptr,
2287 .set_wptr = &radeon_ring_generic_set_wptr,
2288 }
2289 },
2290 .irq = {
2291 .set = &cik_irq_set,
2292 .process = &cik_irq_process,
2293 },
2294 .display = {
2295 .bandwidth_update = &dce8_bandwidth_update,
2296 .get_vblank_counter = &evergreen_get_vblank_counter,
2297 .wait_for_vblank = &dce4_wait_for_vblank,
2298 },
2299 .copy = {
2300 .blit = NULL,
2301 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2302 .dma = &cik_copy_dma,
2303 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2304 .copy = &cik_copy_dma,
2305 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2306 },
2307 .surface = {
2308 .set_reg = r600_set_surface_reg,
2309 .clear_reg = r600_clear_surface_reg,
2310 },
2311 .hpd = {
2312 .init = &evergreen_hpd_init,
2313 .fini = &evergreen_hpd_fini,
2314 .sense = &evergreen_hpd_sense,
2315 .set_polarity = &evergreen_hpd_set_polarity,
2316 },
2317 .pm = {
2318 .misc = &evergreen_pm_misc,
2319 .prepare = &evergreen_pm_prepare,
2320 .finish = &evergreen_pm_finish,
2321 .init_profile = &sumo_pm_init_profile,
2322 .get_dynpm_state = &r600_pm_get_dynpm_state,
2323 .get_engine_clock = &radeon_atom_get_engine_clock,
2324 .set_engine_clock = &radeon_atom_set_engine_clock,
2325 .get_memory_clock = &radeon_atom_get_memory_clock,
2326 .set_memory_clock = &radeon_atom_set_memory_clock,
2327 .get_pcie_lanes = NULL,
2328 .set_pcie_lanes = NULL,
2329 .set_clock_gating = NULL,
2330 .set_uvd_clocks = &cik_set_uvd_clocks,
2331 },
2332 .pflip = {
2333 .pre_page_flip = &evergreen_pre_page_flip,
2334 .page_flip = &evergreen_page_flip,
2335 .post_page_flip = &evergreen_post_page_flip,
2336 },
2337 };
2338
2339 static struct radeon_asic kv_asic = {
2340 .init = &cik_init,
2341 .fini = &cik_fini,
2342 .suspend = &cik_suspend,
2343 .resume = &cik_resume,
2344 .asic_reset = &cik_asic_reset,
2345 .vga_set_state = &r600_vga_set_state,
2346 .ioctl_wait_idle = NULL,
2347 .gui_idle = &r600_gui_idle,
2348 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2349 .get_xclk = &cik_get_xclk,
2350 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2351 .gart = {
2352 .tlb_flush = &cik_pcie_gart_tlb_flush,
2353 .set_page = &rs600_gart_set_page,
2354 },
2355 .vm = {
2356 .init = &cik_vm_init,
2357 .fini = &cik_vm_fini,
2358 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2359 .set_page = &cik_vm_set_page,
2360 },
2361 .ring = {
2362 [RADEON_RING_TYPE_GFX_INDEX] = {
2363 .ib_execute = &cik_ring_ib_execute,
2364 .ib_parse = &cik_ib_parse,
2365 .emit_fence = &cik_fence_gfx_ring_emit,
2366 .emit_semaphore = &cik_semaphore_ring_emit,
2367 .cs_parse = NULL,
2368 .ring_test = &cik_ring_test,
2369 .ib_test = &cik_ib_test,
2370 .is_lockup = &cik_gfx_is_lockup,
2371 .vm_flush = &cik_vm_flush,
2372 .get_rptr = &radeon_ring_generic_get_rptr,
2373 .get_wptr = &radeon_ring_generic_get_wptr,
2374 .set_wptr = &radeon_ring_generic_set_wptr,
2375 },
2376 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2377 .ib_execute = &cik_ring_ib_execute,
2378 .ib_parse = &cik_ib_parse,
2379 .emit_fence = &cik_fence_compute_ring_emit,
2380 .emit_semaphore = &cik_semaphore_ring_emit,
2381 .cs_parse = NULL,
2382 .ring_test = &cik_ring_test,
2383 .ib_test = &cik_ib_test,
2384 .is_lockup = &cik_gfx_is_lockup,
2385 .vm_flush = &cik_vm_flush,
2386 .get_rptr = &cik_compute_ring_get_rptr,
2387 .get_wptr = &cik_compute_ring_get_wptr,
2388 .set_wptr = &cik_compute_ring_set_wptr,
2389 },
2390 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2391 .ib_execute = &cik_ring_ib_execute,
2392 .ib_parse = &cik_ib_parse,
2393 .emit_fence = &cik_fence_compute_ring_emit,
2394 .emit_semaphore = &cik_semaphore_ring_emit,
2395 .cs_parse = NULL,
2396 .ring_test = &cik_ring_test,
2397 .ib_test = &cik_ib_test,
2398 .is_lockup = &cik_gfx_is_lockup,
2399 .vm_flush = &cik_vm_flush,
2400 .get_rptr = &cik_compute_ring_get_rptr,
2401 .get_wptr = &cik_compute_ring_get_wptr,
2402 .set_wptr = &cik_compute_ring_set_wptr,
2403 },
2404 [R600_RING_TYPE_DMA_INDEX] = {
2405 .ib_execute = &cik_sdma_ring_ib_execute,
2406 .ib_parse = &cik_ib_parse,
2407 .emit_fence = &cik_sdma_fence_ring_emit,
2408 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2409 .cs_parse = NULL,
2410 .ring_test = &cik_sdma_ring_test,
2411 .ib_test = &cik_sdma_ib_test,
2412 .is_lockup = &cik_sdma_is_lockup,
2413 .vm_flush = &cik_dma_vm_flush,
2414 .get_rptr = &radeon_ring_generic_get_rptr,
2415 .get_wptr = &radeon_ring_generic_get_wptr,
2416 .set_wptr = &radeon_ring_generic_set_wptr,
2417 },
2418 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2419 .ib_execute = &cik_sdma_ring_ib_execute,
2420 .ib_parse = &cik_ib_parse,
2421 .emit_fence = &cik_sdma_fence_ring_emit,
2422 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2423 .cs_parse = NULL,
2424 .ring_test = &cik_sdma_ring_test,
2425 .ib_test = &cik_sdma_ib_test,
2426 .is_lockup = &cik_sdma_is_lockup,
2427 .vm_flush = &cik_dma_vm_flush,
2428 .get_rptr = &radeon_ring_generic_get_rptr,
2429 .get_wptr = &radeon_ring_generic_get_wptr,
2430 .set_wptr = &radeon_ring_generic_set_wptr,
2431 },
2432 [R600_RING_TYPE_UVD_INDEX] = {
2433 .ib_execute = &r600_uvd_ib_execute,
2434 .emit_fence = &r600_uvd_fence_emit,
2435 .emit_semaphore = &cayman_uvd_semaphore_emit,
2436 .cs_parse = &radeon_uvd_cs_parse,
2437 .ring_test = &r600_uvd_ring_test,
2438 .ib_test = &r600_uvd_ib_test,
2439 .is_lockup = &radeon_ring_test_lockup,
2440 .get_rptr = &radeon_ring_generic_get_rptr,
2441 .get_wptr = &radeon_ring_generic_get_wptr,
2442 .set_wptr = &radeon_ring_generic_set_wptr,
2443 }
2444 },
2445 .irq = {
2446 .set = &cik_irq_set,
2447 .process = &cik_irq_process,
2448 },
2449 .display = {
2450 .bandwidth_update = &dce8_bandwidth_update,
2451 .get_vblank_counter = &evergreen_get_vblank_counter,
2452 .wait_for_vblank = &dce4_wait_for_vblank,
2453 },
2454 .copy = {
2455 .blit = NULL,
2456 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2457 .dma = &cik_copy_dma,
2458 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2459 .copy = &cik_copy_dma,
2460 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2461 },
2462 .surface = {
2463 .set_reg = r600_set_surface_reg,
2464 .clear_reg = r600_clear_surface_reg,
2465 },
2466 .hpd = {
2467 .init = &evergreen_hpd_init,
2468 .fini = &evergreen_hpd_fini,
2469 .sense = &evergreen_hpd_sense,
2470 .set_polarity = &evergreen_hpd_set_polarity,
2471 },
2472 .pm = {
2473 .misc = &evergreen_pm_misc,
2474 .prepare = &evergreen_pm_prepare,
2475 .finish = &evergreen_pm_finish,
2476 .init_profile = &sumo_pm_init_profile,
2477 .get_dynpm_state = &r600_pm_get_dynpm_state,
2478 .get_engine_clock = &radeon_atom_get_engine_clock,
2479 .set_engine_clock = &radeon_atom_set_engine_clock,
2480 .get_memory_clock = &radeon_atom_get_memory_clock,
2481 .set_memory_clock = &radeon_atom_set_memory_clock,
2482 .get_pcie_lanes = NULL,
2483 .set_pcie_lanes = NULL,
2484 .set_clock_gating = NULL,
2485 .set_uvd_clocks = &cik_set_uvd_clocks,
2486 },
2487 .pflip = {
2488 .pre_page_flip = &evergreen_pre_page_flip,
2489 .page_flip = &evergreen_page_flip,
2490 .post_page_flip = &evergreen_post_page_flip,
2491 },
2492 };
2493
2494 /**
2495 * radeon_asic_init - register asic specific callbacks
2496 *
2497 * @rdev: radeon device pointer
2498 *
2499 * Registers the appropriate asic specific callbacks for each
2500 * chip family. Also sets other asics specific info like the number
2501 * of crtcs and the register aperture accessors (all asics).
2502 * Returns 0 for success.
2503 */
2504 int radeon_asic_init(struct radeon_device *rdev)
2505 {
2506 radeon_register_accessor_init(rdev);
2507
2508 /* set the number of crtcs */
2509 if (rdev->flags & RADEON_SINGLE_CRTC)
2510 rdev->num_crtc = 1;
2511 else
2512 rdev->num_crtc = 2;
2513
2514 rdev->has_uvd = false;
2515
2516 switch (rdev->family) {
2517 case CHIP_R100:
2518 case CHIP_RV100:
2519 case CHIP_RS100:
2520 case CHIP_RV200:
2521 case CHIP_RS200:
2522 rdev->asic = &r100_asic;
2523 break;
2524 case CHIP_R200:
2525 case CHIP_RV250:
2526 case CHIP_RS300:
2527 case CHIP_RV280:
2528 rdev->asic = &r200_asic;
2529 break;
2530 case CHIP_R300:
2531 case CHIP_R350:
2532 case CHIP_RV350:
2533 case CHIP_RV380:
2534 if (rdev->flags & RADEON_IS_PCIE)
2535 rdev->asic = &r300_asic_pcie;
2536 else
2537 rdev->asic = &r300_asic;
2538 break;
2539 case CHIP_R420:
2540 case CHIP_R423:
2541 case CHIP_RV410:
2542 rdev->asic = &r420_asic;
2543 /* handle macs */
2544 if (rdev->bios == NULL) {
2545 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2546 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2547 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2548 rdev->asic->pm.set_memory_clock = NULL;
2549 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2550 }
2551 break;
2552 case CHIP_RS400:
2553 case CHIP_RS480:
2554 rdev->asic = &rs400_asic;
2555 break;
2556 case CHIP_RS600:
2557 rdev->asic = &rs600_asic;
2558 break;
2559 case CHIP_RS690:
2560 case CHIP_RS740:
2561 rdev->asic = &rs690_asic;
2562 break;
2563 case CHIP_RV515:
2564 rdev->asic = &rv515_asic;
2565 break;
2566 case CHIP_R520:
2567 case CHIP_RV530:
2568 case CHIP_RV560:
2569 case CHIP_RV570:
2570 case CHIP_R580:
2571 rdev->asic = &r520_asic;
2572 break;
2573 case CHIP_R600:
2574 rdev->asic = &r600_asic;
2575 break;
2576 case CHIP_RV610:
2577 case CHIP_RV630:
2578 case CHIP_RV620:
2579 case CHIP_RV635:
2580 case CHIP_RV670:
2581 rdev->asic = &rv6xx_asic;
2582 rdev->has_uvd = true;
2583 break;
2584 case CHIP_RS780:
2585 case CHIP_RS880:
2586 rdev->asic = &rs780_asic;
2587 rdev->has_uvd = true;
2588 break;
2589 case CHIP_RV770:
2590 case CHIP_RV730:
2591 case CHIP_RV710:
2592 case CHIP_RV740:
2593 rdev->asic = &rv770_asic;
2594 rdev->has_uvd = true;
2595 break;
2596 case CHIP_CEDAR:
2597 case CHIP_REDWOOD:
2598 case CHIP_JUNIPER:
2599 case CHIP_CYPRESS:
2600 case CHIP_HEMLOCK:
2601 /* set num crtcs */
2602 if (rdev->family == CHIP_CEDAR)
2603 rdev->num_crtc = 4;
2604 else
2605 rdev->num_crtc = 6;
2606 rdev->asic = &evergreen_asic;
2607 rdev->has_uvd = true;
2608 break;
2609 case CHIP_PALM:
2610 case CHIP_SUMO:
2611 case CHIP_SUMO2:
2612 rdev->asic = &sumo_asic;
2613 rdev->has_uvd = true;
2614 break;
2615 case CHIP_BARTS:
2616 case CHIP_TURKS:
2617 case CHIP_CAICOS:
2618 /* set num crtcs */
2619 if (rdev->family == CHIP_CAICOS)
2620 rdev->num_crtc = 4;
2621 else
2622 rdev->num_crtc = 6;
2623 rdev->asic = &btc_asic;
2624 rdev->has_uvd = true;
2625 break;
2626 case CHIP_CAYMAN:
2627 rdev->asic = &cayman_asic;
2628 /* set num crtcs */
2629 rdev->num_crtc = 6;
2630 rdev->has_uvd = true;
2631 break;
2632 case CHIP_ARUBA:
2633 rdev->asic = &trinity_asic;
2634 /* set num crtcs */
2635 rdev->num_crtc = 4;
2636 rdev->has_uvd = true;
2637 break;
2638 case CHIP_TAHITI:
2639 case CHIP_PITCAIRN:
2640 case CHIP_VERDE:
2641 case CHIP_OLAND:
2642 case CHIP_HAINAN:
2643 rdev->asic = &si_asic;
2644 /* set num crtcs */
2645 if (rdev->family == CHIP_HAINAN)
2646 rdev->num_crtc = 0;
2647 else if (rdev->family == CHIP_OLAND)
2648 rdev->num_crtc = 2;
2649 else
2650 rdev->num_crtc = 6;
2651 if (rdev->family == CHIP_HAINAN)
2652 rdev->has_uvd = false;
2653 else
2654 rdev->has_uvd = true;
2655 break;
2656 case CHIP_BONAIRE:
2657 rdev->asic = &ci_asic;
2658 rdev->num_crtc = 6;
2659 break;
2660 case CHIP_KAVERI:
2661 case CHIP_KABINI:
2662 rdev->asic = &kv_asic;
2663 /* set num crtcs */
2664 if (rdev->family == CHIP_KAVERI)
2665 rdev->num_crtc = 4;
2666 else
2667 rdev->num_crtc = 2;
2668 break;
2669 default:
2670 /* FIXME: not supported yet */
2671 return -EINVAL;
2672 }
2673
2674 if (rdev->flags & RADEON_IS_IGP) {
2675 rdev->asic->pm.get_memory_clock = NULL;
2676 rdev->asic->pm.set_memory_clock = NULL;
2677 }
2678
2679 return 0;
2680 }
2681
Linux kernel - Deliverables
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