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drm/radeon: make get_temperature functions a callback
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <linux/console.h>
30 #include <drm/drmP.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
36 #include "radeon.h"
37 #include "radeon_asic.h"
38 #include "atom.h"
39
40 /*
41 * Registers accessors functions.
42 */
43 /**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54 {
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58 }
59
60 /**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71 {
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75 }
76
77 /**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
85 static void radeon_register_accessor_init(struct radeon_device *rdev)
86 {
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137 }
138
139
140 /* helper to disable agp */
141 /**
142 * radeon_agp_disable - AGP disable helper function
143 *
144 * @rdev: radeon device pointer
145 *
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
148 */
149 void radeon_agp_disable(struct radeon_device *rdev)
150 {
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
163 } else {
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
168 }
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170 }
171
172 /*
173 * ASIC
174 */
175 static struct radeon_asic r100_asic = {
176 .init = &r100_init,
177 .fini = &r100_fini,
178 .suspend = &r100_suspend,
179 .resume = &r100_resume,
180 .vga_set_state = &r100_vga_set_state,
181 .asic_reset = &r100_asic_reset,
182 .ioctl_wait_idle = NULL,
183 .gui_idle = &r100_gui_idle,
184 .mc_wait_for_idle = &r100_mc_wait_for_idle,
185 .gart = {
186 .tlb_flush = &r100_pci_gart_tlb_flush,
187 .set_page = &r100_pci_gart_set_page,
188 },
189 .ring = {
190 [RADEON_RING_TYPE_GFX_INDEX] = {
191 .ib_execute = &r100_ring_ib_execute,
192 .emit_fence = &r100_fence_ring_emit,
193 .emit_semaphore = &r100_semaphore_ring_emit,
194 .cs_parse = &r100_cs_parse,
195 .ring_start = &r100_ring_start,
196 .ring_test = &r100_ring_test,
197 .ib_test = &r100_ib_test,
198 .is_lockup = &r100_gpu_is_lockup,
199 .get_rptr = &radeon_ring_generic_get_rptr,
200 .get_wptr = &radeon_ring_generic_get_wptr,
201 .set_wptr = &radeon_ring_generic_set_wptr,
202 }
203 },
204 .irq = {
205 .set = &r100_irq_set,
206 .process = &r100_irq_process,
207 },
208 .display = {
209 .bandwidth_update = &r100_bandwidth_update,
210 .get_vblank_counter = &r100_get_vblank_counter,
211 .wait_for_vblank = &r100_wait_for_vblank,
212 .set_backlight_level = &radeon_legacy_set_backlight_level,
213 .get_backlight_level = &radeon_legacy_get_backlight_level,
214 },
215 .copy = {
216 .blit = &r100_copy_blit,
217 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
218 .dma = NULL,
219 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
220 .copy = &r100_copy_blit,
221 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
222 },
223 .surface = {
224 .set_reg = r100_set_surface_reg,
225 .clear_reg = r100_clear_surface_reg,
226 },
227 .hpd = {
228 .init = &r100_hpd_init,
229 .fini = &r100_hpd_fini,
230 .sense = &r100_hpd_sense,
231 .set_polarity = &r100_hpd_set_polarity,
232 },
233 .pm = {
234 .misc = &r100_pm_misc,
235 .prepare = &r100_pm_prepare,
236 .finish = &r100_pm_finish,
237 .init_profile = &r100_pm_init_profile,
238 .get_dynpm_state = &r100_pm_get_dynpm_state,
239 .get_engine_clock = &radeon_legacy_get_engine_clock,
240 .set_engine_clock = &radeon_legacy_set_engine_clock,
241 .get_memory_clock = &radeon_legacy_get_memory_clock,
242 .set_memory_clock = NULL,
243 .get_pcie_lanes = NULL,
244 .set_pcie_lanes = NULL,
245 .set_clock_gating = &radeon_legacy_set_clock_gating,
246 },
247 .pflip = {
248 .pre_page_flip = &r100_pre_page_flip,
249 .page_flip = &r100_page_flip,
250 .post_page_flip = &r100_post_page_flip,
251 },
252 };
253
254 static struct radeon_asic r200_asic = {
255 .init = &r100_init,
256 .fini = &r100_fini,
257 .suspend = &r100_suspend,
258 .resume = &r100_resume,
259 .vga_set_state = &r100_vga_set_state,
260 .asic_reset = &r100_asic_reset,
261 .ioctl_wait_idle = NULL,
262 .gui_idle = &r100_gui_idle,
263 .mc_wait_for_idle = &r100_mc_wait_for_idle,
264 .gart = {
265 .tlb_flush = &r100_pci_gart_tlb_flush,
266 .set_page = &r100_pci_gart_set_page,
267 },
268 .ring = {
269 [RADEON_RING_TYPE_GFX_INDEX] = {
270 .ib_execute = &r100_ring_ib_execute,
271 .emit_fence = &r100_fence_ring_emit,
272 .emit_semaphore = &r100_semaphore_ring_emit,
273 .cs_parse = &r100_cs_parse,
274 .ring_start = &r100_ring_start,
275 .ring_test = &r100_ring_test,
276 .ib_test = &r100_ib_test,
277 .is_lockup = &r100_gpu_is_lockup,
278 .get_rptr = &radeon_ring_generic_get_rptr,
279 .get_wptr = &radeon_ring_generic_get_wptr,
280 .set_wptr = &radeon_ring_generic_set_wptr,
281 }
282 },
283 .irq = {
284 .set = &r100_irq_set,
285 .process = &r100_irq_process,
286 },
287 .display = {
288 .bandwidth_update = &r100_bandwidth_update,
289 .get_vblank_counter = &r100_get_vblank_counter,
290 .wait_for_vblank = &r100_wait_for_vblank,
291 .set_backlight_level = &radeon_legacy_set_backlight_level,
292 .get_backlight_level = &radeon_legacy_get_backlight_level,
293 },
294 .copy = {
295 .blit = &r100_copy_blit,
296 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
297 .dma = &r200_copy_dma,
298 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
299 .copy = &r100_copy_blit,
300 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
301 },
302 .surface = {
303 .set_reg = r100_set_surface_reg,
304 .clear_reg = r100_clear_surface_reg,
305 },
306 .hpd = {
307 .init = &r100_hpd_init,
308 .fini = &r100_hpd_fini,
309 .sense = &r100_hpd_sense,
310 .set_polarity = &r100_hpd_set_polarity,
311 },
312 .pm = {
313 .misc = &r100_pm_misc,
314 .prepare = &r100_pm_prepare,
315 .finish = &r100_pm_finish,
316 .init_profile = &r100_pm_init_profile,
317 .get_dynpm_state = &r100_pm_get_dynpm_state,
318 .get_engine_clock = &radeon_legacy_get_engine_clock,
319 .set_engine_clock = &radeon_legacy_set_engine_clock,
320 .get_memory_clock = &radeon_legacy_get_memory_clock,
321 .set_memory_clock = NULL,
322 .get_pcie_lanes = NULL,
323 .set_pcie_lanes = NULL,
324 .set_clock_gating = &radeon_legacy_set_clock_gating,
325 },
326 .pflip = {
327 .pre_page_flip = &r100_pre_page_flip,
328 .page_flip = &r100_page_flip,
329 .post_page_flip = &r100_post_page_flip,
330 },
331 };
332
333 static struct radeon_asic r300_asic = {
334 .init = &r300_init,
335 .fini = &r300_fini,
336 .suspend = &r300_suspend,
337 .resume = &r300_resume,
338 .vga_set_state = &r100_vga_set_state,
339 .asic_reset = &r300_asic_reset,
340 .ioctl_wait_idle = NULL,
341 .gui_idle = &r100_gui_idle,
342 .mc_wait_for_idle = &r300_mc_wait_for_idle,
343 .gart = {
344 .tlb_flush = &r100_pci_gart_tlb_flush,
345 .set_page = &r100_pci_gart_set_page,
346 },
347 .ring = {
348 [RADEON_RING_TYPE_GFX_INDEX] = {
349 .ib_execute = &r100_ring_ib_execute,
350 .emit_fence = &r300_fence_ring_emit,
351 .emit_semaphore = &r100_semaphore_ring_emit,
352 .cs_parse = &r300_cs_parse,
353 .ring_start = &r300_ring_start,
354 .ring_test = &r100_ring_test,
355 .ib_test = &r100_ib_test,
356 .is_lockup = &r100_gpu_is_lockup,
357 .get_rptr = &radeon_ring_generic_get_rptr,
358 .get_wptr = &radeon_ring_generic_get_wptr,
359 .set_wptr = &radeon_ring_generic_set_wptr,
360 }
361 },
362 .irq = {
363 .set = &r100_irq_set,
364 .process = &r100_irq_process,
365 },
366 .display = {
367 .bandwidth_update = &r100_bandwidth_update,
368 .get_vblank_counter = &r100_get_vblank_counter,
369 .wait_for_vblank = &r100_wait_for_vblank,
370 .set_backlight_level = &radeon_legacy_set_backlight_level,
371 .get_backlight_level = &radeon_legacy_get_backlight_level,
372 },
373 .copy = {
374 .blit = &r100_copy_blit,
375 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
376 .dma = &r200_copy_dma,
377 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
378 .copy = &r100_copy_blit,
379 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
380 },
381 .surface = {
382 .set_reg = r100_set_surface_reg,
383 .clear_reg = r100_clear_surface_reg,
384 },
385 .hpd = {
386 .init = &r100_hpd_init,
387 .fini = &r100_hpd_fini,
388 .sense = &r100_hpd_sense,
389 .set_polarity = &r100_hpd_set_polarity,
390 },
391 .pm = {
392 .misc = &r100_pm_misc,
393 .prepare = &r100_pm_prepare,
394 .finish = &r100_pm_finish,
395 .init_profile = &r100_pm_init_profile,
396 .get_dynpm_state = &r100_pm_get_dynpm_state,
397 .get_engine_clock = &radeon_legacy_get_engine_clock,
398 .set_engine_clock = &radeon_legacy_set_engine_clock,
399 .get_memory_clock = &radeon_legacy_get_memory_clock,
400 .set_memory_clock = NULL,
401 .get_pcie_lanes = &rv370_get_pcie_lanes,
402 .set_pcie_lanes = &rv370_set_pcie_lanes,
403 .set_clock_gating = &radeon_legacy_set_clock_gating,
404 },
405 .pflip = {
406 .pre_page_flip = &r100_pre_page_flip,
407 .page_flip = &r100_page_flip,
408 .post_page_flip = &r100_post_page_flip,
409 },
410 };
411
412 static struct radeon_asic r300_asic_pcie = {
413 .init = &r300_init,
414 .fini = &r300_fini,
415 .suspend = &r300_suspend,
416 .resume = &r300_resume,
417 .vga_set_state = &r100_vga_set_state,
418 .asic_reset = &r300_asic_reset,
419 .ioctl_wait_idle = NULL,
420 .gui_idle = &r100_gui_idle,
421 .mc_wait_for_idle = &r300_mc_wait_for_idle,
422 .gart = {
423 .tlb_flush = &rv370_pcie_gart_tlb_flush,
424 .set_page = &rv370_pcie_gart_set_page,
425 },
426 .ring = {
427 [RADEON_RING_TYPE_GFX_INDEX] = {
428 .ib_execute = &r100_ring_ib_execute,
429 .emit_fence = &r300_fence_ring_emit,
430 .emit_semaphore = &r100_semaphore_ring_emit,
431 .cs_parse = &r300_cs_parse,
432 .ring_start = &r300_ring_start,
433 .ring_test = &r100_ring_test,
434 .ib_test = &r100_ib_test,
435 .is_lockup = &r100_gpu_is_lockup,
436 .get_rptr = &radeon_ring_generic_get_rptr,
437 .get_wptr = &radeon_ring_generic_get_wptr,
438 .set_wptr = &radeon_ring_generic_set_wptr,
439 }
440 },
441 .irq = {
442 .set = &r100_irq_set,
443 .process = &r100_irq_process,
444 },
445 .display = {
446 .bandwidth_update = &r100_bandwidth_update,
447 .get_vblank_counter = &r100_get_vblank_counter,
448 .wait_for_vblank = &r100_wait_for_vblank,
449 .set_backlight_level = &radeon_legacy_set_backlight_level,
450 .get_backlight_level = &radeon_legacy_get_backlight_level,
451 },
452 .copy = {
453 .blit = &r100_copy_blit,
454 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
455 .dma = &r200_copy_dma,
456 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
457 .copy = &r100_copy_blit,
458 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
459 },
460 .surface = {
461 .set_reg = r100_set_surface_reg,
462 .clear_reg = r100_clear_surface_reg,
463 },
464 .hpd = {
465 .init = &r100_hpd_init,
466 .fini = &r100_hpd_fini,
467 .sense = &r100_hpd_sense,
468 .set_polarity = &r100_hpd_set_polarity,
469 },
470 .pm = {
471 .misc = &r100_pm_misc,
472 .prepare = &r100_pm_prepare,
473 .finish = &r100_pm_finish,
474 .init_profile = &r100_pm_init_profile,
475 .get_dynpm_state = &r100_pm_get_dynpm_state,
476 .get_engine_clock = &radeon_legacy_get_engine_clock,
477 .set_engine_clock = &radeon_legacy_set_engine_clock,
478 .get_memory_clock = &radeon_legacy_get_memory_clock,
479 .set_memory_clock = NULL,
480 .get_pcie_lanes = &rv370_get_pcie_lanes,
481 .set_pcie_lanes = &rv370_set_pcie_lanes,
482 .set_clock_gating = &radeon_legacy_set_clock_gating,
483 },
484 .pflip = {
485 .pre_page_flip = &r100_pre_page_flip,
486 .page_flip = &r100_page_flip,
487 .post_page_flip = &r100_post_page_flip,
488 },
489 };
490
491 static struct radeon_asic r420_asic = {
492 .init = &r420_init,
493 .fini = &r420_fini,
494 .suspend = &r420_suspend,
495 .resume = &r420_resume,
496 .vga_set_state = &r100_vga_set_state,
497 .asic_reset = &r300_asic_reset,
498 .ioctl_wait_idle = NULL,
499 .gui_idle = &r100_gui_idle,
500 .mc_wait_for_idle = &r300_mc_wait_for_idle,
501 .gart = {
502 .tlb_flush = &rv370_pcie_gart_tlb_flush,
503 .set_page = &rv370_pcie_gart_set_page,
504 },
505 .ring = {
506 [RADEON_RING_TYPE_GFX_INDEX] = {
507 .ib_execute = &r100_ring_ib_execute,
508 .emit_fence = &r300_fence_ring_emit,
509 .emit_semaphore = &r100_semaphore_ring_emit,
510 .cs_parse = &r300_cs_parse,
511 .ring_start = &r300_ring_start,
512 .ring_test = &r100_ring_test,
513 .ib_test = &r100_ib_test,
514 .is_lockup = &r100_gpu_is_lockup,
515 .get_rptr = &radeon_ring_generic_get_rptr,
516 .get_wptr = &radeon_ring_generic_get_wptr,
517 .set_wptr = &radeon_ring_generic_set_wptr,
518 }
519 },
520 .irq = {
521 .set = &r100_irq_set,
522 .process = &r100_irq_process,
523 },
524 .display = {
525 .bandwidth_update = &r100_bandwidth_update,
526 .get_vblank_counter = &r100_get_vblank_counter,
527 .wait_for_vblank = &r100_wait_for_vblank,
528 .set_backlight_level = &atombios_set_backlight_level,
529 .get_backlight_level = &atombios_get_backlight_level,
530 },
531 .copy = {
532 .blit = &r100_copy_blit,
533 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
534 .dma = &r200_copy_dma,
535 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
536 .copy = &r100_copy_blit,
537 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
538 },
539 .surface = {
540 .set_reg = r100_set_surface_reg,
541 .clear_reg = r100_clear_surface_reg,
542 },
543 .hpd = {
544 .init = &r100_hpd_init,
545 .fini = &r100_hpd_fini,
546 .sense = &r100_hpd_sense,
547 .set_polarity = &r100_hpd_set_polarity,
548 },
549 .pm = {
550 .misc = &r100_pm_misc,
551 .prepare = &r100_pm_prepare,
552 .finish = &r100_pm_finish,
553 .init_profile = &r420_pm_init_profile,
554 .get_dynpm_state = &r100_pm_get_dynpm_state,
555 .get_engine_clock = &radeon_atom_get_engine_clock,
556 .set_engine_clock = &radeon_atom_set_engine_clock,
557 .get_memory_clock = &radeon_atom_get_memory_clock,
558 .set_memory_clock = &radeon_atom_set_memory_clock,
559 .get_pcie_lanes = &rv370_get_pcie_lanes,
560 .set_pcie_lanes = &rv370_set_pcie_lanes,
561 .set_clock_gating = &radeon_atom_set_clock_gating,
562 },
563 .pflip = {
564 .pre_page_flip = &r100_pre_page_flip,
565 .page_flip = &r100_page_flip,
566 .post_page_flip = &r100_post_page_flip,
567 },
568 };
569
570 static struct radeon_asic rs400_asic = {
571 .init = &rs400_init,
572 .fini = &rs400_fini,
573 .suspend = &rs400_suspend,
574 .resume = &rs400_resume,
575 .vga_set_state = &r100_vga_set_state,
576 .asic_reset = &r300_asic_reset,
577 .ioctl_wait_idle = NULL,
578 .gui_idle = &r100_gui_idle,
579 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
580 .gart = {
581 .tlb_flush = &rs400_gart_tlb_flush,
582 .set_page = &rs400_gart_set_page,
583 },
584 .ring = {
585 [RADEON_RING_TYPE_GFX_INDEX] = {
586 .ib_execute = &r100_ring_ib_execute,
587 .emit_fence = &r300_fence_ring_emit,
588 .emit_semaphore = &r100_semaphore_ring_emit,
589 .cs_parse = &r300_cs_parse,
590 .ring_start = &r300_ring_start,
591 .ring_test = &r100_ring_test,
592 .ib_test = &r100_ib_test,
593 .is_lockup = &r100_gpu_is_lockup,
594 .get_rptr = &radeon_ring_generic_get_rptr,
595 .get_wptr = &radeon_ring_generic_get_wptr,
596 .set_wptr = &radeon_ring_generic_set_wptr,
597 }
598 },
599 .irq = {
600 .set = &r100_irq_set,
601 .process = &r100_irq_process,
602 },
603 .display = {
604 .bandwidth_update = &r100_bandwidth_update,
605 .get_vblank_counter = &r100_get_vblank_counter,
606 .wait_for_vblank = &r100_wait_for_vblank,
607 .set_backlight_level = &radeon_legacy_set_backlight_level,
608 .get_backlight_level = &radeon_legacy_get_backlight_level,
609 },
610 .copy = {
611 .blit = &r100_copy_blit,
612 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
613 .dma = &r200_copy_dma,
614 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
615 .copy = &r100_copy_blit,
616 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
617 },
618 .surface = {
619 .set_reg = r100_set_surface_reg,
620 .clear_reg = r100_clear_surface_reg,
621 },
622 .hpd = {
623 .init = &r100_hpd_init,
624 .fini = &r100_hpd_fini,
625 .sense = &r100_hpd_sense,
626 .set_polarity = &r100_hpd_set_polarity,
627 },
628 .pm = {
629 .misc = &r100_pm_misc,
630 .prepare = &r100_pm_prepare,
631 .finish = &r100_pm_finish,
632 .init_profile = &r100_pm_init_profile,
633 .get_dynpm_state = &r100_pm_get_dynpm_state,
634 .get_engine_clock = &radeon_legacy_get_engine_clock,
635 .set_engine_clock = &radeon_legacy_set_engine_clock,
636 .get_memory_clock = &radeon_legacy_get_memory_clock,
637 .set_memory_clock = NULL,
638 .get_pcie_lanes = NULL,
639 .set_pcie_lanes = NULL,
640 .set_clock_gating = &radeon_legacy_set_clock_gating,
641 },
642 .pflip = {
643 .pre_page_flip = &r100_pre_page_flip,
644 .page_flip = &r100_page_flip,
645 .post_page_flip = &r100_post_page_flip,
646 },
647 };
648
649 static struct radeon_asic rs600_asic = {
650 .init = &rs600_init,
651 .fini = &rs600_fini,
652 .suspend = &rs600_suspend,
653 .resume = &rs600_resume,
654 .vga_set_state = &r100_vga_set_state,
655 .asic_reset = &rs600_asic_reset,
656 .ioctl_wait_idle = NULL,
657 .gui_idle = &r100_gui_idle,
658 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
659 .gart = {
660 .tlb_flush = &rs600_gart_tlb_flush,
661 .set_page = &rs600_gart_set_page,
662 },
663 .ring = {
664 [RADEON_RING_TYPE_GFX_INDEX] = {
665 .ib_execute = &r100_ring_ib_execute,
666 .emit_fence = &r300_fence_ring_emit,
667 .emit_semaphore = &r100_semaphore_ring_emit,
668 .cs_parse = &r300_cs_parse,
669 .ring_start = &r300_ring_start,
670 .ring_test = &r100_ring_test,
671 .ib_test = &r100_ib_test,
672 .is_lockup = &r100_gpu_is_lockup,
673 .get_rptr = &radeon_ring_generic_get_rptr,
674 .get_wptr = &radeon_ring_generic_get_wptr,
675 .set_wptr = &radeon_ring_generic_set_wptr,
676 }
677 },
678 .irq = {
679 .set = &rs600_irq_set,
680 .process = &rs600_irq_process,
681 },
682 .display = {
683 .bandwidth_update = &rs600_bandwidth_update,
684 .get_vblank_counter = &rs600_get_vblank_counter,
685 .wait_for_vblank = &avivo_wait_for_vblank,
686 .set_backlight_level = &atombios_set_backlight_level,
687 .get_backlight_level = &atombios_get_backlight_level,
688 .hdmi_enable = &r600_hdmi_enable,
689 .hdmi_setmode = &r600_hdmi_setmode,
690 },
691 .copy = {
692 .blit = &r100_copy_blit,
693 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
694 .dma = &r200_copy_dma,
695 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
696 .copy = &r100_copy_blit,
697 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
698 },
699 .surface = {
700 .set_reg = r100_set_surface_reg,
701 .clear_reg = r100_clear_surface_reg,
702 },
703 .hpd = {
704 .init = &rs600_hpd_init,
705 .fini = &rs600_hpd_fini,
706 .sense = &rs600_hpd_sense,
707 .set_polarity = &rs600_hpd_set_polarity,
708 },
709 .pm = {
710 .misc = &rs600_pm_misc,
711 .prepare = &rs600_pm_prepare,
712 .finish = &rs600_pm_finish,
713 .init_profile = &r420_pm_init_profile,
714 .get_dynpm_state = &r100_pm_get_dynpm_state,
715 .get_engine_clock = &radeon_atom_get_engine_clock,
716 .set_engine_clock = &radeon_atom_set_engine_clock,
717 .get_memory_clock = &radeon_atom_get_memory_clock,
718 .set_memory_clock = &radeon_atom_set_memory_clock,
719 .get_pcie_lanes = NULL,
720 .set_pcie_lanes = NULL,
721 .set_clock_gating = &radeon_atom_set_clock_gating,
722 },
723 .pflip = {
724 .pre_page_flip = &rs600_pre_page_flip,
725 .page_flip = &rs600_page_flip,
726 .post_page_flip = &rs600_post_page_flip,
727 },
728 };
729
730 static struct radeon_asic rs690_asic = {
731 .init = &rs690_init,
732 .fini = &rs690_fini,
733 .suspend = &rs690_suspend,
734 .resume = &rs690_resume,
735 .vga_set_state = &r100_vga_set_state,
736 .asic_reset = &rs600_asic_reset,
737 .ioctl_wait_idle = NULL,
738 .gui_idle = &r100_gui_idle,
739 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
740 .gart = {
741 .tlb_flush = &rs400_gart_tlb_flush,
742 .set_page = &rs400_gart_set_page,
743 },
744 .ring = {
745 [RADEON_RING_TYPE_GFX_INDEX] = {
746 .ib_execute = &r100_ring_ib_execute,
747 .emit_fence = &r300_fence_ring_emit,
748 .emit_semaphore = &r100_semaphore_ring_emit,
749 .cs_parse = &r300_cs_parse,
750 .ring_start = &r300_ring_start,
751 .ring_test = &r100_ring_test,
752 .ib_test = &r100_ib_test,
753 .is_lockup = &r100_gpu_is_lockup,
754 .get_rptr = &radeon_ring_generic_get_rptr,
755 .get_wptr = &radeon_ring_generic_get_wptr,
756 .set_wptr = &radeon_ring_generic_set_wptr,
757 }
758 },
759 .irq = {
760 .set = &rs600_irq_set,
761 .process = &rs600_irq_process,
762 },
763 .display = {
764 .get_vblank_counter = &rs600_get_vblank_counter,
765 .bandwidth_update = &rs690_bandwidth_update,
766 .wait_for_vblank = &avivo_wait_for_vblank,
767 .set_backlight_level = &atombios_set_backlight_level,
768 .get_backlight_level = &atombios_get_backlight_level,
769 .hdmi_enable = &r600_hdmi_enable,
770 .hdmi_setmode = &r600_hdmi_setmode,
771 },
772 .copy = {
773 .blit = &r100_copy_blit,
774 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
775 .dma = &r200_copy_dma,
776 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
777 .copy = &r200_copy_dma,
778 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
779 },
780 .surface = {
781 .set_reg = r100_set_surface_reg,
782 .clear_reg = r100_clear_surface_reg,
783 },
784 .hpd = {
785 .init = &rs600_hpd_init,
786 .fini = &rs600_hpd_fini,
787 .sense = &rs600_hpd_sense,
788 .set_polarity = &rs600_hpd_set_polarity,
789 },
790 .pm = {
791 .misc = &rs600_pm_misc,
792 .prepare = &rs600_pm_prepare,
793 .finish = &rs600_pm_finish,
794 .init_profile = &r420_pm_init_profile,
795 .get_dynpm_state = &r100_pm_get_dynpm_state,
796 .get_engine_clock = &radeon_atom_get_engine_clock,
797 .set_engine_clock = &radeon_atom_set_engine_clock,
798 .get_memory_clock = &radeon_atom_get_memory_clock,
799 .set_memory_clock = &radeon_atom_set_memory_clock,
800 .get_pcie_lanes = NULL,
801 .set_pcie_lanes = NULL,
802 .set_clock_gating = &radeon_atom_set_clock_gating,
803 },
804 .pflip = {
805 .pre_page_flip = &rs600_pre_page_flip,
806 .page_flip = &rs600_page_flip,
807 .post_page_flip = &rs600_post_page_flip,
808 },
809 };
810
811 static struct radeon_asic rv515_asic = {
812 .init = &rv515_init,
813 .fini = &rv515_fini,
814 .suspend = &rv515_suspend,
815 .resume = &rv515_resume,
816 .vga_set_state = &r100_vga_set_state,
817 .asic_reset = &rs600_asic_reset,
818 .ioctl_wait_idle = NULL,
819 .gui_idle = &r100_gui_idle,
820 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
821 .gart = {
822 .tlb_flush = &rv370_pcie_gart_tlb_flush,
823 .set_page = &rv370_pcie_gart_set_page,
824 },
825 .ring = {
826 [RADEON_RING_TYPE_GFX_INDEX] = {
827 .ib_execute = &r100_ring_ib_execute,
828 .emit_fence = &r300_fence_ring_emit,
829 .emit_semaphore = &r100_semaphore_ring_emit,
830 .cs_parse = &r300_cs_parse,
831 .ring_start = &rv515_ring_start,
832 .ring_test = &r100_ring_test,
833 .ib_test = &r100_ib_test,
834 .is_lockup = &r100_gpu_is_lockup,
835 .get_rptr = &radeon_ring_generic_get_rptr,
836 .get_wptr = &radeon_ring_generic_get_wptr,
837 .set_wptr = &radeon_ring_generic_set_wptr,
838 }
839 },
840 .irq = {
841 .set = &rs600_irq_set,
842 .process = &rs600_irq_process,
843 },
844 .display = {
845 .get_vblank_counter = &rs600_get_vblank_counter,
846 .bandwidth_update = &rv515_bandwidth_update,
847 .wait_for_vblank = &avivo_wait_for_vblank,
848 .set_backlight_level = &atombios_set_backlight_level,
849 .get_backlight_level = &atombios_get_backlight_level,
850 },
851 .copy = {
852 .blit = &r100_copy_blit,
853 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
854 .dma = &r200_copy_dma,
855 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
856 .copy = &r100_copy_blit,
857 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
858 },
859 .surface = {
860 .set_reg = r100_set_surface_reg,
861 .clear_reg = r100_clear_surface_reg,
862 },
863 .hpd = {
864 .init = &rs600_hpd_init,
865 .fini = &rs600_hpd_fini,
866 .sense = &rs600_hpd_sense,
867 .set_polarity = &rs600_hpd_set_polarity,
868 },
869 .pm = {
870 .misc = &rs600_pm_misc,
871 .prepare = &rs600_pm_prepare,
872 .finish = &rs600_pm_finish,
873 .init_profile = &r420_pm_init_profile,
874 .get_dynpm_state = &r100_pm_get_dynpm_state,
875 .get_engine_clock = &radeon_atom_get_engine_clock,
876 .set_engine_clock = &radeon_atom_set_engine_clock,
877 .get_memory_clock = &radeon_atom_get_memory_clock,
878 .set_memory_clock = &radeon_atom_set_memory_clock,
879 .get_pcie_lanes = &rv370_get_pcie_lanes,
880 .set_pcie_lanes = &rv370_set_pcie_lanes,
881 .set_clock_gating = &radeon_atom_set_clock_gating,
882 },
883 .pflip = {
884 .pre_page_flip = &rs600_pre_page_flip,
885 .page_flip = &rs600_page_flip,
886 .post_page_flip = &rs600_post_page_flip,
887 },
888 };
889
890 static struct radeon_asic r520_asic = {
891 .init = &r520_init,
892 .fini = &rv515_fini,
893 .suspend = &rv515_suspend,
894 .resume = &r520_resume,
895 .vga_set_state = &r100_vga_set_state,
896 .asic_reset = &rs600_asic_reset,
897 .ioctl_wait_idle = NULL,
898 .gui_idle = &r100_gui_idle,
899 .mc_wait_for_idle = &r520_mc_wait_for_idle,
900 .gart = {
901 .tlb_flush = &rv370_pcie_gart_tlb_flush,
902 .set_page = &rv370_pcie_gart_set_page,
903 },
904 .ring = {
905 [RADEON_RING_TYPE_GFX_INDEX] = {
906 .ib_execute = &r100_ring_ib_execute,
907 .emit_fence = &r300_fence_ring_emit,
908 .emit_semaphore = &r100_semaphore_ring_emit,
909 .cs_parse = &r300_cs_parse,
910 .ring_start = &rv515_ring_start,
911 .ring_test = &r100_ring_test,
912 .ib_test = &r100_ib_test,
913 .is_lockup = &r100_gpu_is_lockup,
914 .get_rptr = &radeon_ring_generic_get_rptr,
915 .get_wptr = &radeon_ring_generic_get_wptr,
916 .set_wptr = &radeon_ring_generic_set_wptr,
917 }
918 },
919 .irq = {
920 .set = &rs600_irq_set,
921 .process = &rs600_irq_process,
922 },
923 .display = {
924 .bandwidth_update = &rv515_bandwidth_update,
925 .get_vblank_counter = &rs600_get_vblank_counter,
926 .wait_for_vblank = &avivo_wait_for_vblank,
927 .set_backlight_level = &atombios_set_backlight_level,
928 .get_backlight_level = &atombios_get_backlight_level,
929 },
930 .copy = {
931 .blit = &r100_copy_blit,
932 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
933 .dma = &r200_copy_dma,
934 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
935 .copy = &r100_copy_blit,
936 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
937 },
938 .surface = {
939 .set_reg = r100_set_surface_reg,
940 .clear_reg = r100_clear_surface_reg,
941 },
942 .hpd = {
943 .init = &rs600_hpd_init,
944 .fini = &rs600_hpd_fini,
945 .sense = &rs600_hpd_sense,
946 .set_polarity = &rs600_hpd_set_polarity,
947 },
948 .pm = {
949 .misc = &rs600_pm_misc,
950 .prepare = &rs600_pm_prepare,
951 .finish = &rs600_pm_finish,
952 .init_profile = &r420_pm_init_profile,
953 .get_dynpm_state = &r100_pm_get_dynpm_state,
954 .get_engine_clock = &radeon_atom_get_engine_clock,
955 .set_engine_clock = &radeon_atom_set_engine_clock,
956 .get_memory_clock = &radeon_atom_get_memory_clock,
957 .set_memory_clock = &radeon_atom_set_memory_clock,
958 .get_pcie_lanes = &rv370_get_pcie_lanes,
959 .set_pcie_lanes = &rv370_set_pcie_lanes,
960 .set_clock_gating = &radeon_atom_set_clock_gating,
961 },
962 .pflip = {
963 .pre_page_flip = &rs600_pre_page_flip,
964 .page_flip = &rs600_page_flip,
965 .post_page_flip = &rs600_post_page_flip,
966 },
967 };
968
969 static struct radeon_asic r600_asic = {
970 .init = &r600_init,
971 .fini = &r600_fini,
972 .suspend = &r600_suspend,
973 .resume = &r600_resume,
974 .vga_set_state = &r600_vga_set_state,
975 .asic_reset = &r600_asic_reset,
976 .ioctl_wait_idle = r600_ioctl_wait_idle,
977 .gui_idle = &r600_gui_idle,
978 .mc_wait_for_idle = &r600_mc_wait_for_idle,
979 .get_xclk = &r600_get_xclk,
980 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
981 .gart = {
982 .tlb_flush = &r600_pcie_gart_tlb_flush,
983 .set_page = &rs600_gart_set_page,
984 },
985 .ring = {
986 [RADEON_RING_TYPE_GFX_INDEX] = {
987 .ib_execute = &r600_ring_ib_execute,
988 .emit_fence = &r600_fence_ring_emit,
989 .emit_semaphore = &r600_semaphore_ring_emit,
990 .cs_parse = &r600_cs_parse,
991 .ring_test = &r600_ring_test,
992 .ib_test = &r600_ib_test,
993 .is_lockup = &r600_gfx_is_lockup,
994 .get_rptr = &radeon_ring_generic_get_rptr,
995 .get_wptr = &radeon_ring_generic_get_wptr,
996 .set_wptr = &radeon_ring_generic_set_wptr,
997 },
998 [R600_RING_TYPE_DMA_INDEX] = {
999 .ib_execute = &r600_dma_ring_ib_execute,
1000 .emit_fence = &r600_dma_fence_ring_emit,
1001 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1002 .cs_parse = &r600_dma_cs_parse,
1003 .ring_test = &r600_dma_ring_test,
1004 .ib_test = &r600_dma_ib_test,
1005 .is_lockup = &r600_dma_is_lockup,
1006 .get_rptr = &radeon_ring_generic_get_rptr,
1007 .get_wptr = &radeon_ring_generic_get_wptr,
1008 .set_wptr = &radeon_ring_generic_set_wptr,
1009 }
1010 },
1011 .irq = {
1012 .set = &r600_irq_set,
1013 .process = &r600_irq_process,
1014 },
1015 .display = {
1016 .bandwidth_update = &rv515_bandwidth_update,
1017 .get_vblank_counter = &rs600_get_vblank_counter,
1018 .wait_for_vblank = &avivo_wait_for_vblank,
1019 .set_backlight_level = &atombios_set_backlight_level,
1020 .get_backlight_level = &atombios_get_backlight_level,
1021 .hdmi_enable = &r600_hdmi_enable,
1022 .hdmi_setmode = &r600_hdmi_setmode,
1023 },
1024 .copy = {
1025 .blit = &r600_copy_blit,
1026 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1027 .dma = &r600_copy_dma,
1028 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1029 .copy = &r600_copy_dma,
1030 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1031 },
1032 .surface = {
1033 .set_reg = r600_set_surface_reg,
1034 .clear_reg = r600_clear_surface_reg,
1035 },
1036 .hpd = {
1037 .init = &r600_hpd_init,
1038 .fini = &r600_hpd_fini,
1039 .sense = &r600_hpd_sense,
1040 .set_polarity = &r600_hpd_set_polarity,
1041 },
1042 .pm = {
1043 .misc = &r600_pm_misc,
1044 .prepare = &rs600_pm_prepare,
1045 .finish = &rs600_pm_finish,
1046 .init_profile = &r600_pm_init_profile,
1047 .get_dynpm_state = &r600_pm_get_dynpm_state,
1048 .get_engine_clock = &radeon_atom_get_engine_clock,
1049 .set_engine_clock = &radeon_atom_set_engine_clock,
1050 .get_memory_clock = &radeon_atom_get_memory_clock,
1051 .set_memory_clock = &radeon_atom_set_memory_clock,
1052 .get_pcie_lanes = &r600_get_pcie_lanes,
1053 .set_pcie_lanes = &r600_set_pcie_lanes,
1054 .set_clock_gating = NULL,
1055 .get_temperature = &rv6xx_get_temp,
1056 },
1057 .pflip = {
1058 .pre_page_flip = &rs600_pre_page_flip,
1059 .page_flip = &rs600_page_flip,
1060 .post_page_flip = &rs600_post_page_flip,
1061 },
1062 };
1063
1064 static struct radeon_asic rs780_asic = {
1065 .init = &r600_init,
1066 .fini = &r600_fini,
1067 .suspend = &r600_suspend,
1068 .resume = &r600_resume,
1069 .vga_set_state = &r600_vga_set_state,
1070 .asic_reset = &r600_asic_reset,
1071 .ioctl_wait_idle = r600_ioctl_wait_idle,
1072 .gui_idle = &r600_gui_idle,
1073 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1074 .get_xclk = &r600_get_xclk,
1075 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1076 .gart = {
1077 .tlb_flush = &r600_pcie_gart_tlb_flush,
1078 .set_page = &rs600_gart_set_page,
1079 },
1080 .ring = {
1081 [RADEON_RING_TYPE_GFX_INDEX] = {
1082 .ib_execute = &r600_ring_ib_execute,
1083 .emit_fence = &r600_fence_ring_emit,
1084 .emit_semaphore = &r600_semaphore_ring_emit,
1085 .cs_parse = &r600_cs_parse,
1086 .ring_test = &r600_ring_test,
1087 .ib_test = &r600_ib_test,
1088 .is_lockup = &r600_gfx_is_lockup,
1089 .get_rptr = &radeon_ring_generic_get_rptr,
1090 .get_wptr = &radeon_ring_generic_get_wptr,
1091 .set_wptr = &radeon_ring_generic_set_wptr,
1092 },
1093 [R600_RING_TYPE_DMA_INDEX] = {
1094 .ib_execute = &r600_dma_ring_ib_execute,
1095 .emit_fence = &r600_dma_fence_ring_emit,
1096 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1097 .cs_parse = &r600_dma_cs_parse,
1098 .ring_test = &r600_dma_ring_test,
1099 .ib_test = &r600_dma_ib_test,
1100 .is_lockup = &r600_dma_is_lockup,
1101 .get_rptr = &radeon_ring_generic_get_rptr,
1102 .get_wptr = &radeon_ring_generic_get_wptr,
1103 .set_wptr = &radeon_ring_generic_set_wptr,
1104 }
1105 },
1106 .irq = {
1107 .set = &r600_irq_set,
1108 .process = &r600_irq_process,
1109 },
1110 .display = {
1111 .bandwidth_update = &rs690_bandwidth_update,
1112 .get_vblank_counter = &rs600_get_vblank_counter,
1113 .wait_for_vblank = &avivo_wait_for_vblank,
1114 .set_backlight_level = &atombios_set_backlight_level,
1115 .get_backlight_level = &atombios_get_backlight_level,
1116 .hdmi_enable = &r600_hdmi_enable,
1117 .hdmi_setmode = &r600_hdmi_setmode,
1118 },
1119 .copy = {
1120 .blit = &r600_copy_blit,
1121 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1122 .dma = &r600_copy_dma,
1123 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1124 .copy = &r600_copy_dma,
1125 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1126 },
1127 .surface = {
1128 .set_reg = r600_set_surface_reg,
1129 .clear_reg = r600_clear_surface_reg,
1130 },
1131 .hpd = {
1132 .init = &r600_hpd_init,
1133 .fini = &r600_hpd_fini,
1134 .sense = &r600_hpd_sense,
1135 .set_polarity = &r600_hpd_set_polarity,
1136 },
1137 .pm = {
1138 .misc = &r600_pm_misc,
1139 .prepare = &rs600_pm_prepare,
1140 .finish = &rs600_pm_finish,
1141 .init_profile = &rs780_pm_init_profile,
1142 .get_dynpm_state = &r600_pm_get_dynpm_state,
1143 .get_engine_clock = &radeon_atom_get_engine_clock,
1144 .set_engine_clock = &radeon_atom_set_engine_clock,
1145 .get_memory_clock = NULL,
1146 .set_memory_clock = NULL,
1147 .get_pcie_lanes = NULL,
1148 .set_pcie_lanes = NULL,
1149 .set_clock_gating = NULL,
1150 .get_temperature = &rv6xx_get_temp,
1151 },
1152 .pflip = {
1153 .pre_page_flip = &rs600_pre_page_flip,
1154 .page_flip = &rs600_page_flip,
1155 .post_page_flip = &rs600_post_page_flip,
1156 },
1157 };
1158
1159 static struct radeon_asic rv770_asic = {
1160 .init = &rv770_init,
1161 .fini = &rv770_fini,
1162 .suspend = &rv770_suspend,
1163 .resume = &rv770_resume,
1164 .asic_reset = &r600_asic_reset,
1165 .vga_set_state = &r600_vga_set_state,
1166 .ioctl_wait_idle = r600_ioctl_wait_idle,
1167 .gui_idle = &r600_gui_idle,
1168 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1169 .get_xclk = &rv770_get_xclk,
1170 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1171 .gart = {
1172 .tlb_flush = &r600_pcie_gart_tlb_flush,
1173 .set_page = &rs600_gart_set_page,
1174 },
1175 .ring = {
1176 [RADEON_RING_TYPE_GFX_INDEX] = {
1177 .ib_execute = &r600_ring_ib_execute,
1178 .emit_fence = &r600_fence_ring_emit,
1179 .emit_semaphore = &r600_semaphore_ring_emit,
1180 .cs_parse = &r600_cs_parse,
1181 .ring_test = &r600_ring_test,
1182 .ib_test = &r600_ib_test,
1183 .is_lockup = &r600_gfx_is_lockup,
1184 .get_rptr = &radeon_ring_generic_get_rptr,
1185 .get_wptr = &radeon_ring_generic_get_wptr,
1186 .set_wptr = &radeon_ring_generic_set_wptr,
1187 },
1188 [R600_RING_TYPE_DMA_INDEX] = {
1189 .ib_execute = &r600_dma_ring_ib_execute,
1190 .emit_fence = &r600_dma_fence_ring_emit,
1191 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1192 .cs_parse = &r600_dma_cs_parse,
1193 .ring_test = &r600_dma_ring_test,
1194 .ib_test = &r600_dma_ib_test,
1195 .is_lockup = &r600_dma_is_lockup,
1196 .get_rptr = &radeon_ring_generic_get_rptr,
1197 .get_wptr = &radeon_ring_generic_get_wptr,
1198 .set_wptr = &radeon_ring_generic_set_wptr,
1199 },
1200 [R600_RING_TYPE_UVD_INDEX] = {
1201 .ib_execute = &r600_uvd_ib_execute,
1202 .emit_fence = &r600_uvd_fence_emit,
1203 .emit_semaphore = &r600_uvd_semaphore_emit,
1204 .cs_parse = &radeon_uvd_cs_parse,
1205 .ring_test = &r600_uvd_ring_test,
1206 .ib_test = &r600_uvd_ib_test,
1207 .is_lockup = &radeon_ring_test_lockup,
1208 .get_rptr = &radeon_ring_generic_get_rptr,
1209 .get_wptr = &radeon_ring_generic_get_wptr,
1210 .set_wptr = &radeon_ring_generic_set_wptr,
1211 }
1212 },
1213 .irq = {
1214 .set = &r600_irq_set,
1215 .process = &r600_irq_process,
1216 },
1217 .display = {
1218 .bandwidth_update = &rv515_bandwidth_update,
1219 .get_vblank_counter = &rs600_get_vblank_counter,
1220 .wait_for_vblank = &avivo_wait_for_vblank,
1221 .set_backlight_level = &atombios_set_backlight_level,
1222 .get_backlight_level = &atombios_get_backlight_level,
1223 .hdmi_enable = &r600_hdmi_enable,
1224 .hdmi_setmode = &r600_hdmi_setmode,
1225 },
1226 .copy = {
1227 .blit = &r600_copy_blit,
1228 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1229 .dma = &rv770_copy_dma,
1230 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1231 .copy = &rv770_copy_dma,
1232 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1233 },
1234 .surface = {
1235 .set_reg = r600_set_surface_reg,
1236 .clear_reg = r600_clear_surface_reg,
1237 },
1238 .hpd = {
1239 .init = &r600_hpd_init,
1240 .fini = &r600_hpd_fini,
1241 .sense = &r600_hpd_sense,
1242 .set_polarity = &r600_hpd_set_polarity,
1243 },
1244 .pm = {
1245 .misc = &rv770_pm_misc,
1246 .prepare = &rs600_pm_prepare,
1247 .finish = &rs600_pm_finish,
1248 .init_profile = &r600_pm_init_profile,
1249 .get_dynpm_state = &r600_pm_get_dynpm_state,
1250 .get_engine_clock = &radeon_atom_get_engine_clock,
1251 .set_engine_clock = &radeon_atom_set_engine_clock,
1252 .get_memory_clock = &radeon_atom_get_memory_clock,
1253 .set_memory_clock = &radeon_atom_set_memory_clock,
1254 .get_pcie_lanes = &r600_get_pcie_lanes,
1255 .set_pcie_lanes = &r600_set_pcie_lanes,
1256 .set_clock_gating = &radeon_atom_set_clock_gating,
1257 .set_uvd_clocks = &rv770_set_uvd_clocks,
1258 .get_temperature = &rv770_get_temp,
1259 },
1260 .pflip = {
1261 .pre_page_flip = &rs600_pre_page_flip,
1262 .page_flip = &rv770_page_flip,
1263 .post_page_flip = &rs600_post_page_flip,
1264 },
1265 };
1266
1267 static struct radeon_asic evergreen_asic = {
1268 .init = &evergreen_init,
1269 .fini = &evergreen_fini,
1270 .suspend = &evergreen_suspend,
1271 .resume = &evergreen_resume,
1272 .asic_reset = &evergreen_asic_reset,
1273 .vga_set_state = &r600_vga_set_state,
1274 .ioctl_wait_idle = r600_ioctl_wait_idle,
1275 .gui_idle = &r600_gui_idle,
1276 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1277 .get_xclk = &rv770_get_xclk,
1278 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1279 .gart = {
1280 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1281 .set_page = &rs600_gart_set_page,
1282 },
1283 .ring = {
1284 [RADEON_RING_TYPE_GFX_INDEX] = {
1285 .ib_execute = &evergreen_ring_ib_execute,
1286 .emit_fence = &r600_fence_ring_emit,
1287 .emit_semaphore = &r600_semaphore_ring_emit,
1288 .cs_parse = &evergreen_cs_parse,
1289 .ring_test = &r600_ring_test,
1290 .ib_test = &r600_ib_test,
1291 .is_lockup = &evergreen_gfx_is_lockup,
1292 .get_rptr = &radeon_ring_generic_get_rptr,
1293 .get_wptr = &radeon_ring_generic_get_wptr,
1294 .set_wptr = &radeon_ring_generic_set_wptr,
1295 },
1296 [R600_RING_TYPE_DMA_INDEX] = {
1297 .ib_execute = &evergreen_dma_ring_ib_execute,
1298 .emit_fence = &evergreen_dma_fence_ring_emit,
1299 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1300 .cs_parse = &evergreen_dma_cs_parse,
1301 .ring_test = &r600_dma_ring_test,
1302 .ib_test = &r600_dma_ib_test,
1303 .is_lockup = &evergreen_dma_is_lockup,
1304 .get_rptr = &radeon_ring_generic_get_rptr,
1305 .get_wptr = &radeon_ring_generic_get_wptr,
1306 .set_wptr = &radeon_ring_generic_set_wptr,
1307 },
1308 [R600_RING_TYPE_UVD_INDEX] = {
1309 .ib_execute = &r600_uvd_ib_execute,
1310 .emit_fence = &r600_uvd_fence_emit,
1311 .emit_semaphore = &r600_uvd_semaphore_emit,
1312 .cs_parse = &radeon_uvd_cs_parse,
1313 .ring_test = &r600_uvd_ring_test,
1314 .ib_test = &r600_uvd_ib_test,
1315 .is_lockup = &radeon_ring_test_lockup,
1316 .get_rptr = &radeon_ring_generic_get_rptr,
1317 .get_wptr = &radeon_ring_generic_get_wptr,
1318 .set_wptr = &radeon_ring_generic_set_wptr,
1319 }
1320 },
1321 .irq = {
1322 .set = &evergreen_irq_set,
1323 .process = &evergreen_irq_process,
1324 },
1325 .display = {
1326 .bandwidth_update = &evergreen_bandwidth_update,
1327 .get_vblank_counter = &evergreen_get_vblank_counter,
1328 .wait_for_vblank = &dce4_wait_for_vblank,
1329 .set_backlight_level = &atombios_set_backlight_level,
1330 .get_backlight_level = &atombios_get_backlight_level,
1331 .hdmi_enable = &evergreen_hdmi_enable,
1332 .hdmi_setmode = &evergreen_hdmi_setmode,
1333 },
1334 .copy = {
1335 .blit = &r600_copy_blit,
1336 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1337 .dma = &evergreen_copy_dma,
1338 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1339 .copy = &evergreen_copy_dma,
1340 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1341 },
1342 .surface = {
1343 .set_reg = r600_set_surface_reg,
1344 .clear_reg = r600_clear_surface_reg,
1345 },
1346 .hpd = {
1347 .init = &evergreen_hpd_init,
1348 .fini = &evergreen_hpd_fini,
1349 .sense = &evergreen_hpd_sense,
1350 .set_polarity = &evergreen_hpd_set_polarity,
1351 },
1352 .pm = {
1353 .misc = &evergreen_pm_misc,
1354 .prepare = &evergreen_pm_prepare,
1355 .finish = &evergreen_pm_finish,
1356 .init_profile = &r600_pm_init_profile,
1357 .get_dynpm_state = &r600_pm_get_dynpm_state,
1358 .get_engine_clock = &radeon_atom_get_engine_clock,
1359 .set_engine_clock = &radeon_atom_set_engine_clock,
1360 .get_memory_clock = &radeon_atom_get_memory_clock,
1361 .set_memory_clock = &radeon_atom_set_memory_clock,
1362 .get_pcie_lanes = &r600_get_pcie_lanes,
1363 .set_pcie_lanes = &r600_set_pcie_lanes,
1364 .set_clock_gating = NULL,
1365 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1366 .get_temperature = &evergreen_get_temp,
1367 },
1368 .pflip = {
1369 .pre_page_flip = &evergreen_pre_page_flip,
1370 .page_flip = &evergreen_page_flip,
1371 .post_page_flip = &evergreen_post_page_flip,
1372 },
1373 };
1374
1375 static struct radeon_asic sumo_asic = {
1376 .init = &evergreen_init,
1377 .fini = &evergreen_fini,
1378 .suspend = &evergreen_suspend,
1379 .resume = &evergreen_resume,
1380 .asic_reset = &evergreen_asic_reset,
1381 .vga_set_state = &r600_vga_set_state,
1382 .ioctl_wait_idle = r600_ioctl_wait_idle,
1383 .gui_idle = &r600_gui_idle,
1384 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1385 .get_xclk = &r600_get_xclk,
1386 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1387 .gart = {
1388 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1389 .set_page = &rs600_gart_set_page,
1390 },
1391 .ring = {
1392 [RADEON_RING_TYPE_GFX_INDEX] = {
1393 .ib_execute = &evergreen_ring_ib_execute,
1394 .emit_fence = &r600_fence_ring_emit,
1395 .emit_semaphore = &r600_semaphore_ring_emit,
1396 .cs_parse = &evergreen_cs_parse,
1397 .ring_test = &r600_ring_test,
1398 .ib_test = &r600_ib_test,
1399 .is_lockup = &evergreen_gfx_is_lockup,
1400 .get_rptr = &radeon_ring_generic_get_rptr,
1401 .get_wptr = &radeon_ring_generic_get_wptr,
1402 .set_wptr = &radeon_ring_generic_set_wptr,
1403 },
1404 [R600_RING_TYPE_DMA_INDEX] = {
1405 .ib_execute = &evergreen_dma_ring_ib_execute,
1406 .emit_fence = &evergreen_dma_fence_ring_emit,
1407 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1408 .cs_parse = &evergreen_dma_cs_parse,
1409 .ring_test = &r600_dma_ring_test,
1410 .ib_test = &r600_dma_ib_test,
1411 .is_lockup = &evergreen_dma_is_lockup,
1412 .get_rptr = &radeon_ring_generic_get_rptr,
1413 .get_wptr = &radeon_ring_generic_get_wptr,
1414 .set_wptr = &radeon_ring_generic_set_wptr,
1415 },
1416 [R600_RING_TYPE_UVD_INDEX] = {
1417 .ib_execute = &r600_uvd_ib_execute,
1418 .emit_fence = &r600_uvd_fence_emit,
1419 .emit_semaphore = &r600_uvd_semaphore_emit,
1420 .cs_parse = &radeon_uvd_cs_parse,
1421 .ring_test = &r600_uvd_ring_test,
1422 .ib_test = &r600_uvd_ib_test,
1423 .is_lockup = &radeon_ring_test_lockup,
1424 .get_rptr = &radeon_ring_generic_get_rptr,
1425 .get_wptr = &radeon_ring_generic_get_wptr,
1426 .set_wptr = &radeon_ring_generic_set_wptr,
1427 }
1428 },
1429 .irq = {
1430 .set = &evergreen_irq_set,
1431 .process = &evergreen_irq_process,
1432 },
1433 .display = {
1434 .bandwidth_update = &evergreen_bandwidth_update,
1435 .get_vblank_counter = &evergreen_get_vblank_counter,
1436 .wait_for_vblank = &dce4_wait_for_vblank,
1437 .set_backlight_level = &atombios_set_backlight_level,
1438 .get_backlight_level = &atombios_get_backlight_level,
1439 .hdmi_enable = &evergreen_hdmi_enable,
1440 .hdmi_setmode = &evergreen_hdmi_setmode,
1441 },
1442 .copy = {
1443 .blit = &r600_copy_blit,
1444 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1445 .dma = &evergreen_copy_dma,
1446 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1447 .copy = &evergreen_copy_dma,
1448 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1449 },
1450 .surface = {
1451 .set_reg = r600_set_surface_reg,
1452 .clear_reg = r600_clear_surface_reg,
1453 },
1454 .hpd = {
1455 .init = &evergreen_hpd_init,
1456 .fini = &evergreen_hpd_fini,
1457 .sense = &evergreen_hpd_sense,
1458 .set_polarity = &evergreen_hpd_set_polarity,
1459 },
1460 .pm = {
1461 .misc = &evergreen_pm_misc,
1462 .prepare = &evergreen_pm_prepare,
1463 .finish = &evergreen_pm_finish,
1464 .init_profile = &sumo_pm_init_profile,
1465 .get_dynpm_state = &r600_pm_get_dynpm_state,
1466 .get_engine_clock = &radeon_atom_get_engine_clock,
1467 .set_engine_clock = &radeon_atom_set_engine_clock,
1468 .get_memory_clock = NULL,
1469 .set_memory_clock = NULL,
1470 .get_pcie_lanes = NULL,
1471 .set_pcie_lanes = NULL,
1472 .set_clock_gating = NULL,
1473 .set_uvd_clocks = &sumo_set_uvd_clocks,
1474 .get_temperature = &sumo_get_temp,
1475 },
1476 .pflip = {
1477 .pre_page_flip = &evergreen_pre_page_flip,
1478 .page_flip = &evergreen_page_flip,
1479 .post_page_flip = &evergreen_post_page_flip,
1480 },
1481 };
1482
1483 static struct radeon_asic btc_asic = {
1484 .init = &evergreen_init,
1485 .fini = &evergreen_fini,
1486 .suspend = &evergreen_suspend,
1487 .resume = &evergreen_resume,
1488 .asic_reset = &evergreen_asic_reset,
1489 .vga_set_state = &r600_vga_set_state,
1490 .ioctl_wait_idle = r600_ioctl_wait_idle,
1491 .gui_idle = &r600_gui_idle,
1492 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1493 .get_xclk = &rv770_get_xclk,
1494 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1495 .gart = {
1496 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1497 .set_page = &rs600_gart_set_page,
1498 },
1499 .ring = {
1500 [RADEON_RING_TYPE_GFX_INDEX] = {
1501 .ib_execute = &evergreen_ring_ib_execute,
1502 .emit_fence = &r600_fence_ring_emit,
1503 .emit_semaphore = &r600_semaphore_ring_emit,
1504 .cs_parse = &evergreen_cs_parse,
1505 .ring_test = &r600_ring_test,
1506 .ib_test = &r600_ib_test,
1507 .is_lockup = &evergreen_gfx_is_lockup,
1508 .get_rptr = &radeon_ring_generic_get_rptr,
1509 .get_wptr = &radeon_ring_generic_get_wptr,
1510 .set_wptr = &radeon_ring_generic_set_wptr,
1511 },
1512 [R600_RING_TYPE_DMA_INDEX] = {
1513 .ib_execute = &evergreen_dma_ring_ib_execute,
1514 .emit_fence = &evergreen_dma_fence_ring_emit,
1515 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1516 .cs_parse = &evergreen_dma_cs_parse,
1517 .ring_test = &r600_dma_ring_test,
1518 .ib_test = &r600_dma_ib_test,
1519 .is_lockup = &evergreen_dma_is_lockup,
1520 .get_rptr = &radeon_ring_generic_get_rptr,
1521 .get_wptr = &radeon_ring_generic_get_wptr,
1522 .set_wptr = &radeon_ring_generic_set_wptr,
1523 },
1524 [R600_RING_TYPE_UVD_INDEX] = {
1525 .ib_execute = &r600_uvd_ib_execute,
1526 .emit_fence = &r600_uvd_fence_emit,
1527 .emit_semaphore = &r600_uvd_semaphore_emit,
1528 .cs_parse = &radeon_uvd_cs_parse,
1529 .ring_test = &r600_uvd_ring_test,
1530 .ib_test = &r600_uvd_ib_test,
1531 .is_lockup = &radeon_ring_test_lockup,
1532 .get_rptr = &radeon_ring_generic_get_rptr,
1533 .get_wptr = &radeon_ring_generic_get_wptr,
1534 .set_wptr = &radeon_ring_generic_set_wptr,
1535 }
1536 },
1537 .irq = {
1538 .set = &evergreen_irq_set,
1539 .process = &evergreen_irq_process,
1540 },
1541 .display = {
1542 .bandwidth_update = &evergreen_bandwidth_update,
1543 .get_vblank_counter = &evergreen_get_vblank_counter,
1544 .wait_for_vblank = &dce4_wait_for_vblank,
1545 .set_backlight_level = &atombios_set_backlight_level,
1546 .get_backlight_level = &atombios_get_backlight_level,
1547 .hdmi_enable = &evergreen_hdmi_enable,
1548 .hdmi_setmode = &evergreen_hdmi_setmode,
1549 },
1550 .copy = {
1551 .blit = &r600_copy_blit,
1552 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1553 .dma = &evergreen_copy_dma,
1554 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1555 .copy = &evergreen_copy_dma,
1556 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1557 },
1558 .surface = {
1559 .set_reg = r600_set_surface_reg,
1560 .clear_reg = r600_clear_surface_reg,
1561 },
1562 .hpd = {
1563 .init = &evergreen_hpd_init,
1564 .fini = &evergreen_hpd_fini,
1565 .sense = &evergreen_hpd_sense,
1566 .set_polarity = &evergreen_hpd_set_polarity,
1567 },
1568 .pm = {
1569 .misc = &evergreen_pm_misc,
1570 .prepare = &evergreen_pm_prepare,
1571 .finish = &evergreen_pm_finish,
1572 .init_profile = &btc_pm_init_profile,
1573 .get_dynpm_state = &r600_pm_get_dynpm_state,
1574 .get_engine_clock = &radeon_atom_get_engine_clock,
1575 .set_engine_clock = &radeon_atom_set_engine_clock,
1576 .get_memory_clock = &radeon_atom_get_memory_clock,
1577 .set_memory_clock = &radeon_atom_set_memory_clock,
1578 .get_pcie_lanes = &r600_get_pcie_lanes,
1579 .set_pcie_lanes = &r600_set_pcie_lanes,
1580 .set_clock_gating = NULL,
1581 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1582 .get_temperature = &evergreen_get_temp,
1583 },
1584 .pflip = {
1585 .pre_page_flip = &evergreen_pre_page_flip,
1586 .page_flip = &evergreen_page_flip,
1587 .post_page_flip = &evergreen_post_page_flip,
1588 },
1589 };
1590
1591 static struct radeon_asic cayman_asic = {
1592 .init = &cayman_init,
1593 .fini = &cayman_fini,
1594 .suspend = &cayman_suspend,
1595 .resume = &cayman_resume,
1596 .asic_reset = &cayman_asic_reset,
1597 .vga_set_state = &r600_vga_set_state,
1598 .ioctl_wait_idle = r600_ioctl_wait_idle,
1599 .gui_idle = &r600_gui_idle,
1600 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1601 .get_xclk = &rv770_get_xclk,
1602 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1603 .gart = {
1604 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1605 .set_page = &rs600_gart_set_page,
1606 },
1607 .vm = {
1608 .init = &cayman_vm_init,
1609 .fini = &cayman_vm_fini,
1610 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1611 .set_page = &cayman_vm_set_page,
1612 },
1613 .ring = {
1614 [RADEON_RING_TYPE_GFX_INDEX] = {
1615 .ib_execute = &cayman_ring_ib_execute,
1616 .ib_parse = &evergreen_ib_parse,
1617 .emit_fence = &cayman_fence_ring_emit,
1618 .emit_semaphore = &r600_semaphore_ring_emit,
1619 .cs_parse = &evergreen_cs_parse,
1620 .ring_test = &r600_ring_test,
1621 .ib_test = &r600_ib_test,
1622 .is_lockup = &cayman_gfx_is_lockup,
1623 .vm_flush = &cayman_vm_flush,
1624 .get_rptr = &radeon_ring_generic_get_rptr,
1625 .get_wptr = &radeon_ring_generic_get_wptr,
1626 .set_wptr = &radeon_ring_generic_set_wptr,
1627 },
1628 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1629 .ib_execute = &cayman_ring_ib_execute,
1630 .ib_parse = &evergreen_ib_parse,
1631 .emit_fence = &cayman_fence_ring_emit,
1632 .emit_semaphore = &r600_semaphore_ring_emit,
1633 .cs_parse = &evergreen_cs_parse,
1634 .ring_test = &r600_ring_test,
1635 .ib_test = &r600_ib_test,
1636 .is_lockup = &cayman_gfx_is_lockup,
1637 .vm_flush = &cayman_vm_flush,
1638 .get_rptr = &radeon_ring_generic_get_rptr,
1639 .get_wptr = &radeon_ring_generic_get_wptr,
1640 .set_wptr = &radeon_ring_generic_set_wptr,
1641 },
1642 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1643 .ib_execute = &cayman_ring_ib_execute,
1644 .ib_parse = &evergreen_ib_parse,
1645 .emit_fence = &cayman_fence_ring_emit,
1646 .emit_semaphore = &r600_semaphore_ring_emit,
1647 .cs_parse = &evergreen_cs_parse,
1648 .ring_test = &r600_ring_test,
1649 .ib_test = &r600_ib_test,
1650 .is_lockup = &cayman_gfx_is_lockup,
1651 .vm_flush = &cayman_vm_flush,
1652 .get_rptr = &radeon_ring_generic_get_rptr,
1653 .get_wptr = &radeon_ring_generic_get_wptr,
1654 .set_wptr = &radeon_ring_generic_set_wptr,
1655 },
1656 [R600_RING_TYPE_DMA_INDEX] = {
1657 .ib_execute = &cayman_dma_ring_ib_execute,
1658 .ib_parse = &evergreen_dma_ib_parse,
1659 .emit_fence = &evergreen_dma_fence_ring_emit,
1660 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1661 .cs_parse = &evergreen_dma_cs_parse,
1662 .ring_test = &r600_dma_ring_test,
1663 .ib_test = &r600_dma_ib_test,
1664 .is_lockup = &cayman_dma_is_lockup,
1665 .vm_flush = &cayman_dma_vm_flush,
1666 .get_rptr = &radeon_ring_generic_get_rptr,
1667 .get_wptr = &radeon_ring_generic_get_wptr,
1668 .set_wptr = &radeon_ring_generic_set_wptr,
1669 },
1670 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1671 .ib_execute = &cayman_dma_ring_ib_execute,
1672 .ib_parse = &evergreen_dma_ib_parse,
1673 .emit_fence = &evergreen_dma_fence_ring_emit,
1674 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1675 .cs_parse = &evergreen_dma_cs_parse,
1676 .ring_test = &r600_dma_ring_test,
1677 .ib_test = &r600_dma_ib_test,
1678 .is_lockup = &cayman_dma_is_lockup,
1679 .vm_flush = &cayman_dma_vm_flush,
1680 .get_rptr = &radeon_ring_generic_get_rptr,
1681 .get_wptr = &radeon_ring_generic_get_wptr,
1682 .set_wptr = &radeon_ring_generic_set_wptr,
1683 },
1684 [R600_RING_TYPE_UVD_INDEX] = {
1685 .ib_execute = &r600_uvd_ib_execute,
1686 .emit_fence = &r600_uvd_fence_emit,
1687 .emit_semaphore = &cayman_uvd_semaphore_emit,
1688 .cs_parse = &radeon_uvd_cs_parse,
1689 .ring_test = &r600_uvd_ring_test,
1690 .ib_test = &r600_uvd_ib_test,
1691 .is_lockup = &radeon_ring_test_lockup,
1692 .get_rptr = &radeon_ring_generic_get_rptr,
1693 .get_wptr = &radeon_ring_generic_get_wptr,
1694 .set_wptr = &radeon_ring_generic_set_wptr,
1695 }
1696 },
1697 .irq = {
1698 .set = &evergreen_irq_set,
1699 .process = &evergreen_irq_process,
1700 },
1701 .display = {
1702 .bandwidth_update = &evergreen_bandwidth_update,
1703 .get_vblank_counter = &evergreen_get_vblank_counter,
1704 .wait_for_vblank = &dce4_wait_for_vblank,
1705 .set_backlight_level = &atombios_set_backlight_level,
1706 .get_backlight_level = &atombios_get_backlight_level,
1707 .hdmi_enable = &evergreen_hdmi_enable,
1708 .hdmi_setmode = &evergreen_hdmi_setmode,
1709 },
1710 .copy = {
1711 .blit = &r600_copy_blit,
1712 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1713 .dma = &evergreen_copy_dma,
1714 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1715 .copy = &evergreen_copy_dma,
1716 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1717 },
1718 .surface = {
1719 .set_reg = r600_set_surface_reg,
1720 .clear_reg = r600_clear_surface_reg,
1721 },
1722 .hpd = {
1723 .init = &evergreen_hpd_init,
1724 .fini = &evergreen_hpd_fini,
1725 .sense = &evergreen_hpd_sense,
1726 .set_polarity = &evergreen_hpd_set_polarity,
1727 },
1728 .pm = {
1729 .misc = &evergreen_pm_misc,
1730 .prepare = &evergreen_pm_prepare,
1731 .finish = &evergreen_pm_finish,
1732 .init_profile = &btc_pm_init_profile,
1733 .get_dynpm_state = &r600_pm_get_dynpm_state,
1734 .get_engine_clock = &radeon_atom_get_engine_clock,
1735 .set_engine_clock = &radeon_atom_set_engine_clock,
1736 .get_memory_clock = &radeon_atom_get_memory_clock,
1737 .set_memory_clock = &radeon_atom_set_memory_clock,
1738 .get_pcie_lanes = &r600_get_pcie_lanes,
1739 .set_pcie_lanes = &r600_set_pcie_lanes,
1740 .set_clock_gating = NULL,
1741 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1742 .get_temperature = &evergreen_get_temp,
1743 },
1744 .pflip = {
1745 .pre_page_flip = &evergreen_pre_page_flip,
1746 .page_flip = &evergreen_page_flip,
1747 .post_page_flip = &evergreen_post_page_flip,
1748 },
1749 };
1750
1751 static struct radeon_asic trinity_asic = {
1752 .init = &cayman_init,
1753 .fini = &cayman_fini,
1754 .suspend = &cayman_suspend,
1755 .resume = &cayman_resume,
1756 .asic_reset = &cayman_asic_reset,
1757 .vga_set_state = &r600_vga_set_state,
1758 .ioctl_wait_idle = r600_ioctl_wait_idle,
1759 .gui_idle = &r600_gui_idle,
1760 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1761 .get_xclk = &r600_get_xclk,
1762 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1763 .gart = {
1764 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1765 .set_page = &rs600_gart_set_page,
1766 },
1767 .vm = {
1768 .init = &cayman_vm_init,
1769 .fini = &cayman_vm_fini,
1770 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1771 .set_page = &cayman_vm_set_page,
1772 },
1773 .ring = {
1774 [RADEON_RING_TYPE_GFX_INDEX] = {
1775 .ib_execute = &cayman_ring_ib_execute,
1776 .ib_parse = &evergreen_ib_parse,
1777 .emit_fence = &cayman_fence_ring_emit,
1778 .emit_semaphore = &r600_semaphore_ring_emit,
1779 .cs_parse = &evergreen_cs_parse,
1780 .ring_test = &r600_ring_test,
1781 .ib_test = &r600_ib_test,
1782 .is_lockup = &cayman_gfx_is_lockup,
1783 .vm_flush = &cayman_vm_flush,
1784 .get_rptr = &radeon_ring_generic_get_rptr,
1785 .get_wptr = &radeon_ring_generic_get_wptr,
1786 .set_wptr = &radeon_ring_generic_set_wptr,
1787 },
1788 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1789 .ib_execute = &cayman_ring_ib_execute,
1790 .ib_parse = &evergreen_ib_parse,
1791 .emit_fence = &cayman_fence_ring_emit,
1792 .emit_semaphore = &r600_semaphore_ring_emit,
1793 .cs_parse = &evergreen_cs_parse,
1794 .ring_test = &r600_ring_test,
1795 .ib_test = &r600_ib_test,
1796 .is_lockup = &cayman_gfx_is_lockup,
1797 .vm_flush = &cayman_vm_flush,
1798 .get_rptr = &radeon_ring_generic_get_rptr,
1799 .get_wptr = &radeon_ring_generic_get_wptr,
1800 .set_wptr = &radeon_ring_generic_set_wptr,
1801 },
1802 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1803 .ib_execute = &cayman_ring_ib_execute,
1804 .ib_parse = &evergreen_ib_parse,
1805 .emit_fence = &cayman_fence_ring_emit,
1806 .emit_semaphore = &r600_semaphore_ring_emit,
1807 .cs_parse = &evergreen_cs_parse,
1808 .ring_test = &r600_ring_test,
1809 .ib_test = &r600_ib_test,
1810 .is_lockup = &cayman_gfx_is_lockup,
1811 .vm_flush = &cayman_vm_flush,
1812 .get_rptr = &radeon_ring_generic_get_rptr,
1813 .get_wptr = &radeon_ring_generic_get_wptr,
1814 .set_wptr = &radeon_ring_generic_set_wptr,
1815 },
1816 [R600_RING_TYPE_DMA_INDEX] = {
1817 .ib_execute = &cayman_dma_ring_ib_execute,
1818 .ib_parse = &evergreen_dma_ib_parse,
1819 .emit_fence = &evergreen_dma_fence_ring_emit,
1820 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1821 .cs_parse = &evergreen_dma_cs_parse,
1822 .ring_test = &r600_dma_ring_test,
1823 .ib_test = &r600_dma_ib_test,
1824 .is_lockup = &cayman_dma_is_lockup,
1825 .vm_flush = &cayman_dma_vm_flush,
1826 .get_rptr = &radeon_ring_generic_get_rptr,
1827 .get_wptr = &radeon_ring_generic_get_wptr,
1828 .set_wptr = &radeon_ring_generic_set_wptr,
1829 },
1830 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1831 .ib_execute = &cayman_dma_ring_ib_execute,
1832 .ib_parse = &evergreen_dma_ib_parse,
1833 .emit_fence = &evergreen_dma_fence_ring_emit,
1834 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1835 .cs_parse = &evergreen_dma_cs_parse,
1836 .ring_test = &r600_dma_ring_test,
1837 .ib_test = &r600_dma_ib_test,
1838 .is_lockup = &cayman_dma_is_lockup,
1839 .vm_flush = &cayman_dma_vm_flush,
1840 .get_rptr = &radeon_ring_generic_get_rptr,
1841 .get_wptr = &radeon_ring_generic_get_wptr,
1842 .set_wptr = &radeon_ring_generic_set_wptr,
1843 },
1844 [R600_RING_TYPE_UVD_INDEX] = {
1845 .ib_execute = &r600_uvd_ib_execute,
1846 .emit_fence = &r600_uvd_fence_emit,
1847 .emit_semaphore = &cayman_uvd_semaphore_emit,
1848 .cs_parse = &radeon_uvd_cs_parse,
1849 .ring_test = &r600_uvd_ring_test,
1850 .ib_test = &r600_uvd_ib_test,
1851 .is_lockup = &radeon_ring_test_lockup,
1852 .get_rptr = &radeon_ring_generic_get_rptr,
1853 .get_wptr = &radeon_ring_generic_get_wptr,
1854 .set_wptr = &radeon_ring_generic_set_wptr,
1855 }
1856 },
1857 .irq = {
1858 .set = &evergreen_irq_set,
1859 .process = &evergreen_irq_process,
1860 },
1861 .display = {
1862 .bandwidth_update = &dce6_bandwidth_update,
1863 .get_vblank_counter = &evergreen_get_vblank_counter,
1864 .wait_for_vblank = &dce4_wait_for_vblank,
1865 .set_backlight_level = &atombios_set_backlight_level,
1866 .get_backlight_level = &atombios_get_backlight_level,
1867 },
1868 .copy = {
1869 .blit = &r600_copy_blit,
1870 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1871 .dma = &evergreen_copy_dma,
1872 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1873 .copy = &evergreen_copy_dma,
1874 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1875 },
1876 .surface = {
1877 .set_reg = r600_set_surface_reg,
1878 .clear_reg = r600_clear_surface_reg,
1879 },
1880 .hpd = {
1881 .init = &evergreen_hpd_init,
1882 .fini = &evergreen_hpd_fini,
1883 .sense = &evergreen_hpd_sense,
1884 .set_polarity = &evergreen_hpd_set_polarity,
1885 },
1886 .pm = {
1887 .misc = &evergreen_pm_misc,
1888 .prepare = &evergreen_pm_prepare,
1889 .finish = &evergreen_pm_finish,
1890 .init_profile = &sumo_pm_init_profile,
1891 .get_dynpm_state = &r600_pm_get_dynpm_state,
1892 .get_engine_clock = &radeon_atom_get_engine_clock,
1893 .set_engine_clock = &radeon_atom_set_engine_clock,
1894 .get_memory_clock = NULL,
1895 .set_memory_clock = NULL,
1896 .get_pcie_lanes = NULL,
1897 .set_pcie_lanes = NULL,
1898 .set_clock_gating = NULL,
1899 .set_uvd_clocks = &sumo_set_uvd_clocks,
1900 },
1901 .pflip = {
1902 .pre_page_flip = &evergreen_pre_page_flip,
1903 .page_flip = &evergreen_page_flip,
1904 .post_page_flip = &evergreen_post_page_flip,
1905 },
1906 };
1907
1908 static struct radeon_asic si_asic = {
1909 .init = &si_init,
1910 .fini = &si_fini,
1911 .suspend = &si_suspend,
1912 .resume = &si_resume,
1913 .asic_reset = &si_asic_reset,
1914 .vga_set_state = &r600_vga_set_state,
1915 .ioctl_wait_idle = r600_ioctl_wait_idle,
1916 .gui_idle = &r600_gui_idle,
1917 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1918 .get_xclk = &si_get_xclk,
1919 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1920 .gart = {
1921 .tlb_flush = &si_pcie_gart_tlb_flush,
1922 .set_page = &rs600_gart_set_page,
1923 },
1924 .vm = {
1925 .init = &si_vm_init,
1926 .fini = &si_vm_fini,
1927 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1928 .set_page = &si_vm_set_page,
1929 },
1930 .ring = {
1931 [RADEON_RING_TYPE_GFX_INDEX] = {
1932 .ib_execute = &si_ring_ib_execute,
1933 .ib_parse = &si_ib_parse,
1934 .emit_fence = &si_fence_ring_emit,
1935 .emit_semaphore = &r600_semaphore_ring_emit,
1936 .cs_parse = NULL,
1937 .ring_test = &r600_ring_test,
1938 .ib_test = &r600_ib_test,
1939 .is_lockup = &si_gfx_is_lockup,
1940 .vm_flush = &si_vm_flush,
1941 .get_rptr = &radeon_ring_generic_get_rptr,
1942 .get_wptr = &radeon_ring_generic_get_wptr,
1943 .set_wptr = &radeon_ring_generic_set_wptr,
1944 },
1945 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1946 .ib_execute = &si_ring_ib_execute,
1947 .ib_parse = &si_ib_parse,
1948 .emit_fence = &si_fence_ring_emit,
1949 .emit_semaphore = &r600_semaphore_ring_emit,
1950 .cs_parse = NULL,
1951 .ring_test = &r600_ring_test,
1952 .ib_test = &r600_ib_test,
1953 .is_lockup = &si_gfx_is_lockup,
1954 .vm_flush = &si_vm_flush,
1955 .get_rptr = &radeon_ring_generic_get_rptr,
1956 .get_wptr = &radeon_ring_generic_get_wptr,
1957 .set_wptr = &radeon_ring_generic_set_wptr,
1958 },
1959 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1960 .ib_execute = &si_ring_ib_execute,
1961 .ib_parse = &si_ib_parse,
1962 .emit_fence = &si_fence_ring_emit,
1963 .emit_semaphore = &r600_semaphore_ring_emit,
1964 .cs_parse = NULL,
1965 .ring_test = &r600_ring_test,
1966 .ib_test = &r600_ib_test,
1967 .is_lockup = &si_gfx_is_lockup,
1968 .vm_flush = &si_vm_flush,
1969 .get_rptr = &radeon_ring_generic_get_rptr,
1970 .get_wptr = &radeon_ring_generic_get_wptr,
1971 .set_wptr = &radeon_ring_generic_set_wptr,
1972 },
1973 [R600_RING_TYPE_DMA_INDEX] = {
1974 .ib_execute = &cayman_dma_ring_ib_execute,
1975 .ib_parse = &evergreen_dma_ib_parse,
1976 .emit_fence = &evergreen_dma_fence_ring_emit,
1977 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1978 .cs_parse = NULL,
1979 .ring_test = &r600_dma_ring_test,
1980 .ib_test = &r600_dma_ib_test,
1981 .is_lockup = &si_dma_is_lockup,
1982 .vm_flush = &si_dma_vm_flush,
1983 .get_rptr = &radeon_ring_generic_get_rptr,
1984 .get_wptr = &radeon_ring_generic_get_wptr,
1985 .set_wptr = &radeon_ring_generic_set_wptr,
1986 },
1987 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1988 .ib_execute = &cayman_dma_ring_ib_execute,
1989 .ib_parse = &evergreen_dma_ib_parse,
1990 .emit_fence = &evergreen_dma_fence_ring_emit,
1991 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1992 .cs_parse = NULL,
1993 .ring_test = &r600_dma_ring_test,
1994 .ib_test = &r600_dma_ib_test,
1995 .is_lockup = &si_dma_is_lockup,
1996 .vm_flush = &si_dma_vm_flush,
1997 .get_rptr = &radeon_ring_generic_get_rptr,
1998 .get_wptr = &radeon_ring_generic_get_wptr,
1999 .set_wptr = &radeon_ring_generic_set_wptr,
2000 },
2001 [R600_RING_TYPE_UVD_INDEX] = {
2002 .ib_execute = &r600_uvd_ib_execute,
2003 .emit_fence = &r600_uvd_fence_emit,
2004 .emit_semaphore = &cayman_uvd_semaphore_emit,
2005 .cs_parse = &radeon_uvd_cs_parse,
2006 .ring_test = &r600_uvd_ring_test,
2007 .ib_test = &r600_uvd_ib_test,
2008 .is_lockup = &radeon_ring_test_lockup,
2009 .get_rptr = &radeon_ring_generic_get_rptr,
2010 .get_wptr = &radeon_ring_generic_get_wptr,
2011 .set_wptr = &radeon_ring_generic_set_wptr,
2012 }
2013 },
2014 .irq = {
2015 .set = &si_irq_set,
2016 .process = &si_irq_process,
2017 },
2018 .display = {
2019 .bandwidth_update = &dce6_bandwidth_update,
2020 .get_vblank_counter = &evergreen_get_vblank_counter,
2021 .wait_for_vblank = &dce4_wait_for_vblank,
2022 .set_backlight_level = &atombios_set_backlight_level,
2023 .get_backlight_level = &atombios_get_backlight_level,
2024 },
2025 .copy = {
2026 .blit = NULL,
2027 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2028 .dma = &si_copy_dma,
2029 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2030 .copy = &si_copy_dma,
2031 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2032 },
2033 .surface = {
2034 .set_reg = r600_set_surface_reg,
2035 .clear_reg = r600_clear_surface_reg,
2036 },
2037 .hpd = {
2038 .init = &evergreen_hpd_init,
2039 .fini = &evergreen_hpd_fini,
2040 .sense = &evergreen_hpd_sense,
2041 .set_polarity = &evergreen_hpd_set_polarity,
2042 },
2043 .pm = {
2044 .misc = &evergreen_pm_misc,
2045 .prepare = &evergreen_pm_prepare,
2046 .finish = &evergreen_pm_finish,
2047 .init_profile = &sumo_pm_init_profile,
2048 .get_dynpm_state = &r600_pm_get_dynpm_state,
2049 .get_engine_clock = &radeon_atom_get_engine_clock,
2050 .set_engine_clock = &radeon_atom_set_engine_clock,
2051 .get_memory_clock = &radeon_atom_get_memory_clock,
2052 .set_memory_clock = &radeon_atom_set_memory_clock,
2053 .get_pcie_lanes = &r600_get_pcie_lanes,
2054 .set_pcie_lanes = &r600_set_pcie_lanes,
2055 .set_clock_gating = NULL,
2056 .set_uvd_clocks = &si_set_uvd_clocks,
2057 .get_temperature = &si_get_temp,
2058 },
2059 .pflip = {
2060 .pre_page_flip = &evergreen_pre_page_flip,
2061 .page_flip = &evergreen_page_flip,
2062 .post_page_flip = &evergreen_post_page_flip,
2063 },
2064 };
2065
2066 static struct radeon_asic ci_asic = {
2067 .init = &cik_init,
2068 .fini = &cik_fini,
2069 .suspend = &cik_suspend,
2070 .resume = &cik_resume,
2071 .asic_reset = &cik_asic_reset,
2072 .vga_set_state = &r600_vga_set_state,
2073 .ioctl_wait_idle = NULL,
2074 .gui_idle = &r600_gui_idle,
2075 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2076 .get_xclk = &cik_get_xclk,
2077 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2078 .gart = {
2079 .tlb_flush = &cik_pcie_gart_tlb_flush,
2080 .set_page = &rs600_gart_set_page,
2081 },
2082 .vm = {
2083 .init = &cik_vm_init,
2084 .fini = &cik_vm_fini,
2085 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2086 .set_page = &cik_vm_set_page,
2087 },
2088 .ring = {
2089 [RADEON_RING_TYPE_GFX_INDEX] = {
2090 .ib_execute = &cik_ring_ib_execute,
2091 .ib_parse = &cik_ib_parse,
2092 .emit_fence = &cik_fence_gfx_ring_emit,
2093 .emit_semaphore = &cik_semaphore_ring_emit,
2094 .cs_parse = NULL,
2095 .ring_test = &cik_ring_test,
2096 .ib_test = &cik_ib_test,
2097 .is_lockup = &cik_gfx_is_lockup,
2098 .vm_flush = &cik_vm_flush,
2099 .get_rptr = &radeon_ring_generic_get_rptr,
2100 .get_wptr = &radeon_ring_generic_get_wptr,
2101 .set_wptr = &radeon_ring_generic_set_wptr,
2102 },
2103 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2104 .ib_execute = &cik_ring_ib_execute,
2105 .ib_parse = &cik_ib_parse,
2106 .emit_fence = &cik_fence_compute_ring_emit,
2107 .emit_semaphore = &cik_semaphore_ring_emit,
2108 .cs_parse = NULL,
2109 .ring_test = &cik_ring_test,
2110 .ib_test = &cik_ib_test,
2111 .is_lockup = &cik_gfx_is_lockup,
2112 .vm_flush = &cik_vm_flush,
2113 .get_rptr = &cik_compute_ring_get_rptr,
2114 .get_wptr = &cik_compute_ring_get_wptr,
2115 .set_wptr = &cik_compute_ring_set_wptr,
2116 },
2117 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2118 .ib_execute = &cik_ring_ib_execute,
2119 .ib_parse = &cik_ib_parse,
2120 .emit_fence = &cik_fence_compute_ring_emit,
2121 .emit_semaphore = &cik_semaphore_ring_emit,
2122 .cs_parse = NULL,
2123 .ring_test = &cik_ring_test,
2124 .ib_test = &cik_ib_test,
2125 .is_lockup = &cik_gfx_is_lockup,
2126 .vm_flush = &cik_vm_flush,
2127 .get_rptr = &cik_compute_ring_get_rptr,
2128 .get_wptr = &cik_compute_ring_get_wptr,
2129 .set_wptr = &cik_compute_ring_set_wptr,
2130 },
2131 [R600_RING_TYPE_DMA_INDEX] = {
2132 .ib_execute = &cik_sdma_ring_ib_execute,
2133 .ib_parse = &cik_ib_parse,
2134 .emit_fence = &cik_sdma_fence_ring_emit,
2135 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2136 .cs_parse = NULL,
2137 .ring_test = &cik_sdma_ring_test,
2138 .ib_test = &cik_sdma_ib_test,
2139 .is_lockup = &cik_sdma_is_lockup,
2140 .vm_flush = &cik_dma_vm_flush,
2141 .get_rptr = &radeon_ring_generic_get_rptr,
2142 .get_wptr = &radeon_ring_generic_get_wptr,
2143 .set_wptr = &radeon_ring_generic_set_wptr,
2144 },
2145 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2146 .ib_execute = &cik_sdma_ring_ib_execute,
2147 .ib_parse = &cik_ib_parse,
2148 .emit_fence = &cik_sdma_fence_ring_emit,
2149 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2150 .cs_parse = NULL,
2151 .ring_test = &cik_sdma_ring_test,
2152 .ib_test = &cik_sdma_ib_test,
2153 .is_lockup = &cik_sdma_is_lockup,
2154 .vm_flush = &cik_dma_vm_flush,
2155 .get_rptr = &radeon_ring_generic_get_rptr,
2156 .get_wptr = &radeon_ring_generic_get_wptr,
2157 .set_wptr = &radeon_ring_generic_set_wptr,
2158 },
2159 [R600_RING_TYPE_UVD_INDEX] = {
2160 .ib_execute = &r600_uvd_ib_execute,
2161 .emit_fence = &r600_uvd_fence_emit,
2162 .emit_semaphore = &cayman_uvd_semaphore_emit,
2163 .cs_parse = &radeon_uvd_cs_parse,
2164 .ring_test = &r600_uvd_ring_test,
2165 .ib_test = &r600_uvd_ib_test,
2166 .is_lockup = &radeon_ring_test_lockup,
2167 .get_rptr = &radeon_ring_generic_get_rptr,
2168 .get_wptr = &radeon_ring_generic_get_wptr,
2169 .set_wptr = &radeon_ring_generic_set_wptr,
2170 }
2171 },
2172 .irq = {
2173 .set = &cik_irq_set,
2174 .process = &cik_irq_process,
2175 },
2176 .display = {
2177 .bandwidth_update = &dce8_bandwidth_update,
2178 .get_vblank_counter = &evergreen_get_vblank_counter,
2179 .wait_for_vblank = &dce4_wait_for_vblank,
2180 },
2181 .copy = {
2182 .blit = NULL,
2183 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2184 .dma = &cik_copy_dma,
2185 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2186 .copy = &cik_copy_dma,
2187 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2188 },
2189 .surface = {
2190 .set_reg = r600_set_surface_reg,
2191 .clear_reg = r600_clear_surface_reg,
2192 },
2193 .hpd = {
2194 .init = &evergreen_hpd_init,
2195 .fini = &evergreen_hpd_fini,
2196 .sense = &evergreen_hpd_sense,
2197 .set_polarity = &evergreen_hpd_set_polarity,
2198 },
2199 .pm = {
2200 .misc = &evergreen_pm_misc,
2201 .prepare = &evergreen_pm_prepare,
2202 .finish = &evergreen_pm_finish,
2203 .init_profile = &sumo_pm_init_profile,
2204 .get_dynpm_state = &r600_pm_get_dynpm_state,
2205 .get_engine_clock = &radeon_atom_get_engine_clock,
2206 .set_engine_clock = &radeon_atom_set_engine_clock,
2207 .get_memory_clock = &radeon_atom_get_memory_clock,
2208 .set_memory_clock = &radeon_atom_set_memory_clock,
2209 .get_pcie_lanes = NULL,
2210 .set_pcie_lanes = NULL,
2211 .set_clock_gating = NULL,
2212 .set_uvd_clocks = &cik_set_uvd_clocks,
2213 },
2214 .pflip = {
2215 .pre_page_flip = &evergreen_pre_page_flip,
2216 .page_flip = &evergreen_page_flip,
2217 .post_page_flip = &evergreen_post_page_flip,
2218 },
2219 };
2220
2221 static struct radeon_asic kv_asic = {
2222 .init = &cik_init,
2223 .fini = &cik_fini,
2224 .suspend = &cik_suspend,
2225 .resume = &cik_resume,
2226 .asic_reset = &cik_asic_reset,
2227 .vga_set_state = &r600_vga_set_state,
2228 .ioctl_wait_idle = NULL,
2229 .gui_idle = &r600_gui_idle,
2230 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2231 .get_xclk = &cik_get_xclk,
2232 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2233 .gart = {
2234 .tlb_flush = &cik_pcie_gart_tlb_flush,
2235 .set_page = &rs600_gart_set_page,
2236 },
2237 .vm = {
2238 .init = &cik_vm_init,
2239 .fini = &cik_vm_fini,
2240 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2241 .set_page = &cik_vm_set_page,
2242 },
2243 .ring = {
2244 [RADEON_RING_TYPE_GFX_INDEX] = {
2245 .ib_execute = &cik_ring_ib_execute,
2246 .ib_parse = &cik_ib_parse,
2247 .emit_fence = &cik_fence_gfx_ring_emit,
2248 .emit_semaphore = &cik_semaphore_ring_emit,
2249 .cs_parse = NULL,
2250 .ring_test = &cik_ring_test,
2251 .ib_test = &cik_ib_test,
2252 .is_lockup = &cik_gfx_is_lockup,
2253 .vm_flush = &cik_vm_flush,
2254 .get_rptr = &radeon_ring_generic_get_rptr,
2255 .get_wptr = &radeon_ring_generic_get_wptr,
2256 .set_wptr = &radeon_ring_generic_set_wptr,
2257 },
2258 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2259 .ib_execute = &cik_ring_ib_execute,
2260 .ib_parse = &cik_ib_parse,
2261 .emit_fence = &cik_fence_compute_ring_emit,
2262 .emit_semaphore = &cik_semaphore_ring_emit,
2263 .cs_parse = NULL,
2264 .ring_test = &cik_ring_test,
2265 .ib_test = &cik_ib_test,
2266 .is_lockup = &cik_gfx_is_lockup,
2267 .vm_flush = &cik_vm_flush,
2268 .get_rptr = &cik_compute_ring_get_rptr,
2269 .get_wptr = &cik_compute_ring_get_wptr,
2270 .set_wptr = &cik_compute_ring_set_wptr,
2271 },
2272 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2273 .ib_execute = &cik_ring_ib_execute,
2274 .ib_parse = &cik_ib_parse,
2275 .emit_fence = &cik_fence_compute_ring_emit,
2276 .emit_semaphore = &cik_semaphore_ring_emit,
2277 .cs_parse = NULL,
2278 .ring_test = &cik_ring_test,
2279 .ib_test = &cik_ib_test,
2280 .is_lockup = &cik_gfx_is_lockup,
2281 .vm_flush = &cik_vm_flush,
2282 .get_rptr = &cik_compute_ring_get_rptr,
2283 .get_wptr = &cik_compute_ring_get_wptr,
2284 .set_wptr = &cik_compute_ring_set_wptr,
2285 },
2286 [R600_RING_TYPE_DMA_INDEX] = {
2287 .ib_execute = &cik_sdma_ring_ib_execute,
2288 .ib_parse = &cik_ib_parse,
2289 .emit_fence = &cik_sdma_fence_ring_emit,
2290 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2291 .cs_parse = NULL,
2292 .ring_test = &cik_sdma_ring_test,
2293 .ib_test = &cik_sdma_ib_test,
2294 .is_lockup = &cik_sdma_is_lockup,
2295 .vm_flush = &cik_dma_vm_flush,
2296 .get_rptr = &radeon_ring_generic_get_rptr,
2297 .get_wptr = &radeon_ring_generic_get_wptr,
2298 .set_wptr = &radeon_ring_generic_set_wptr,
2299 },
2300 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2301 .ib_execute = &cik_sdma_ring_ib_execute,
2302 .ib_parse = &cik_ib_parse,
2303 .emit_fence = &cik_sdma_fence_ring_emit,
2304 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2305 .cs_parse = NULL,
2306 .ring_test = &cik_sdma_ring_test,
2307 .ib_test = &cik_sdma_ib_test,
2308 .is_lockup = &cik_sdma_is_lockup,
2309 .vm_flush = &cik_dma_vm_flush,
2310 .get_rptr = &radeon_ring_generic_get_rptr,
2311 .get_wptr = &radeon_ring_generic_get_wptr,
2312 .set_wptr = &radeon_ring_generic_set_wptr,
2313 },
2314 [R600_RING_TYPE_UVD_INDEX] = {
2315 .ib_execute = &r600_uvd_ib_execute,
2316 .emit_fence = &r600_uvd_fence_emit,
2317 .emit_semaphore = &cayman_uvd_semaphore_emit,
2318 .cs_parse = &radeon_uvd_cs_parse,
2319 .ring_test = &r600_uvd_ring_test,
2320 .ib_test = &r600_uvd_ib_test,
2321 .is_lockup = &radeon_ring_test_lockup,
2322 .get_rptr = &radeon_ring_generic_get_rptr,
2323 .get_wptr = &radeon_ring_generic_get_wptr,
2324 .set_wptr = &radeon_ring_generic_set_wptr,
2325 }
2326 },
2327 .irq = {
2328 .set = &cik_irq_set,
2329 .process = &cik_irq_process,
2330 },
2331 .display = {
2332 .bandwidth_update = &dce8_bandwidth_update,
2333 .get_vblank_counter = &evergreen_get_vblank_counter,
2334 .wait_for_vblank = &dce4_wait_for_vblank,
2335 },
2336 .copy = {
2337 .blit = NULL,
2338 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2339 .dma = &cik_copy_dma,
2340 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2341 .copy = &cik_copy_dma,
2342 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2343 },
2344 .surface = {
2345 .set_reg = r600_set_surface_reg,
2346 .clear_reg = r600_clear_surface_reg,
2347 },
2348 .hpd = {
2349 .init = &evergreen_hpd_init,
2350 .fini = &evergreen_hpd_fini,
2351 .sense = &evergreen_hpd_sense,
2352 .set_polarity = &evergreen_hpd_set_polarity,
2353 },
2354 .pm = {
2355 .misc = &evergreen_pm_misc,
2356 .prepare = &evergreen_pm_prepare,
2357 .finish = &evergreen_pm_finish,
2358 .init_profile = &sumo_pm_init_profile,
2359 .get_dynpm_state = &r600_pm_get_dynpm_state,
2360 .get_engine_clock = &radeon_atom_get_engine_clock,
2361 .set_engine_clock = &radeon_atom_set_engine_clock,
2362 .get_memory_clock = &radeon_atom_get_memory_clock,
2363 .set_memory_clock = &radeon_atom_set_memory_clock,
2364 .get_pcie_lanes = NULL,
2365 .set_pcie_lanes = NULL,
2366 .set_clock_gating = NULL,
2367 .set_uvd_clocks = &cik_set_uvd_clocks,
2368 },
2369 .pflip = {
2370 .pre_page_flip = &evergreen_pre_page_flip,
2371 .page_flip = &evergreen_page_flip,
2372 .post_page_flip = &evergreen_post_page_flip,
2373 },
2374 };
2375
2376 /**
2377 * radeon_asic_init - register asic specific callbacks
2378 *
2379 * @rdev: radeon device pointer
2380 *
2381 * Registers the appropriate asic specific callbacks for each
2382 * chip family. Also sets other asics specific info like the number
2383 * of crtcs and the register aperture accessors (all asics).
2384 * Returns 0 for success.
2385 */
2386 int radeon_asic_init(struct radeon_device *rdev)
2387 {
2388 radeon_register_accessor_init(rdev);
2389
2390 /* set the number of crtcs */
2391 if (rdev->flags & RADEON_SINGLE_CRTC)
2392 rdev->num_crtc = 1;
2393 else
2394 rdev->num_crtc = 2;
2395
2396 rdev->has_uvd = false;
2397
2398 switch (rdev->family) {
2399 case CHIP_R100:
2400 case CHIP_RV100:
2401 case CHIP_RS100:
2402 case CHIP_RV200:
2403 case CHIP_RS200:
2404 rdev->asic = &r100_asic;
2405 break;
2406 case CHIP_R200:
2407 case CHIP_RV250:
2408 case CHIP_RS300:
2409 case CHIP_RV280:
2410 rdev->asic = &r200_asic;
2411 break;
2412 case CHIP_R300:
2413 case CHIP_R350:
2414 case CHIP_RV350:
2415 case CHIP_RV380:
2416 if (rdev->flags & RADEON_IS_PCIE)
2417 rdev->asic = &r300_asic_pcie;
2418 else
2419 rdev->asic = &r300_asic;
2420 break;
2421 case CHIP_R420:
2422 case CHIP_R423:
2423 case CHIP_RV410:
2424 rdev->asic = &r420_asic;
2425 /* handle macs */
2426 if (rdev->bios == NULL) {
2427 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2428 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2429 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2430 rdev->asic->pm.set_memory_clock = NULL;
2431 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2432 }
2433 break;
2434 case CHIP_RS400:
2435 case CHIP_RS480:
2436 rdev->asic = &rs400_asic;
2437 break;
2438 case CHIP_RS600:
2439 rdev->asic = &rs600_asic;
2440 break;
2441 case CHIP_RS690:
2442 case CHIP_RS740:
2443 rdev->asic = &rs690_asic;
2444 break;
2445 case CHIP_RV515:
2446 rdev->asic = &rv515_asic;
2447 break;
2448 case CHIP_R520:
2449 case CHIP_RV530:
2450 case CHIP_RV560:
2451 case CHIP_RV570:
2452 case CHIP_R580:
2453 rdev->asic = &r520_asic;
2454 break;
2455 case CHIP_R600:
2456 case CHIP_RV610:
2457 case CHIP_RV630:
2458 case CHIP_RV620:
2459 case CHIP_RV635:
2460 case CHIP_RV670:
2461 rdev->asic = &r600_asic;
2462 if (rdev->family == CHIP_R600)
2463 rdev->has_uvd = false;
2464 else
2465 rdev->has_uvd = true;
2466 break;
2467 case CHIP_RS780:
2468 case CHIP_RS880:
2469 rdev->asic = &rs780_asic;
2470 rdev->has_uvd = true;
2471 break;
2472 case CHIP_RV770:
2473 case CHIP_RV730:
2474 case CHIP_RV710:
2475 case CHIP_RV740:
2476 rdev->asic = &rv770_asic;
2477 rdev->has_uvd = true;
2478 break;
2479 case CHIP_CEDAR:
2480 case CHIP_REDWOOD:
2481 case CHIP_JUNIPER:
2482 case CHIP_CYPRESS:
2483 case CHIP_HEMLOCK:
2484 /* set num crtcs */
2485 if (rdev->family == CHIP_CEDAR)
2486 rdev->num_crtc = 4;
2487 else
2488 rdev->num_crtc = 6;
2489 rdev->asic = &evergreen_asic;
2490 rdev->has_uvd = true;
2491 break;
2492 case CHIP_PALM:
2493 case CHIP_SUMO:
2494 case CHIP_SUMO2:
2495 rdev->asic = &sumo_asic;
2496 rdev->has_uvd = true;
2497 break;
2498 case CHIP_BARTS:
2499 case CHIP_TURKS:
2500 case CHIP_CAICOS:
2501 /* set num crtcs */
2502 if (rdev->family == CHIP_CAICOS)
2503 rdev->num_crtc = 4;
2504 else
2505 rdev->num_crtc = 6;
2506 rdev->asic = &btc_asic;
2507 rdev->has_uvd = true;
2508 break;
2509 case CHIP_CAYMAN:
2510 rdev->asic = &cayman_asic;
2511 /* set num crtcs */
2512 rdev->num_crtc = 6;
2513 rdev->has_uvd = true;
2514 break;
2515 case CHIP_ARUBA:
2516 rdev->asic = &trinity_asic;
2517 /* set num crtcs */
2518 rdev->num_crtc = 4;
2519 rdev->has_uvd = true;
2520 break;
2521 case CHIP_TAHITI:
2522 case CHIP_PITCAIRN:
2523 case CHIP_VERDE:
2524 case CHIP_OLAND:
2525 case CHIP_HAINAN:
2526 rdev->asic = &si_asic;
2527 /* set num crtcs */
2528 if (rdev->family == CHIP_HAINAN)
2529 rdev->num_crtc = 0;
2530 else if (rdev->family == CHIP_OLAND)
2531 rdev->num_crtc = 2;
2532 else
2533 rdev->num_crtc = 6;
2534 if (rdev->family == CHIP_HAINAN)
2535 rdev->has_uvd = false;
2536 else
2537 rdev->has_uvd = true;
2538 break;
2539 case CHIP_BONAIRE:
2540 rdev->asic = &ci_asic;
2541 rdev->num_crtc = 6;
2542 break;
2543 case CHIP_KAVERI:
2544 case CHIP_KABINI:
2545 rdev->asic = &kv_asic;
2546 /* set num crtcs */
2547 if (rdev->family == CHIP_KAVERI)
2548 rdev->num_crtc = 4;
2549 else
2550 rdev->num_crtc = 2;
2551 break;
2552 default:
2553 /* FIXME: not supported yet */
2554 return -EINVAL;
2555 }
2556
2557 if (rdev->flags & RADEON_IS_IGP) {
2558 rdev->asic->pm.get_memory_clock = NULL;
2559 rdev->asic->pm.set_memory_clock = NULL;
2560 }
2561
2562 return 0;
2563 }
2564
Linux kernel - Deliverables
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