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radeon/audio: consolidate audio_mode_set() functions
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <linux/console.h>
30 #include <drm/drmP.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
36 #include "radeon.h"
37 #include "radeon_asic.h"
38 #include "atom.h"
39
40 /*
41 * Registers accessors functions.
42 */
43 /**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54 {
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58 }
59
60 /**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71 {
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75 }
76
77 /**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
85 static void radeon_register_accessor_init(struct radeon_device *rdev)
86 {
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137 }
138
139
140 /* helper to disable agp */
141 /**
142 * radeon_agp_disable - AGP disable helper function
143 *
144 * @rdev: radeon device pointer
145 *
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
148 */
149 void radeon_agp_disable(struct radeon_device *rdev)
150 {
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
163 } else {
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
168 }
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170 }
171
172 /*
173 * ASIC
174 */
175
176 static struct radeon_asic_ring r100_gfx_ring = {
177 .ib_execute = &r100_ring_ib_execute,
178 .emit_fence = &r100_fence_ring_emit,
179 .emit_semaphore = &r100_semaphore_ring_emit,
180 .cs_parse = &r100_cs_parse,
181 .ring_start = &r100_ring_start,
182 .ring_test = &r100_ring_test,
183 .ib_test = &r100_ib_test,
184 .is_lockup = &r100_gpu_is_lockup,
185 .get_rptr = &r100_gfx_get_rptr,
186 .get_wptr = &r100_gfx_get_wptr,
187 .set_wptr = &r100_gfx_set_wptr,
188 };
189
190 static struct radeon_asic r100_asic = {
191 .init = &r100_init,
192 .fini = &r100_fini,
193 .suspend = &r100_suspend,
194 .resume = &r100_resume,
195 .vga_set_state = &r100_vga_set_state,
196 .asic_reset = &r100_asic_reset,
197 .mmio_hdp_flush = NULL,
198 .gui_idle = &r100_gui_idle,
199 .mc_wait_for_idle = &r100_mc_wait_for_idle,
200 .gart = {
201 .tlb_flush = &r100_pci_gart_tlb_flush,
202 .set_page = &r100_pci_gart_set_page,
203 },
204 .ring = {
205 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
206 },
207 .irq = {
208 .set = &r100_irq_set,
209 .process = &r100_irq_process,
210 },
211 .display = {
212 .bandwidth_update = &r100_bandwidth_update,
213 .get_vblank_counter = &r100_get_vblank_counter,
214 .wait_for_vblank = &r100_wait_for_vblank,
215 .set_backlight_level = &radeon_legacy_set_backlight_level,
216 .get_backlight_level = &radeon_legacy_get_backlight_level,
217 },
218 .copy = {
219 .blit = &r100_copy_blit,
220 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
221 .dma = NULL,
222 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
223 .copy = &r100_copy_blit,
224 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
225 },
226 .surface = {
227 .set_reg = r100_set_surface_reg,
228 .clear_reg = r100_clear_surface_reg,
229 },
230 .hpd = {
231 .init = &r100_hpd_init,
232 .fini = &r100_hpd_fini,
233 .sense = &r100_hpd_sense,
234 .set_polarity = &r100_hpd_set_polarity,
235 },
236 .pm = {
237 .misc = &r100_pm_misc,
238 .prepare = &r100_pm_prepare,
239 .finish = &r100_pm_finish,
240 .init_profile = &r100_pm_init_profile,
241 .get_dynpm_state = &r100_pm_get_dynpm_state,
242 .get_engine_clock = &radeon_legacy_get_engine_clock,
243 .set_engine_clock = &radeon_legacy_set_engine_clock,
244 .get_memory_clock = &radeon_legacy_get_memory_clock,
245 .set_memory_clock = NULL,
246 .get_pcie_lanes = NULL,
247 .set_pcie_lanes = NULL,
248 .set_clock_gating = &radeon_legacy_set_clock_gating,
249 },
250 .pflip = {
251 .page_flip = &r100_page_flip,
252 .page_flip_pending = &r100_page_flip_pending,
253 },
254 };
255
256 static struct radeon_asic r200_asic = {
257 .init = &r100_init,
258 .fini = &r100_fini,
259 .suspend = &r100_suspend,
260 .resume = &r100_resume,
261 .vga_set_state = &r100_vga_set_state,
262 .asic_reset = &r100_asic_reset,
263 .mmio_hdp_flush = NULL,
264 .gui_idle = &r100_gui_idle,
265 .mc_wait_for_idle = &r100_mc_wait_for_idle,
266 .gart = {
267 .tlb_flush = &r100_pci_gart_tlb_flush,
268 .set_page = &r100_pci_gart_set_page,
269 },
270 .ring = {
271 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
272 },
273 .irq = {
274 .set = &r100_irq_set,
275 .process = &r100_irq_process,
276 },
277 .display = {
278 .bandwidth_update = &r100_bandwidth_update,
279 .get_vblank_counter = &r100_get_vblank_counter,
280 .wait_for_vblank = &r100_wait_for_vblank,
281 .set_backlight_level = &radeon_legacy_set_backlight_level,
282 .get_backlight_level = &radeon_legacy_get_backlight_level,
283 },
284 .copy = {
285 .blit = &r100_copy_blit,
286 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
287 .dma = &r200_copy_dma,
288 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
289 .copy = &r100_copy_blit,
290 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
291 },
292 .surface = {
293 .set_reg = r100_set_surface_reg,
294 .clear_reg = r100_clear_surface_reg,
295 },
296 .hpd = {
297 .init = &r100_hpd_init,
298 .fini = &r100_hpd_fini,
299 .sense = &r100_hpd_sense,
300 .set_polarity = &r100_hpd_set_polarity,
301 },
302 .pm = {
303 .misc = &r100_pm_misc,
304 .prepare = &r100_pm_prepare,
305 .finish = &r100_pm_finish,
306 .init_profile = &r100_pm_init_profile,
307 .get_dynpm_state = &r100_pm_get_dynpm_state,
308 .get_engine_clock = &radeon_legacy_get_engine_clock,
309 .set_engine_clock = &radeon_legacy_set_engine_clock,
310 .get_memory_clock = &radeon_legacy_get_memory_clock,
311 .set_memory_clock = NULL,
312 .get_pcie_lanes = NULL,
313 .set_pcie_lanes = NULL,
314 .set_clock_gating = &radeon_legacy_set_clock_gating,
315 },
316 .pflip = {
317 .page_flip = &r100_page_flip,
318 .page_flip_pending = &r100_page_flip_pending,
319 },
320 };
321
322 static struct radeon_asic_ring r300_gfx_ring = {
323 .ib_execute = &r100_ring_ib_execute,
324 .emit_fence = &r300_fence_ring_emit,
325 .emit_semaphore = &r100_semaphore_ring_emit,
326 .cs_parse = &r300_cs_parse,
327 .ring_start = &r300_ring_start,
328 .ring_test = &r100_ring_test,
329 .ib_test = &r100_ib_test,
330 .is_lockup = &r100_gpu_is_lockup,
331 .get_rptr = &r100_gfx_get_rptr,
332 .get_wptr = &r100_gfx_get_wptr,
333 .set_wptr = &r100_gfx_set_wptr,
334 };
335
336 static struct radeon_asic_ring rv515_gfx_ring = {
337 .ib_execute = &r100_ring_ib_execute,
338 .emit_fence = &r300_fence_ring_emit,
339 .emit_semaphore = &r100_semaphore_ring_emit,
340 .cs_parse = &r300_cs_parse,
341 .ring_start = &rv515_ring_start,
342 .ring_test = &r100_ring_test,
343 .ib_test = &r100_ib_test,
344 .is_lockup = &r100_gpu_is_lockup,
345 .get_rptr = &r100_gfx_get_rptr,
346 .get_wptr = &r100_gfx_get_wptr,
347 .set_wptr = &r100_gfx_set_wptr,
348 };
349
350 static struct radeon_asic r300_asic = {
351 .init = &r300_init,
352 .fini = &r300_fini,
353 .suspend = &r300_suspend,
354 .resume = &r300_resume,
355 .vga_set_state = &r100_vga_set_state,
356 .asic_reset = &r300_asic_reset,
357 .mmio_hdp_flush = NULL,
358 .gui_idle = &r100_gui_idle,
359 .mc_wait_for_idle = &r300_mc_wait_for_idle,
360 .gart = {
361 .tlb_flush = &r100_pci_gart_tlb_flush,
362 .set_page = &r100_pci_gart_set_page,
363 },
364 .ring = {
365 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
366 },
367 .irq = {
368 .set = &r100_irq_set,
369 .process = &r100_irq_process,
370 },
371 .display = {
372 .bandwidth_update = &r100_bandwidth_update,
373 .get_vblank_counter = &r100_get_vblank_counter,
374 .wait_for_vblank = &r100_wait_for_vblank,
375 .set_backlight_level = &radeon_legacy_set_backlight_level,
376 .get_backlight_level = &radeon_legacy_get_backlight_level,
377 },
378 .copy = {
379 .blit = &r100_copy_blit,
380 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
381 .dma = &r200_copy_dma,
382 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
383 .copy = &r100_copy_blit,
384 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
385 },
386 .surface = {
387 .set_reg = r100_set_surface_reg,
388 .clear_reg = r100_clear_surface_reg,
389 },
390 .hpd = {
391 .init = &r100_hpd_init,
392 .fini = &r100_hpd_fini,
393 .sense = &r100_hpd_sense,
394 .set_polarity = &r100_hpd_set_polarity,
395 },
396 .pm = {
397 .misc = &r100_pm_misc,
398 .prepare = &r100_pm_prepare,
399 .finish = &r100_pm_finish,
400 .init_profile = &r100_pm_init_profile,
401 .get_dynpm_state = &r100_pm_get_dynpm_state,
402 .get_engine_clock = &radeon_legacy_get_engine_clock,
403 .set_engine_clock = &radeon_legacy_set_engine_clock,
404 .get_memory_clock = &radeon_legacy_get_memory_clock,
405 .set_memory_clock = NULL,
406 .get_pcie_lanes = &rv370_get_pcie_lanes,
407 .set_pcie_lanes = &rv370_set_pcie_lanes,
408 .set_clock_gating = &radeon_legacy_set_clock_gating,
409 },
410 .pflip = {
411 .page_flip = &r100_page_flip,
412 .page_flip_pending = &r100_page_flip_pending,
413 },
414 };
415
416 static struct radeon_asic r300_asic_pcie = {
417 .init = &r300_init,
418 .fini = &r300_fini,
419 .suspend = &r300_suspend,
420 .resume = &r300_resume,
421 .vga_set_state = &r100_vga_set_state,
422 .asic_reset = &r300_asic_reset,
423 .mmio_hdp_flush = NULL,
424 .gui_idle = &r100_gui_idle,
425 .mc_wait_for_idle = &r300_mc_wait_for_idle,
426 .gart = {
427 .tlb_flush = &rv370_pcie_gart_tlb_flush,
428 .set_page = &rv370_pcie_gart_set_page,
429 },
430 .ring = {
431 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
432 },
433 .irq = {
434 .set = &r100_irq_set,
435 .process = &r100_irq_process,
436 },
437 .display = {
438 .bandwidth_update = &r100_bandwidth_update,
439 .get_vblank_counter = &r100_get_vblank_counter,
440 .wait_for_vblank = &r100_wait_for_vblank,
441 .set_backlight_level = &radeon_legacy_set_backlight_level,
442 .get_backlight_level = &radeon_legacy_get_backlight_level,
443 },
444 .copy = {
445 .blit = &r100_copy_blit,
446 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
447 .dma = &r200_copy_dma,
448 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
449 .copy = &r100_copy_blit,
450 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
451 },
452 .surface = {
453 .set_reg = r100_set_surface_reg,
454 .clear_reg = r100_clear_surface_reg,
455 },
456 .hpd = {
457 .init = &r100_hpd_init,
458 .fini = &r100_hpd_fini,
459 .sense = &r100_hpd_sense,
460 .set_polarity = &r100_hpd_set_polarity,
461 },
462 .pm = {
463 .misc = &r100_pm_misc,
464 .prepare = &r100_pm_prepare,
465 .finish = &r100_pm_finish,
466 .init_profile = &r100_pm_init_profile,
467 .get_dynpm_state = &r100_pm_get_dynpm_state,
468 .get_engine_clock = &radeon_legacy_get_engine_clock,
469 .set_engine_clock = &radeon_legacy_set_engine_clock,
470 .get_memory_clock = &radeon_legacy_get_memory_clock,
471 .set_memory_clock = NULL,
472 .get_pcie_lanes = &rv370_get_pcie_lanes,
473 .set_pcie_lanes = &rv370_set_pcie_lanes,
474 .set_clock_gating = &radeon_legacy_set_clock_gating,
475 },
476 .pflip = {
477 .page_flip = &r100_page_flip,
478 .page_flip_pending = &r100_page_flip_pending,
479 },
480 };
481
482 static struct radeon_asic r420_asic = {
483 .init = &r420_init,
484 .fini = &r420_fini,
485 .suspend = &r420_suspend,
486 .resume = &r420_resume,
487 .vga_set_state = &r100_vga_set_state,
488 .asic_reset = &r300_asic_reset,
489 .mmio_hdp_flush = NULL,
490 .gui_idle = &r100_gui_idle,
491 .mc_wait_for_idle = &r300_mc_wait_for_idle,
492 .gart = {
493 .tlb_flush = &rv370_pcie_gart_tlb_flush,
494 .set_page = &rv370_pcie_gart_set_page,
495 },
496 .ring = {
497 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
498 },
499 .irq = {
500 .set = &r100_irq_set,
501 .process = &r100_irq_process,
502 },
503 .display = {
504 .bandwidth_update = &r100_bandwidth_update,
505 .get_vblank_counter = &r100_get_vblank_counter,
506 .wait_for_vblank = &r100_wait_for_vblank,
507 .set_backlight_level = &atombios_set_backlight_level,
508 .get_backlight_level = &atombios_get_backlight_level,
509 },
510 .copy = {
511 .blit = &r100_copy_blit,
512 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
513 .dma = &r200_copy_dma,
514 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
515 .copy = &r100_copy_blit,
516 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
517 },
518 .surface = {
519 .set_reg = r100_set_surface_reg,
520 .clear_reg = r100_clear_surface_reg,
521 },
522 .hpd = {
523 .init = &r100_hpd_init,
524 .fini = &r100_hpd_fini,
525 .sense = &r100_hpd_sense,
526 .set_polarity = &r100_hpd_set_polarity,
527 },
528 .pm = {
529 .misc = &r100_pm_misc,
530 .prepare = &r100_pm_prepare,
531 .finish = &r100_pm_finish,
532 .init_profile = &r420_pm_init_profile,
533 .get_dynpm_state = &r100_pm_get_dynpm_state,
534 .get_engine_clock = &radeon_atom_get_engine_clock,
535 .set_engine_clock = &radeon_atom_set_engine_clock,
536 .get_memory_clock = &radeon_atom_get_memory_clock,
537 .set_memory_clock = &radeon_atom_set_memory_clock,
538 .get_pcie_lanes = &rv370_get_pcie_lanes,
539 .set_pcie_lanes = &rv370_set_pcie_lanes,
540 .set_clock_gating = &radeon_atom_set_clock_gating,
541 },
542 .pflip = {
543 .page_flip = &r100_page_flip,
544 .page_flip_pending = &r100_page_flip_pending,
545 },
546 };
547
548 static struct radeon_asic rs400_asic = {
549 .init = &rs400_init,
550 .fini = &rs400_fini,
551 .suspend = &rs400_suspend,
552 .resume = &rs400_resume,
553 .vga_set_state = &r100_vga_set_state,
554 .asic_reset = &r300_asic_reset,
555 .mmio_hdp_flush = NULL,
556 .gui_idle = &r100_gui_idle,
557 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
558 .gart = {
559 .tlb_flush = &rs400_gart_tlb_flush,
560 .set_page = &rs400_gart_set_page,
561 },
562 .ring = {
563 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
564 },
565 .irq = {
566 .set = &r100_irq_set,
567 .process = &r100_irq_process,
568 },
569 .display = {
570 .bandwidth_update = &r100_bandwidth_update,
571 .get_vblank_counter = &r100_get_vblank_counter,
572 .wait_for_vblank = &r100_wait_for_vblank,
573 .set_backlight_level = &radeon_legacy_set_backlight_level,
574 .get_backlight_level = &radeon_legacy_get_backlight_level,
575 },
576 .copy = {
577 .blit = &r100_copy_blit,
578 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
579 .dma = &r200_copy_dma,
580 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
581 .copy = &r100_copy_blit,
582 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
583 },
584 .surface = {
585 .set_reg = r100_set_surface_reg,
586 .clear_reg = r100_clear_surface_reg,
587 },
588 .hpd = {
589 .init = &r100_hpd_init,
590 .fini = &r100_hpd_fini,
591 .sense = &r100_hpd_sense,
592 .set_polarity = &r100_hpd_set_polarity,
593 },
594 .pm = {
595 .misc = &r100_pm_misc,
596 .prepare = &r100_pm_prepare,
597 .finish = &r100_pm_finish,
598 .init_profile = &r100_pm_init_profile,
599 .get_dynpm_state = &r100_pm_get_dynpm_state,
600 .get_engine_clock = &radeon_legacy_get_engine_clock,
601 .set_engine_clock = &radeon_legacy_set_engine_clock,
602 .get_memory_clock = &radeon_legacy_get_memory_clock,
603 .set_memory_clock = NULL,
604 .get_pcie_lanes = NULL,
605 .set_pcie_lanes = NULL,
606 .set_clock_gating = &radeon_legacy_set_clock_gating,
607 },
608 .pflip = {
609 .page_flip = &r100_page_flip,
610 .page_flip_pending = &r100_page_flip_pending,
611 },
612 };
613
614 static struct radeon_asic rs600_asic = {
615 .init = &rs600_init,
616 .fini = &rs600_fini,
617 .suspend = &rs600_suspend,
618 .resume = &rs600_resume,
619 .vga_set_state = &r100_vga_set_state,
620 .asic_reset = &rs600_asic_reset,
621 .mmio_hdp_flush = NULL,
622 .gui_idle = &r100_gui_idle,
623 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
624 .gart = {
625 .tlb_flush = &rs600_gart_tlb_flush,
626 .set_page = &rs600_gart_set_page,
627 },
628 .ring = {
629 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
630 },
631 .irq = {
632 .set = &rs600_irq_set,
633 .process = &rs600_irq_process,
634 },
635 .display = {
636 .bandwidth_update = &rs600_bandwidth_update,
637 .get_vblank_counter = &rs600_get_vblank_counter,
638 .wait_for_vblank = &avivo_wait_for_vblank,
639 .set_backlight_level = &atombios_set_backlight_level,
640 .get_backlight_level = &atombios_get_backlight_level,
641 .hdmi_enable = &r600_hdmi_enable,
642 },
643 .copy = {
644 .blit = &r100_copy_blit,
645 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
646 .dma = &r200_copy_dma,
647 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
648 .copy = &r100_copy_blit,
649 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
650 },
651 .surface = {
652 .set_reg = r100_set_surface_reg,
653 .clear_reg = r100_clear_surface_reg,
654 },
655 .hpd = {
656 .init = &rs600_hpd_init,
657 .fini = &rs600_hpd_fini,
658 .sense = &rs600_hpd_sense,
659 .set_polarity = &rs600_hpd_set_polarity,
660 },
661 .pm = {
662 .misc = &rs600_pm_misc,
663 .prepare = &rs600_pm_prepare,
664 .finish = &rs600_pm_finish,
665 .init_profile = &r420_pm_init_profile,
666 .get_dynpm_state = &r100_pm_get_dynpm_state,
667 .get_engine_clock = &radeon_atom_get_engine_clock,
668 .set_engine_clock = &radeon_atom_set_engine_clock,
669 .get_memory_clock = &radeon_atom_get_memory_clock,
670 .set_memory_clock = &radeon_atom_set_memory_clock,
671 .get_pcie_lanes = NULL,
672 .set_pcie_lanes = NULL,
673 .set_clock_gating = &radeon_atom_set_clock_gating,
674 },
675 .pflip = {
676 .page_flip = &rs600_page_flip,
677 .page_flip_pending = &rs600_page_flip_pending,
678 },
679 };
680
681 static struct radeon_asic rs690_asic = {
682 .init = &rs690_init,
683 .fini = &rs690_fini,
684 .suspend = &rs690_suspend,
685 .resume = &rs690_resume,
686 .vga_set_state = &r100_vga_set_state,
687 .asic_reset = &rs600_asic_reset,
688 .mmio_hdp_flush = NULL,
689 .gui_idle = &r100_gui_idle,
690 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
691 .gart = {
692 .tlb_flush = &rs400_gart_tlb_flush,
693 .set_page = &rs400_gart_set_page,
694 },
695 .ring = {
696 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
697 },
698 .irq = {
699 .set = &rs600_irq_set,
700 .process = &rs600_irq_process,
701 },
702 .display = {
703 .get_vblank_counter = &rs600_get_vblank_counter,
704 .bandwidth_update = &rs690_bandwidth_update,
705 .wait_for_vblank = &avivo_wait_for_vblank,
706 .set_backlight_level = &atombios_set_backlight_level,
707 .get_backlight_level = &atombios_get_backlight_level,
708 .hdmi_enable = &r600_hdmi_enable,
709 },
710 .copy = {
711 .blit = &r100_copy_blit,
712 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
713 .dma = &r200_copy_dma,
714 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
715 .copy = &r200_copy_dma,
716 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
717 },
718 .surface = {
719 .set_reg = r100_set_surface_reg,
720 .clear_reg = r100_clear_surface_reg,
721 },
722 .hpd = {
723 .init = &rs600_hpd_init,
724 .fini = &rs600_hpd_fini,
725 .sense = &rs600_hpd_sense,
726 .set_polarity = &rs600_hpd_set_polarity,
727 },
728 .pm = {
729 .misc = &rs600_pm_misc,
730 .prepare = &rs600_pm_prepare,
731 .finish = &rs600_pm_finish,
732 .init_profile = &r420_pm_init_profile,
733 .get_dynpm_state = &r100_pm_get_dynpm_state,
734 .get_engine_clock = &radeon_atom_get_engine_clock,
735 .set_engine_clock = &radeon_atom_set_engine_clock,
736 .get_memory_clock = &radeon_atom_get_memory_clock,
737 .set_memory_clock = &radeon_atom_set_memory_clock,
738 .get_pcie_lanes = NULL,
739 .set_pcie_lanes = NULL,
740 .set_clock_gating = &radeon_atom_set_clock_gating,
741 },
742 .pflip = {
743 .page_flip = &rs600_page_flip,
744 .page_flip_pending = &rs600_page_flip_pending,
745 },
746 };
747
748 static struct radeon_asic rv515_asic = {
749 .init = &rv515_init,
750 .fini = &rv515_fini,
751 .suspend = &rv515_suspend,
752 .resume = &rv515_resume,
753 .vga_set_state = &r100_vga_set_state,
754 .asic_reset = &rs600_asic_reset,
755 .mmio_hdp_flush = NULL,
756 .gui_idle = &r100_gui_idle,
757 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
758 .gart = {
759 .tlb_flush = &rv370_pcie_gart_tlb_flush,
760 .set_page = &rv370_pcie_gart_set_page,
761 },
762 .ring = {
763 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
764 },
765 .irq = {
766 .set = &rs600_irq_set,
767 .process = &rs600_irq_process,
768 },
769 .display = {
770 .get_vblank_counter = &rs600_get_vblank_counter,
771 .bandwidth_update = &rv515_bandwidth_update,
772 .wait_for_vblank = &avivo_wait_for_vblank,
773 .set_backlight_level = &atombios_set_backlight_level,
774 .get_backlight_level = &atombios_get_backlight_level,
775 },
776 .copy = {
777 .blit = &r100_copy_blit,
778 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
779 .dma = &r200_copy_dma,
780 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
781 .copy = &r100_copy_blit,
782 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
783 },
784 .surface = {
785 .set_reg = r100_set_surface_reg,
786 .clear_reg = r100_clear_surface_reg,
787 },
788 .hpd = {
789 .init = &rs600_hpd_init,
790 .fini = &rs600_hpd_fini,
791 .sense = &rs600_hpd_sense,
792 .set_polarity = &rs600_hpd_set_polarity,
793 },
794 .pm = {
795 .misc = &rs600_pm_misc,
796 .prepare = &rs600_pm_prepare,
797 .finish = &rs600_pm_finish,
798 .init_profile = &r420_pm_init_profile,
799 .get_dynpm_state = &r100_pm_get_dynpm_state,
800 .get_engine_clock = &radeon_atom_get_engine_clock,
801 .set_engine_clock = &radeon_atom_set_engine_clock,
802 .get_memory_clock = &radeon_atom_get_memory_clock,
803 .set_memory_clock = &radeon_atom_set_memory_clock,
804 .get_pcie_lanes = &rv370_get_pcie_lanes,
805 .set_pcie_lanes = &rv370_set_pcie_lanes,
806 .set_clock_gating = &radeon_atom_set_clock_gating,
807 },
808 .pflip = {
809 .page_flip = &rs600_page_flip,
810 .page_flip_pending = &rs600_page_flip_pending,
811 },
812 };
813
814 static struct radeon_asic r520_asic = {
815 .init = &r520_init,
816 .fini = &rv515_fini,
817 .suspend = &rv515_suspend,
818 .resume = &r520_resume,
819 .vga_set_state = &r100_vga_set_state,
820 .asic_reset = &rs600_asic_reset,
821 .mmio_hdp_flush = NULL,
822 .gui_idle = &r100_gui_idle,
823 .mc_wait_for_idle = &r520_mc_wait_for_idle,
824 .gart = {
825 .tlb_flush = &rv370_pcie_gart_tlb_flush,
826 .set_page = &rv370_pcie_gart_set_page,
827 },
828 .ring = {
829 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
830 },
831 .irq = {
832 .set = &rs600_irq_set,
833 .process = &rs600_irq_process,
834 },
835 .display = {
836 .bandwidth_update = &rv515_bandwidth_update,
837 .get_vblank_counter = &rs600_get_vblank_counter,
838 .wait_for_vblank = &avivo_wait_for_vblank,
839 .set_backlight_level = &atombios_set_backlight_level,
840 .get_backlight_level = &atombios_get_backlight_level,
841 },
842 .copy = {
843 .blit = &r100_copy_blit,
844 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
845 .dma = &r200_copy_dma,
846 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
847 .copy = &r100_copy_blit,
848 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
849 },
850 .surface = {
851 .set_reg = r100_set_surface_reg,
852 .clear_reg = r100_clear_surface_reg,
853 },
854 .hpd = {
855 .init = &rs600_hpd_init,
856 .fini = &rs600_hpd_fini,
857 .sense = &rs600_hpd_sense,
858 .set_polarity = &rs600_hpd_set_polarity,
859 },
860 .pm = {
861 .misc = &rs600_pm_misc,
862 .prepare = &rs600_pm_prepare,
863 .finish = &rs600_pm_finish,
864 .init_profile = &r420_pm_init_profile,
865 .get_dynpm_state = &r100_pm_get_dynpm_state,
866 .get_engine_clock = &radeon_atom_get_engine_clock,
867 .set_engine_clock = &radeon_atom_set_engine_clock,
868 .get_memory_clock = &radeon_atom_get_memory_clock,
869 .set_memory_clock = &radeon_atom_set_memory_clock,
870 .get_pcie_lanes = &rv370_get_pcie_lanes,
871 .set_pcie_lanes = &rv370_set_pcie_lanes,
872 .set_clock_gating = &radeon_atom_set_clock_gating,
873 },
874 .pflip = {
875 .page_flip = &rs600_page_flip,
876 .page_flip_pending = &rs600_page_flip_pending,
877 },
878 };
879
880 static struct radeon_asic_ring r600_gfx_ring = {
881 .ib_execute = &r600_ring_ib_execute,
882 .emit_fence = &r600_fence_ring_emit,
883 .emit_semaphore = &r600_semaphore_ring_emit,
884 .cs_parse = &r600_cs_parse,
885 .ring_test = &r600_ring_test,
886 .ib_test = &r600_ib_test,
887 .is_lockup = &r600_gfx_is_lockup,
888 .get_rptr = &r600_gfx_get_rptr,
889 .get_wptr = &r600_gfx_get_wptr,
890 .set_wptr = &r600_gfx_set_wptr,
891 };
892
893 static struct radeon_asic_ring r600_dma_ring = {
894 .ib_execute = &r600_dma_ring_ib_execute,
895 .emit_fence = &r600_dma_fence_ring_emit,
896 .emit_semaphore = &r600_dma_semaphore_ring_emit,
897 .cs_parse = &r600_dma_cs_parse,
898 .ring_test = &r600_dma_ring_test,
899 .ib_test = &r600_dma_ib_test,
900 .is_lockup = &r600_dma_is_lockup,
901 .get_rptr = &r600_dma_get_rptr,
902 .get_wptr = &r600_dma_get_wptr,
903 .set_wptr = &r600_dma_set_wptr,
904 };
905
906 static struct radeon_asic r600_asic = {
907 .init = &r600_init,
908 .fini = &r600_fini,
909 .suspend = &r600_suspend,
910 .resume = &r600_resume,
911 .vga_set_state = &r600_vga_set_state,
912 .asic_reset = &r600_asic_reset,
913 .mmio_hdp_flush = r600_mmio_hdp_flush,
914 .gui_idle = &r600_gui_idle,
915 .mc_wait_for_idle = &r600_mc_wait_for_idle,
916 .get_xclk = &r600_get_xclk,
917 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
918 .gart = {
919 .tlb_flush = &r600_pcie_gart_tlb_flush,
920 .set_page = &rs600_gart_set_page,
921 },
922 .ring = {
923 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
924 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
925 },
926 .irq = {
927 .set = &r600_irq_set,
928 .process = &r600_irq_process,
929 },
930 .display = {
931 .bandwidth_update = &rv515_bandwidth_update,
932 .get_vblank_counter = &rs600_get_vblank_counter,
933 .wait_for_vblank = &avivo_wait_for_vblank,
934 .set_backlight_level = &atombios_set_backlight_level,
935 .get_backlight_level = &atombios_get_backlight_level,
936 .hdmi_enable = &r600_hdmi_enable,
937 },
938 .copy = {
939 .blit = &r600_copy_cpdma,
940 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
941 .dma = &r600_copy_dma,
942 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
943 .copy = &r600_copy_cpdma,
944 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
945 },
946 .surface = {
947 .set_reg = r600_set_surface_reg,
948 .clear_reg = r600_clear_surface_reg,
949 },
950 .hpd = {
951 .init = &r600_hpd_init,
952 .fini = &r600_hpd_fini,
953 .sense = &r600_hpd_sense,
954 .set_polarity = &r600_hpd_set_polarity,
955 },
956 .pm = {
957 .misc = &r600_pm_misc,
958 .prepare = &rs600_pm_prepare,
959 .finish = &rs600_pm_finish,
960 .init_profile = &r600_pm_init_profile,
961 .get_dynpm_state = &r600_pm_get_dynpm_state,
962 .get_engine_clock = &radeon_atom_get_engine_clock,
963 .set_engine_clock = &radeon_atom_set_engine_clock,
964 .get_memory_clock = &radeon_atom_get_memory_clock,
965 .set_memory_clock = &radeon_atom_set_memory_clock,
966 .get_pcie_lanes = &r600_get_pcie_lanes,
967 .set_pcie_lanes = &r600_set_pcie_lanes,
968 .set_clock_gating = NULL,
969 .get_temperature = &rv6xx_get_temp,
970 },
971 .pflip = {
972 .page_flip = &rs600_page_flip,
973 .page_flip_pending = &rs600_page_flip_pending,
974 },
975 };
976
977 static struct radeon_asic_ring rv6xx_uvd_ring = {
978 .ib_execute = &uvd_v1_0_ib_execute,
979 .emit_fence = &uvd_v1_0_fence_emit,
980 .emit_semaphore = &uvd_v1_0_semaphore_emit,
981 .cs_parse = &radeon_uvd_cs_parse,
982 .ring_test = &uvd_v1_0_ring_test,
983 .ib_test = &uvd_v1_0_ib_test,
984 .is_lockup = &radeon_ring_test_lockup,
985 .get_rptr = &uvd_v1_0_get_rptr,
986 .get_wptr = &uvd_v1_0_get_wptr,
987 .set_wptr = &uvd_v1_0_set_wptr,
988 };
989
990 static struct radeon_asic rv6xx_asic = {
991 .init = &r600_init,
992 .fini = &r600_fini,
993 .suspend = &r600_suspend,
994 .resume = &r600_resume,
995 .vga_set_state = &r600_vga_set_state,
996 .asic_reset = &r600_asic_reset,
997 .mmio_hdp_flush = r600_mmio_hdp_flush,
998 .gui_idle = &r600_gui_idle,
999 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1000 .get_xclk = &r600_get_xclk,
1001 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1002 .gart = {
1003 .tlb_flush = &r600_pcie_gart_tlb_flush,
1004 .set_page = &rs600_gart_set_page,
1005 },
1006 .ring = {
1007 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1008 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1009 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1010 },
1011 .irq = {
1012 .set = &r600_irq_set,
1013 .process = &r600_irq_process,
1014 },
1015 .display = {
1016 .bandwidth_update = &rv515_bandwidth_update,
1017 .get_vblank_counter = &rs600_get_vblank_counter,
1018 .wait_for_vblank = &avivo_wait_for_vblank,
1019 .set_backlight_level = &atombios_set_backlight_level,
1020 .get_backlight_level = &atombios_get_backlight_level,
1021 .hdmi_enable = &r600_hdmi_enable,
1022 },
1023 .copy = {
1024 .blit = &r600_copy_cpdma,
1025 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1026 .dma = &r600_copy_dma,
1027 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1028 .copy = &r600_copy_cpdma,
1029 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1030 },
1031 .surface = {
1032 .set_reg = r600_set_surface_reg,
1033 .clear_reg = r600_clear_surface_reg,
1034 },
1035 .hpd = {
1036 .init = &r600_hpd_init,
1037 .fini = &r600_hpd_fini,
1038 .sense = &r600_hpd_sense,
1039 .set_polarity = &r600_hpd_set_polarity,
1040 },
1041 .pm = {
1042 .misc = &r600_pm_misc,
1043 .prepare = &rs600_pm_prepare,
1044 .finish = &rs600_pm_finish,
1045 .init_profile = &r600_pm_init_profile,
1046 .get_dynpm_state = &r600_pm_get_dynpm_state,
1047 .get_engine_clock = &radeon_atom_get_engine_clock,
1048 .set_engine_clock = &radeon_atom_set_engine_clock,
1049 .get_memory_clock = &radeon_atom_get_memory_clock,
1050 .set_memory_clock = &radeon_atom_set_memory_clock,
1051 .get_pcie_lanes = &r600_get_pcie_lanes,
1052 .set_pcie_lanes = &r600_set_pcie_lanes,
1053 .set_clock_gating = NULL,
1054 .get_temperature = &rv6xx_get_temp,
1055 .set_uvd_clocks = &r600_set_uvd_clocks,
1056 },
1057 .dpm = {
1058 .init = &rv6xx_dpm_init,
1059 .setup_asic = &rv6xx_setup_asic,
1060 .enable = &rv6xx_dpm_enable,
1061 .late_enable = &r600_dpm_late_enable,
1062 .disable = &rv6xx_dpm_disable,
1063 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1064 .set_power_state = &rv6xx_dpm_set_power_state,
1065 .post_set_power_state = &r600_dpm_post_set_power_state,
1066 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1067 .fini = &rv6xx_dpm_fini,
1068 .get_sclk = &rv6xx_dpm_get_sclk,
1069 .get_mclk = &rv6xx_dpm_get_mclk,
1070 .print_power_state = &rv6xx_dpm_print_power_state,
1071 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1072 .force_performance_level = &rv6xx_dpm_force_performance_level,
1073 },
1074 .pflip = {
1075 .page_flip = &rs600_page_flip,
1076 .page_flip_pending = &rs600_page_flip_pending,
1077 },
1078 };
1079
1080 static struct radeon_asic rs780_asic = {
1081 .init = &r600_init,
1082 .fini = &r600_fini,
1083 .suspend = &r600_suspend,
1084 .resume = &r600_resume,
1085 .vga_set_state = &r600_vga_set_state,
1086 .asic_reset = &r600_asic_reset,
1087 .mmio_hdp_flush = r600_mmio_hdp_flush,
1088 .gui_idle = &r600_gui_idle,
1089 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1090 .get_xclk = &r600_get_xclk,
1091 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1092 .gart = {
1093 .tlb_flush = &r600_pcie_gart_tlb_flush,
1094 .set_page = &rs600_gart_set_page,
1095 },
1096 .ring = {
1097 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1098 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1099 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1100 },
1101 .irq = {
1102 .set = &r600_irq_set,
1103 .process = &r600_irq_process,
1104 },
1105 .display = {
1106 .bandwidth_update = &rs690_bandwidth_update,
1107 .get_vblank_counter = &rs600_get_vblank_counter,
1108 .wait_for_vblank = &avivo_wait_for_vblank,
1109 .set_backlight_level = &atombios_set_backlight_level,
1110 .get_backlight_level = &atombios_get_backlight_level,
1111 .hdmi_enable = &r600_hdmi_enable,
1112 },
1113 .copy = {
1114 .blit = &r600_copy_cpdma,
1115 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1116 .dma = &r600_copy_dma,
1117 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1118 .copy = &r600_copy_cpdma,
1119 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1120 },
1121 .surface = {
1122 .set_reg = r600_set_surface_reg,
1123 .clear_reg = r600_clear_surface_reg,
1124 },
1125 .hpd = {
1126 .init = &r600_hpd_init,
1127 .fini = &r600_hpd_fini,
1128 .sense = &r600_hpd_sense,
1129 .set_polarity = &r600_hpd_set_polarity,
1130 },
1131 .pm = {
1132 .misc = &r600_pm_misc,
1133 .prepare = &rs600_pm_prepare,
1134 .finish = &rs600_pm_finish,
1135 .init_profile = &rs780_pm_init_profile,
1136 .get_dynpm_state = &r600_pm_get_dynpm_state,
1137 .get_engine_clock = &radeon_atom_get_engine_clock,
1138 .set_engine_clock = &radeon_atom_set_engine_clock,
1139 .get_memory_clock = NULL,
1140 .set_memory_clock = NULL,
1141 .get_pcie_lanes = NULL,
1142 .set_pcie_lanes = NULL,
1143 .set_clock_gating = NULL,
1144 .get_temperature = &rv6xx_get_temp,
1145 .set_uvd_clocks = &r600_set_uvd_clocks,
1146 },
1147 .dpm = {
1148 .init = &rs780_dpm_init,
1149 .setup_asic = &rs780_dpm_setup_asic,
1150 .enable = &rs780_dpm_enable,
1151 .late_enable = &r600_dpm_late_enable,
1152 .disable = &rs780_dpm_disable,
1153 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1154 .set_power_state = &rs780_dpm_set_power_state,
1155 .post_set_power_state = &r600_dpm_post_set_power_state,
1156 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1157 .fini = &rs780_dpm_fini,
1158 .get_sclk = &rs780_dpm_get_sclk,
1159 .get_mclk = &rs780_dpm_get_mclk,
1160 .print_power_state = &rs780_dpm_print_power_state,
1161 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1162 .force_performance_level = &rs780_dpm_force_performance_level,
1163 },
1164 .pflip = {
1165 .page_flip = &rs600_page_flip,
1166 .page_flip_pending = &rs600_page_flip_pending,
1167 },
1168 };
1169
1170 static struct radeon_asic_ring rv770_uvd_ring = {
1171 .ib_execute = &uvd_v1_0_ib_execute,
1172 .emit_fence = &uvd_v2_2_fence_emit,
1173 .emit_semaphore = &uvd_v1_0_semaphore_emit,
1174 .cs_parse = &radeon_uvd_cs_parse,
1175 .ring_test = &uvd_v1_0_ring_test,
1176 .ib_test = &uvd_v1_0_ib_test,
1177 .is_lockup = &radeon_ring_test_lockup,
1178 .get_rptr = &uvd_v1_0_get_rptr,
1179 .get_wptr = &uvd_v1_0_get_wptr,
1180 .set_wptr = &uvd_v1_0_set_wptr,
1181 };
1182
1183 static struct radeon_asic rv770_asic = {
1184 .init = &rv770_init,
1185 .fini = &rv770_fini,
1186 .suspend = &rv770_suspend,
1187 .resume = &rv770_resume,
1188 .asic_reset = &r600_asic_reset,
1189 .vga_set_state = &r600_vga_set_state,
1190 .mmio_hdp_flush = r600_mmio_hdp_flush,
1191 .gui_idle = &r600_gui_idle,
1192 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1193 .get_xclk = &rv770_get_xclk,
1194 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1195 .gart = {
1196 .tlb_flush = &r600_pcie_gart_tlb_flush,
1197 .set_page = &rs600_gart_set_page,
1198 },
1199 .ring = {
1200 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1201 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1202 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1203 },
1204 .irq = {
1205 .set = &r600_irq_set,
1206 .process = &r600_irq_process,
1207 },
1208 .display = {
1209 .bandwidth_update = &rv515_bandwidth_update,
1210 .get_vblank_counter = &rs600_get_vblank_counter,
1211 .wait_for_vblank = &avivo_wait_for_vblank,
1212 .set_backlight_level = &atombios_set_backlight_level,
1213 .get_backlight_level = &atombios_get_backlight_level,
1214 .hdmi_enable = &r600_hdmi_enable,
1215 },
1216 .copy = {
1217 .blit = &r600_copy_cpdma,
1218 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1219 .dma = &rv770_copy_dma,
1220 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1221 .copy = &rv770_copy_dma,
1222 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1223 },
1224 .surface = {
1225 .set_reg = r600_set_surface_reg,
1226 .clear_reg = r600_clear_surface_reg,
1227 },
1228 .hpd = {
1229 .init = &r600_hpd_init,
1230 .fini = &r600_hpd_fini,
1231 .sense = &r600_hpd_sense,
1232 .set_polarity = &r600_hpd_set_polarity,
1233 },
1234 .pm = {
1235 .misc = &rv770_pm_misc,
1236 .prepare = &rs600_pm_prepare,
1237 .finish = &rs600_pm_finish,
1238 .init_profile = &r600_pm_init_profile,
1239 .get_dynpm_state = &r600_pm_get_dynpm_state,
1240 .get_engine_clock = &radeon_atom_get_engine_clock,
1241 .set_engine_clock = &radeon_atom_set_engine_clock,
1242 .get_memory_clock = &radeon_atom_get_memory_clock,
1243 .set_memory_clock = &radeon_atom_set_memory_clock,
1244 .get_pcie_lanes = &r600_get_pcie_lanes,
1245 .set_pcie_lanes = &r600_set_pcie_lanes,
1246 .set_clock_gating = &radeon_atom_set_clock_gating,
1247 .set_uvd_clocks = &rv770_set_uvd_clocks,
1248 .get_temperature = &rv770_get_temp,
1249 },
1250 .dpm = {
1251 .init = &rv770_dpm_init,
1252 .setup_asic = &rv770_dpm_setup_asic,
1253 .enable = &rv770_dpm_enable,
1254 .late_enable = &rv770_dpm_late_enable,
1255 .disable = &rv770_dpm_disable,
1256 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1257 .set_power_state = &rv770_dpm_set_power_state,
1258 .post_set_power_state = &r600_dpm_post_set_power_state,
1259 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1260 .fini = &rv770_dpm_fini,
1261 .get_sclk = &rv770_dpm_get_sclk,
1262 .get_mclk = &rv770_dpm_get_mclk,
1263 .print_power_state = &rv770_dpm_print_power_state,
1264 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1265 .force_performance_level = &rv770_dpm_force_performance_level,
1266 .vblank_too_short = &rv770_dpm_vblank_too_short,
1267 },
1268 .pflip = {
1269 .page_flip = &rv770_page_flip,
1270 .page_flip_pending = &rv770_page_flip_pending,
1271 },
1272 };
1273
1274 static struct radeon_asic_ring evergreen_gfx_ring = {
1275 .ib_execute = &evergreen_ring_ib_execute,
1276 .emit_fence = &r600_fence_ring_emit,
1277 .emit_semaphore = &r600_semaphore_ring_emit,
1278 .cs_parse = &evergreen_cs_parse,
1279 .ring_test = &r600_ring_test,
1280 .ib_test = &r600_ib_test,
1281 .is_lockup = &evergreen_gfx_is_lockup,
1282 .get_rptr = &r600_gfx_get_rptr,
1283 .get_wptr = &r600_gfx_get_wptr,
1284 .set_wptr = &r600_gfx_set_wptr,
1285 };
1286
1287 static struct radeon_asic_ring evergreen_dma_ring = {
1288 .ib_execute = &evergreen_dma_ring_ib_execute,
1289 .emit_fence = &evergreen_dma_fence_ring_emit,
1290 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1291 .cs_parse = &evergreen_dma_cs_parse,
1292 .ring_test = &r600_dma_ring_test,
1293 .ib_test = &r600_dma_ib_test,
1294 .is_lockup = &evergreen_dma_is_lockup,
1295 .get_rptr = &r600_dma_get_rptr,
1296 .get_wptr = &r600_dma_get_wptr,
1297 .set_wptr = &r600_dma_set_wptr,
1298 };
1299
1300 static struct radeon_asic evergreen_asic = {
1301 .init = &evergreen_init,
1302 .fini = &evergreen_fini,
1303 .suspend = &evergreen_suspend,
1304 .resume = &evergreen_resume,
1305 .asic_reset = &evergreen_asic_reset,
1306 .vga_set_state = &r600_vga_set_state,
1307 .mmio_hdp_flush = r600_mmio_hdp_flush,
1308 .gui_idle = &r600_gui_idle,
1309 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1310 .get_xclk = &rv770_get_xclk,
1311 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1312 .gart = {
1313 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1314 .set_page = &rs600_gart_set_page,
1315 },
1316 .ring = {
1317 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1318 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1319 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1320 },
1321 .irq = {
1322 .set = &evergreen_irq_set,
1323 .process = &evergreen_irq_process,
1324 },
1325 .display = {
1326 .bandwidth_update = &evergreen_bandwidth_update,
1327 .get_vblank_counter = &evergreen_get_vblank_counter,
1328 .wait_for_vblank = &dce4_wait_for_vblank,
1329 .set_backlight_level = &atombios_set_backlight_level,
1330 .get_backlight_level = &atombios_get_backlight_level,
1331 .hdmi_enable = &evergreen_hdmi_enable,
1332 },
1333 .copy = {
1334 .blit = &r600_copy_cpdma,
1335 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1336 .dma = &evergreen_copy_dma,
1337 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1338 .copy = &evergreen_copy_dma,
1339 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1340 },
1341 .surface = {
1342 .set_reg = r600_set_surface_reg,
1343 .clear_reg = r600_clear_surface_reg,
1344 },
1345 .hpd = {
1346 .init = &evergreen_hpd_init,
1347 .fini = &evergreen_hpd_fini,
1348 .sense = &evergreen_hpd_sense,
1349 .set_polarity = &evergreen_hpd_set_polarity,
1350 },
1351 .pm = {
1352 .misc = &evergreen_pm_misc,
1353 .prepare = &evergreen_pm_prepare,
1354 .finish = &evergreen_pm_finish,
1355 .init_profile = &r600_pm_init_profile,
1356 .get_dynpm_state = &r600_pm_get_dynpm_state,
1357 .get_engine_clock = &radeon_atom_get_engine_clock,
1358 .set_engine_clock = &radeon_atom_set_engine_clock,
1359 .get_memory_clock = &radeon_atom_get_memory_clock,
1360 .set_memory_clock = &radeon_atom_set_memory_clock,
1361 .get_pcie_lanes = &r600_get_pcie_lanes,
1362 .set_pcie_lanes = &r600_set_pcie_lanes,
1363 .set_clock_gating = NULL,
1364 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1365 .get_temperature = &evergreen_get_temp,
1366 },
1367 .dpm = {
1368 .init = &cypress_dpm_init,
1369 .setup_asic = &cypress_dpm_setup_asic,
1370 .enable = &cypress_dpm_enable,
1371 .late_enable = &rv770_dpm_late_enable,
1372 .disable = &cypress_dpm_disable,
1373 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1374 .set_power_state = &cypress_dpm_set_power_state,
1375 .post_set_power_state = &r600_dpm_post_set_power_state,
1376 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1377 .fini = &cypress_dpm_fini,
1378 .get_sclk = &rv770_dpm_get_sclk,
1379 .get_mclk = &rv770_dpm_get_mclk,
1380 .print_power_state = &rv770_dpm_print_power_state,
1381 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1382 .force_performance_level = &rv770_dpm_force_performance_level,
1383 .vblank_too_short = &cypress_dpm_vblank_too_short,
1384 },
1385 .pflip = {
1386 .page_flip = &evergreen_page_flip,
1387 .page_flip_pending = &evergreen_page_flip_pending,
1388 },
1389 };
1390
1391 static struct radeon_asic sumo_asic = {
1392 .init = &evergreen_init,
1393 .fini = &evergreen_fini,
1394 .suspend = &evergreen_suspend,
1395 .resume = &evergreen_resume,
1396 .asic_reset = &evergreen_asic_reset,
1397 .vga_set_state = &r600_vga_set_state,
1398 .mmio_hdp_flush = r600_mmio_hdp_flush,
1399 .gui_idle = &r600_gui_idle,
1400 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1401 .get_xclk = &r600_get_xclk,
1402 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1403 .gart = {
1404 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1405 .set_page = &rs600_gart_set_page,
1406 },
1407 .ring = {
1408 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1409 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1410 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1411 },
1412 .irq = {
1413 .set = &evergreen_irq_set,
1414 .process = &evergreen_irq_process,
1415 },
1416 .display = {
1417 .bandwidth_update = &evergreen_bandwidth_update,
1418 .get_vblank_counter = &evergreen_get_vblank_counter,
1419 .wait_for_vblank = &dce4_wait_for_vblank,
1420 .set_backlight_level = &atombios_set_backlight_level,
1421 .get_backlight_level = &atombios_get_backlight_level,
1422 .hdmi_enable = &evergreen_hdmi_enable,
1423 },
1424 .copy = {
1425 .blit = &r600_copy_cpdma,
1426 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1427 .dma = &evergreen_copy_dma,
1428 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1429 .copy = &evergreen_copy_dma,
1430 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1431 },
1432 .surface = {
1433 .set_reg = r600_set_surface_reg,
1434 .clear_reg = r600_clear_surface_reg,
1435 },
1436 .hpd = {
1437 .init = &evergreen_hpd_init,
1438 .fini = &evergreen_hpd_fini,
1439 .sense = &evergreen_hpd_sense,
1440 .set_polarity = &evergreen_hpd_set_polarity,
1441 },
1442 .pm = {
1443 .misc = &evergreen_pm_misc,
1444 .prepare = &evergreen_pm_prepare,
1445 .finish = &evergreen_pm_finish,
1446 .init_profile = &sumo_pm_init_profile,
1447 .get_dynpm_state = &r600_pm_get_dynpm_state,
1448 .get_engine_clock = &radeon_atom_get_engine_clock,
1449 .set_engine_clock = &radeon_atom_set_engine_clock,
1450 .get_memory_clock = NULL,
1451 .set_memory_clock = NULL,
1452 .get_pcie_lanes = NULL,
1453 .set_pcie_lanes = NULL,
1454 .set_clock_gating = NULL,
1455 .set_uvd_clocks = &sumo_set_uvd_clocks,
1456 .get_temperature = &sumo_get_temp,
1457 },
1458 .dpm = {
1459 .init = &sumo_dpm_init,
1460 .setup_asic = &sumo_dpm_setup_asic,
1461 .enable = &sumo_dpm_enable,
1462 .late_enable = &sumo_dpm_late_enable,
1463 .disable = &sumo_dpm_disable,
1464 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1465 .set_power_state = &sumo_dpm_set_power_state,
1466 .post_set_power_state = &sumo_dpm_post_set_power_state,
1467 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1468 .fini = &sumo_dpm_fini,
1469 .get_sclk = &sumo_dpm_get_sclk,
1470 .get_mclk = &sumo_dpm_get_mclk,
1471 .print_power_state = &sumo_dpm_print_power_state,
1472 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1473 .force_performance_level = &sumo_dpm_force_performance_level,
1474 },
1475 .pflip = {
1476 .page_flip = &evergreen_page_flip,
1477 .page_flip_pending = &evergreen_page_flip_pending,
1478 },
1479 };
1480
1481 static struct radeon_asic btc_asic = {
1482 .init = &evergreen_init,
1483 .fini = &evergreen_fini,
1484 .suspend = &evergreen_suspend,
1485 .resume = &evergreen_resume,
1486 .asic_reset = &evergreen_asic_reset,
1487 .vga_set_state = &r600_vga_set_state,
1488 .mmio_hdp_flush = r600_mmio_hdp_flush,
1489 .gui_idle = &r600_gui_idle,
1490 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1491 .get_xclk = &rv770_get_xclk,
1492 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1493 .gart = {
1494 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1495 .set_page = &rs600_gart_set_page,
1496 },
1497 .ring = {
1498 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1499 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1500 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1501 },
1502 .irq = {
1503 .set = &evergreen_irq_set,
1504 .process = &evergreen_irq_process,
1505 },
1506 .display = {
1507 .bandwidth_update = &evergreen_bandwidth_update,
1508 .get_vblank_counter = &evergreen_get_vblank_counter,
1509 .wait_for_vblank = &dce4_wait_for_vblank,
1510 .set_backlight_level = &atombios_set_backlight_level,
1511 .get_backlight_level = &atombios_get_backlight_level,
1512 .hdmi_enable = &evergreen_hdmi_enable,
1513 },
1514 .copy = {
1515 .blit = &r600_copy_cpdma,
1516 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1517 .dma = &evergreen_copy_dma,
1518 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1519 .copy = &evergreen_copy_dma,
1520 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1521 },
1522 .surface = {
1523 .set_reg = r600_set_surface_reg,
1524 .clear_reg = r600_clear_surface_reg,
1525 },
1526 .hpd = {
1527 .init = &evergreen_hpd_init,
1528 .fini = &evergreen_hpd_fini,
1529 .sense = &evergreen_hpd_sense,
1530 .set_polarity = &evergreen_hpd_set_polarity,
1531 },
1532 .pm = {
1533 .misc = &evergreen_pm_misc,
1534 .prepare = &evergreen_pm_prepare,
1535 .finish = &evergreen_pm_finish,
1536 .init_profile = &btc_pm_init_profile,
1537 .get_dynpm_state = &r600_pm_get_dynpm_state,
1538 .get_engine_clock = &radeon_atom_get_engine_clock,
1539 .set_engine_clock = &radeon_atom_set_engine_clock,
1540 .get_memory_clock = &radeon_atom_get_memory_clock,
1541 .set_memory_clock = &radeon_atom_set_memory_clock,
1542 .get_pcie_lanes = &r600_get_pcie_lanes,
1543 .set_pcie_lanes = &r600_set_pcie_lanes,
1544 .set_clock_gating = NULL,
1545 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1546 .get_temperature = &evergreen_get_temp,
1547 },
1548 .dpm = {
1549 .init = &btc_dpm_init,
1550 .setup_asic = &btc_dpm_setup_asic,
1551 .enable = &btc_dpm_enable,
1552 .late_enable = &rv770_dpm_late_enable,
1553 .disable = &btc_dpm_disable,
1554 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1555 .set_power_state = &btc_dpm_set_power_state,
1556 .post_set_power_state = &btc_dpm_post_set_power_state,
1557 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1558 .fini = &btc_dpm_fini,
1559 .get_sclk = &btc_dpm_get_sclk,
1560 .get_mclk = &btc_dpm_get_mclk,
1561 .print_power_state = &rv770_dpm_print_power_state,
1562 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1563 .force_performance_level = &rv770_dpm_force_performance_level,
1564 .vblank_too_short = &btc_dpm_vblank_too_short,
1565 },
1566 .pflip = {
1567 .page_flip = &evergreen_page_flip,
1568 .page_flip_pending = &evergreen_page_flip_pending,
1569 },
1570 };
1571
1572 static struct radeon_asic_ring cayman_gfx_ring = {
1573 .ib_execute = &cayman_ring_ib_execute,
1574 .ib_parse = &evergreen_ib_parse,
1575 .emit_fence = &cayman_fence_ring_emit,
1576 .emit_semaphore = &r600_semaphore_ring_emit,
1577 .cs_parse = &evergreen_cs_parse,
1578 .ring_test = &r600_ring_test,
1579 .ib_test = &r600_ib_test,
1580 .is_lockup = &cayman_gfx_is_lockup,
1581 .vm_flush = &cayman_vm_flush,
1582 .get_rptr = &cayman_gfx_get_rptr,
1583 .get_wptr = &cayman_gfx_get_wptr,
1584 .set_wptr = &cayman_gfx_set_wptr,
1585 };
1586
1587 static struct radeon_asic_ring cayman_dma_ring = {
1588 .ib_execute = &cayman_dma_ring_ib_execute,
1589 .ib_parse = &evergreen_dma_ib_parse,
1590 .emit_fence = &evergreen_dma_fence_ring_emit,
1591 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1592 .cs_parse = &evergreen_dma_cs_parse,
1593 .ring_test = &r600_dma_ring_test,
1594 .ib_test = &r600_dma_ib_test,
1595 .is_lockup = &cayman_dma_is_lockup,
1596 .vm_flush = &cayman_dma_vm_flush,
1597 .get_rptr = &cayman_dma_get_rptr,
1598 .get_wptr = &cayman_dma_get_wptr,
1599 .set_wptr = &cayman_dma_set_wptr
1600 };
1601
1602 static struct radeon_asic_ring cayman_uvd_ring = {
1603 .ib_execute = &uvd_v1_0_ib_execute,
1604 .emit_fence = &uvd_v2_2_fence_emit,
1605 .emit_semaphore = &uvd_v3_1_semaphore_emit,
1606 .cs_parse = &radeon_uvd_cs_parse,
1607 .ring_test = &uvd_v1_0_ring_test,
1608 .ib_test = &uvd_v1_0_ib_test,
1609 .is_lockup = &radeon_ring_test_lockup,
1610 .get_rptr = &uvd_v1_0_get_rptr,
1611 .get_wptr = &uvd_v1_0_get_wptr,
1612 .set_wptr = &uvd_v1_0_set_wptr,
1613 };
1614
1615 static struct radeon_asic cayman_asic = {
1616 .init = &cayman_init,
1617 .fini = &cayman_fini,
1618 .suspend = &cayman_suspend,
1619 .resume = &cayman_resume,
1620 .asic_reset = &cayman_asic_reset,
1621 .vga_set_state = &r600_vga_set_state,
1622 .mmio_hdp_flush = r600_mmio_hdp_flush,
1623 .gui_idle = &r600_gui_idle,
1624 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1625 .get_xclk = &rv770_get_xclk,
1626 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1627 .gart = {
1628 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1629 .set_page = &rs600_gart_set_page,
1630 },
1631 .vm = {
1632 .init = &cayman_vm_init,
1633 .fini = &cayman_vm_fini,
1634 .copy_pages = &cayman_dma_vm_copy_pages,
1635 .write_pages = &cayman_dma_vm_write_pages,
1636 .set_pages = &cayman_dma_vm_set_pages,
1637 .pad_ib = &cayman_dma_vm_pad_ib,
1638 },
1639 .ring = {
1640 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1641 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1642 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1643 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1644 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1645 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1646 },
1647 .irq = {
1648 .set = &evergreen_irq_set,
1649 .process = &evergreen_irq_process,
1650 },
1651 .display = {
1652 .bandwidth_update = &evergreen_bandwidth_update,
1653 .get_vblank_counter = &evergreen_get_vblank_counter,
1654 .wait_for_vblank = &dce4_wait_for_vblank,
1655 .set_backlight_level = &atombios_set_backlight_level,
1656 .get_backlight_level = &atombios_get_backlight_level,
1657 .hdmi_enable = &evergreen_hdmi_enable,
1658 },
1659 .copy = {
1660 .blit = &r600_copy_cpdma,
1661 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1662 .dma = &evergreen_copy_dma,
1663 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1664 .copy = &evergreen_copy_dma,
1665 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1666 },
1667 .surface = {
1668 .set_reg = r600_set_surface_reg,
1669 .clear_reg = r600_clear_surface_reg,
1670 },
1671 .hpd = {
1672 .init = &evergreen_hpd_init,
1673 .fini = &evergreen_hpd_fini,
1674 .sense = &evergreen_hpd_sense,
1675 .set_polarity = &evergreen_hpd_set_polarity,
1676 },
1677 .pm = {
1678 .misc = &evergreen_pm_misc,
1679 .prepare = &evergreen_pm_prepare,
1680 .finish = &evergreen_pm_finish,
1681 .init_profile = &btc_pm_init_profile,
1682 .get_dynpm_state = &r600_pm_get_dynpm_state,
1683 .get_engine_clock = &radeon_atom_get_engine_clock,
1684 .set_engine_clock = &radeon_atom_set_engine_clock,
1685 .get_memory_clock = &radeon_atom_get_memory_clock,
1686 .set_memory_clock = &radeon_atom_set_memory_clock,
1687 .get_pcie_lanes = &r600_get_pcie_lanes,
1688 .set_pcie_lanes = &r600_set_pcie_lanes,
1689 .set_clock_gating = NULL,
1690 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1691 .get_temperature = &evergreen_get_temp,
1692 },
1693 .dpm = {
1694 .init = &ni_dpm_init,
1695 .setup_asic = &ni_dpm_setup_asic,
1696 .enable = &ni_dpm_enable,
1697 .late_enable = &rv770_dpm_late_enable,
1698 .disable = &ni_dpm_disable,
1699 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1700 .set_power_state = &ni_dpm_set_power_state,
1701 .post_set_power_state = &ni_dpm_post_set_power_state,
1702 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1703 .fini = &ni_dpm_fini,
1704 .get_sclk = &ni_dpm_get_sclk,
1705 .get_mclk = &ni_dpm_get_mclk,
1706 .print_power_state = &ni_dpm_print_power_state,
1707 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1708 .force_performance_level = &ni_dpm_force_performance_level,
1709 .vblank_too_short = &ni_dpm_vblank_too_short,
1710 },
1711 .pflip = {
1712 .page_flip = &evergreen_page_flip,
1713 .page_flip_pending = &evergreen_page_flip_pending,
1714 },
1715 };
1716
1717 static struct radeon_asic trinity_asic = {
1718 .init = &cayman_init,
1719 .fini = &cayman_fini,
1720 .suspend = &cayman_suspend,
1721 .resume = &cayman_resume,
1722 .asic_reset = &cayman_asic_reset,
1723 .vga_set_state = &r600_vga_set_state,
1724 .mmio_hdp_flush = r600_mmio_hdp_flush,
1725 .gui_idle = &r600_gui_idle,
1726 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1727 .get_xclk = &r600_get_xclk,
1728 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1729 .gart = {
1730 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1731 .set_page = &rs600_gart_set_page,
1732 },
1733 .vm = {
1734 .init = &cayman_vm_init,
1735 .fini = &cayman_vm_fini,
1736 .copy_pages = &cayman_dma_vm_copy_pages,
1737 .write_pages = &cayman_dma_vm_write_pages,
1738 .set_pages = &cayman_dma_vm_set_pages,
1739 .pad_ib = &cayman_dma_vm_pad_ib,
1740 },
1741 .ring = {
1742 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1743 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1744 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1745 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1746 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1747 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1748 },
1749 .irq = {
1750 .set = &evergreen_irq_set,
1751 .process = &evergreen_irq_process,
1752 },
1753 .display = {
1754 .bandwidth_update = &dce6_bandwidth_update,
1755 .get_vblank_counter = &evergreen_get_vblank_counter,
1756 .wait_for_vblank = &dce4_wait_for_vblank,
1757 .set_backlight_level = &atombios_set_backlight_level,
1758 .get_backlight_level = &atombios_get_backlight_level,
1759 .hdmi_enable = &evergreen_hdmi_enable,
1760 },
1761 .copy = {
1762 .blit = &r600_copy_cpdma,
1763 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1764 .dma = &evergreen_copy_dma,
1765 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1766 .copy = &evergreen_copy_dma,
1767 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1768 },
1769 .surface = {
1770 .set_reg = r600_set_surface_reg,
1771 .clear_reg = r600_clear_surface_reg,
1772 },
1773 .hpd = {
1774 .init = &evergreen_hpd_init,
1775 .fini = &evergreen_hpd_fini,
1776 .sense = &evergreen_hpd_sense,
1777 .set_polarity = &evergreen_hpd_set_polarity,
1778 },
1779 .pm = {
1780 .misc = &evergreen_pm_misc,
1781 .prepare = &evergreen_pm_prepare,
1782 .finish = &evergreen_pm_finish,
1783 .init_profile = &sumo_pm_init_profile,
1784 .get_dynpm_state = &r600_pm_get_dynpm_state,
1785 .get_engine_clock = &radeon_atom_get_engine_clock,
1786 .set_engine_clock = &radeon_atom_set_engine_clock,
1787 .get_memory_clock = NULL,
1788 .set_memory_clock = NULL,
1789 .get_pcie_lanes = NULL,
1790 .set_pcie_lanes = NULL,
1791 .set_clock_gating = NULL,
1792 .set_uvd_clocks = &sumo_set_uvd_clocks,
1793 .get_temperature = &tn_get_temp,
1794 },
1795 .dpm = {
1796 .init = &trinity_dpm_init,
1797 .setup_asic = &trinity_dpm_setup_asic,
1798 .enable = &trinity_dpm_enable,
1799 .late_enable = &trinity_dpm_late_enable,
1800 .disable = &trinity_dpm_disable,
1801 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1802 .set_power_state = &trinity_dpm_set_power_state,
1803 .post_set_power_state = &trinity_dpm_post_set_power_state,
1804 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1805 .fini = &trinity_dpm_fini,
1806 .get_sclk = &trinity_dpm_get_sclk,
1807 .get_mclk = &trinity_dpm_get_mclk,
1808 .print_power_state = &trinity_dpm_print_power_state,
1809 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1810 .force_performance_level = &trinity_dpm_force_performance_level,
1811 .enable_bapm = &trinity_dpm_enable_bapm,
1812 },
1813 .pflip = {
1814 .page_flip = &evergreen_page_flip,
1815 .page_flip_pending = &evergreen_page_flip_pending,
1816 },
1817 };
1818
1819 static struct radeon_asic_ring si_gfx_ring = {
1820 .ib_execute = &si_ring_ib_execute,
1821 .ib_parse = &si_ib_parse,
1822 .emit_fence = &si_fence_ring_emit,
1823 .emit_semaphore = &r600_semaphore_ring_emit,
1824 .cs_parse = NULL,
1825 .ring_test = &r600_ring_test,
1826 .ib_test = &r600_ib_test,
1827 .is_lockup = &si_gfx_is_lockup,
1828 .vm_flush = &si_vm_flush,
1829 .get_rptr = &cayman_gfx_get_rptr,
1830 .get_wptr = &cayman_gfx_get_wptr,
1831 .set_wptr = &cayman_gfx_set_wptr,
1832 };
1833
1834 static struct radeon_asic_ring si_dma_ring = {
1835 .ib_execute = &cayman_dma_ring_ib_execute,
1836 .ib_parse = &evergreen_dma_ib_parse,
1837 .emit_fence = &evergreen_dma_fence_ring_emit,
1838 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1839 .cs_parse = NULL,
1840 .ring_test = &r600_dma_ring_test,
1841 .ib_test = &r600_dma_ib_test,
1842 .is_lockup = &si_dma_is_lockup,
1843 .vm_flush = &si_dma_vm_flush,
1844 .get_rptr = &cayman_dma_get_rptr,
1845 .get_wptr = &cayman_dma_get_wptr,
1846 .set_wptr = &cayman_dma_set_wptr,
1847 };
1848
1849 static struct radeon_asic si_asic = {
1850 .init = &si_init,
1851 .fini = &si_fini,
1852 .suspend = &si_suspend,
1853 .resume = &si_resume,
1854 .asic_reset = &si_asic_reset,
1855 .vga_set_state = &r600_vga_set_state,
1856 .mmio_hdp_flush = r600_mmio_hdp_flush,
1857 .gui_idle = &r600_gui_idle,
1858 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1859 .get_xclk = &si_get_xclk,
1860 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1861 .gart = {
1862 .tlb_flush = &si_pcie_gart_tlb_flush,
1863 .set_page = &rs600_gart_set_page,
1864 },
1865 .vm = {
1866 .init = &si_vm_init,
1867 .fini = &si_vm_fini,
1868 .copy_pages = &si_dma_vm_copy_pages,
1869 .write_pages = &si_dma_vm_write_pages,
1870 .set_pages = &si_dma_vm_set_pages,
1871 .pad_ib = &cayman_dma_vm_pad_ib,
1872 },
1873 .ring = {
1874 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1875 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1876 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1877 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1878 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1879 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1880 },
1881 .irq = {
1882 .set = &si_irq_set,
1883 .process = &si_irq_process,
1884 },
1885 .display = {
1886 .bandwidth_update = &dce6_bandwidth_update,
1887 .get_vblank_counter = &evergreen_get_vblank_counter,
1888 .wait_for_vblank = &dce4_wait_for_vblank,
1889 .set_backlight_level = &atombios_set_backlight_level,
1890 .get_backlight_level = &atombios_get_backlight_level,
1891 .hdmi_enable = &evergreen_hdmi_enable,
1892 },
1893 .copy = {
1894 .blit = &r600_copy_cpdma,
1895 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1896 .dma = &si_copy_dma,
1897 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1898 .copy = &si_copy_dma,
1899 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1900 },
1901 .surface = {
1902 .set_reg = r600_set_surface_reg,
1903 .clear_reg = r600_clear_surface_reg,
1904 },
1905 .hpd = {
1906 .init = &evergreen_hpd_init,
1907 .fini = &evergreen_hpd_fini,
1908 .sense = &evergreen_hpd_sense,
1909 .set_polarity = &evergreen_hpd_set_polarity,
1910 },
1911 .pm = {
1912 .misc = &evergreen_pm_misc,
1913 .prepare = &evergreen_pm_prepare,
1914 .finish = &evergreen_pm_finish,
1915 .init_profile = &sumo_pm_init_profile,
1916 .get_dynpm_state = &r600_pm_get_dynpm_state,
1917 .get_engine_clock = &radeon_atom_get_engine_clock,
1918 .set_engine_clock = &radeon_atom_set_engine_clock,
1919 .get_memory_clock = &radeon_atom_get_memory_clock,
1920 .set_memory_clock = &radeon_atom_set_memory_clock,
1921 .get_pcie_lanes = &r600_get_pcie_lanes,
1922 .set_pcie_lanes = &r600_set_pcie_lanes,
1923 .set_clock_gating = NULL,
1924 .set_uvd_clocks = &si_set_uvd_clocks,
1925 .get_temperature = &si_get_temp,
1926 },
1927 .dpm = {
1928 .init = &si_dpm_init,
1929 .setup_asic = &si_dpm_setup_asic,
1930 .enable = &si_dpm_enable,
1931 .late_enable = &si_dpm_late_enable,
1932 .disable = &si_dpm_disable,
1933 .pre_set_power_state = &si_dpm_pre_set_power_state,
1934 .set_power_state = &si_dpm_set_power_state,
1935 .post_set_power_state = &si_dpm_post_set_power_state,
1936 .display_configuration_changed = &si_dpm_display_configuration_changed,
1937 .fini = &si_dpm_fini,
1938 .get_sclk = &ni_dpm_get_sclk,
1939 .get_mclk = &ni_dpm_get_mclk,
1940 .print_power_state = &ni_dpm_print_power_state,
1941 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1942 .force_performance_level = &si_dpm_force_performance_level,
1943 .vblank_too_short = &ni_dpm_vblank_too_short,
1944 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
1945 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
1946 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
1947 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
1948 },
1949 .pflip = {
1950 .page_flip = &evergreen_page_flip,
1951 .page_flip_pending = &evergreen_page_flip_pending,
1952 },
1953 };
1954
1955 static struct radeon_asic_ring ci_gfx_ring = {
1956 .ib_execute = &cik_ring_ib_execute,
1957 .ib_parse = &cik_ib_parse,
1958 .emit_fence = &cik_fence_gfx_ring_emit,
1959 .emit_semaphore = &cik_semaphore_ring_emit,
1960 .cs_parse = NULL,
1961 .ring_test = &cik_ring_test,
1962 .ib_test = &cik_ib_test,
1963 .is_lockup = &cik_gfx_is_lockup,
1964 .vm_flush = &cik_vm_flush,
1965 .get_rptr = &cik_gfx_get_rptr,
1966 .get_wptr = &cik_gfx_get_wptr,
1967 .set_wptr = &cik_gfx_set_wptr,
1968 };
1969
1970 static struct radeon_asic_ring ci_cp_ring = {
1971 .ib_execute = &cik_ring_ib_execute,
1972 .ib_parse = &cik_ib_parse,
1973 .emit_fence = &cik_fence_compute_ring_emit,
1974 .emit_semaphore = &cik_semaphore_ring_emit,
1975 .cs_parse = NULL,
1976 .ring_test = &cik_ring_test,
1977 .ib_test = &cik_ib_test,
1978 .is_lockup = &cik_gfx_is_lockup,
1979 .vm_flush = &cik_vm_flush,
1980 .get_rptr = &cik_compute_get_rptr,
1981 .get_wptr = &cik_compute_get_wptr,
1982 .set_wptr = &cik_compute_set_wptr,
1983 };
1984
1985 static struct radeon_asic_ring ci_dma_ring = {
1986 .ib_execute = &cik_sdma_ring_ib_execute,
1987 .ib_parse = &cik_ib_parse,
1988 .emit_fence = &cik_sdma_fence_ring_emit,
1989 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
1990 .cs_parse = NULL,
1991 .ring_test = &cik_sdma_ring_test,
1992 .ib_test = &cik_sdma_ib_test,
1993 .is_lockup = &cik_sdma_is_lockup,
1994 .vm_flush = &cik_dma_vm_flush,
1995 .get_rptr = &cik_sdma_get_rptr,
1996 .get_wptr = &cik_sdma_get_wptr,
1997 .set_wptr = &cik_sdma_set_wptr,
1998 };
1999
2000 static struct radeon_asic_ring ci_vce_ring = {
2001 .ib_execute = &radeon_vce_ib_execute,
2002 .emit_fence = &radeon_vce_fence_emit,
2003 .emit_semaphore = &radeon_vce_semaphore_emit,
2004 .cs_parse = &radeon_vce_cs_parse,
2005 .ring_test = &radeon_vce_ring_test,
2006 .ib_test = &radeon_vce_ib_test,
2007 .is_lockup = &radeon_ring_test_lockup,
2008 .get_rptr = &vce_v1_0_get_rptr,
2009 .get_wptr = &vce_v1_0_get_wptr,
2010 .set_wptr = &vce_v1_0_set_wptr,
2011 };
2012
2013 static struct radeon_asic ci_asic = {
2014 .init = &cik_init,
2015 .fini = &cik_fini,
2016 .suspend = &cik_suspend,
2017 .resume = &cik_resume,
2018 .asic_reset = &cik_asic_reset,
2019 .vga_set_state = &r600_vga_set_state,
2020 .mmio_hdp_flush = &r600_mmio_hdp_flush,
2021 .gui_idle = &r600_gui_idle,
2022 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2023 .get_xclk = &cik_get_xclk,
2024 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2025 .gart = {
2026 .tlb_flush = &cik_pcie_gart_tlb_flush,
2027 .set_page = &rs600_gart_set_page,
2028 },
2029 .vm = {
2030 .init = &cik_vm_init,
2031 .fini = &cik_vm_fini,
2032 .copy_pages = &cik_sdma_vm_copy_pages,
2033 .write_pages = &cik_sdma_vm_write_pages,
2034 .set_pages = &cik_sdma_vm_set_pages,
2035 .pad_ib = &cik_sdma_vm_pad_ib,
2036 },
2037 .ring = {
2038 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2039 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2040 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2041 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2042 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2043 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2044 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2045 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2046 },
2047 .irq = {
2048 .set = &cik_irq_set,
2049 .process = &cik_irq_process,
2050 },
2051 .display = {
2052 .bandwidth_update = &dce8_bandwidth_update,
2053 .get_vblank_counter = &evergreen_get_vblank_counter,
2054 .wait_for_vblank = &dce4_wait_for_vblank,
2055 .set_backlight_level = &atombios_set_backlight_level,
2056 .get_backlight_level = &atombios_get_backlight_level,
2057 .hdmi_enable = &evergreen_hdmi_enable,
2058 },
2059 .copy = {
2060 .blit = &cik_copy_cpdma,
2061 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2062 .dma = &cik_copy_dma,
2063 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2064 .copy = &cik_copy_dma,
2065 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2066 },
2067 .surface = {
2068 .set_reg = r600_set_surface_reg,
2069 .clear_reg = r600_clear_surface_reg,
2070 },
2071 .hpd = {
2072 .init = &evergreen_hpd_init,
2073 .fini = &evergreen_hpd_fini,
2074 .sense = &evergreen_hpd_sense,
2075 .set_polarity = &evergreen_hpd_set_polarity,
2076 },
2077 .pm = {
2078 .misc = &evergreen_pm_misc,
2079 .prepare = &evergreen_pm_prepare,
2080 .finish = &evergreen_pm_finish,
2081 .init_profile = &sumo_pm_init_profile,
2082 .get_dynpm_state = &r600_pm_get_dynpm_state,
2083 .get_engine_clock = &radeon_atom_get_engine_clock,
2084 .set_engine_clock = &radeon_atom_set_engine_clock,
2085 .get_memory_clock = &radeon_atom_get_memory_clock,
2086 .set_memory_clock = &radeon_atom_set_memory_clock,
2087 .get_pcie_lanes = NULL,
2088 .set_pcie_lanes = NULL,
2089 .set_clock_gating = NULL,
2090 .set_uvd_clocks = &cik_set_uvd_clocks,
2091 .set_vce_clocks = &cik_set_vce_clocks,
2092 .get_temperature = &ci_get_temp,
2093 },
2094 .dpm = {
2095 .init = &ci_dpm_init,
2096 .setup_asic = &ci_dpm_setup_asic,
2097 .enable = &ci_dpm_enable,
2098 .late_enable = &ci_dpm_late_enable,
2099 .disable = &ci_dpm_disable,
2100 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2101 .set_power_state = &ci_dpm_set_power_state,
2102 .post_set_power_state = &ci_dpm_post_set_power_state,
2103 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2104 .fini = &ci_dpm_fini,
2105 .get_sclk = &ci_dpm_get_sclk,
2106 .get_mclk = &ci_dpm_get_mclk,
2107 .print_power_state = &ci_dpm_print_power_state,
2108 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2109 .force_performance_level = &ci_dpm_force_performance_level,
2110 .vblank_too_short = &ci_dpm_vblank_too_short,
2111 .powergate_uvd = &ci_dpm_powergate_uvd,
2112 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
2113 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
2114 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
2115 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
2116 },
2117 .pflip = {
2118 .page_flip = &evergreen_page_flip,
2119 .page_flip_pending = &evergreen_page_flip_pending,
2120 },
2121 };
2122
2123 static struct radeon_asic kv_asic = {
2124 .init = &cik_init,
2125 .fini = &cik_fini,
2126 .suspend = &cik_suspend,
2127 .resume = &cik_resume,
2128 .asic_reset = &cik_asic_reset,
2129 .vga_set_state = &r600_vga_set_state,
2130 .mmio_hdp_flush = &r600_mmio_hdp_flush,
2131 .gui_idle = &r600_gui_idle,
2132 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2133 .get_xclk = &cik_get_xclk,
2134 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2135 .gart = {
2136 .tlb_flush = &cik_pcie_gart_tlb_flush,
2137 .set_page = &rs600_gart_set_page,
2138 },
2139 .vm = {
2140 .init = &cik_vm_init,
2141 .fini = &cik_vm_fini,
2142 .copy_pages = &cik_sdma_vm_copy_pages,
2143 .write_pages = &cik_sdma_vm_write_pages,
2144 .set_pages = &cik_sdma_vm_set_pages,
2145 .pad_ib = &cik_sdma_vm_pad_ib,
2146 },
2147 .ring = {
2148 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2149 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2150 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2151 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2152 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2153 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2154 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2155 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2156 },
2157 .irq = {
2158 .set = &cik_irq_set,
2159 .process = &cik_irq_process,
2160 },
2161 .display = {
2162 .bandwidth_update = &dce8_bandwidth_update,
2163 .get_vblank_counter = &evergreen_get_vblank_counter,
2164 .wait_for_vblank = &dce4_wait_for_vblank,
2165 .set_backlight_level = &atombios_set_backlight_level,
2166 .get_backlight_level = &atombios_get_backlight_level,
2167 .hdmi_enable = &evergreen_hdmi_enable,
2168 },
2169 .copy = {
2170 .blit = &cik_copy_cpdma,
2171 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2172 .dma = &cik_copy_dma,
2173 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2174 .copy = &cik_copy_dma,
2175 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2176 },
2177 .surface = {
2178 .set_reg = r600_set_surface_reg,
2179 .clear_reg = r600_clear_surface_reg,
2180 },
2181 .hpd = {
2182 .init = &evergreen_hpd_init,
2183 .fini = &evergreen_hpd_fini,
2184 .sense = &evergreen_hpd_sense,
2185 .set_polarity = &evergreen_hpd_set_polarity,
2186 },
2187 .pm = {
2188 .misc = &evergreen_pm_misc,
2189 .prepare = &evergreen_pm_prepare,
2190 .finish = &evergreen_pm_finish,
2191 .init_profile = &sumo_pm_init_profile,
2192 .get_dynpm_state = &r600_pm_get_dynpm_state,
2193 .get_engine_clock = &radeon_atom_get_engine_clock,
2194 .set_engine_clock = &radeon_atom_set_engine_clock,
2195 .get_memory_clock = &radeon_atom_get_memory_clock,
2196 .set_memory_clock = &radeon_atom_set_memory_clock,
2197 .get_pcie_lanes = NULL,
2198 .set_pcie_lanes = NULL,
2199 .set_clock_gating = NULL,
2200 .set_uvd_clocks = &cik_set_uvd_clocks,
2201 .set_vce_clocks = &cik_set_vce_clocks,
2202 .get_temperature = &kv_get_temp,
2203 },
2204 .dpm = {
2205 .init = &kv_dpm_init,
2206 .setup_asic = &kv_dpm_setup_asic,
2207 .enable = &kv_dpm_enable,
2208 .late_enable = &kv_dpm_late_enable,
2209 .disable = &kv_dpm_disable,
2210 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2211 .set_power_state = &kv_dpm_set_power_state,
2212 .post_set_power_state = &kv_dpm_post_set_power_state,
2213 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2214 .fini = &kv_dpm_fini,
2215 .get_sclk = &kv_dpm_get_sclk,
2216 .get_mclk = &kv_dpm_get_mclk,
2217 .print_power_state = &kv_dpm_print_power_state,
2218 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2219 .force_performance_level = &kv_dpm_force_performance_level,
2220 .powergate_uvd = &kv_dpm_powergate_uvd,
2221 .enable_bapm = &kv_dpm_enable_bapm,
2222 },
2223 .pflip = {
2224 .page_flip = &evergreen_page_flip,
2225 .page_flip_pending = &evergreen_page_flip_pending,
2226 },
2227 };
2228
2229 /**
2230 * radeon_asic_init - register asic specific callbacks
2231 *
2232 * @rdev: radeon device pointer
2233 *
2234 * Registers the appropriate asic specific callbacks for each
2235 * chip family. Also sets other asics specific info like the number
2236 * of crtcs and the register aperture accessors (all asics).
2237 * Returns 0 for success.
2238 */
2239 int radeon_asic_init(struct radeon_device *rdev)
2240 {
2241 radeon_register_accessor_init(rdev);
2242
2243 /* set the number of crtcs */
2244 if (rdev->flags & RADEON_SINGLE_CRTC)
2245 rdev->num_crtc = 1;
2246 else
2247 rdev->num_crtc = 2;
2248
2249 rdev->has_uvd = false;
2250
2251 switch (rdev->family) {
2252 case CHIP_R100:
2253 case CHIP_RV100:
2254 case CHIP_RS100:
2255 case CHIP_RV200:
2256 case CHIP_RS200:
2257 rdev->asic = &r100_asic;
2258 break;
2259 case CHIP_R200:
2260 case CHIP_RV250:
2261 case CHIP_RS300:
2262 case CHIP_RV280:
2263 rdev->asic = &r200_asic;
2264 break;
2265 case CHIP_R300:
2266 case CHIP_R350:
2267 case CHIP_RV350:
2268 case CHIP_RV380:
2269 if (rdev->flags & RADEON_IS_PCIE)
2270 rdev->asic = &r300_asic_pcie;
2271 else
2272 rdev->asic = &r300_asic;
2273 break;
2274 case CHIP_R420:
2275 case CHIP_R423:
2276 case CHIP_RV410:
2277 rdev->asic = &r420_asic;
2278 /* handle macs */
2279 if (rdev->bios == NULL) {
2280 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2281 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2282 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2283 rdev->asic->pm.set_memory_clock = NULL;
2284 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2285 }
2286 break;
2287 case CHIP_RS400:
2288 case CHIP_RS480:
2289 rdev->asic = &rs400_asic;
2290 break;
2291 case CHIP_RS600:
2292 rdev->asic = &rs600_asic;
2293 break;
2294 case CHIP_RS690:
2295 case CHIP_RS740:
2296 rdev->asic = &rs690_asic;
2297 break;
2298 case CHIP_RV515:
2299 rdev->asic = &rv515_asic;
2300 break;
2301 case CHIP_R520:
2302 case CHIP_RV530:
2303 case CHIP_RV560:
2304 case CHIP_RV570:
2305 case CHIP_R580:
2306 rdev->asic = &r520_asic;
2307 break;
2308 case CHIP_R600:
2309 rdev->asic = &r600_asic;
2310 break;
2311 case CHIP_RV610:
2312 case CHIP_RV630:
2313 case CHIP_RV620:
2314 case CHIP_RV635:
2315 case CHIP_RV670:
2316 rdev->asic = &rv6xx_asic;
2317 rdev->has_uvd = true;
2318 break;
2319 case CHIP_RS780:
2320 case CHIP_RS880:
2321 rdev->asic = &rs780_asic;
2322 /* 760G/780V/880V don't have UVD */
2323 if ((rdev->pdev->device == 0x9616)||
2324 (rdev->pdev->device == 0x9611)||
2325 (rdev->pdev->device == 0x9613)||
2326 (rdev->pdev->device == 0x9711)||
2327 (rdev->pdev->device == 0x9713))
2328 rdev->has_uvd = false;
2329 else
2330 rdev->has_uvd = true;
2331 break;
2332 case CHIP_RV770:
2333 case CHIP_RV730:
2334 case CHIP_RV710:
2335 case CHIP_RV740:
2336 rdev->asic = &rv770_asic;
2337 rdev->has_uvd = true;
2338 break;
2339 case CHIP_CEDAR:
2340 case CHIP_REDWOOD:
2341 case CHIP_JUNIPER:
2342 case CHIP_CYPRESS:
2343 case CHIP_HEMLOCK:
2344 /* set num crtcs */
2345 if (rdev->family == CHIP_CEDAR)
2346 rdev->num_crtc = 4;
2347 else
2348 rdev->num_crtc = 6;
2349 rdev->asic = &evergreen_asic;
2350 rdev->has_uvd = true;
2351 break;
2352 case CHIP_PALM:
2353 case CHIP_SUMO:
2354 case CHIP_SUMO2:
2355 rdev->asic = &sumo_asic;
2356 rdev->has_uvd = true;
2357 break;
2358 case CHIP_BARTS:
2359 case CHIP_TURKS:
2360 case CHIP_CAICOS:
2361 /* set num crtcs */
2362 if (rdev->family == CHIP_CAICOS)
2363 rdev->num_crtc = 4;
2364 else
2365 rdev->num_crtc = 6;
2366 rdev->asic = &btc_asic;
2367 rdev->has_uvd = true;
2368 break;
2369 case CHIP_CAYMAN:
2370 rdev->asic = &cayman_asic;
2371 /* set num crtcs */
2372 rdev->num_crtc = 6;
2373 rdev->has_uvd = true;
2374 break;
2375 case CHIP_ARUBA:
2376 rdev->asic = &trinity_asic;
2377 /* set num crtcs */
2378 rdev->num_crtc = 4;
2379 rdev->has_uvd = true;
2380 break;
2381 case CHIP_TAHITI:
2382 case CHIP_PITCAIRN:
2383 case CHIP_VERDE:
2384 case CHIP_OLAND:
2385 case CHIP_HAINAN:
2386 rdev->asic = &si_asic;
2387 /* set num crtcs */
2388 if (rdev->family == CHIP_HAINAN)
2389 rdev->num_crtc = 0;
2390 else if (rdev->family == CHIP_OLAND)
2391 rdev->num_crtc = 2;
2392 else
2393 rdev->num_crtc = 6;
2394 if (rdev->family == CHIP_HAINAN)
2395 rdev->has_uvd = false;
2396 else
2397 rdev->has_uvd = true;
2398 switch (rdev->family) {
2399 case CHIP_TAHITI:
2400 rdev->cg_flags =
2401 RADEON_CG_SUPPORT_GFX_MGCG |
2402 RADEON_CG_SUPPORT_GFX_MGLS |
2403 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2404 RADEON_CG_SUPPORT_GFX_CGLS |
2405 RADEON_CG_SUPPORT_GFX_CGTS |
2406 RADEON_CG_SUPPORT_GFX_CP_LS |
2407 RADEON_CG_SUPPORT_MC_MGCG |
2408 RADEON_CG_SUPPORT_SDMA_MGCG |
2409 RADEON_CG_SUPPORT_BIF_LS |
2410 RADEON_CG_SUPPORT_VCE_MGCG |
2411 RADEON_CG_SUPPORT_UVD_MGCG |
2412 RADEON_CG_SUPPORT_HDP_LS |
2413 RADEON_CG_SUPPORT_HDP_MGCG;
2414 rdev->pg_flags = 0;
2415 break;
2416 case CHIP_PITCAIRN:
2417 rdev->cg_flags =
2418 RADEON_CG_SUPPORT_GFX_MGCG |
2419 RADEON_CG_SUPPORT_GFX_MGLS |
2420 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2421 RADEON_CG_SUPPORT_GFX_CGLS |
2422 RADEON_CG_SUPPORT_GFX_CGTS |
2423 RADEON_CG_SUPPORT_GFX_CP_LS |
2424 RADEON_CG_SUPPORT_GFX_RLC_LS |
2425 RADEON_CG_SUPPORT_MC_LS |
2426 RADEON_CG_SUPPORT_MC_MGCG |
2427 RADEON_CG_SUPPORT_SDMA_MGCG |
2428 RADEON_CG_SUPPORT_BIF_LS |
2429 RADEON_CG_SUPPORT_VCE_MGCG |
2430 RADEON_CG_SUPPORT_UVD_MGCG |
2431 RADEON_CG_SUPPORT_HDP_LS |
2432 RADEON_CG_SUPPORT_HDP_MGCG;
2433 rdev->pg_flags = 0;
2434 break;
2435 case CHIP_VERDE:
2436 rdev->cg_flags =
2437 RADEON_CG_SUPPORT_GFX_MGCG |
2438 RADEON_CG_SUPPORT_GFX_MGLS |
2439 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2440 RADEON_CG_SUPPORT_GFX_CGLS |
2441 RADEON_CG_SUPPORT_GFX_CGTS |
2442 RADEON_CG_SUPPORT_GFX_CP_LS |
2443 RADEON_CG_SUPPORT_GFX_RLC_LS |
2444 RADEON_CG_SUPPORT_MC_LS |
2445 RADEON_CG_SUPPORT_MC_MGCG |
2446 RADEON_CG_SUPPORT_SDMA_MGCG |
2447 RADEON_CG_SUPPORT_BIF_LS |
2448 RADEON_CG_SUPPORT_VCE_MGCG |
2449 RADEON_CG_SUPPORT_UVD_MGCG |
2450 RADEON_CG_SUPPORT_HDP_LS |
2451 RADEON_CG_SUPPORT_HDP_MGCG;
2452 rdev->pg_flags = 0 |
2453 /*RADEON_PG_SUPPORT_GFX_PG | */
2454 RADEON_PG_SUPPORT_SDMA;
2455 break;
2456 case CHIP_OLAND:
2457 rdev->cg_flags =
2458 RADEON_CG_SUPPORT_GFX_MGCG |
2459 RADEON_CG_SUPPORT_GFX_MGLS |
2460 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2461 RADEON_CG_SUPPORT_GFX_CGLS |
2462 RADEON_CG_SUPPORT_GFX_CGTS |
2463 RADEON_CG_SUPPORT_GFX_CP_LS |
2464 RADEON_CG_SUPPORT_GFX_RLC_LS |
2465 RADEON_CG_SUPPORT_MC_LS |
2466 RADEON_CG_SUPPORT_MC_MGCG |
2467 RADEON_CG_SUPPORT_SDMA_MGCG |
2468 RADEON_CG_SUPPORT_BIF_LS |
2469 RADEON_CG_SUPPORT_UVD_MGCG |
2470 RADEON_CG_SUPPORT_HDP_LS |
2471 RADEON_CG_SUPPORT_HDP_MGCG;
2472 rdev->pg_flags = 0;
2473 break;
2474 case CHIP_HAINAN:
2475 rdev->cg_flags =
2476 RADEON_CG_SUPPORT_GFX_MGCG |
2477 RADEON_CG_SUPPORT_GFX_MGLS |
2478 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2479 RADEON_CG_SUPPORT_GFX_CGLS |
2480 RADEON_CG_SUPPORT_GFX_CGTS |
2481 RADEON_CG_SUPPORT_GFX_CP_LS |
2482 RADEON_CG_SUPPORT_GFX_RLC_LS |
2483 RADEON_CG_SUPPORT_MC_LS |
2484 RADEON_CG_SUPPORT_MC_MGCG |
2485 RADEON_CG_SUPPORT_SDMA_MGCG |
2486 RADEON_CG_SUPPORT_BIF_LS |
2487 RADEON_CG_SUPPORT_HDP_LS |
2488 RADEON_CG_SUPPORT_HDP_MGCG;
2489 rdev->pg_flags = 0;
2490 break;
2491 default:
2492 rdev->cg_flags = 0;
2493 rdev->pg_flags = 0;
2494 break;
2495 }
2496 break;
2497 case CHIP_BONAIRE:
2498 case CHIP_HAWAII:
2499 rdev->asic = &ci_asic;
2500 rdev->num_crtc = 6;
2501 rdev->has_uvd = true;
2502 if (rdev->family == CHIP_BONAIRE) {
2503 rdev->cg_flags =
2504 RADEON_CG_SUPPORT_GFX_MGCG |
2505 RADEON_CG_SUPPORT_GFX_MGLS |
2506 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2507 RADEON_CG_SUPPORT_GFX_CGLS |
2508 RADEON_CG_SUPPORT_GFX_CGTS |
2509 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2510 RADEON_CG_SUPPORT_GFX_CP_LS |
2511 RADEON_CG_SUPPORT_MC_LS |
2512 RADEON_CG_SUPPORT_MC_MGCG |
2513 RADEON_CG_SUPPORT_SDMA_MGCG |
2514 RADEON_CG_SUPPORT_SDMA_LS |
2515 RADEON_CG_SUPPORT_BIF_LS |
2516 RADEON_CG_SUPPORT_VCE_MGCG |
2517 RADEON_CG_SUPPORT_UVD_MGCG |
2518 RADEON_CG_SUPPORT_HDP_LS |
2519 RADEON_CG_SUPPORT_HDP_MGCG;
2520 rdev->pg_flags = 0;
2521 } else {
2522 rdev->cg_flags =
2523 RADEON_CG_SUPPORT_GFX_MGCG |
2524 RADEON_CG_SUPPORT_GFX_MGLS |
2525 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2526 RADEON_CG_SUPPORT_GFX_CGLS |
2527 RADEON_CG_SUPPORT_GFX_CGTS |
2528 RADEON_CG_SUPPORT_GFX_CP_LS |
2529 RADEON_CG_SUPPORT_MC_LS |
2530 RADEON_CG_SUPPORT_MC_MGCG |
2531 RADEON_CG_SUPPORT_SDMA_MGCG |
2532 RADEON_CG_SUPPORT_SDMA_LS |
2533 RADEON_CG_SUPPORT_BIF_LS |
2534 RADEON_CG_SUPPORT_VCE_MGCG |
2535 RADEON_CG_SUPPORT_UVD_MGCG |
2536 RADEON_CG_SUPPORT_HDP_LS |
2537 RADEON_CG_SUPPORT_HDP_MGCG;
2538 rdev->pg_flags = 0;
2539 }
2540 break;
2541 case CHIP_KAVERI:
2542 case CHIP_KABINI:
2543 case CHIP_MULLINS:
2544 rdev->asic = &kv_asic;
2545 /* set num crtcs */
2546 if (rdev->family == CHIP_KAVERI) {
2547 rdev->num_crtc = 4;
2548 rdev->cg_flags =
2549 RADEON_CG_SUPPORT_GFX_MGCG |
2550 RADEON_CG_SUPPORT_GFX_MGLS |
2551 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2552 RADEON_CG_SUPPORT_GFX_CGLS |
2553 RADEON_CG_SUPPORT_GFX_CGTS |
2554 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2555 RADEON_CG_SUPPORT_GFX_CP_LS |
2556 RADEON_CG_SUPPORT_SDMA_MGCG |
2557 RADEON_CG_SUPPORT_SDMA_LS |
2558 RADEON_CG_SUPPORT_BIF_LS |
2559 RADEON_CG_SUPPORT_VCE_MGCG |
2560 RADEON_CG_SUPPORT_UVD_MGCG |
2561 RADEON_CG_SUPPORT_HDP_LS |
2562 RADEON_CG_SUPPORT_HDP_MGCG;
2563 rdev->pg_flags = 0;
2564 /*RADEON_PG_SUPPORT_GFX_PG |
2565 RADEON_PG_SUPPORT_GFX_SMG |
2566 RADEON_PG_SUPPORT_GFX_DMG |
2567 RADEON_PG_SUPPORT_UVD |
2568 RADEON_PG_SUPPORT_VCE |
2569 RADEON_PG_SUPPORT_CP |
2570 RADEON_PG_SUPPORT_GDS |
2571 RADEON_PG_SUPPORT_RLC_SMU_HS |
2572 RADEON_PG_SUPPORT_ACP |
2573 RADEON_PG_SUPPORT_SAMU;*/
2574 } else {
2575 rdev->num_crtc = 2;
2576 rdev->cg_flags =
2577 RADEON_CG_SUPPORT_GFX_MGCG |
2578 RADEON_CG_SUPPORT_GFX_MGLS |
2579 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2580 RADEON_CG_SUPPORT_GFX_CGLS |
2581 RADEON_CG_SUPPORT_GFX_CGTS |
2582 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2583 RADEON_CG_SUPPORT_GFX_CP_LS |
2584 RADEON_CG_SUPPORT_SDMA_MGCG |
2585 RADEON_CG_SUPPORT_SDMA_LS |
2586 RADEON_CG_SUPPORT_BIF_LS |
2587 RADEON_CG_SUPPORT_VCE_MGCG |
2588 RADEON_CG_SUPPORT_UVD_MGCG |
2589 RADEON_CG_SUPPORT_HDP_LS |
2590 RADEON_CG_SUPPORT_HDP_MGCG;
2591 rdev->pg_flags = 0;
2592 /*RADEON_PG_SUPPORT_GFX_PG |
2593 RADEON_PG_SUPPORT_GFX_SMG |
2594 RADEON_PG_SUPPORT_UVD |
2595 RADEON_PG_SUPPORT_VCE |
2596 RADEON_PG_SUPPORT_CP |
2597 RADEON_PG_SUPPORT_GDS |
2598 RADEON_PG_SUPPORT_RLC_SMU_HS |
2599 RADEON_PG_SUPPORT_SAMU;*/
2600 }
2601 rdev->has_uvd = true;
2602 break;
2603 default:
2604 /* FIXME: not supported yet */
2605 return -EINVAL;
2606 }
2607
2608 if (rdev->flags & RADEON_IS_IGP) {
2609 rdev->asic->pm.get_memory_clock = NULL;
2610 rdev->asic->pm.set_memory_clock = NULL;
2611 }
2612
2613 return 0;
2614 }
2615
Linux kernel - Deliverables
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