2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/console.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
37 #include "radeon_asic.h"
41 * Registers accessors functions.
44 * radeon_invalid_rreg - dummy reg read function
46 * @rdev: radeon device pointer
47 * @reg: offset of register
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
53 static uint32_t radeon_invalid_rreg(struct radeon_device
*rdev
, uint32_t reg
)
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
61 * radeon_invalid_wreg - dummy reg write function
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
70 static void radeon_invalid_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
78 * radeon_register_accessor_init - sets up the register accessor callbacks
80 * @rdev: radeon device pointer
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
85 static void radeon_register_accessor_init(struct radeon_device
*rdev
)
87 rdev
->mc_rreg
= &radeon_invalid_rreg
;
88 rdev
->mc_wreg
= &radeon_invalid_wreg
;
89 rdev
->pll_rreg
= &radeon_invalid_rreg
;
90 rdev
->pll_wreg
= &radeon_invalid_wreg
;
91 rdev
->pciep_rreg
= &radeon_invalid_rreg
;
92 rdev
->pciep_wreg
= &radeon_invalid_wreg
;
94 /* Don't change order as we are overridding accessor. */
95 if (rdev
->family
< CHIP_RV515
) {
96 rdev
->pcie_reg_mask
= 0xff;
98 rdev
->pcie_reg_mask
= 0x7ff;
100 /* FIXME: not sure here */
101 if (rdev
->family
<= CHIP_R580
) {
102 rdev
->pll_rreg
= &r100_pll_rreg
;
103 rdev
->pll_wreg
= &r100_pll_wreg
;
105 if (rdev
->family
>= CHIP_R420
) {
106 rdev
->mc_rreg
= &r420_mc_rreg
;
107 rdev
->mc_wreg
= &r420_mc_wreg
;
109 if (rdev
->family
>= CHIP_RV515
) {
110 rdev
->mc_rreg
= &rv515_mc_rreg
;
111 rdev
->mc_wreg
= &rv515_mc_wreg
;
113 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
114 rdev
->mc_rreg
= &rs400_mc_rreg
;
115 rdev
->mc_wreg
= &rs400_mc_wreg
;
117 if (rdev
->family
== CHIP_RS690
|| rdev
->family
== CHIP_RS740
) {
118 rdev
->mc_rreg
= &rs690_mc_rreg
;
119 rdev
->mc_wreg
= &rs690_mc_wreg
;
121 if (rdev
->family
== CHIP_RS600
) {
122 rdev
->mc_rreg
= &rs600_mc_rreg
;
123 rdev
->mc_wreg
= &rs600_mc_wreg
;
125 if (rdev
->family
== CHIP_RS780
|| rdev
->family
== CHIP_RS880
) {
126 rdev
->mc_rreg
= &rs780_mc_rreg
;
127 rdev
->mc_wreg
= &rs780_mc_wreg
;
130 if (rdev
->family
>= CHIP_BONAIRE
) {
131 rdev
->pciep_rreg
= &cik_pciep_rreg
;
132 rdev
->pciep_wreg
= &cik_pciep_wreg
;
133 } else if (rdev
->family
>= CHIP_R600
) {
134 rdev
->pciep_rreg
= &r600_pciep_rreg
;
135 rdev
->pciep_wreg
= &r600_pciep_wreg
;
140 /* helper to disable agp */
142 * radeon_agp_disable - AGP disable helper function
144 * @rdev: radeon device pointer
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
149 void radeon_agp_disable(struct radeon_device
*rdev
)
151 rdev
->flags
&= ~RADEON_IS_AGP
;
152 if (rdev
->family
>= CHIP_R600
) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev
->flags
|= RADEON_IS_PCIE
;
155 } else if (rdev
->family
>= CHIP_RV515
||
156 rdev
->family
== CHIP_RV380
||
157 rdev
->family
== CHIP_RV410
||
158 rdev
->family
== CHIP_R423
) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev
->flags
|= RADEON_IS_PCIE
;
161 rdev
->asic
->gart
.tlb_flush
= &rv370_pcie_gart_tlb_flush
;
162 rdev
->asic
->gart
.set_page
= &rv370_pcie_gart_set_page
;
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev
->flags
|= RADEON_IS_PCI
;
166 rdev
->asic
->gart
.tlb_flush
= &r100_pci_gart_tlb_flush
;
167 rdev
->asic
->gart
.set_page
= &r100_pci_gart_set_page
;
169 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
176 static struct radeon_asic_ring r100_gfx_ring
= {
177 .ib_execute
= &r100_ring_ib_execute
,
178 .emit_fence
= &r100_fence_ring_emit
,
179 .emit_semaphore
= &r100_semaphore_ring_emit
,
180 .cs_parse
= &r100_cs_parse
,
181 .ring_start
= &r100_ring_start
,
182 .ring_test
= &r100_ring_test
,
183 .ib_test
= &r100_ib_test
,
184 .is_lockup
= &r100_gpu_is_lockup
,
185 .get_rptr
= &radeon_ring_generic_get_rptr
,
186 .get_wptr
= &radeon_ring_generic_get_wptr
,
187 .set_wptr
= &radeon_ring_generic_set_wptr
,
190 static struct radeon_asic r100_asic
= {
193 .suspend
= &r100_suspend
,
194 .resume
= &r100_resume
,
195 .vga_set_state
= &r100_vga_set_state
,
196 .asic_reset
= &r100_asic_reset
,
197 .ioctl_wait_idle
= NULL
,
198 .gui_idle
= &r100_gui_idle
,
199 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
201 .tlb_flush
= &r100_pci_gart_tlb_flush
,
202 .set_page
= &r100_pci_gart_set_page
,
205 [RADEON_RING_TYPE_GFX_INDEX
] = &r100_gfx_ring
208 .set
= &r100_irq_set
,
209 .process
= &r100_irq_process
,
212 .bandwidth_update
= &r100_bandwidth_update
,
213 .get_vblank_counter
= &r100_get_vblank_counter
,
214 .wait_for_vblank
= &r100_wait_for_vblank
,
215 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
216 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
219 .blit
= &r100_copy_blit
,
220 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
222 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
223 .copy
= &r100_copy_blit
,
224 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
227 .set_reg
= r100_set_surface_reg
,
228 .clear_reg
= r100_clear_surface_reg
,
231 .init
= &r100_hpd_init
,
232 .fini
= &r100_hpd_fini
,
233 .sense
= &r100_hpd_sense
,
234 .set_polarity
= &r100_hpd_set_polarity
,
237 .misc
= &r100_pm_misc
,
238 .prepare
= &r100_pm_prepare
,
239 .finish
= &r100_pm_finish
,
240 .init_profile
= &r100_pm_init_profile
,
241 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
242 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
243 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
244 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
245 .set_memory_clock
= NULL
,
246 .get_pcie_lanes
= NULL
,
247 .set_pcie_lanes
= NULL
,
248 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
251 .pre_page_flip
= &r100_pre_page_flip
,
252 .page_flip
= &r100_page_flip
,
253 .post_page_flip
= &r100_post_page_flip
,
257 static struct radeon_asic r200_asic
= {
260 .suspend
= &r100_suspend
,
261 .resume
= &r100_resume
,
262 .vga_set_state
= &r100_vga_set_state
,
263 .asic_reset
= &r100_asic_reset
,
264 .ioctl_wait_idle
= NULL
,
265 .gui_idle
= &r100_gui_idle
,
266 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
268 .tlb_flush
= &r100_pci_gart_tlb_flush
,
269 .set_page
= &r100_pci_gart_set_page
,
272 [RADEON_RING_TYPE_GFX_INDEX
] = &r100_gfx_ring
275 .set
= &r100_irq_set
,
276 .process
= &r100_irq_process
,
279 .bandwidth_update
= &r100_bandwidth_update
,
280 .get_vblank_counter
= &r100_get_vblank_counter
,
281 .wait_for_vblank
= &r100_wait_for_vblank
,
282 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
283 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
286 .blit
= &r100_copy_blit
,
287 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
288 .dma
= &r200_copy_dma
,
289 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
290 .copy
= &r100_copy_blit
,
291 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
294 .set_reg
= r100_set_surface_reg
,
295 .clear_reg
= r100_clear_surface_reg
,
298 .init
= &r100_hpd_init
,
299 .fini
= &r100_hpd_fini
,
300 .sense
= &r100_hpd_sense
,
301 .set_polarity
= &r100_hpd_set_polarity
,
304 .misc
= &r100_pm_misc
,
305 .prepare
= &r100_pm_prepare
,
306 .finish
= &r100_pm_finish
,
307 .init_profile
= &r100_pm_init_profile
,
308 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
309 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
310 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
311 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
312 .set_memory_clock
= NULL
,
313 .get_pcie_lanes
= NULL
,
314 .set_pcie_lanes
= NULL
,
315 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
318 .pre_page_flip
= &r100_pre_page_flip
,
319 .page_flip
= &r100_page_flip
,
320 .post_page_flip
= &r100_post_page_flip
,
324 static struct radeon_asic_ring r300_gfx_ring
= {
325 .ib_execute
= &r100_ring_ib_execute
,
326 .emit_fence
= &r300_fence_ring_emit
,
327 .emit_semaphore
= &r100_semaphore_ring_emit
,
328 .cs_parse
= &r300_cs_parse
,
329 .ring_start
= &r300_ring_start
,
330 .ring_test
= &r100_ring_test
,
331 .ib_test
= &r100_ib_test
,
332 .is_lockup
= &r100_gpu_is_lockup
,
333 .get_rptr
= &radeon_ring_generic_get_rptr
,
334 .get_wptr
= &radeon_ring_generic_get_wptr
,
335 .set_wptr
= &radeon_ring_generic_set_wptr
,
338 static struct radeon_asic r300_asic
= {
341 .suspend
= &r300_suspend
,
342 .resume
= &r300_resume
,
343 .vga_set_state
= &r100_vga_set_state
,
344 .asic_reset
= &r300_asic_reset
,
345 .ioctl_wait_idle
= NULL
,
346 .gui_idle
= &r100_gui_idle
,
347 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
349 .tlb_flush
= &r100_pci_gart_tlb_flush
,
350 .set_page
= &r100_pci_gart_set_page
,
353 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
356 .set
= &r100_irq_set
,
357 .process
= &r100_irq_process
,
360 .bandwidth_update
= &r100_bandwidth_update
,
361 .get_vblank_counter
= &r100_get_vblank_counter
,
362 .wait_for_vblank
= &r100_wait_for_vblank
,
363 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
364 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
367 .blit
= &r100_copy_blit
,
368 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
369 .dma
= &r200_copy_dma
,
370 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
371 .copy
= &r100_copy_blit
,
372 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
375 .set_reg
= r100_set_surface_reg
,
376 .clear_reg
= r100_clear_surface_reg
,
379 .init
= &r100_hpd_init
,
380 .fini
= &r100_hpd_fini
,
381 .sense
= &r100_hpd_sense
,
382 .set_polarity
= &r100_hpd_set_polarity
,
385 .misc
= &r100_pm_misc
,
386 .prepare
= &r100_pm_prepare
,
387 .finish
= &r100_pm_finish
,
388 .init_profile
= &r100_pm_init_profile
,
389 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
390 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
391 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
392 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
393 .set_memory_clock
= NULL
,
394 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
395 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
396 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
399 .pre_page_flip
= &r100_pre_page_flip
,
400 .page_flip
= &r100_page_flip
,
401 .post_page_flip
= &r100_post_page_flip
,
405 static struct radeon_asic r300_asic_pcie
= {
408 .suspend
= &r300_suspend
,
409 .resume
= &r300_resume
,
410 .vga_set_state
= &r100_vga_set_state
,
411 .asic_reset
= &r300_asic_reset
,
412 .ioctl_wait_idle
= NULL
,
413 .gui_idle
= &r100_gui_idle
,
414 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
416 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
417 .set_page
= &rv370_pcie_gart_set_page
,
420 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
423 .set
= &r100_irq_set
,
424 .process
= &r100_irq_process
,
427 .bandwidth_update
= &r100_bandwidth_update
,
428 .get_vblank_counter
= &r100_get_vblank_counter
,
429 .wait_for_vblank
= &r100_wait_for_vblank
,
430 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
431 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
434 .blit
= &r100_copy_blit
,
435 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
436 .dma
= &r200_copy_dma
,
437 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
438 .copy
= &r100_copy_blit
,
439 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
442 .set_reg
= r100_set_surface_reg
,
443 .clear_reg
= r100_clear_surface_reg
,
446 .init
= &r100_hpd_init
,
447 .fini
= &r100_hpd_fini
,
448 .sense
= &r100_hpd_sense
,
449 .set_polarity
= &r100_hpd_set_polarity
,
452 .misc
= &r100_pm_misc
,
453 .prepare
= &r100_pm_prepare
,
454 .finish
= &r100_pm_finish
,
455 .init_profile
= &r100_pm_init_profile
,
456 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
457 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
458 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
459 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
460 .set_memory_clock
= NULL
,
461 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
462 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
463 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
466 .pre_page_flip
= &r100_pre_page_flip
,
467 .page_flip
= &r100_page_flip
,
468 .post_page_flip
= &r100_post_page_flip
,
472 static struct radeon_asic r420_asic
= {
475 .suspend
= &r420_suspend
,
476 .resume
= &r420_resume
,
477 .vga_set_state
= &r100_vga_set_state
,
478 .asic_reset
= &r300_asic_reset
,
479 .ioctl_wait_idle
= NULL
,
480 .gui_idle
= &r100_gui_idle
,
481 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
483 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
484 .set_page
= &rv370_pcie_gart_set_page
,
487 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
490 .set
= &r100_irq_set
,
491 .process
= &r100_irq_process
,
494 .bandwidth_update
= &r100_bandwidth_update
,
495 .get_vblank_counter
= &r100_get_vblank_counter
,
496 .wait_for_vblank
= &r100_wait_for_vblank
,
497 .set_backlight_level
= &atombios_set_backlight_level
,
498 .get_backlight_level
= &atombios_get_backlight_level
,
501 .blit
= &r100_copy_blit
,
502 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
503 .dma
= &r200_copy_dma
,
504 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
505 .copy
= &r100_copy_blit
,
506 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
509 .set_reg
= r100_set_surface_reg
,
510 .clear_reg
= r100_clear_surface_reg
,
513 .init
= &r100_hpd_init
,
514 .fini
= &r100_hpd_fini
,
515 .sense
= &r100_hpd_sense
,
516 .set_polarity
= &r100_hpd_set_polarity
,
519 .misc
= &r100_pm_misc
,
520 .prepare
= &r100_pm_prepare
,
521 .finish
= &r100_pm_finish
,
522 .init_profile
= &r420_pm_init_profile
,
523 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
524 .get_engine_clock
= &radeon_atom_get_engine_clock
,
525 .set_engine_clock
= &radeon_atom_set_engine_clock
,
526 .get_memory_clock
= &radeon_atom_get_memory_clock
,
527 .set_memory_clock
= &radeon_atom_set_memory_clock
,
528 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
529 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
530 .set_clock_gating
= &radeon_atom_set_clock_gating
,
533 .pre_page_flip
= &r100_pre_page_flip
,
534 .page_flip
= &r100_page_flip
,
535 .post_page_flip
= &r100_post_page_flip
,
539 static struct radeon_asic rs400_asic
= {
542 .suspend
= &rs400_suspend
,
543 .resume
= &rs400_resume
,
544 .vga_set_state
= &r100_vga_set_state
,
545 .asic_reset
= &r300_asic_reset
,
546 .ioctl_wait_idle
= NULL
,
547 .gui_idle
= &r100_gui_idle
,
548 .mc_wait_for_idle
= &rs400_mc_wait_for_idle
,
550 .tlb_flush
= &rs400_gart_tlb_flush
,
551 .set_page
= &rs400_gart_set_page
,
554 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
557 .set
= &r100_irq_set
,
558 .process
= &r100_irq_process
,
561 .bandwidth_update
= &r100_bandwidth_update
,
562 .get_vblank_counter
= &r100_get_vblank_counter
,
563 .wait_for_vblank
= &r100_wait_for_vblank
,
564 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
565 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
568 .blit
= &r100_copy_blit
,
569 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
570 .dma
= &r200_copy_dma
,
571 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
572 .copy
= &r100_copy_blit
,
573 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
576 .set_reg
= r100_set_surface_reg
,
577 .clear_reg
= r100_clear_surface_reg
,
580 .init
= &r100_hpd_init
,
581 .fini
= &r100_hpd_fini
,
582 .sense
= &r100_hpd_sense
,
583 .set_polarity
= &r100_hpd_set_polarity
,
586 .misc
= &r100_pm_misc
,
587 .prepare
= &r100_pm_prepare
,
588 .finish
= &r100_pm_finish
,
589 .init_profile
= &r100_pm_init_profile
,
590 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
591 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
592 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
593 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
594 .set_memory_clock
= NULL
,
595 .get_pcie_lanes
= NULL
,
596 .set_pcie_lanes
= NULL
,
597 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
600 .pre_page_flip
= &r100_pre_page_flip
,
601 .page_flip
= &r100_page_flip
,
602 .post_page_flip
= &r100_post_page_flip
,
606 static struct radeon_asic rs600_asic
= {
609 .suspend
= &rs600_suspend
,
610 .resume
= &rs600_resume
,
611 .vga_set_state
= &r100_vga_set_state
,
612 .asic_reset
= &rs600_asic_reset
,
613 .ioctl_wait_idle
= NULL
,
614 .gui_idle
= &r100_gui_idle
,
615 .mc_wait_for_idle
= &rs600_mc_wait_for_idle
,
617 .tlb_flush
= &rs600_gart_tlb_flush
,
618 .set_page
= &rs600_gart_set_page
,
621 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
624 .set
= &rs600_irq_set
,
625 .process
= &rs600_irq_process
,
628 .bandwidth_update
= &rs600_bandwidth_update
,
629 .get_vblank_counter
= &rs600_get_vblank_counter
,
630 .wait_for_vblank
= &avivo_wait_for_vblank
,
631 .set_backlight_level
= &atombios_set_backlight_level
,
632 .get_backlight_level
= &atombios_get_backlight_level
,
633 .hdmi_enable
= &r600_hdmi_enable
,
634 .hdmi_setmode
= &r600_hdmi_setmode
,
637 .blit
= &r100_copy_blit
,
638 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
639 .dma
= &r200_copy_dma
,
640 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
641 .copy
= &r100_copy_blit
,
642 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
645 .set_reg
= r100_set_surface_reg
,
646 .clear_reg
= r100_clear_surface_reg
,
649 .init
= &rs600_hpd_init
,
650 .fini
= &rs600_hpd_fini
,
651 .sense
= &rs600_hpd_sense
,
652 .set_polarity
= &rs600_hpd_set_polarity
,
655 .misc
= &rs600_pm_misc
,
656 .prepare
= &rs600_pm_prepare
,
657 .finish
= &rs600_pm_finish
,
658 .init_profile
= &r420_pm_init_profile
,
659 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
660 .get_engine_clock
= &radeon_atom_get_engine_clock
,
661 .set_engine_clock
= &radeon_atom_set_engine_clock
,
662 .get_memory_clock
= &radeon_atom_get_memory_clock
,
663 .set_memory_clock
= &radeon_atom_set_memory_clock
,
664 .get_pcie_lanes
= NULL
,
665 .set_pcie_lanes
= NULL
,
666 .set_clock_gating
= &radeon_atom_set_clock_gating
,
669 .pre_page_flip
= &rs600_pre_page_flip
,
670 .page_flip
= &rs600_page_flip
,
671 .post_page_flip
= &rs600_post_page_flip
,
675 static struct radeon_asic rs690_asic
= {
678 .suspend
= &rs690_suspend
,
679 .resume
= &rs690_resume
,
680 .vga_set_state
= &r100_vga_set_state
,
681 .asic_reset
= &rs600_asic_reset
,
682 .ioctl_wait_idle
= NULL
,
683 .gui_idle
= &r100_gui_idle
,
684 .mc_wait_for_idle
= &rs690_mc_wait_for_idle
,
686 .tlb_flush
= &rs400_gart_tlb_flush
,
687 .set_page
= &rs400_gart_set_page
,
690 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
693 .set
= &rs600_irq_set
,
694 .process
= &rs600_irq_process
,
697 .get_vblank_counter
= &rs600_get_vblank_counter
,
698 .bandwidth_update
= &rs690_bandwidth_update
,
699 .wait_for_vblank
= &avivo_wait_for_vblank
,
700 .set_backlight_level
= &atombios_set_backlight_level
,
701 .get_backlight_level
= &atombios_get_backlight_level
,
702 .hdmi_enable
= &r600_hdmi_enable
,
703 .hdmi_setmode
= &r600_hdmi_setmode
,
706 .blit
= &r100_copy_blit
,
707 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
708 .dma
= &r200_copy_dma
,
709 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
710 .copy
= &r200_copy_dma
,
711 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
714 .set_reg
= r100_set_surface_reg
,
715 .clear_reg
= r100_clear_surface_reg
,
718 .init
= &rs600_hpd_init
,
719 .fini
= &rs600_hpd_fini
,
720 .sense
= &rs600_hpd_sense
,
721 .set_polarity
= &rs600_hpd_set_polarity
,
724 .misc
= &rs600_pm_misc
,
725 .prepare
= &rs600_pm_prepare
,
726 .finish
= &rs600_pm_finish
,
727 .init_profile
= &r420_pm_init_profile
,
728 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
729 .get_engine_clock
= &radeon_atom_get_engine_clock
,
730 .set_engine_clock
= &radeon_atom_set_engine_clock
,
731 .get_memory_clock
= &radeon_atom_get_memory_clock
,
732 .set_memory_clock
= &radeon_atom_set_memory_clock
,
733 .get_pcie_lanes
= NULL
,
734 .set_pcie_lanes
= NULL
,
735 .set_clock_gating
= &radeon_atom_set_clock_gating
,
738 .pre_page_flip
= &rs600_pre_page_flip
,
739 .page_flip
= &rs600_page_flip
,
740 .post_page_flip
= &rs600_post_page_flip
,
744 static struct radeon_asic rv515_asic
= {
747 .suspend
= &rv515_suspend
,
748 .resume
= &rv515_resume
,
749 .vga_set_state
= &r100_vga_set_state
,
750 .asic_reset
= &rs600_asic_reset
,
751 .ioctl_wait_idle
= NULL
,
752 .gui_idle
= &r100_gui_idle
,
753 .mc_wait_for_idle
= &rv515_mc_wait_for_idle
,
755 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
756 .set_page
= &rv370_pcie_gart_set_page
,
759 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
762 .set
= &rs600_irq_set
,
763 .process
= &rs600_irq_process
,
766 .get_vblank_counter
= &rs600_get_vblank_counter
,
767 .bandwidth_update
= &rv515_bandwidth_update
,
768 .wait_for_vblank
= &avivo_wait_for_vblank
,
769 .set_backlight_level
= &atombios_set_backlight_level
,
770 .get_backlight_level
= &atombios_get_backlight_level
,
773 .blit
= &r100_copy_blit
,
774 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
775 .dma
= &r200_copy_dma
,
776 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
777 .copy
= &r100_copy_blit
,
778 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
781 .set_reg
= r100_set_surface_reg
,
782 .clear_reg
= r100_clear_surface_reg
,
785 .init
= &rs600_hpd_init
,
786 .fini
= &rs600_hpd_fini
,
787 .sense
= &rs600_hpd_sense
,
788 .set_polarity
= &rs600_hpd_set_polarity
,
791 .misc
= &rs600_pm_misc
,
792 .prepare
= &rs600_pm_prepare
,
793 .finish
= &rs600_pm_finish
,
794 .init_profile
= &r420_pm_init_profile
,
795 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
796 .get_engine_clock
= &radeon_atom_get_engine_clock
,
797 .set_engine_clock
= &radeon_atom_set_engine_clock
,
798 .get_memory_clock
= &radeon_atom_get_memory_clock
,
799 .set_memory_clock
= &radeon_atom_set_memory_clock
,
800 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
801 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
802 .set_clock_gating
= &radeon_atom_set_clock_gating
,
805 .pre_page_flip
= &rs600_pre_page_flip
,
806 .page_flip
= &rs600_page_flip
,
807 .post_page_flip
= &rs600_post_page_flip
,
811 static struct radeon_asic r520_asic
= {
814 .suspend
= &rv515_suspend
,
815 .resume
= &r520_resume
,
816 .vga_set_state
= &r100_vga_set_state
,
817 .asic_reset
= &rs600_asic_reset
,
818 .ioctl_wait_idle
= NULL
,
819 .gui_idle
= &r100_gui_idle
,
820 .mc_wait_for_idle
= &r520_mc_wait_for_idle
,
822 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
823 .set_page
= &rv370_pcie_gart_set_page
,
826 [RADEON_RING_TYPE_GFX_INDEX
] = &r300_gfx_ring
829 .set
= &rs600_irq_set
,
830 .process
= &rs600_irq_process
,
833 .bandwidth_update
= &rv515_bandwidth_update
,
834 .get_vblank_counter
= &rs600_get_vblank_counter
,
835 .wait_for_vblank
= &avivo_wait_for_vblank
,
836 .set_backlight_level
= &atombios_set_backlight_level
,
837 .get_backlight_level
= &atombios_get_backlight_level
,
840 .blit
= &r100_copy_blit
,
841 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
842 .dma
= &r200_copy_dma
,
843 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
844 .copy
= &r100_copy_blit
,
845 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
848 .set_reg
= r100_set_surface_reg
,
849 .clear_reg
= r100_clear_surface_reg
,
852 .init
= &rs600_hpd_init
,
853 .fini
= &rs600_hpd_fini
,
854 .sense
= &rs600_hpd_sense
,
855 .set_polarity
= &rs600_hpd_set_polarity
,
858 .misc
= &rs600_pm_misc
,
859 .prepare
= &rs600_pm_prepare
,
860 .finish
= &rs600_pm_finish
,
861 .init_profile
= &r420_pm_init_profile
,
862 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
863 .get_engine_clock
= &radeon_atom_get_engine_clock
,
864 .set_engine_clock
= &radeon_atom_set_engine_clock
,
865 .get_memory_clock
= &radeon_atom_get_memory_clock
,
866 .set_memory_clock
= &radeon_atom_set_memory_clock
,
867 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
868 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
869 .set_clock_gating
= &radeon_atom_set_clock_gating
,
872 .pre_page_flip
= &rs600_pre_page_flip
,
873 .page_flip
= &rs600_page_flip
,
874 .post_page_flip
= &rs600_post_page_flip
,
878 static struct radeon_asic_ring r600_gfx_ring
= {
879 .ib_execute
= &r600_ring_ib_execute
,
880 .emit_fence
= &r600_fence_ring_emit
,
881 .emit_semaphore
= &r600_semaphore_ring_emit
,
882 .cs_parse
= &r600_cs_parse
,
883 .ring_test
= &r600_ring_test
,
884 .ib_test
= &r600_ib_test
,
885 .is_lockup
= &r600_gfx_is_lockup
,
886 .get_rptr
= &radeon_ring_generic_get_rptr
,
887 .get_wptr
= &radeon_ring_generic_get_wptr
,
888 .set_wptr
= &radeon_ring_generic_set_wptr
,
891 static struct radeon_asic_ring r600_dma_ring
= {
892 .ib_execute
= &r600_dma_ring_ib_execute
,
893 .emit_fence
= &r600_dma_fence_ring_emit
,
894 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
895 .cs_parse
= &r600_dma_cs_parse
,
896 .ring_test
= &r600_dma_ring_test
,
897 .ib_test
= &r600_dma_ib_test
,
898 .is_lockup
= &r600_dma_is_lockup
,
899 .get_rptr
= &r600_dma_get_rptr
,
900 .get_wptr
= &r600_dma_get_wptr
,
901 .set_wptr
= &r600_dma_set_wptr
,
904 static struct radeon_asic r600_asic
= {
907 .suspend
= &r600_suspend
,
908 .resume
= &r600_resume
,
909 .vga_set_state
= &r600_vga_set_state
,
910 .asic_reset
= &r600_asic_reset
,
911 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
912 .gui_idle
= &r600_gui_idle
,
913 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
914 .get_xclk
= &r600_get_xclk
,
915 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
917 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
918 .set_page
= &rs600_gart_set_page
,
921 [RADEON_RING_TYPE_GFX_INDEX
] = &r600_gfx_ring
,
922 [R600_RING_TYPE_DMA_INDEX
] = &r600_dma_ring
,
925 .set
= &r600_irq_set
,
926 .process
= &r600_irq_process
,
929 .bandwidth_update
= &rv515_bandwidth_update
,
930 .get_vblank_counter
= &rs600_get_vblank_counter
,
931 .wait_for_vblank
= &avivo_wait_for_vblank
,
932 .set_backlight_level
= &atombios_set_backlight_level
,
933 .get_backlight_level
= &atombios_get_backlight_level
,
934 .hdmi_enable
= &r600_hdmi_enable
,
935 .hdmi_setmode
= &r600_hdmi_setmode
,
938 .blit
= &r600_copy_cpdma
,
939 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
940 .dma
= &r600_copy_dma
,
941 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
942 .copy
= &r600_copy_cpdma
,
943 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
946 .set_reg
= r600_set_surface_reg
,
947 .clear_reg
= r600_clear_surface_reg
,
950 .init
= &r600_hpd_init
,
951 .fini
= &r600_hpd_fini
,
952 .sense
= &r600_hpd_sense
,
953 .set_polarity
= &r600_hpd_set_polarity
,
956 .misc
= &r600_pm_misc
,
957 .prepare
= &rs600_pm_prepare
,
958 .finish
= &rs600_pm_finish
,
959 .init_profile
= &r600_pm_init_profile
,
960 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
961 .get_engine_clock
= &radeon_atom_get_engine_clock
,
962 .set_engine_clock
= &radeon_atom_set_engine_clock
,
963 .get_memory_clock
= &radeon_atom_get_memory_clock
,
964 .set_memory_clock
= &radeon_atom_set_memory_clock
,
965 .get_pcie_lanes
= &r600_get_pcie_lanes
,
966 .set_pcie_lanes
= &r600_set_pcie_lanes
,
967 .set_clock_gating
= NULL
,
968 .get_temperature
= &rv6xx_get_temp
,
971 .pre_page_flip
= &rs600_pre_page_flip
,
972 .page_flip
= &rs600_page_flip
,
973 .post_page_flip
= &rs600_post_page_flip
,
977 static struct radeon_asic rv6xx_asic
= {
980 .suspend
= &r600_suspend
,
981 .resume
= &r600_resume
,
982 .vga_set_state
= &r600_vga_set_state
,
983 .asic_reset
= &r600_asic_reset
,
984 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
985 .gui_idle
= &r600_gui_idle
,
986 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
987 .get_xclk
= &r600_get_xclk
,
988 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
990 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
991 .set_page
= &rs600_gart_set_page
,
994 [RADEON_RING_TYPE_GFX_INDEX
] = &r600_gfx_ring
,
995 [R600_RING_TYPE_DMA_INDEX
] = &r600_dma_ring
,
998 .set
= &r600_irq_set
,
999 .process
= &r600_irq_process
,
1002 .bandwidth_update
= &rv515_bandwidth_update
,
1003 .get_vblank_counter
= &rs600_get_vblank_counter
,
1004 .wait_for_vblank
= &avivo_wait_for_vblank
,
1005 .set_backlight_level
= &atombios_set_backlight_level
,
1006 .get_backlight_level
= &atombios_get_backlight_level
,
1009 .blit
= &r600_copy_cpdma
,
1010 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1011 .dma
= &r600_copy_dma
,
1012 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1013 .copy
= &r600_copy_cpdma
,
1014 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1017 .set_reg
= r600_set_surface_reg
,
1018 .clear_reg
= r600_clear_surface_reg
,
1021 .init
= &r600_hpd_init
,
1022 .fini
= &r600_hpd_fini
,
1023 .sense
= &r600_hpd_sense
,
1024 .set_polarity
= &r600_hpd_set_polarity
,
1027 .misc
= &r600_pm_misc
,
1028 .prepare
= &rs600_pm_prepare
,
1029 .finish
= &rs600_pm_finish
,
1030 .init_profile
= &r600_pm_init_profile
,
1031 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1032 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1033 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1034 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1035 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1036 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1037 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1038 .set_clock_gating
= NULL
,
1039 .get_temperature
= &rv6xx_get_temp
,
1042 .init
= &rv6xx_dpm_init
,
1043 .setup_asic
= &rv6xx_setup_asic
,
1044 .enable
= &rv6xx_dpm_enable
,
1045 .disable
= &rv6xx_dpm_disable
,
1046 .pre_set_power_state
= &r600_dpm_pre_set_power_state
,
1047 .set_power_state
= &rv6xx_dpm_set_power_state
,
1048 .post_set_power_state
= &r600_dpm_post_set_power_state
,
1049 .display_configuration_changed
= &rv6xx_dpm_display_configuration_changed
,
1050 .fini
= &rv6xx_dpm_fini
,
1051 .get_sclk
= &rv6xx_dpm_get_sclk
,
1052 .get_mclk
= &rv6xx_dpm_get_mclk
,
1053 .print_power_state
= &rv6xx_dpm_print_power_state
,
1054 .debugfs_print_current_performance_level
= &rv6xx_dpm_debugfs_print_current_performance_level
,
1055 .force_performance_level
= &rv6xx_dpm_force_performance_level
,
1058 .pre_page_flip
= &rs600_pre_page_flip
,
1059 .page_flip
= &rs600_page_flip
,
1060 .post_page_flip
= &rs600_post_page_flip
,
1064 static struct radeon_asic rs780_asic
= {
1067 .suspend
= &r600_suspend
,
1068 .resume
= &r600_resume
,
1069 .vga_set_state
= &r600_vga_set_state
,
1070 .asic_reset
= &r600_asic_reset
,
1071 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1072 .gui_idle
= &r600_gui_idle
,
1073 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1074 .get_xclk
= &r600_get_xclk
,
1075 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1077 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1078 .set_page
= &rs600_gart_set_page
,
1081 [RADEON_RING_TYPE_GFX_INDEX
] = &r600_gfx_ring
,
1082 [R600_RING_TYPE_DMA_INDEX
] = &r600_dma_ring
,
1085 .set
= &r600_irq_set
,
1086 .process
= &r600_irq_process
,
1089 .bandwidth_update
= &rs690_bandwidth_update
,
1090 .get_vblank_counter
= &rs600_get_vblank_counter
,
1091 .wait_for_vblank
= &avivo_wait_for_vblank
,
1092 .set_backlight_level
= &atombios_set_backlight_level
,
1093 .get_backlight_level
= &atombios_get_backlight_level
,
1094 .hdmi_enable
= &r600_hdmi_enable
,
1095 .hdmi_setmode
= &r600_hdmi_setmode
,
1098 .blit
= &r600_copy_cpdma
,
1099 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1100 .dma
= &r600_copy_dma
,
1101 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1102 .copy
= &r600_copy_cpdma
,
1103 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1106 .set_reg
= r600_set_surface_reg
,
1107 .clear_reg
= r600_clear_surface_reg
,
1110 .init
= &r600_hpd_init
,
1111 .fini
= &r600_hpd_fini
,
1112 .sense
= &r600_hpd_sense
,
1113 .set_polarity
= &r600_hpd_set_polarity
,
1116 .misc
= &r600_pm_misc
,
1117 .prepare
= &rs600_pm_prepare
,
1118 .finish
= &rs600_pm_finish
,
1119 .init_profile
= &rs780_pm_init_profile
,
1120 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1121 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1122 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1123 .get_memory_clock
= NULL
,
1124 .set_memory_clock
= NULL
,
1125 .get_pcie_lanes
= NULL
,
1126 .set_pcie_lanes
= NULL
,
1127 .set_clock_gating
= NULL
,
1128 .get_temperature
= &rv6xx_get_temp
,
1131 .init
= &rs780_dpm_init
,
1132 .setup_asic
= &rs780_dpm_setup_asic
,
1133 .enable
= &rs780_dpm_enable
,
1134 .disable
= &rs780_dpm_disable
,
1135 .pre_set_power_state
= &r600_dpm_pre_set_power_state
,
1136 .set_power_state
= &rs780_dpm_set_power_state
,
1137 .post_set_power_state
= &r600_dpm_post_set_power_state
,
1138 .display_configuration_changed
= &rs780_dpm_display_configuration_changed
,
1139 .fini
= &rs780_dpm_fini
,
1140 .get_sclk
= &rs780_dpm_get_sclk
,
1141 .get_mclk
= &rs780_dpm_get_mclk
,
1142 .print_power_state
= &rs780_dpm_print_power_state
,
1143 .debugfs_print_current_performance_level
= &rs780_dpm_debugfs_print_current_performance_level
,
1146 .pre_page_flip
= &rs600_pre_page_flip
,
1147 .page_flip
= &rs600_page_flip
,
1148 .post_page_flip
= &rs600_post_page_flip
,
1152 static struct radeon_asic_ring rv770_uvd_ring
= {
1153 .ib_execute
= &uvd_v1_0_ib_execute
,
1154 .emit_fence
= &uvd_v2_2_fence_emit
,
1155 .emit_semaphore
= &uvd_v1_0_semaphore_emit
,
1156 .cs_parse
= &radeon_uvd_cs_parse
,
1157 .ring_test
= &uvd_v1_0_ring_test
,
1158 .ib_test
= &uvd_v1_0_ib_test
,
1159 .is_lockup
= &radeon_ring_test_lockup
,
1160 .get_rptr
= &uvd_v1_0_get_rptr
,
1161 .get_wptr
= &uvd_v1_0_get_wptr
,
1162 .set_wptr
= &uvd_v1_0_set_wptr
,
1165 static struct radeon_asic rv770_asic
= {
1166 .init
= &rv770_init
,
1167 .fini
= &rv770_fini
,
1168 .suspend
= &rv770_suspend
,
1169 .resume
= &rv770_resume
,
1170 .asic_reset
= &r600_asic_reset
,
1171 .vga_set_state
= &r600_vga_set_state
,
1172 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1173 .gui_idle
= &r600_gui_idle
,
1174 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1175 .get_xclk
= &rv770_get_xclk
,
1176 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1178 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1179 .set_page
= &rs600_gart_set_page
,
1182 [RADEON_RING_TYPE_GFX_INDEX
] = &r600_gfx_ring
,
1183 [R600_RING_TYPE_DMA_INDEX
] = &r600_dma_ring
,
1184 [R600_RING_TYPE_UVD_INDEX
] = &rv770_uvd_ring
,
1187 .set
= &r600_irq_set
,
1188 .process
= &r600_irq_process
,
1191 .bandwidth_update
= &rv515_bandwidth_update
,
1192 .get_vblank_counter
= &rs600_get_vblank_counter
,
1193 .wait_for_vblank
= &avivo_wait_for_vblank
,
1194 .set_backlight_level
= &atombios_set_backlight_level
,
1195 .get_backlight_level
= &atombios_get_backlight_level
,
1196 .hdmi_enable
= &r600_hdmi_enable
,
1197 .hdmi_setmode
= &r600_hdmi_setmode
,
1200 .blit
= &r600_copy_cpdma
,
1201 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1202 .dma
= &rv770_copy_dma
,
1203 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1204 .copy
= &rv770_copy_dma
,
1205 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1208 .set_reg
= r600_set_surface_reg
,
1209 .clear_reg
= r600_clear_surface_reg
,
1212 .init
= &r600_hpd_init
,
1213 .fini
= &r600_hpd_fini
,
1214 .sense
= &r600_hpd_sense
,
1215 .set_polarity
= &r600_hpd_set_polarity
,
1218 .misc
= &rv770_pm_misc
,
1219 .prepare
= &rs600_pm_prepare
,
1220 .finish
= &rs600_pm_finish
,
1221 .init_profile
= &r600_pm_init_profile
,
1222 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1223 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1224 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1225 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1226 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1227 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1228 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1229 .set_clock_gating
= &radeon_atom_set_clock_gating
,
1230 .set_uvd_clocks
= &rv770_set_uvd_clocks
,
1231 .get_temperature
= &rv770_get_temp
,
1234 .init
= &rv770_dpm_init
,
1235 .setup_asic
= &rv770_dpm_setup_asic
,
1236 .enable
= &rv770_dpm_enable
,
1237 .disable
= &rv770_dpm_disable
,
1238 .pre_set_power_state
= &r600_dpm_pre_set_power_state
,
1239 .set_power_state
= &rv770_dpm_set_power_state
,
1240 .post_set_power_state
= &r600_dpm_post_set_power_state
,
1241 .display_configuration_changed
= &rv770_dpm_display_configuration_changed
,
1242 .fini
= &rv770_dpm_fini
,
1243 .get_sclk
= &rv770_dpm_get_sclk
,
1244 .get_mclk
= &rv770_dpm_get_mclk
,
1245 .print_power_state
= &rv770_dpm_print_power_state
,
1246 .debugfs_print_current_performance_level
= &rv770_dpm_debugfs_print_current_performance_level
,
1247 .force_performance_level
= &rv770_dpm_force_performance_level
,
1248 .vblank_too_short
= &rv770_dpm_vblank_too_short
,
1251 .pre_page_flip
= &rs600_pre_page_flip
,
1252 .page_flip
= &rv770_page_flip
,
1253 .post_page_flip
= &rs600_post_page_flip
,
1257 static struct radeon_asic_ring evergreen_gfx_ring
= {
1258 .ib_execute
= &evergreen_ring_ib_execute
,
1259 .emit_fence
= &r600_fence_ring_emit
,
1260 .emit_semaphore
= &r600_semaphore_ring_emit
,
1261 .cs_parse
= &evergreen_cs_parse
,
1262 .ring_test
= &r600_ring_test
,
1263 .ib_test
= &r600_ib_test
,
1264 .is_lockup
= &evergreen_gfx_is_lockup
,
1265 .get_rptr
= &radeon_ring_generic_get_rptr
,
1266 .get_wptr
= &radeon_ring_generic_get_wptr
,
1267 .set_wptr
= &radeon_ring_generic_set_wptr
,
1270 static struct radeon_asic_ring evergreen_dma_ring
= {
1271 .ib_execute
= &evergreen_dma_ring_ib_execute
,
1272 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1273 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1274 .cs_parse
= &evergreen_dma_cs_parse
,
1275 .ring_test
= &r600_dma_ring_test
,
1276 .ib_test
= &r600_dma_ib_test
,
1277 .is_lockup
= &evergreen_dma_is_lockup
,
1278 .get_rptr
= &r600_dma_get_rptr
,
1279 .get_wptr
= &r600_dma_get_wptr
,
1280 .set_wptr
= &r600_dma_set_wptr
,
1283 static struct radeon_asic evergreen_asic
= {
1284 .init
= &evergreen_init
,
1285 .fini
= &evergreen_fini
,
1286 .suspend
= &evergreen_suspend
,
1287 .resume
= &evergreen_resume
,
1288 .asic_reset
= &evergreen_asic_reset
,
1289 .vga_set_state
= &r600_vga_set_state
,
1290 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1291 .gui_idle
= &r600_gui_idle
,
1292 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1293 .get_xclk
= &rv770_get_xclk
,
1294 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1296 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1297 .set_page
= &rs600_gart_set_page
,
1300 [RADEON_RING_TYPE_GFX_INDEX
] = &evergreen_gfx_ring
,
1301 [R600_RING_TYPE_DMA_INDEX
] = &evergreen_dma_ring
,
1302 [R600_RING_TYPE_UVD_INDEX
] = &rv770_uvd_ring
,
1305 .set
= &evergreen_irq_set
,
1306 .process
= &evergreen_irq_process
,
1309 .bandwidth_update
= &evergreen_bandwidth_update
,
1310 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1311 .wait_for_vblank
= &dce4_wait_for_vblank
,
1312 .set_backlight_level
= &atombios_set_backlight_level
,
1313 .get_backlight_level
= &atombios_get_backlight_level
,
1314 .hdmi_enable
= &evergreen_hdmi_enable
,
1315 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1318 .blit
= &r600_copy_cpdma
,
1319 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1320 .dma
= &evergreen_copy_dma
,
1321 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1322 .copy
= &evergreen_copy_dma
,
1323 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1326 .set_reg
= r600_set_surface_reg
,
1327 .clear_reg
= r600_clear_surface_reg
,
1330 .init
= &evergreen_hpd_init
,
1331 .fini
= &evergreen_hpd_fini
,
1332 .sense
= &evergreen_hpd_sense
,
1333 .set_polarity
= &evergreen_hpd_set_polarity
,
1336 .misc
= &evergreen_pm_misc
,
1337 .prepare
= &evergreen_pm_prepare
,
1338 .finish
= &evergreen_pm_finish
,
1339 .init_profile
= &r600_pm_init_profile
,
1340 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1341 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1342 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1343 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1344 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1345 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1346 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1347 .set_clock_gating
= NULL
,
1348 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1349 .get_temperature
= &evergreen_get_temp
,
1352 .init
= &cypress_dpm_init
,
1353 .setup_asic
= &cypress_dpm_setup_asic
,
1354 .enable
= &cypress_dpm_enable
,
1355 .disable
= &cypress_dpm_disable
,
1356 .pre_set_power_state
= &r600_dpm_pre_set_power_state
,
1357 .set_power_state
= &cypress_dpm_set_power_state
,
1358 .post_set_power_state
= &r600_dpm_post_set_power_state
,
1359 .display_configuration_changed
= &cypress_dpm_display_configuration_changed
,
1360 .fini
= &cypress_dpm_fini
,
1361 .get_sclk
= &rv770_dpm_get_sclk
,
1362 .get_mclk
= &rv770_dpm_get_mclk
,
1363 .print_power_state
= &rv770_dpm_print_power_state
,
1364 .debugfs_print_current_performance_level
= &rv770_dpm_debugfs_print_current_performance_level
,
1365 .force_performance_level
= &rv770_dpm_force_performance_level
,
1366 .vblank_too_short
= &cypress_dpm_vblank_too_short
,
1369 .pre_page_flip
= &evergreen_pre_page_flip
,
1370 .page_flip
= &evergreen_page_flip
,
1371 .post_page_flip
= &evergreen_post_page_flip
,
1375 static struct radeon_asic sumo_asic
= {
1376 .init
= &evergreen_init
,
1377 .fini
= &evergreen_fini
,
1378 .suspend
= &evergreen_suspend
,
1379 .resume
= &evergreen_resume
,
1380 .asic_reset
= &evergreen_asic_reset
,
1381 .vga_set_state
= &r600_vga_set_state
,
1382 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1383 .gui_idle
= &r600_gui_idle
,
1384 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1385 .get_xclk
= &r600_get_xclk
,
1386 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1388 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1389 .set_page
= &rs600_gart_set_page
,
1392 [RADEON_RING_TYPE_GFX_INDEX
] = &evergreen_gfx_ring
,
1393 [R600_RING_TYPE_DMA_INDEX
] = &evergreen_dma_ring
,
1394 [R600_RING_TYPE_UVD_INDEX
] = &rv770_uvd_ring
,
1397 .set
= &evergreen_irq_set
,
1398 .process
= &evergreen_irq_process
,
1401 .bandwidth_update
= &evergreen_bandwidth_update
,
1402 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1403 .wait_for_vblank
= &dce4_wait_for_vblank
,
1404 .set_backlight_level
= &atombios_set_backlight_level
,
1405 .get_backlight_level
= &atombios_get_backlight_level
,
1406 .hdmi_enable
= &evergreen_hdmi_enable
,
1407 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1410 .blit
= &r600_copy_cpdma
,
1411 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1412 .dma
= &evergreen_copy_dma
,
1413 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1414 .copy
= &evergreen_copy_dma
,
1415 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1418 .set_reg
= r600_set_surface_reg
,
1419 .clear_reg
= r600_clear_surface_reg
,
1422 .init
= &evergreen_hpd_init
,
1423 .fini
= &evergreen_hpd_fini
,
1424 .sense
= &evergreen_hpd_sense
,
1425 .set_polarity
= &evergreen_hpd_set_polarity
,
1428 .misc
= &evergreen_pm_misc
,
1429 .prepare
= &evergreen_pm_prepare
,
1430 .finish
= &evergreen_pm_finish
,
1431 .init_profile
= &sumo_pm_init_profile
,
1432 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1433 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1434 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1435 .get_memory_clock
= NULL
,
1436 .set_memory_clock
= NULL
,
1437 .get_pcie_lanes
= NULL
,
1438 .set_pcie_lanes
= NULL
,
1439 .set_clock_gating
= NULL
,
1440 .set_uvd_clocks
= &sumo_set_uvd_clocks
,
1441 .get_temperature
= &sumo_get_temp
,
1444 .init
= &sumo_dpm_init
,
1445 .setup_asic
= &sumo_dpm_setup_asic
,
1446 .enable
= &sumo_dpm_enable
,
1447 .disable
= &sumo_dpm_disable
,
1448 .pre_set_power_state
= &sumo_dpm_pre_set_power_state
,
1449 .set_power_state
= &sumo_dpm_set_power_state
,
1450 .post_set_power_state
= &sumo_dpm_post_set_power_state
,
1451 .display_configuration_changed
= &sumo_dpm_display_configuration_changed
,
1452 .fini
= &sumo_dpm_fini
,
1453 .get_sclk
= &sumo_dpm_get_sclk
,
1454 .get_mclk
= &sumo_dpm_get_mclk
,
1455 .print_power_state
= &sumo_dpm_print_power_state
,
1456 .debugfs_print_current_performance_level
= &sumo_dpm_debugfs_print_current_performance_level
,
1457 .force_performance_level
= &sumo_dpm_force_performance_level
,
1460 .pre_page_flip
= &evergreen_pre_page_flip
,
1461 .page_flip
= &evergreen_page_flip
,
1462 .post_page_flip
= &evergreen_post_page_flip
,
1466 static struct radeon_asic btc_asic
= {
1467 .init
= &evergreen_init
,
1468 .fini
= &evergreen_fini
,
1469 .suspend
= &evergreen_suspend
,
1470 .resume
= &evergreen_resume
,
1471 .asic_reset
= &evergreen_asic_reset
,
1472 .vga_set_state
= &r600_vga_set_state
,
1473 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1474 .gui_idle
= &r600_gui_idle
,
1475 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1476 .get_xclk
= &rv770_get_xclk
,
1477 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1479 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1480 .set_page
= &rs600_gart_set_page
,
1483 [RADEON_RING_TYPE_GFX_INDEX
] = &evergreen_gfx_ring
,
1484 [R600_RING_TYPE_DMA_INDEX
] = &evergreen_dma_ring
,
1485 [R600_RING_TYPE_UVD_INDEX
] = &rv770_uvd_ring
,
1488 .set
= &evergreen_irq_set
,
1489 .process
= &evergreen_irq_process
,
1492 .bandwidth_update
= &evergreen_bandwidth_update
,
1493 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1494 .wait_for_vblank
= &dce4_wait_for_vblank
,
1495 .set_backlight_level
= &atombios_set_backlight_level
,
1496 .get_backlight_level
= &atombios_get_backlight_level
,
1497 .hdmi_enable
= &evergreen_hdmi_enable
,
1498 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1501 .blit
= &r600_copy_cpdma
,
1502 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1503 .dma
= &evergreen_copy_dma
,
1504 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1505 .copy
= &evergreen_copy_dma
,
1506 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1509 .set_reg
= r600_set_surface_reg
,
1510 .clear_reg
= r600_clear_surface_reg
,
1513 .init
= &evergreen_hpd_init
,
1514 .fini
= &evergreen_hpd_fini
,
1515 .sense
= &evergreen_hpd_sense
,
1516 .set_polarity
= &evergreen_hpd_set_polarity
,
1519 .misc
= &evergreen_pm_misc
,
1520 .prepare
= &evergreen_pm_prepare
,
1521 .finish
= &evergreen_pm_finish
,
1522 .init_profile
= &btc_pm_init_profile
,
1523 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1524 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1525 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1526 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1527 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1528 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1529 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1530 .set_clock_gating
= NULL
,
1531 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1532 .get_temperature
= &evergreen_get_temp
,
1535 .init
= &btc_dpm_init
,
1536 .setup_asic
= &btc_dpm_setup_asic
,
1537 .enable
= &btc_dpm_enable
,
1538 .disable
= &btc_dpm_disable
,
1539 .pre_set_power_state
= &btc_dpm_pre_set_power_state
,
1540 .set_power_state
= &btc_dpm_set_power_state
,
1541 .post_set_power_state
= &btc_dpm_post_set_power_state
,
1542 .display_configuration_changed
= &cypress_dpm_display_configuration_changed
,
1543 .fini
= &btc_dpm_fini
,
1544 .get_sclk
= &btc_dpm_get_sclk
,
1545 .get_mclk
= &btc_dpm_get_mclk
,
1546 .print_power_state
= &rv770_dpm_print_power_state
,
1547 .debugfs_print_current_performance_level
= &rv770_dpm_debugfs_print_current_performance_level
,
1548 .force_performance_level
= &rv770_dpm_force_performance_level
,
1549 .vblank_too_short
= &btc_dpm_vblank_too_short
,
1552 .pre_page_flip
= &evergreen_pre_page_flip
,
1553 .page_flip
= &evergreen_page_flip
,
1554 .post_page_flip
= &evergreen_post_page_flip
,
1558 static struct radeon_asic_ring cayman_gfx_ring
= {
1559 .ib_execute
= &cayman_ring_ib_execute
,
1560 .ib_parse
= &evergreen_ib_parse
,
1561 .emit_fence
= &cayman_fence_ring_emit
,
1562 .emit_semaphore
= &r600_semaphore_ring_emit
,
1563 .cs_parse
= &evergreen_cs_parse
,
1564 .ring_test
= &r600_ring_test
,
1565 .ib_test
= &r600_ib_test
,
1566 .is_lockup
= &cayman_gfx_is_lockup
,
1567 .vm_flush
= &cayman_vm_flush
,
1568 .get_rptr
= &radeon_ring_generic_get_rptr
,
1569 .get_wptr
= &radeon_ring_generic_get_wptr
,
1570 .set_wptr
= &radeon_ring_generic_set_wptr
,
1573 static struct radeon_asic_ring cayman_dma_ring
= {
1574 .ib_execute
= &cayman_dma_ring_ib_execute
,
1575 .ib_parse
= &evergreen_dma_ib_parse
,
1576 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1577 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1578 .cs_parse
= &evergreen_dma_cs_parse
,
1579 .ring_test
= &r600_dma_ring_test
,
1580 .ib_test
= &r600_dma_ib_test
,
1581 .is_lockup
= &cayman_dma_is_lockup
,
1582 .vm_flush
= &cayman_dma_vm_flush
,
1583 .get_rptr
= &r600_dma_get_rptr
,
1584 .get_wptr
= &r600_dma_get_wptr
,
1585 .set_wptr
= &r600_dma_set_wptr
1588 static struct radeon_asic_ring cayman_uvd_ring
= {
1589 .ib_execute
= &uvd_v1_0_ib_execute
,
1590 .emit_fence
= &uvd_v2_2_fence_emit
,
1591 .emit_semaphore
= &uvd_v3_1_semaphore_emit
,
1592 .cs_parse
= &radeon_uvd_cs_parse
,
1593 .ring_test
= &uvd_v1_0_ring_test
,
1594 .ib_test
= &uvd_v1_0_ib_test
,
1595 .is_lockup
= &radeon_ring_test_lockup
,
1596 .get_rptr
= &uvd_v1_0_get_rptr
,
1597 .get_wptr
= &uvd_v1_0_get_wptr
,
1598 .set_wptr
= &uvd_v1_0_set_wptr
,
1601 static struct radeon_asic cayman_asic
= {
1602 .init
= &cayman_init
,
1603 .fini
= &cayman_fini
,
1604 .suspend
= &cayman_suspend
,
1605 .resume
= &cayman_resume
,
1606 .asic_reset
= &cayman_asic_reset
,
1607 .vga_set_state
= &r600_vga_set_state
,
1608 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1609 .gui_idle
= &r600_gui_idle
,
1610 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1611 .get_xclk
= &rv770_get_xclk
,
1612 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1614 .tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1615 .set_page
= &rs600_gart_set_page
,
1618 .init
= &cayman_vm_init
,
1619 .fini
= &cayman_vm_fini
,
1620 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1621 .set_page
= &cayman_vm_set_page
,
1624 [RADEON_RING_TYPE_GFX_INDEX
] = &cayman_gfx_ring
,
1625 [CAYMAN_RING_TYPE_CP1_INDEX
] = &cayman_gfx_ring
,
1626 [CAYMAN_RING_TYPE_CP2_INDEX
] = &cayman_gfx_ring
,
1627 [R600_RING_TYPE_DMA_INDEX
] = &cayman_dma_ring
,
1628 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &cayman_dma_ring
,
1629 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
1632 .set
= &evergreen_irq_set
,
1633 .process
= &evergreen_irq_process
,
1636 .bandwidth_update
= &evergreen_bandwidth_update
,
1637 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1638 .wait_for_vblank
= &dce4_wait_for_vblank
,
1639 .set_backlight_level
= &atombios_set_backlight_level
,
1640 .get_backlight_level
= &atombios_get_backlight_level
,
1641 .hdmi_enable
= &evergreen_hdmi_enable
,
1642 .hdmi_setmode
= &evergreen_hdmi_setmode
,
1645 .blit
= &r600_copy_cpdma
,
1646 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1647 .dma
= &evergreen_copy_dma
,
1648 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1649 .copy
= &evergreen_copy_dma
,
1650 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1653 .set_reg
= r600_set_surface_reg
,
1654 .clear_reg
= r600_clear_surface_reg
,
1657 .init
= &evergreen_hpd_init
,
1658 .fini
= &evergreen_hpd_fini
,
1659 .sense
= &evergreen_hpd_sense
,
1660 .set_polarity
= &evergreen_hpd_set_polarity
,
1663 .misc
= &evergreen_pm_misc
,
1664 .prepare
= &evergreen_pm_prepare
,
1665 .finish
= &evergreen_pm_finish
,
1666 .init_profile
= &btc_pm_init_profile
,
1667 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1668 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1669 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1670 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1671 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1672 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1673 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1674 .set_clock_gating
= NULL
,
1675 .set_uvd_clocks
= &evergreen_set_uvd_clocks
,
1676 .get_temperature
= &evergreen_get_temp
,
1679 .init
= &ni_dpm_init
,
1680 .setup_asic
= &ni_dpm_setup_asic
,
1681 .enable
= &ni_dpm_enable
,
1682 .disable
= &ni_dpm_disable
,
1683 .pre_set_power_state
= &ni_dpm_pre_set_power_state
,
1684 .set_power_state
= &ni_dpm_set_power_state
,
1685 .post_set_power_state
= &ni_dpm_post_set_power_state
,
1686 .display_configuration_changed
= &cypress_dpm_display_configuration_changed
,
1687 .fini
= &ni_dpm_fini
,
1688 .get_sclk
= &ni_dpm_get_sclk
,
1689 .get_mclk
= &ni_dpm_get_mclk
,
1690 .print_power_state
= &ni_dpm_print_power_state
,
1691 .debugfs_print_current_performance_level
= &ni_dpm_debugfs_print_current_performance_level
,
1692 .force_performance_level
= &ni_dpm_force_performance_level
,
1693 .vblank_too_short
= &ni_dpm_vblank_too_short
,
1696 .pre_page_flip
= &evergreen_pre_page_flip
,
1697 .page_flip
= &evergreen_page_flip
,
1698 .post_page_flip
= &evergreen_post_page_flip
,
1702 static struct radeon_asic trinity_asic
= {
1703 .init
= &cayman_init
,
1704 .fini
= &cayman_fini
,
1705 .suspend
= &cayman_suspend
,
1706 .resume
= &cayman_resume
,
1707 .asic_reset
= &cayman_asic_reset
,
1708 .vga_set_state
= &r600_vga_set_state
,
1709 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1710 .gui_idle
= &r600_gui_idle
,
1711 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1712 .get_xclk
= &r600_get_xclk
,
1713 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1715 .tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1716 .set_page
= &rs600_gart_set_page
,
1719 .init
= &cayman_vm_init
,
1720 .fini
= &cayman_vm_fini
,
1721 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1722 .set_page
= &cayman_vm_set_page
,
1725 [RADEON_RING_TYPE_GFX_INDEX
] = &cayman_gfx_ring
,
1726 [CAYMAN_RING_TYPE_CP1_INDEX
] = &cayman_gfx_ring
,
1727 [CAYMAN_RING_TYPE_CP2_INDEX
] = &cayman_gfx_ring
,
1728 [R600_RING_TYPE_DMA_INDEX
] = &cayman_dma_ring
,
1729 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &cayman_dma_ring
,
1730 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
1733 .set
= &evergreen_irq_set
,
1734 .process
= &evergreen_irq_process
,
1737 .bandwidth_update
= &dce6_bandwidth_update
,
1738 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1739 .wait_for_vblank
= &dce4_wait_for_vblank
,
1740 .set_backlight_level
= &atombios_set_backlight_level
,
1741 .get_backlight_level
= &atombios_get_backlight_level
,
1744 .blit
= &r600_copy_cpdma
,
1745 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1746 .dma
= &evergreen_copy_dma
,
1747 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1748 .copy
= &evergreen_copy_dma
,
1749 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1752 .set_reg
= r600_set_surface_reg
,
1753 .clear_reg
= r600_clear_surface_reg
,
1756 .init
= &evergreen_hpd_init
,
1757 .fini
= &evergreen_hpd_fini
,
1758 .sense
= &evergreen_hpd_sense
,
1759 .set_polarity
= &evergreen_hpd_set_polarity
,
1762 .misc
= &evergreen_pm_misc
,
1763 .prepare
= &evergreen_pm_prepare
,
1764 .finish
= &evergreen_pm_finish
,
1765 .init_profile
= &sumo_pm_init_profile
,
1766 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1767 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1768 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1769 .get_memory_clock
= NULL
,
1770 .set_memory_clock
= NULL
,
1771 .get_pcie_lanes
= NULL
,
1772 .set_pcie_lanes
= NULL
,
1773 .set_clock_gating
= NULL
,
1774 .set_uvd_clocks
= &sumo_set_uvd_clocks
,
1775 .get_temperature
= &tn_get_temp
,
1778 .init
= &trinity_dpm_init
,
1779 .setup_asic
= &trinity_dpm_setup_asic
,
1780 .enable
= &trinity_dpm_enable
,
1781 .disable
= &trinity_dpm_disable
,
1782 .pre_set_power_state
= &trinity_dpm_pre_set_power_state
,
1783 .set_power_state
= &trinity_dpm_set_power_state
,
1784 .post_set_power_state
= &trinity_dpm_post_set_power_state
,
1785 .display_configuration_changed
= &trinity_dpm_display_configuration_changed
,
1786 .fini
= &trinity_dpm_fini
,
1787 .get_sclk
= &trinity_dpm_get_sclk
,
1788 .get_mclk
= &trinity_dpm_get_mclk
,
1789 .print_power_state
= &trinity_dpm_print_power_state
,
1790 .debugfs_print_current_performance_level
= &trinity_dpm_debugfs_print_current_performance_level
,
1791 .force_performance_level
= &trinity_dpm_force_performance_level
,
1794 .pre_page_flip
= &evergreen_pre_page_flip
,
1795 .page_flip
= &evergreen_page_flip
,
1796 .post_page_flip
= &evergreen_post_page_flip
,
1800 static struct radeon_asic_ring si_gfx_ring
= {
1801 .ib_execute
= &si_ring_ib_execute
,
1802 .ib_parse
= &si_ib_parse
,
1803 .emit_fence
= &si_fence_ring_emit
,
1804 .emit_semaphore
= &r600_semaphore_ring_emit
,
1806 .ring_test
= &r600_ring_test
,
1807 .ib_test
= &r600_ib_test
,
1808 .is_lockup
= &si_gfx_is_lockup
,
1809 .vm_flush
= &si_vm_flush
,
1810 .get_rptr
= &radeon_ring_generic_get_rptr
,
1811 .get_wptr
= &radeon_ring_generic_get_wptr
,
1812 .set_wptr
= &radeon_ring_generic_set_wptr
,
1815 static struct radeon_asic_ring si_dma_ring
= {
1816 .ib_execute
= &cayman_dma_ring_ib_execute
,
1817 .ib_parse
= &evergreen_dma_ib_parse
,
1818 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1819 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1821 .ring_test
= &r600_dma_ring_test
,
1822 .ib_test
= &r600_dma_ib_test
,
1823 .is_lockup
= &si_dma_is_lockup
,
1824 .vm_flush
= &si_dma_vm_flush
,
1825 .get_rptr
= &r600_dma_get_rptr
,
1826 .get_wptr
= &r600_dma_get_wptr
,
1827 .set_wptr
= &r600_dma_set_wptr
,
1830 static struct radeon_asic si_asic
= {
1833 .suspend
= &si_suspend
,
1834 .resume
= &si_resume
,
1835 .asic_reset
= &si_asic_reset
,
1836 .vga_set_state
= &r600_vga_set_state
,
1837 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1838 .gui_idle
= &r600_gui_idle
,
1839 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1840 .get_xclk
= &si_get_xclk
,
1841 .get_gpu_clock_counter
= &si_get_gpu_clock_counter
,
1843 .tlb_flush
= &si_pcie_gart_tlb_flush
,
1844 .set_page
= &rs600_gart_set_page
,
1847 .init
= &si_vm_init
,
1848 .fini
= &si_vm_fini
,
1849 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1850 .set_page
= &si_vm_set_page
,
1853 [RADEON_RING_TYPE_GFX_INDEX
] = &si_gfx_ring
,
1854 [CAYMAN_RING_TYPE_CP1_INDEX
] = &si_gfx_ring
,
1855 [CAYMAN_RING_TYPE_CP2_INDEX
] = &si_gfx_ring
,
1856 [R600_RING_TYPE_DMA_INDEX
] = &si_dma_ring
,
1857 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &si_dma_ring
,
1858 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
1862 .process
= &si_irq_process
,
1865 .bandwidth_update
= &dce6_bandwidth_update
,
1866 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1867 .wait_for_vblank
= &dce4_wait_for_vblank
,
1868 .set_backlight_level
= &atombios_set_backlight_level
,
1869 .get_backlight_level
= &atombios_get_backlight_level
,
1873 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1874 .dma
= &si_copy_dma
,
1875 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1876 .copy
= &si_copy_dma
,
1877 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1880 .set_reg
= r600_set_surface_reg
,
1881 .clear_reg
= r600_clear_surface_reg
,
1884 .init
= &evergreen_hpd_init
,
1885 .fini
= &evergreen_hpd_fini
,
1886 .sense
= &evergreen_hpd_sense
,
1887 .set_polarity
= &evergreen_hpd_set_polarity
,
1890 .misc
= &evergreen_pm_misc
,
1891 .prepare
= &evergreen_pm_prepare
,
1892 .finish
= &evergreen_pm_finish
,
1893 .init_profile
= &sumo_pm_init_profile
,
1894 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1895 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1896 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1897 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1898 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1899 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1900 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1901 .set_clock_gating
= NULL
,
1902 .set_uvd_clocks
= &si_set_uvd_clocks
,
1903 .get_temperature
= &si_get_temp
,
1906 .init
= &si_dpm_init
,
1907 .setup_asic
= &si_dpm_setup_asic
,
1908 .enable
= &si_dpm_enable
,
1909 .disable
= &si_dpm_disable
,
1910 .pre_set_power_state
= &si_dpm_pre_set_power_state
,
1911 .set_power_state
= &si_dpm_set_power_state
,
1912 .post_set_power_state
= &si_dpm_post_set_power_state
,
1913 .display_configuration_changed
= &si_dpm_display_configuration_changed
,
1914 .fini
= &si_dpm_fini
,
1915 .get_sclk
= &ni_dpm_get_sclk
,
1916 .get_mclk
= &ni_dpm_get_mclk
,
1917 .print_power_state
= &ni_dpm_print_power_state
,
1918 .debugfs_print_current_performance_level
= &si_dpm_debugfs_print_current_performance_level
,
1919 .force_performance_level
= &si_dpm_force_performance_level
,
1920 .vblank_too_short
= &ni_dpm_vblank_too_short
,
1923 .pre_page_flip
= &evergreen_pre_page_flip
,
1924 .page_flip
= &evergreen_page_flip
,
1925 .post_page_flip
= &evergreen_post_page_flip
,
1929 static struct radeon_asic_ring ci_gfx_ring
= {
1930 .ib_execute
= &cik_ring_ib_execute
,
1931 .ib_parse
= &cik_ib_parse
,
1932 .emit_fence
= &cik_fence_gfx_ring_emit
,
1933 .emit_semaphore
= &cik_semaphore_ring_emit
,
1935 .ring_test
= &cik_ring_test
,
1936 .ib_test
= &cik_ib_test
,
1937 .is_lockup
= &cik_gfx_is_lockup
,
1938 .vm_flush
= &cik_vm_flush
,
1939 .get_rptr
= &radeon_ring_generic_get_rptr
,
1940 .get_wptr
= &radeon_ring_generic_get_wptr
,
1941 .set_wptr
= &radeon_ring_generic_set_wptr
,
1944 static struct radeon_asic_ring ci_cp_ring
= {
1945 .ib_execute
= &cik_ring_ib_execute
,
1946 .ib_parse
= &cik_ib_parse
,
1947 .emit_fence
= &cik_fence_compute_ring_emit
,
1948 .emit_semaphore
= &cik_semaphore_ring_emit
,
1950 .ring_test
= &cik_ring_test
,
1951 .ib_test
= &cik_ib_test
,
1952 .is_lockup
= &cik_gfx_is_lockup
,
1953 .vm_flush
= &cik_vm_flush
,
1954 .get_rptr
= &cik_compute_ring_get_rptr
,
1955 .get_wptr
= &cik_compute_ring_get_wptr
,
1956 .set_wptr
= &cik_compute_ring_set_wptr
,
1959 static struct radeon_asic_ring ci_dma_ring
= {
1960 .ib_execute
= &cik_sdma_ring_ib_execute
,
1961 .ib_parse
= &cik_ib_parse
,
1962 .emit_fence
= &cik_sdma_fence_ring_emit
,
1963 .emit_semaphore
= &cik_sdma_semaphore_ring_emit
,
1965 .ring_test
= &cik_sdma_ring_test
,
1966 .ib_test
= &cik_sdma_ib_test
,
1967 .is_lockup
= &cik_sdma_is_lockup
,
1968 .vm_flush
= &cik_dma_vm_flush
,
1969 .get_rptr
= &r600_dma_get_rptr
,
1970 .get_wptr
= &r600_dma_get_wptr
,
1971 .set_wptr
= &r600_dma_set_wptr
,
1974 static struct radeon_asic ci_asic
= {
1977 .suspend
= &cik_suspend
,
1978 .resume
= &cik_resume
,
1979 .asic_reset
= &cik_asic_reset
,
1980 .vga_set_state
= &r600_vga_set_state
,
1981 .ioctl_wait_idle
= NULL
,
1982 .gui_idle
= &r600_gui_idle
,
1983 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1984 .get_xclk
= &cik_get_xclk
,
1985 .get_gpu_clock_counter
= &cik_get_gpu_clock_counter
,
1987 .tlb_flush
= &cik_pcie_gart_tlb_flush
,
1988 .set_page
= &rs600_gart_set_page
,
1991 .init
= &cik_vm_init
,
1992 .fini
= &cik_vm_fini
,
1993 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1994 .set_page
= &cik_vm_set_page
,
1997 [RADEON_RING_TYPE_GFX_INDEX
] = &ci_gfx_ring
,
1998 [CAYMAN_RING_TYPE_CP1_INDEX
] = &ci_cp_ring
,
1999 [CAYMAN_RING_TYPE_CP2_INDEX
] = &ci_cp_ring
,
2000 [R600_RING_TYPE_DMA_INDEX
] = &ci_dma_ring
,
2001 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &ci_dma_ring
,
2002 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
2005 .set
= &cik_irq_set
,
2006 .process
= &cik_irq_process
,
2009 .bandwidth_update
= &dce8_bandwidth_update
,
2010 .get_vblank_counter
= &evergreen_get_vblank_counter
,
2011 .wait_for_vblank
= &dce4_wait_for_vblank
,
2015 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
2016 .dma
= &cik_copy_dma
,
2017 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2018 .copy
= &cik_copy_dma
,
2019 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2022 .set_reg
= r600_set_surface_reg
,
2023 .clear_reg
= r600_clear_surface_reg
,
2026 .init
= &evergreen_hpd_init
,
2027 .fini
= &evergreen_hpd_fini
,
2028 .sense
= &evergreen_hpd_sense
,
2029 .set_polarity
= &evergreen_hpd_set_polarity
,
2032 .misc
= &evergreen_pm_misc
,
2033 .prepare
= &evergreen_pm_prepare
,
2034 .finish
= &evergreen_pm_finish
,
2035 .init_profile
= &sumo_pm_init_profile
,
2036 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
2037 .get_engine_clock
= &radeon_atom_get_engine_clock
,
2038 .set_engine_clock
= &radeon_atom_set_engine_clock
,
2039 .get_memory_clock
= &radeon_atom_get_memory_clock
,
2040 .set_memory_clock
= &radeon_atom_set_memory_clock
,
2041 .get_pcie_lanes
= NULL
,
2042 .set_pcie_lanes
= NULL
,
2043 .set_clock_gating
= NULL
,
2044 .set_uvd_clocks
= &cik_set_uvd_clocks
,
2045 .get_temperature
= &ci_get_temp
,
2048 .init
= &ci_dpm_init
,
2049 .setup_asic
= &ci_dpm_setup_asic
,
2050 .enable
= &ci_dpm_enable
,
2051 .disable
= &ci_dpm_disable
,
2052 .pre_set_power_state
= &ci_dpm_pre_set_power_state
,
2053 .set_power_state
= &ci_dpm_set_power_state
,
2054 .post_set_power_state
= &ci_dpm_post_set_power_state
,
2055 .display_configuration_changed
= &ci_dpm_display_configuration_changed
,
2056 .fini
= &ci_dpm_fini
,
2057 .get_sclk
= &ci_dpm_get_sclk
,
2058 .get_mclk
= &ci_dpm_get_mclk
,
2059 .print_power_state
= &ci_dpm_print_power_state
,
2060 .debugfs_print_current_performance_level
= &ci_dpm_debugfs_print_current_performance_level
,
2061 .force_performance_level
= &ci_dpm_force_performance_level
,
2062 .vblank_too_short
= &ci_dpm_vblank_too_short
,
2063 .powergate_uvd
= &ci_dpm_powergate_uvd
,
2066 .pre_page_flip
= &evergreen_pre_page_flip
,
2067 .page_flip
= &evergreen_page_flip
,
2068 .post_page_flip
= &evergreen_post_page_flip
,
2072 static struct radeon_asic kv_asic
= {
2075 .suspend
= &cik_suspend
,
2076 .resume
= &cik_resume
,
2077 .asic_reset
= &cik_asic_reset
,
2078 .vga_set_state
= &r600_vga_set_state
,
2079 .ioctl_wait_idle
= NULL
,
2080 .gui_idle
= &r600_gui_idle
,
2081 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
2082 .get_xclk
= &cik_get_xclk
,
2083 .get_gpu_clock_counter
= &cik_get_gpu_clock_counter
,
2085 .tlb_flush
= &cik_pcie_gart_tlb_flush
,
2086 .set_page
= &rs600_gart_set_page
,
2089 .init
= &cik_vm_init
,
2090 .fini
= &cik_vm_fini
,
2091 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2092 .set_page
= &cik_vm_set_page
,
2095 [RADEON_RING_TYPE_GFX_INDEX
] = &ci_gfx_ring
,
2096 [CAYMAN_RING_TYPE_CP1_INDEX
] = &ci_cp_ring
,
2097 [CAYMAN_RING_TYPE_CP2_INDEX
] = &ci_cp_ring
,
2098 [R600_RING_TYPE_DMA_INDEX
] = &ci_dma_ring
,
2099 [CAYMAN_RING_TYPE_DMA1_INDEX
] = &ci_dma_ring
,
2100 [R600_RING_TYPE_UVD_INDEX
] = &cayman_uvd_ring
,
2103 .set
= &cik_irq_set
,
2104 .process
= &cik_irq_process
,
2107 .bandwidth_update
= &dce8_bandwidth_update
,
2108 .get_vblank_counter
= &evergreen_get_vblank_counter
,
2109 .wait_for_vblank
= &dce4_wait_for_vblank
,
2113 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
2114 .dma
= &cik_copy_dma
,
2115 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2116 .copy
= &cik_copy_dma
,
2117 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
2120 .set_reg
= r600_set_surface_reg
,
2121 .clear_reg
= r600_clear_surface_reg
,
2124 .init
= &evergreen_hpd_init
,
2125 .fini
= &evergreen_hpd_fini
,
2126 .sense
= &evergreen_hpd_sense
,
2127 .set_polarity
= &evergreen_hpd_set_polarity
,
2130 .misc
= &evergreen_pm_misc
,
2131 .prepare
= &evergreen_pm_prepare
,
2132 .finish
= &evergreen_pm_finish
,
2133 .init_profile
= &sumo_pm_init_profile
,
2134 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
2135 .get_engine_clock
= &radeon_atom_get_engine_clock
,
2136 .set_engine_clock
= &radeon_atom_set_engine_clock
,
2137 .get_memory_clock
= &radeon_atom_get_memory_clock
,
2138 .set_memory_clock
= &radeon_atom_set_memory_clock
,
2139 .get_pcie_lanes
= NULL
,
2140 .set_pcie_lanes
= NULL
,
2141 .set_clock_gating
= NULL
,
2142 .set_uvd_clocks
= &cik_set_uvd_clocks
,
2143 .get_temperature
= &kv_get_temp
,
2146 .init
= &kv_dpm_init
,
2147 .setup_asic
= &kv_dpm_setup_asic
,
2148 .enable
= &kv_dpm_enable
,
2149 .disable
= &kv_dpm_disable
,
2150 .pre_set_power_state
= &kv_dpm_pre_set_power_state
,
2151 .set_power_state
= &kv_dpm_set_power_state
,
2152 .post_set_power_state
= &kv_dpm_post_set_power_state
,
2153 .display_configuration_changed
= &kv_dpm_display_configuration_changed
,
2154 .fini
= &kv_dpm_fini
,
2155 .get_sclk
= &kv_dpm_get_sclk
,
2156 .get_mclk
= &kv_dpm_get_mclk
,
2157 .print_power_state
= &kv_dpm_print_power_state
,
2158 .debugfs_print_current_performance_level
= &kv_dpm_debugfs_print_current_performance_level
,
2159 .force_performance_level
= &kv_dpm_force_performance_level
,
2160 .powergate_uvd
= &kv_dpm_powergate_uvd
,
2163 .pre_page_flip
= &evergreen_pre_page_flip
,
2164 .page_flip
= &evergreen_page_flip
,
2165 .post_page_flip
= &evergreen_post_page_flip
,
2170 * radeon_asic_init - register asic specific callbacks
2172 * @rdev: radeon device pointer
2174 * Registers the appropriate asic specific callbacks for each
2175 * chip family. Also sets other asics specific info like the number
2176 * of crtcs and the register aperture accessors (all asics).
2177 * Returns 0 for success.
2179 int radeon_asic_init(struct radeon_device
*rdev
)
2181 radeon_register_accessor_init(rdev
);
2183 /* set the number of crtcs */
2184 if (rdev
->flags
& RADEON_SINGLE_CRTC
)
2189 rdev
->has_uvd
= false;
2191 switch (rdev
->family
) {
2197 rdev
->asic
= &r100_asic
;
2203 rdev
->asic
= &r200_asic
;
2209 if (rdev
->flags
& RADEON_IS_PCIE
)
2210 rdev
->asic
= &r300_asic_pcie
;
2212 rdev
->asic
= &r300_asic
;
2217 rdev
->asic
= &r420_asic
;
2219 if (rdev
->bios
== NULL
) {
2220 rdev
->asic
->pm
.get_engine_clock
= &radeon_legacy_get_engine_clock
;
2221 rdev
->asic
->pm
.set_engine_clock
= &radeon_legacy_set_engine_clock
;
2222 rdev
->asic
->pm
.get_memory_clock
= &radeon_legacy_get_memory_clock
;
2223 rdev
->asic
->pm
.set_memory_clock
= NULL
;
2224 rdev
->asic
->display
.set_backlight_level
= &radeon_legacy_set_backlight_level
;
2229 rdev
->asic
= &rs400_asic
;
2232 rdev
->asic
= &rs600_asic
;
2236 rdev
->asic
= &rs690_asic
;
2239 rdev
->asic
= &rv515_asic
;
2246 rdev
->asic
= &r520_asic
;
2249 rdev
->asic
= &r600_asic
;
2256 rdev
->asic
= &rv6xx_asic
;
2257 rdev
->has_uvd
= true;
2261 rdev
->asic
= &rs780_asic
;
2262 rdev
->has_uvd
= true;
2268 rdev
->asic
= &rv770_asic
;
2269 rdev
->has_uvd
= true;
2277 if (rdev
->family
== CHIP_CEDAR
)
2281 rdev
->asic
= &evergreen_asic
;
2282 rdev
->has_uvd
= true;
2287 rdev
->asic
= &sumo_asic
;
2288 rdev
->has_uvd
= true;
2294 if (rdev
->family
== CHIP_CAICOS
)
2298 rdev
->asic
= &btc_asic
;
2299 rdev
->has_uvd
= true;
2302 rdev
->asic
= &cayman_asic
;
2305 rdev
->has_uvd
= true;
2308 rdev
->asic
= &trinity_asic
;
2311 rdev
->has_uvd
= true;
2318 rdev
->asic
= &si_asic
;
2320 if (rdev
->family
== CHIP_HAINAN
)
2322 else if (rdev
->family
== CHIP_OLAND
)
2326 if (rdev
->family
== CHIP_HAINAN
)
2327 rdev
->has_uvd
= false;
2329 rdev
->has_uvd
= true;
2332 rdev
->asic
= &ci_asic
;
2334 rdev
->has_uvd
= true;
2338 rdev
->asic
= &kv_asic
;
2340 if (rdev
->family
== CHIP_KAVERI
)
2344 rdev
->has_uvd
= true;
2347 /* FIXME: not supported yet */
2351 if (rdev
->flags
& RADEON_IS_IGP
) {
2352 rdev
->asic
->pm
.get_memory_clock
= NULL
;
2353 rdev
->asic
->pm
.set_memory_clock
= NULL
;