2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/console.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
37 #include "radeon_asic.h"
41 * Registers accessors functions.
43 static uint32_t radeon_invalid_rreg(struct radeon_device
*rdev
, uint32_t reg
)
45 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
50 static void radeon_invalid_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
52 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
57 static void radeon_register_accessor_init(struct radeon_device
*rdev
)
59 rdev
->mc_rreg
= &radeon_invalid_rreg
;
60 rdev
->mc_wreg
= &radeon_invalid_wreg
;
61 rdev
->pll_rreg
= &radeon_invalid_rreg
;
62 rdev
->pll_wreg
= &radeon_invalid_wreg
;
63 rdev
->pciep_rreg
= &radeon_invalid_rreg
;
64 rdev
->pciep_wreg
= &radeon_invalid_wreg
;
66 /* Don't change order as we are overridding accessor. */
67 if (rdev
->family
< CHIP_RV515
) {
68 rdev
->pcie_reg_mask
= 0xff;
70 rdev
->pcie_reg_mask
= 0x7ff;
72 /* FIXME: not sure here */
73 if (rdev
->family
<= CHIP_R580
) {
74 rdev
->pll_rreg
= &r100_pll_rreg
;
75 rdev
->pll_wreg
= &r100_pll_wreg
;
77 if (rdev
->family
>= CHIP_R420
) {
78 rdev
->mc_rreg
= &r420_mc_rreg
;
79 rdev
->mc_wreg
= &r420_mc_wreg
;
81 if (rdev
->family
>= CHIP_RV515
) {
82 rdev
->mc_rreg
= &rv515_mc_rreg
;
83 rdev
->mc_wreg
= &rv515_mc_wreg
;
85 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
86 rdev
->mc_rreg
= &rs400_mc_rreg
;
87 rdev
->mc_wreg
= &rs400_mc_wreg
;
89 if (rdev
->family
== CHIP_RS690
|| rdev
->family
== CHIP_RS740
) {
90 rdev
->mc_rreg
= &rs690_mc_rreg
;
91 rdev
->mc_wreg
= &rs690_mc_wreg
;
93 if (rdev
->family
== CHIP_RS600
) {
94 rdev
->mc_rreg
= &rs600_mc_rreg
;
95 rdev
->mc_wreg
= &rs600_mc_wreg
;
97 if (rdev
->family
>= CHIP_R600
) {
98 rdev
->pciep_rreg
= &r600_pciep_rreg
;
99 rdev
->pciep_wreg
= &r600_pciep_wreg
;
104 /* helper to disable agp */
105 void radeon_agp_disable(struct radeon_device
*rdev
)
107 rdev
->flags
&= ~RADEON_IS_AGP
;
108 if (rdev
->family
>= CHIP_R600
) {
109 DRM_INFO("Forcing AGP to PCIE mode\n");
110 rdev
->flags
|= RADEON_IS_PCIE
;
111 } else if (rdev
->family
>= CHIP_RV515
||
112 rdev
->family
== CHIP_RV380
||
113 rdev
->family
== CHIP_RV410
||
114 rdev
->family
== CHIP_R423
) {
115 DRM_INFO("Forcing AGP to PCIE mode\n");
116 rdev
->flags
|= RADEON_IS_PCIE
;
117 rdev
->asic
->gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
;
118 rdev
->asic
->gart_set_page
= &rv370_pcie_gart_set_page
;
120 DRM_INFO("Forcing AGP to PCI mode\n");
121 rdev
->flags
|= RADEON_IS_PCI
;
122 rdev
->asic
->gart_tlb_flush
= &r100_pci_gart_tlb_flush
;
123 rdev
->asic
->gart_set_page
= &r100_pci_gart_set_page
;
125 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
131 static struct radeon_asic r100_asic
= {
134 .suspend
= &r100_suspend
,
135 .resume
= &r100_resume
,
136 .vga_set_state
= &r100_vga_set_state
,
137 .gpu_is_lockup
= &r100_gpu_is_lockup
,
138 .asic_reset
= &r100_asic_reset
,
139 .gart_tlb_flush
= &r100_pci_gart_tlb_flush
,
140 .gart_set_page
= &r100_pci_gart_set_page
,
141 .ring_start
= &r100_ring_start
,
142 .ring_test
= &r100_ring_test
,
144 [RADEON_RING_TYPE_GFX_INDEX
] = {
145 .ib_execute
= &r100_ring_ib_execute
,
146 .emit_fence
= &r100_fence_ring_emit
,
147 .emit_semaphore
= &r100_semaphore_ring_emit
,
150 .irq_set
= &r100_irq_set
,
151 .irq_process
= &r100_irq_process
,
152 .get_vblank_counter
= &r100_get_vblank_counter
,
153 .cs_parse
= &r100_cs_parse
,
154 .copy_blit
= &r100_copy_blit
,
156 .copy
= &r100_copy_blit
,
157 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
158 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
159 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
160 .set_memory_clock
= NULL
,
161 .get_pcie_lanes
= NULL
,
162 .set_pcie_lanes
= NULL
,
163 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
164 .set_surface_reg
= r100_set_surface_reg
,
165 .clear_surface_reg
= r100_clear_surface_reg
,
166 .bandwidth_update
= &r100_bandwidth_update
,
168 .init
= &r100_hpd_init
,
169 .fini
= &r100_hpd_fini
,
170 .sense
= &r100_hpd_sense
,
171 .set_polarity
= &r100_hpd_set_polarity
,
173 .ioctl_wait_idle
= NULL
,
174 .gui_idle
= &r100_gui_idle
,
175 .pm_misc
= &r100_pm_misc
,
176 .pm_prepare
= &r100_pm_prepare
,
177 .pm_finish
= &r100_pm_finish
,
178 .pm_init_profile
= &r100_pm_init_profile
,
179 .pm_get_dynpm_state
= &r100_pm_get_dynpm_state
,
181 .pre_page_flip
= &r100_pre_page_flip
,
182 .page_flip
= &r100_page_flip
,
183 .post_page_flip
= &r100_post_page_flip
,
185 .wait_for_vblank
= &r100_wait_for_vblank
,
186 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
189 static struct radeon_asic r200_asic
= {
192 .suspend
= &r100_suspend
,
193 .resume
= &r100_resume
,
194 .vga_set_state
= &r100_vga_set_state
,
195 .gpu_is_lockup
= &r100_gpu_is_lockup
,
196 .asic_reset
= &r100_asic_reset
,
197 .gart_tlb_flush
= &r100_pci_gart_tlb_flush
,
198 .gart_set_page
= &r100_pci_gart_set_page
,
199 .ring_start
= &r100_ring_start
,
200 .ring_test
= &r100_ring_test
,
202 [RADEON_RING_TYPE_GFX_INDEX
] = {
203 .ib_execute
= &r100_ring_ib_execute
,
204 .emit_fence
= &r100_fence_ring_emit
,
205 .emit_semaphore
= &r100_semaphore_ring_emit
,
208 .irq_set
= &r100_irq_set
,
209 .irq_process
= &r100_irq_process
,
210 .get_vblank_counter
= &r100_get_vblank_counter
,
211 .cs_parse
= &r100_cs_parse
,
212 .copy_blit
= &r100_copy_blit
,
213 .copy_dma
= &r200_copy_dma
,
214 .copy
= &r100_copy_blit
,
215 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
216 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
217 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
218 .set_memory_clock
= NULL
,
219 .set_pcie_lanes
= NULL
,
220 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
221 .set_surface_reg
= r100_set_surface_reg
,
222 .clear_surface_reg
= r100_clear_surface_reg
,
223 .bandwidth_update
= &r100_bandwidth_update
,
225 .init
= &r100_hpd_init
,
226 .fini
= &r100_hpd_fini
,
227 .sense
= &r100_hpd_sense
,
228 .set_polarity
= &r100_hpd_set_polarity
,
230 .ioctl_wait_idle
= NULL
,
231 .gui_idle
= &r100_gui_idle
,
232 .pm_misc
= &r100_pm_misc
,
233 .pm_prepare
= &r100_pm_prepare
,
234 .pm_finish
= &r100_pm_finish
,
235 .pm_init_profile
= &r100_pm_init_profile
,
236 .pm_get_dynpm_state
= &r100_pm_get_dynpm_state
,
238 .pre_page_flip
= &r100_pre_page_flip
,
239 .page_flip
= &r100_page_flip
,
240 .post_page_flip
= &r100_post_page_flip
,
242 .wait_for_vblank
= &r100_wait_for_vblank
,
243 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
246 static struct radeon_asic r300_asic
= {
249 .suspend
= &r300_suspend
,
250 .resume
= &r300_resume
,
251 .vga_set_state
= &r100_vga_set_state
,
252 .gpu_is_lockup
= &r300_gpu_is_lockup
,
253 .asic_reset
= &r300_asic_reset
,
254 .gart_tlb_flush
= &r100_pci_gart_tlb_flush
,
255 .gart_set_page
= &r100_pci_gart_set_page
,
256 .ring_start
= &r300_ring_start
,
257 .ring_test
= &r100_ring_test
,
259 [RADEON_RING_TYPE_GFX_INDEX
] = {
260 .ib_execute
= &r100_ring_ib_execute
,
261 .emit_fence
= &r300_fence_ring_emit
,
262 .emit_semaphore
= &r100_semaphore_ring_emit
,
265 .irq_set
= &r100_irq_set
,
266 .irq_process
= &r100_irq_process
,
267 .get_vblank_counter
= &r100_get_vblank_counter
,
268 .cs_parse
= &r300_cs_parse
,
269 .copy_blit
= &r100_copy_blit
,
270 .copy_dma
= &r200_copy_dma
,
271 .copy
= &r100_copy_blit
,
272 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
273 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
274 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
275 .set_memory_clock
= NULL
,
276 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
277 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
278 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
279 .set_surface_reg
= r100_set_surface_reg
,
280 .clear_surface_reg
= r100_clear_surface_reg
,
281 .bandwidth_update
= &r100_bandwidth_update
,
283 .init
= &r100_hpd_init
,
284 .fini
= &r100_hpd_fini
,
285 .sense
= &r100_hpd_sense
,
286 .set_polarity
= &r100_hpd_set_polarity
,
288 .ioctl_wait_idle
= NULL
,
289 .gui_idle
= &r100_gui_idle
,
290 .pm_misc
= &r100_pm_misc
,
291 .pm_prepare
= &r100_pm_prepare
,
292 .pm_finish
= &r100_pm_finish
,
293 .pm_init_profile
= &r100_pm_init_profile
,
294 .pm_get_dynpm_state
= &r100_pm_get_dynpm_state
,
296 .pre_page_flip
= &r100_pre_page_flip
,
297 .page_flip
= &r100_page_flip
,
298 .post_page_flip
= &r100_post_page_flip
,
300 .wait_for_vblank
= &r100_wait_for_vblank
,
301 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
304 static struct radeon_asic r300_asic_pcie
= {
307 .suspend
= &r300_suspend
,
308 .resume
= &r300_resume
,
309 .vga_set_state
= &r100_vga_set_state
,
310 .gpu_is_lockup
= &r300_gpu_is_lockup
,
311 .asic_reset
= &r300_asic_reset
,
312 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
313 .gart_set_page
= &rv370_pcie_gart_set_page
,
314 .ring_start
= &r300_ring_start
,
315 .ring_test
= &r100_ring_test
,
317 [RADEON_RING_TYPE_GFX_INDEX
] = {
318 .ib_execute
= &r100_ring_ib_execute
,
319 .emit_fence
= &r300_fence_ring_emit
,
320 .emit_semaphore
= &r100_semaphore_ring_emit
,
323 .irq_set
= &r100_irq_set
,
324 .irq_process
= &r100_irq_process
,
325 .get_vblank_counter
= &r100_get_vblank_counter
,
326 .cs_parse
= &r300_cs_parse
,
327 .copy_blit
= &r100_copy_blit
,
328 .copy_dma
= &r200_copy_dma
,
329 .copy
= &r100_copy_blit
,
330 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
331 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
332 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
333 .set_memory_clock
= NULL
,
334 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
335 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
336 .set_surface_reg
= r100_set_surface_reg
,
337 .clear_surface_reg
= r100_clear_surface_reg
,
338 .bandwidth_update
= &r100_bandwidth_update
,
340 .init
= &r100_hpd_init
,
341 .fini
= &r100_hpd_fini
,
342 .sense
= &r100_hpd_sense
,
343 .set_polarity
= &r100_hpd_set_polarity
,
345 .ioctl_wait_idle
= NULL
,
346 .gui_idle
= &r100_gui_idle
,
347 .pm_misc
= &r100_pm_misc
,
348 .pm_prepare
= &r100_pm_prepare
,
349 .pm_finish
= &r100_pm_finish
,
350 .pm_init_profile
= &r100_pm_init_profile
,
351 .pm_get_dynpm_state
= &r100_pm_get_dynpm_state
,
353 .pre_page_flip
= &r100_pre_page_flip
,
354 .page_flip
= &r100_page_flip
,
355 .post_page_flip
= &r100_post_page_flip
,
357 .wait_for_vblank
= &r100_wait_for_vblank
,
358 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
361 static struct radeon_asic r420_asic
= {
364 .suspend
= &r420_suspend
,
365 .resume
= &r420_resume
,
366 .vga_set_state
= &r100_vga_set_state
,
367 .gpu_is_lockup
= &r300_gpu_is_lockup
,
368 .asic_reset
= &r300_asic_reset
,
369 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
370 .gart_set_page
= &rv370_pcie_gart_set_page
,
371 .ring_start
= &r300_ring_start
,
372 .ring_test
= &r100_ring_test
,
374 [RADEON_RING_TYPE_GFX_INDEX
] = {
375 .ib_execute
= &r100_ring_ib_execute
,
376 .emit_fence
= &r300_fence_ring_emit
,
377 .emit_semaphore
= &r100_semaphore_ring_emit
,
380 .irq_set
= &r100_irq_set
,
381 .irq_process
= &r100_irq_process
,
382 .get_vblank_counter
= &r100_get_vblank_counter
,
383 .cs_parse
= &r300_cs_parse
,
384 .copy_blit
= &r100_copy_blit
,
385 .copy_dma
= &r200_copy_dma
,
386 .copy
= &r100_copy_blit
,
387 .get_engine_clock
= &radeon_atom_get_engine_clock
,
388 .set_engine_clock
= &radeon_atom_set_engine_clock
,
389 .get_memory_clock
= &radeon_atom_get_memory_clock
,
390 .set_memory_clock
= &radeon_atom_set_memory_clock
,
391 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
392 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
393 .set_clock_gating
= &radeon_atom_set_clock_gating
,
394 .set_surface_reg
= r100_set_surface_reg
,
395 .clear_surface_reg
= r100_clear_surface_reg
,
396 .bandwidth_update
= &r100_bandwidth_update
,
398 .init
= &r100_hpd_init
,
399 .fini
= &r100_hpd_fini
,
400 .sense
= &r100_hpd_sense
,
401 .set_polarity
= &r100_hpd_set_polarity
,
403 .ioctl_wait_idle
= NULL
,
404 .gui_idle
= &r100_gui_idle
,
405 .pm_misc
= &r100_pm_misc
,
406 .pm_prepare
= &r100_pm_prepare
,
407 .pm_finish
= &r100_pm_finish
,
408 .pm_init_profile
= &r420_pm_init_profile
,
409 .pm_get_dynpm_state
= &r100_pm_get_dynpm_state
,
411 .pre_page_flip
= &r100_pre_page_flip
,
412 .page_flip
= &r100_page_flip
,
413 .post_page_flip
= &r100_post_page_flip
,
415 .wait_for_vblank
= &r100_wait_for_vblank
,
416 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
419 static struct radeon_asic rs400_asic
= {
422 .suspend
= &rs400_suspend
,
423 .resume
= &rs400_resume
,
424 .vga_set_state
= &r100_vga_set_state
,
425 .gpu_is_lockup
= &r300_gpu_is_lockup
,
426 .asic_reset
= &r300_asic_reset
,
427 .gart_tlb_flush
= &rs400_gart_tlb_flush
,
428 .gart_set_page
= &rs400_gart_set_page
,
429 .ring_start
= &r300_ring_start
,
430 .ring_test
= &r100_ring_test
,
432 [RADEON_RING_TYPE_GFX_INDEX
] = {
433 .ib_execute
= &r100_ring_ib_execute
,
434 .emit_fence
= &r300_fence_ring_emit
,
435 .emit_semaphore
= &r100_semaphore_ring_emit
,
438 .irq_set
= &r100_irq_set
,
439 .irq_process
= &r100_irq_process
,
440 .get_vblank_counter
= &r100_get_vblank_counter
,
441 .cs_parse
= &r300_cs_parse
,
442 .copy_blit
= &r100_copy_blit
,
443 .copy_dma
= &r200_copy_dma
,
444 .copy
= &r100_copy_blit
,
445 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
446 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
447 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
448 .set_memory_clock
= NULL
,
449 .get_pcie_lanes
= NULL
,
450 .set_pcie_lanes
= NULL
,
451 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
452 .set_surface_reg
= r100_set_surface_reg
,
453 .clear_surface_reg
= r100_clear_surface_reg
,
454 .bandwidth_update
= &r100_bandwidth_update
,
456 .init
= &r100_hpd_init
,
457 .fini
= &r100_hpd_fini
,
458 .sense
= &r100_hpd_sense
,
459 .set_polarity
= &r100_hpd_set_polarity
,
461 .ioctl_wait_idle
= NULL
,
462 .gui_idle
= &r100_gui_idle
,
463 .pm_misc
= &r100_pm_misc
,
464 .pm_prepare
= &r100_pm_prepare
,
465 .pm_finish
= &r100_pm_finish
,
466 .pm_init_profile
= &r100_pm_init_profile
,
467 .pm_get_dynpm_state
= &r100_pm_get_dynpm_state
,
469 .pre_page_flip
= &r100_pre_page_flip
,
470 .page_flip
= &r100_page_flip
,
471 .post_page_flip
= &r100_post_page_flip
,
473 .wait_for_vblank
= &r100_wait_for_vblank
,
474 .mc_wait_for_idle
= &rs400_mc_wait_for_idle
,
477 static struct radeon_asic rs600_asic
= {
480 .suspend
= &rs600_suspend
,
481 .resume
= &rs600_resume
,
482 .vga_set_state
= &r100_vga_set_state
,
483 .gpu_is_lockup
= &r300_gpu_is_lockup
,
484 .asic_reset
= &rs600_asic_reset
,
485 .gart_tlb_flush
= &rs600_gart_tlb_flush
,
486 .gart_set_page
= &rs600_gart_set_page
,
487 .ring_start
= &r300_ring_start
,
488 .ring_test
= &r100_ring_test
,
490 [RADEON_RING_TYPE_GFX_INDEX
] = {
491 .ib_execute
= &r100_ring_ib_execute
,
492 .emit_fence
= &r300_fence_ring_emit
,
493 .emit_semaphore
= &r100_semaphore_ring_emit
,
496 .irq_set
= &rs600_irq_set
,
497 .irq_process
= &rs600_irq_process
,
498 .get_vblank_counter
= &rs600_get_vblank_counter
,
499 .cs_parse
= &r300_cs_parse
,
500 .copy_blit
= &r100_copy_blit
,
501 .copy_dma
= &r200_copy_dma
,
502 .copy
= &r100_copy_blit
,
503 .get_engine_clock
= &radeon_atom_get_engine_clock
,
504 .set_engine_clock
= &radeon_atom_set_engine_clock
,
505 .get_memory_clock
= &radeon_atom_get_memory_clock
,
506 .set_memory_clock
= &radeon_atom_set_memory_clock
,
507 .get_pcie_lanes
= NULL
,
508 .set_pcie_lanes
= NULL
,
509 .set_clock_gating
= &radeon_atom_set_clock_gating
,
510 .set_surface_reg
= r100_set_surface_reg
,
511 .clear_surface_reg
= r100_clear_surface_reg
,
512 .bandwidth_update
= &rs600_bandwidth_update
,
514 .init
= &rs600_hpd_init
,
515 .fini
= &rs600_hpd_fini
,
516 .sense
= &rs600_hpd_sense
,
517 .set_polarity
= &rs600_hpd_set_polarity
,
519 .ioctl_wait_idle
= NULL
,
520 .gui_idle
= &r100_gui_idle
,
521 .pm_misc
= &rs600_pm_misc
,
522 .pm_prepare
= &rs600_pm_prepare
,
523 .pm_finish
= &rs600_pm_finish
,
524 .pm_init_profile
= &r420_pm_init_profile
,
525 .pm_get_dynpm_state
= &r100_pm_get_dynpm_state
,
527 .pre_page_flip
= &rs600_pre_page_flip
,
528 .page_flip
= &rs600_page_flip
,
529 .post_page_flip
= &rs600_post_page_flip
,
531 .wait_for_vblank
= &avivo_wait_for_vblank
,
532 .mc_wait_for_idle
= &rs600_mc_wait_for_idle
,
535 static struct radeon_asic rs690_asic
= {
538 .suspend
= &rs690_suspend
,
539 .resume
= &rs690_resume
,
540 .vga_set_state
= &r100_vga_set_state
,
541 .gpu_is_lockup
= &r300_gpu_is_lockup
,
542 .asic_reset
= &rs600_asic_reset
,
543 .gart_tlb_flush
= &rs400_gart_tlb_flush
,
544 .gart_set_page
= &rs400_gart_set_page
,
545 .ring_start
= &r300_ring_start
,
546 .ring_test
= &r100_ring_test
,
548 [RADEON_RING_TYPE_GFX_INDEX
] = {
549 .ib_execute
= &r100_ring_ib_execute
,
550 .emit_fence
= &r300_fence_ring_emit
,
551 .emit_semaphore
= &r100_semaphore_ring_emit
,
554 .irq_set
= &rs600_irq_set
,
555 .irq_process
= &rs600_irq_process
,
556 .get_vblank_counter
= &rs600_get_vblank_counter
,
557 .cs_parse
= &r300_cs_parse
,
558 .copy_blit
= &r100_copy_blit
,
559 .copy_dma
= &r200_copy_dma
,
560 .copy
= &r200_copy_dma
,
561 .get_engine_clock
= &radeon_atom_get_engine_clock
,
562 .set_engine_clock
= &radeon_atom_set_engine_clock
,
563 .get_memory_clock
= &radeon_atom_get_memory_clock
,
564 .set_memory_clock
= &radeon_atom_set_memory_clock
,
565 .get_pcie_lanes
= NULL
,
566 .set_pcie_lanes
= NULL
,
567 .set_clock_gating
= &radeon_atom_set_clock_gating
,
568 .set_surface_reg
= r100_set_surface_reg
,
569 .clear_surface_reg
= r100_clear_surface_reg
,
570 .bandwidth_update
= &rs690_bandwidth_update
,
572 .init
= &rs600_hpd_init
,
573 .fini
= &rs600_hpd_fini
,
574 .sense
= &rs600_hpd_sense
,
575 .set_polarity
= &rs600_hpd_set_polarity
,
577 .ioctl_wait_idle
= NULL
,
578 .gui_idle
= &r100_gui_idle
,
579 .pm_misc
= &rs600_pm_misc
,
580 .pm_prepare
= &rs600_pm_prepare
,
581 .pm_finish
= &rs600_pm_finish
,
582 .pm_init_profile
= &r420_pm_init_profile
,
583 .pm_get_dynpm_state
= &r100_pm_get_dynpm_state
,
585 .pre_page_flip
= &rs600_pre_page_flip
,
586 .page_flip
= &rs600_page_flip
,
587 .post_page_flip
= &rs600_post_page_flip
,
589 .wait_for_vblank
= &avivo_wait_for_vblank
,
590 .mc_wait_for_idle
= &rs690_mc_wait_for_idle
,
593 static struct radeon_asic rv515_asic
= {
596 .suspend
= &rv515_suspend
,
597 .resume
= &rv515_resume
,
598 .vga_set_state
= &r100_vga_set_state
,
599 .gpu_is_lockup
= &r300_gpu_is_lockup
,
600 .asic_reset
= &rs600_asic_reset
,
601 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
602 .gart_set_page
= &rv370_pcie_gart_set_page
,
603 .ring_start
= &rv515_ring_start
,
604 .ring_test
= &r100_ring_test
,
606 [RADEON_RING_TYPE_GFX_INDEX
] = {
607 .ib_execute
= &r100_ring_ib_execute
,
608 .emit_fence
= &r300_fence_ring_emit
,
609 .emit_semaphore
= &r100_semaphore_ring_emit
,
612 .irq_set
= &rs600_irq_set
,
613 .irq_process
= &rs600_irq_process
,
614 .get_vblank_counter
= &rs600_get_vblank_counter
,
615 .cs_parse
= &r300_cs_parse
,
616 .copy_blit
= &r100_copy_blit
,
617 .copy_dma
= &r200_copy_dma
,
618 .copy
= &r100_copy_blit
,
619 .get_engine_clock
= &radeon_atom_get_engine_clock
,
620 .set_engine_clock
= &radeon_atom_set_engine_clock
,
621 .get_memory_clock
= &radeon_atom_get_memory_clock
,
622 .set_memory_clock
= &radeon_atom_set_memory_clock
,
623 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
624 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
625 .set_clock_gating
= &radeon_atom_set_clock_gating
,
626 .set_surface_reg
= r100_set_surface_reg
,
627 .clear_surface_reg
= r100_clear_surface_reg
,
628 .bandwidth_update
= &rv515_bandwidth_update
,
630 .init
= &rs600_hpd_init
,
631 .fini
= &rs600_hpd_fini
,
632 .sense
= &rs600_hpd_sense
,
633 .set_polarity
= &rs600_hpd_set_polarity
,
635 .ioctl_wait_idle
= NULL
,
636 .gui_idle
= &r100_gui_idle
,
637 .pm_misc
= &rs600_pm_misc
,
638 .pm_prepare
= &rs600_pm_prepare
,
639 .pm_finish
= &rs600_pm_finish
,
640 .pm_init_profile
= &r420_pm_init_profile
,
641 .pm_get_dynpm_state
= &r100_pm_get_dynpm_state
,
643 .pre_page_flip
= &rs600_pre_page_flip
,
644 .page_flip
= &rs600_page_flip
,
645 .post_page_flip
= &rs600_post_page_flip
,
647 .wait_for_vblank
= &avivo_wait_for_vblank
,
648 .mc_wait_for_idle
= &rv515_mc_wait_for_idle
,
651 static struct radeon_asic r520_asic
= {
654 .suspend
= &rv515_suspend
,
655 .resume
= &r520_resume
,
656 .vga_set_state
= &r100_vga_set_state
,
657 .gpu_is_lockup
= &r300_gpu_is_lockup
,
658 .asic_reset
= &rs600_asic_reset
,
659 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
660 .gart_set_page
= &rv370_pcie_gart_set_page
,
661 .ring_start
= &rv515_ring_start
,
662 .ring_test
= &r100_ring_test
,
664 [RADEON_RING_TYPE_GFX_INDEX
] = {
665 .ib_execute
= &r100_ring_ib_execute
,
666 .emit_fence
= &r300_fence_ring_emit
,
667 .emit_semaphore
= &r100_semaphore_ring_emit
,
670 .irq_set
= &rs600_irq_set
,
671 .irq_process
= &rs600_irq_process
,
672 .get_vblank_counter
= &rs600_get_vblank_counter
,
673 .cs_parse
= &r300_cs_parse
,
674 .copy_blit
= &r100_copy_blit
,
675 .copy_dma
= &r200_copy_dma
,
676 .copy
= &r100_copy_blit
,
677 .get_engine_clock
= &radeon_atom_get_engine_clock
,
678 .set_engine_clock
= &radeon_atom_set_engine_clock
,
679 .get_memory_clock
= &radeon_atom_get_memory_clock
,
680 .set_memory_clock
= &radeon_atom_set_memory_clock
,
681 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
682 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
683 .set_clock_gating
= &radeon_atom_set_clock_gating
,
684 .set_surface_reg
= r100_set_surface_reg
,
685 .clear_surface_reg
= r100_clear_surface_reg
,
686 .bandwidth_update
= &rv515_bandwidth_update
,
688 .init
= &rs600_hpd_init
,
689 .fini
= &rs600_hpd_fini
,
690 .sense
= &rs600_hpd_sense
,
691 .set_polarity
= &rs600_hpd_set_polarity
,
693 .ioctl_wait_idle
= NULL
,
694 .gui_idle
= &r100_gui_idle
,
695 .pm_misc
= &rs600_pm_misc
,
696 .pm_prepare
= &rs600_pm_prepare
,
697 .pm_finish
= &rs600_pm_finish
,
698 .pm_init_profile
= &r420_pm_init_profile
,
699 .pm_get_dynpm_state
= &r100_pm_get_dynpm_state
,
701 .pre_page_flip
= &rs600_pre_page_flip
,
702 .page_flip
= &rs600_page_flip
,
703 .post_page_flip
= &rs600_post_page_flip
,
705 .wait_for_vblank
= &avivo_wait_for_vblank
,
706 .mc_wait_for_idle
= &r520_mc_wait_for_idle
,
709 static struct radeon_asic r600_asic
= {
712 .suspend
= &r600_suspend
,
713 .resume
= &r600_resume
,
714 .vga_set_state
= &r600_vga_set_state
,
715 .gpu_is_lockup
= &r600_gpu_is_lockup
,
716 .asic_reset
= &r600_asic_reset
,
717 .gart_tlb_flush
= &r600_pcie_gart_tlb_flush
,
718 .gart_set_page
= &rs600_gart_set_page
,
719 .ring_test
= &r600_ring_test
,
721 [RADEON_RING_TYPE_GFX_INDEX
] = {
722 .ib_execute
= &r600_ring_ib_execute
,
723 .emit_fence
= &r600_fence_ring_emit
,
724 .emit_semaphore
= &r600_semaphore_ring_emit
,
727 .irq_set
= &r600_irq_set
,
728 .irq_process
= &r600_irq_process
,
729 .get_vblank_counter
= &rs600_get_vblank_counter
,
730 .cs_parse
= &r600_cs_parse
,
731 .copy_blit
= &r600_copy_blit
,
733 .copy
= &r600_copy_blit
,
734 .get_engine_clock
= &radeon_atom_get_engine_clock
,
735 .set_engine_clock
= &radeon_atom_set_engine_clock
,
736 .get_memory_clock
= &radeon_atom_get_memory_clock
,
737 .set_memory_clock
= &radeon_atom_set_memory_clock
,
738 .get_pcie_lanes
= &r600_get_pcie_lanes
,
739 .set_pcie_lanes
= &r600_set_pcie_lanes
,
740 .set_clock_gating
= NULL
,
741 .set_surface_reg
= r600_set_surface_reg
,
742 .clear_surface_reg
= r600_clear_surface_reg
,
743 .bandwidth_update
= &rv515_bandwidth_update
,
745 .init
= &r600_hpd_init
,
746 .fini
= &r600_hpd_fini
,
747 .sense
= &r600_hpd_sense
,
748 .set_polarity
= &r600_hpd_set_polarity
,
750 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
751 .gui_idle
= &r600_gui_idle
,
752 .pm_misc
= &r600_pm_misc
,
753 .pm_prepare
= &rs600_pm_prepare
,
754 .pm_finish
= &rs600_pm_finish
,
755 .pm_init_profile
= &r600_pm_init_profile
,
756 .pm_get_dynpm_state
= &r600_pm_get_dynpm_state
,
758 .pre_page_flip
= &rs600_pre_page_flip
,
759 .page_flip
= &rs600_page_flip
,
760 .post_page_flip
= &rs600_post_page_flip
,
762 .wait_for_vblank
= &avivo_wait_for_vblank
,
763 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
766 static struct radeon_asic rs780_asic
= {
769 .suspend
= &r600_suspend
,
770 .resume
= &r600_resume
,
771 .gpu_is_lockup
= &r600_gpu_is_lockup
,
772 .vga_set_state
= &r600_vga_set_state
,
773 .asic_reset
= &r600_asic_reset
,
774 .gart_tlb_flush
= &r600_pcie_gart_tlb_flush
,
775 .gart_set_page
= &rs600_gart_set_page
,
776 .ring_test
= &r600_ring_test
,
778 [RADEON_RING_TYPE_GFX_INDEX
] = {
779 .ib_execute
= &r600_ring_ib_execute
,
780 .emit_fence
= &r600_fence_ring_emit
,
781 .emit_semaphore
= &r600_semaphore_ring_emit
,
784 .irq_set
= &r600_irq_set
,
785 .irq_process
= &r600_irq_process
,
786 .get_vblank_counter
= &rs600_get_vblank_counter
,
787 .cs_parse
= &r600_cs_parse
,
788 .copy_blit
= &r600_copy_blit
,
790 .copy
= &r600_copy_blit
,
791 .get_engine_clock
= &radeon_atom_get_engine_clock
,
792 .set_engine_clock
= &radeon_atom_set_engine_clock
,
793 .get_memory_clock
= NULL
,
794 .set_memory_clock
= NULL
,
795 .get_pcie_lanes
= NULL
,
796 .set_pcie_lanes
= NULL
,
797 .set_clock_gating
= NULL
,
798 .set_surface_reg
= r600_set_surface_reg
,
799 .clear_surface_reg
= r600_clear_surface_reg
,
800 .bandwidth_update
= &rs690_bandwidth_update
,
802 .init
= &r600_hpd_init
,
803 .fini
= &r600_hpd_fini
,
804 .sense
= &r600_hpd_sense
,
805 .set_polarity
= &r600_hpd_set_polarity
,
807 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
808 .gui_idle
= &r600_gui_idle
,
809 .pm_misc
= &r600_pm_misc
,
810 .pm_prepare
= &rs600_pm_prepare
,
811 .pm_finish
= &rs600_pm_finish
,
812 .pm_init_profile
= &rs780_pm_init_profile
,
813 .pm_get_dynpm_state
= &r600_pm_get_dynpm_state
,
815 .pre_page_flip
= &rs600_pre_page_flip
,
816 .page_flip
= &rs600_page_flip
,
817 .post_page_flip
= &rs600_post_page_flip
,
819 .wait_for_vblank
= &avivo_wait_for_vblank
,
820 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
823 static struct radeon_asic rv770_asic
= {
826 .suspend
= &rv770_suspend
,
827 .resume
= &rv770_resume
,
828 .asic_reset
= &r600_asic_reset
,
829 .gpu_is_lockup
= &r600_gpu_is_lockup
,
830 .vga_set_state
= &r600_vga_set_state
,
831 .gart_tlb_flush
= &r600_pcie_gart_tlb_flush
,
832 .gart_set_page
= &rs600_gart_set_page
,
833 .ring_test
= &r600_ring_test
,
835 [RADEON_RING_TYPE_GFX_INDEX
] = {
836 .ib_execute
= &r600_ring_ib_execute
,
837 .emit_fence
= &r600_fence_ring_emit
,
838 .emit_semaphore
= &r600_semaphore_ring_emit
,
841 .irq_set
= &r600_irq_set
,
842 .irq_process
= &r600_irq_process
,
843 .get_vblank_counter
= &rs600_get_vblank_counter
,
844 .cs_parse
= &r600_cs_parse
,
845 .copy_blit
= &r600_copy_blit
,
847 .copy
= &r600_copy_blit
,
848 .get_engine_clock
= &radeon_atom_get_engine_clock
,
849 .set_engine_clock
= &radeon_atom_set_engine_clock
,
850 .get_memory_clock
= &radeon_atom_get_memory_clock
,
851 .set_memory_clock
= &radeon_atom_set_memory_clock
,
852 .get_pcie_lanes
= &r600_get_pcie_lanes
,
853 .set_pcie_lanes
= &r600_set_pcie_lanes
,
854 .set_clock_gating
= &radeon_atom_set_clock_gating
,
855 .set_surface_reg
= r600_set_surface_reg
,
856 .clear_surface_reg
= r600_clear_surface_reg
,
857 .bandwidth_update
= &rv515_bandwidth_update
,
859 .init
= &r600_hpd_init
,
860 .fini
= &r600_hpd_fini
,
861 .sense
= &r600_hpd_sense
,
862 .set_polarity
= &r600_hpd_set_polarity
,
864 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
865 .gui_idle
= &r600_gui_idle
,
866 .pm_misc
= &rv770_pm_misc
,
867 .pm_prepare
= &rs600_pm_prepare
,
868 .pm_finish
= &rs600_pm_finish
,
869 .pm_init_profile
= &r600_pm_init_profile
,
870 .pm_get_dynpm_state
= &r600_pm_get_dynpm_state
,
872 .pre_page_flip
= &rs600_pre_page_flip
,
873 .page_flip
= &rv770_page_flip
,
874 .post_page_flip
= &rs600_post_page_flip
,
876 .wait_for_vblank
= &avivo_wait_for_vblank
,
877 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
880 static struct radeon_asic evergreen_asic
= {
881 .init
= &evergreen_init
,
882 .fini
= &evergreen_fini
,
883 .suspend
= &evergreen_suspend
,
884 .resume
= &evergreen_resume
,
885 .gpu_is_lockup
= &evergreen_gpu_is_lockup
,
886 .asic_reset
= &evergreen_asic_reset
,
887 .vga_set_state
= &r600_vga_set_state
,
888 .gart_tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
889 .gart_set_page
= &rs600_gart_set_page
,
890 .ring_test
= &r600_ring_test
,
892 [RADEON_RING_TYPE_GFX_INDEX
] = {
893 .ib_execute
= &evergreen_ring_ib_execute
,
894 .emit_fence
= &r600_fence_ring_emit
,
895 .emit_semaphore
= &r600_semaphore_ring_emit
,
898 .irq_set
= &evergreen_irq_set
,
899 .irq_process
= &evergreen_irq_process
,
900 .get_vblank_counter
= &evergreen_get_vblank_counter
,
901 .cs_parse
= &evergreen_cs_parse
,
902 .copy_blit
= &r600_copy_blit
,
904 .copy
= &r600_copy_blit
,
905 .get_engine_clock
= &radeon_atom_get_engine_clock
,
906 .set_engine_clock
= &radeon_atom_set_engine_clock
,
907 .get_memory_clock
= &radeon_atom_get_memory_clock
,
908 .set_memory_clock
= &radeon_atom_set_memory_clock
,
909 .get_pcie_lanes
= &r600_get_pcie_lanes
,
910 .set_pcie_lanes
= &r600_set_pcie_lanes
,
911 .set_clock_gating
= NULL
,
912 .set_surface_reg
= r600_set_surface_reg
,
913 .clear_surface_reg
= r600_clear_surface_reg
,
914 .bandwidth_update
= &evergreen_bandwidth_update
,
916 .init
= &evergreen_hpd_init
,
917 .fini
= &evergreen_hpd_fini
,
918 .sense
= &evergreen_hpd_sense
,
919 .set_polarity
= &evergreen_hpd_set_polarity
,
921 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
922 .gui_idle
= &r600_gui_idle
,
923 .pm_misc
= &evergreen_pm_misc
,
924 .pm_prepare
= &evergreen_pm_prepare
,
925 .pm_finish
= &evergreen_pm_finish
,
926 .pm_init_profile
= &r600_pm_init_profile
,
927 .pm_get_dynpm_state
= &r600_pm_get_dynpm_state
,
929 .pre_page_flip
= &evergreen_pre_page_flip
,
930 .page_flip
= &evergreen_page_flip
,
931 .post_page_flip
= &evergreen_post_page_flip
,
933 .wait_for_vblank
= &dce4_wait_for_vblank
,
934 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
937 static struct radeon_asic sumo_asic
= {
938 .init
= &evergreen_init
,
939 .fini
= &evergreen_fini
,
940 .suspend
= &evergreen_suspend
,
941 .resume
= &evergreen_resume
,
942 .gpu_is_lockup
= &evergreen_gpu_is_lockup
,
943 .asic_reset
= &evergreen_asic_reset
,
944 .vga_set_state
= &r600_vga_set_state
,
945 .gart_tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
946 .gart_set_page
= &rs600_gart_set_page
,
947 .ring_test
= &r600_ring_test
,
949 [RADEON_RING_TYPE_GFX_INDEX
] = {
950 .ib_execute
= &evergreen_ring_ib_execute
,
951 .emit_fence
= &r600_fence_ring_emit
,
952 .emit_semaphore
= &r600_semaphore_ring_emit
,
955 .irq_set
= &evergreen_irq_set
,
956 .irq_process
= &evergreen_irq_process
,
957 .get_vblank_counter
= &evergreen_get_vblank_counter
,
958 .cs_parse
= &evergreen_cs_parse
,
959 .copy_blit
= &r600_copy_blit
,
961 .copy
= &r600_copy_blit
,
962 .get_engine_clock
= &radeon_atom_get_engine_clock
,
963 .set_engine_clock
= &radeon_atom_set_engine_clock
,
964 .get_memory_clock
= NULL
,
965 .set_memory_clock
= NULL
,
966 .get_pcie_lanes
= NULL
,
967 .set_pcie_lanes
= NULL
,
968 .set_clock_gating
= NULL
,
969 .set_surface_reg
= r600_set_surface_reg
,
970 .clear_surface_reg
= r600_clear_surface_reg
,
971 .bandwidth_update
= &evergreen_bandwidth_update
,
973 .init
= &evergreen_hpd_init
,
974 .fini
= &evergreen_hpd_fini
,
975 .sense
= &evergreen_hpd_sense
,
976 .set_polarity
= &evergreen_hpd_set_polarity
,
978 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
979 .gui_idle
= &r600_gui_idle
,
980 .pm_misc
= &evergreen_pm_misc
,
981 .pm_prepare
= &evergreen_pm_prepare
,
982 .pm_finish
= &evergreen_pm_finish
,
983 .pm_init_profile
= &sumo_pm_init_profile
,
984 .pm_get_dynpm_state
= &r600_pm_get_dynpm_state
,
986 .pre_page_flip
= &evergreen_pre_page_flip
,
987 .page_flip
= &evergreen_page_flip
,
988 .post_page_flip
= &evergreen_post_page_flip
,
990 .wait_for_vblank
= &dce4_wait_for_vblank
,
991 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
994 static struct radeon_asic btc_asic
= {
995 .init
= &evergreen_init
,
996 .fini
= &evergreen_fini
,
997 .suspend
= &evergreen_suspend
,
998 .resume
= &evergreen_resume
,
999 .gpu_is_lockup
= &evergreen_gpu_is_lockup
,
1000 .asic_reset
= &evergreen_asic_reset
,
1001 .vga_set_state
= &r600_vga_set_state
,
1002 .gart_tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1003 .gart_set_page
= &rs600_gart_set_page
,
1004 .ring_test
= &r600_ring_test
,
1006 [RADEON_RING_TYPE_GFX_INDEX
] = {
1007 .ib_execute
= &evergreen_ring_ib_execute
,
1008 .emit_fence
= &r600_fence_ring_emit
,
1009 .emit_semaphore
= &r600_semaphore_ring_emit
,
1012 .irq_set
= &evergreen_irq_set
,
1013 .irq_process
= &evergreen_irq_process
,
1014 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1015 .cs_parse
= &evergreen_cs_parse
,
1016 .copy_blit
= &r600_copy_blit
,
1018 .copy
= &r600_copy_blit
,
1019 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1020 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1021 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1022 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1023 .get_pcie_lanes
= NULL
,
1024 .set_pcie_lanes
= NULL
,
1025 .set_clock_gating
= NULL
,
1026 .set_surface_reg
= r600_set_surface_reg
,
1027 .clear_surface_reg
= r600_clear_surface_reg
,
1028 .bandwidth_update
= &evergreen_bandwidth_update
,
1030 .init
= &evergreen_hpd_init
,
1031 .fini
= &evergreen_hpd_fini
,
1032 .sense
= &evergreen_hpd_sense
,
1033 .set_polarity
= &evergreen_hpd_set_polarity
,
1035 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1036 .gui_idle
= &r600_gui_idle
,
1037 .pm_misc
= &evergreen_pm_misc
,
1038 .pm_prepare
= &evergreen_pm_prepare
,
1039 .pm_finish
= &evergreen_pm_finish
,
1040 .pm_init_profile
= &r600_pm_init_profile
,
1041 .pm_get_dynpm_state
= &r600_pm_get_dynpm_state
,
1043 .pre_page_flip
= &evergreen_pre_page_flip
,
1044 .page_flip
= &evergreen_page_flip
,
1045 .post_page_flip
= &evergreen_post_page_flip
,
1047 .wait_for_vblank
= &dce4_wait_for_vblank
,
1048 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1051 static const struct radeon_vm_funcs cayman_vm_funcs
= {
1052 .init
= &cayman_vm_init
,
1053 .fini
= &cayman_vm_fini
,
1054 .bind
= &cayman_vm_bind
,
1055 .unbind
= &cayman_vm_unbind
,
1056 .tlb_flush
= &cayman_vm_tlb_flush
,
1057 .page_flags
= &cayman_vm_page_flags
,
1058 .set_page
= &cayman_vm_set_page
,
1061 static struct radeon_asic cayman_asic
= {
1062 .init
= &cayman_init
,
1063 .fini
= &cayman_fini
,
1064 .suspend
= &cayman_suspend
,
1065 .resume
= &cayman_resume
,
1066 .gpu_is_lockup
= &cayman_gpu_is_lockup
,
1067 .asic_reset
= &cayman_asic_reset
,
1068 .vga_set_state
= &r600_vga_set_state
,
1069 .gart_tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1070 .gart_set_page
= &rs600_gart_set_page
,
1071 .ring_test
= &r600_ring_test
,
1073 [RADEON_RING_TYPE_GFX_INDEX
] = {
1074 .ib_execute
= &cayman_ring_ib_execute
,
1075 .ib_parse
= &evergreen_ib_parse
,
1076 .emit_fence
= &cayman_fence_ring_emit
,
1077 .emit_semaphore
= &r600_semaphore_ring_emit
,
1079 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
1080 .ib_execute
= &cayman_ring_ib_execute
,
1081 .ib_parse
= &evergreen_ib_parse
,
1082 .emit_fence
= &cayman_fence_ring_emit
,
1083 .emit_semaphore
= &r600_semaphore_ring_emit
,
1085 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
1086 .ib_execute
= &cayman_ring_ib_execute
,
1087 .ib_parse
= &evergreen_ib_parse
,
1088 .emit_fence
= &cayman_fence_ring_emit
,
1089 .emit_semaphore
= &r600_semaphore_ring_emit
,
1092 .irq_set
= &evergreen_irq_set
,
1093 .irq_process
= &evergreen_irq_process
,
1094 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1095 .cs_parse
= &evergreen_cs_parse
,
1096 .copy_blit
= &r600_copy_blit
,
1098 .copy
= &r600_copy_blit
,
1099 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1100 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1101 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1102 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1103 .get_pcie_lanes
= NULL
,
1104 .set_pcie_lanes
= NULL
,
1105 .set_clock_gating
= NULL
,
1106 .set_surface_reg
= r600_set_surface_reg
,
1107 .clear_surface_reg
= r600_clear_surface_reg
,
1108 .bandwidth_update
= &evergreen_bandwidth_update
,
1110 .init
= &evergreen_hpd_init
,
1111 .fini
= &evergreen_hpd_fini
,
1112 .sense
= &evergreen_hpd_sense
,
1113 .set_polarity
= &evergreen_hpd_set_polarity
,
1115 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1116 .gui_idle
= &r600_gui_idle
,
1117 .pm_misc
= &evergreen_pm_misc
,
1118 .pm_prepare
= &evergreen_pm_prepare
,
1119 .pm_finish
= &evergreen_pm_finish
,
1120 .pm_init_profile
= &r600_pm_init_profile
,
1121 .pm_get_dynpm_state
= &r600_pm_get_dynpm_state
,
1123 .pre_page_flip
= &evergreen_pre_page_flip
,
1124 .page_flip
= &evergreen_page_flip
,
1125 .post_page_flip
= &evergreen_post_page_flip
,
1127 .wait_for_vblank
= &dce4_wait_for_vblank
,
1128 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1131 int radeon_asic_init(struct radeon_device
*rdev
)
1133 radeon_register_accessor_init(rdev
);
1135 /* set the number of crtcs */
1136 if (rdev
->flags
& RADEON_SINGLE_CRTC
)
1141 /* set the ring used for bo copies */
1142 rdev
->copy_ring
= RADEON_RING_TYPE_GFX_INDEX
;
1144 switch (rdev
->family
) {
1150 rdev
->asic
= &r100_asic
;
1156 rdev
->asic
= &r200_asic
;
1162 if (rdev
->flags
& RADEON_IS_PCIE
)
1163 rdev
->asic
= &r300_asic_pcie
;
1165 rdev
->asic
= &r300_asic
;
1170 rdev
->asic
= &r420_asic
;
1172 if (rdev
->bios
== NULL
) {
1173 rdev
->asic
->get_engine_clock
= &radeon_legacy_get_engine_clock
;
1174 rdev
->asic
->set_engine_clock
= &radeon_legacy_set_engine_clock
;
1175 rdev
->asic
->get_memory_clock
= &radeon_legacy_get_memory_clock
;
1176 rdev
->asic
->set_memory_clock
= NULL
;
1181 rdev
->asic
= &rs400_asic
;
1184 rdev
->asic
= &rs600_asic
;
1188 rdev
->asic
= &rs690_asic
;
1191 rdev
->asic
= &rv515_asic
;
1198 rdev
->asic
= &r520_asic
;
1206 rdev
->asic
= &r600_asic
;
1210 rdev
->asic
= &rs780_asic
;
1216 rdev
->asic
= &rv770_asic
;
1224 if (rdev
->family
== CHIP_CEDAR
)
1228 rdev
->asic
= &evergreen_asic
;
1233 rdev
->asic
= &sumo_asic
;
1239 if (rdev
->family
== CHIP_CAICOS
)
1243 rdev
->asic
= &btc_asic
;
1246 rdev
->asic
= &cayman_asic
;
1249 rdev
->vm_manager
.funcs
= &cayman_vm_funcs
;
1252 /* FIXME: not supported yet */
1256 if (rdev
->flags
& RADEON_IS_IGP
) {
1257 rdev
->asic
->get_memory_clock
= NULL
;
1258 rdev
->asic
->set_memory_clock
= NULL
;