2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/console.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
37 #include "radeon_asic.h"
41 * Registers accessors functions.
44 * radeon_invalid_rreg - dummy reg read function
46 * @rdev: radeon device pointer
47 * @reg: offset of register
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
53 static uint32_t radeon_invalid_rreg(struct radeon_device
*rdev
, uint32_t reg
)
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
61 * radeon_invalid_wreg - dummy reg write function
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
70 static void radeon_invalid_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
78 * radeon_register_accessor_init - sets up the register accessor callbacks
80 * @rdev: radeon device pointer
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
85 static void radeon_register_accessor_init(struct radeon_device
*rdev
)
87 rdev
->mc_rreg
= &radeon_invalid_rreg
;
88 rdev
->mc_wreg
= &radeon_invalid_wreg
;
89 rdev
->pll_rreg
= &radeon_invalid_rreg
;
90 rdev
->pll_wreg
= &radeon_invalid_wreg
;
91 rdev
->pciep_rreg
= &radeon_invalid_rreg
;
92 rdev
->pciep_wreg
= &radeon_invalid_wreg
;
94 /* Don't change order as we are overridding accessor. */
95 if (rdev
->family
< CHIP_RV515
) {
96 rdev
->pcie_reg_mask
= 0xff;
98 rdev
->pcie_reg_mask
= 0x7ff;
100 /* FIXME: not sure here */
101 if (rdev
->family
<= CHIP_R580
) {
102 rdev
->pll_rreg
= &r100_pll_rreg
;
103 rdev
->pll_wreg
= &r100_pll_wreg
;
105 if (rdev
->family
>= CHIP_R420
) {
106 rdev
->mc_rreg
= &r420_mc_rreg
;
107 rdev
->mc_wreg
= &r420_mc_wreg
;
109 if (rdev
->family
>= CHIP_RV515
) {
110 rdev
->mc_rreg
= &rv515_mc_rreg
;
111 rdev
->mc_wreg
= &rv515_mc_wreg
;
113 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
114 rdev
->mc_rreg
= &rs400_mc_rreg
;
115 rdev
->mc_wreg
= &rs400_mc_wreg
;
117 if (rdev
->family
== CHIP_RS690
|| rdev
->family
== CHIP_RS740
) {
118 rdev
->mc_rreg
= &rs690_mc_rreg
;
119 rdev
->mc_wreg
= &rs690_mc_wreg
;
121 if (rdev
->family
== CHIP_RS600
) {
122 rdev
->mc_rreg
= &rs600_mc_rreg
;
123 rdev
->mc_wreg
= &rs600_mc_wreg
;
125 if (rdev
->family
>= CHIP_R600
) {
126 rdev
->pciep_rreg
= &r600_pciep_rreg
;
127 rdev
->pciep_wreg
= &r600_pciep_wreg
;
132 /* helper to disable agp */
134 * radeon_agp_disable - AGP disable helper function
136 * @rdev: radeon device pointer
138 * Removes AGP flags and changes the gart callbacks on AGP
139 * cards when using the internal gart rather than AGP (all asics).
141 void radeon_agp_disable(struct radeon_device
*rdev
)
143 rdev
->flags
&= ~RADEON_IS_AGP
;
144 if (rdev
->family
>= CHIP_R600
) {
145 DRM_INFO("Forcing AGP to PCIE mode\n");
146 rdev
->flags
|= RADEON_IS_PCIE
;
147 } else if (rdev
->family
>= CHIP_RV515
||
148 rdev
->family
== CHIP_RV380
||
149 rdev
->family
== CHIP_RV410
||
150 rdev
->family
== CHIP_R423
) {
151 DRM_INFO("Forcing AGP to PCIE mode\n");
152 rdev
->flags
|= RADEON_IS_PCIE
;
153 rdev
->asic
->gart
.tlb_flush
= &rv370_pcie_gart_tlb_flush
;
154 rdev
->asic
->gart
.set_page
= &rv370_pcie_gart_set_page
;
156 DRM_INFO("Forcing AGP to PCI mode\n");
157 rdev
->flags
|= RADEON_IS_PCI
;
158 rdev
->asic
->gart
.tlb_flush
= &r100_pci_gart_tlb_flush
;
159 rdev
->asic
->gart
.set_page
= &r100_pci_gart_set_page
;
161 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
167 static struct radeon_asic r100_asic
= {
170 .suspend
= &r100_suspend
,
171 .resume
= &r100_resume
,
172 .vga_set_state
= &r100_vga_set_state
,
173 .asic_reset
= &r100_asic_reset
,
174 .ioctl_wait_idle
= NULL
,
175 .gui_idle
= &r100_gui_idle
,
176 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
178 .tlb_flush
= &r100_pci_gart_tlb_flush
,
179 .set_page
= &r100_pci_gart_set_page
,
182 [RADEON_RING_TYPE_GFX_INDEX
] = {
183 .ib_execute
= &r100_ring_ib_execute
,
184 .emit_fence
= &r100_fence_ring_emit
,
185 .emit_semaphore
= &r100_semaphore_ring_emit
,
186 .cs_parse
= &r100_cs_parse
,
187 .ring_start
= &r100_ring_start
,
188 .ring_test
= &r100_ring_test
,
189 .ib_test
= &r100_ib_test
,
190 .is_lockup
= &r100_gpu_is_lockup
,
194 .set
= &r100_irq_set
,
195 .process
= &r100_irq_process
,
198 .bandwidth_update
= &r100_bandwidth_update
,
199 .get_vblank_counter
= &r100_get_vblank_counter
,
200 .wait_for_vblank
= &r100_wait_for_vblank
,
201 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
202 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
205 .blit
= &r100_copy_blit
,
206 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
208 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
209 .copy
= &r100_copy_blit
,
210 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
213 .set_reg
= r100_set_surface_reg
,
214 .clear_reg
= r100_clear_surface_reg
,
217 .init
= &r100_hpd_init
,
218 .fini
= &r100_hpd_fini
,
219 .sense
= &r100_hpd_sense
,
220 .set_polarity
= &r100_hpd_set_polarity
,
223 .misc
= &r100_pm_misc
,
224 .prepare
= &r100_pm_prepare
,
225 .finish
= &r100_pm_finish
,
226 .init_profile
= &r100_pm_init_profile
,
227 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
228 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
229 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
230 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
231 .set_memory_clock
= NULL
,
232 .get_pcie_lanes
= NULL
,
233 .set_pcie_lanes
= NULL
,
234 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
237 .pre_page_flip
= &r100_pre_page_flip
,
238 .page_flip
= &r100_page_flip
,
239 .post_page_flip
= &r100_post_page_flip
,
243 static struct radeon_asic r200_asic
= {
246 .suspend
= &r100_suspend
,
247 .resume
= &r100_resume
,
248 .vga_set_state
= &r100_vga_set_state
,
249 .asic_reset
= &r100_asic_reset
,
250 .ioctl_wait_idle
= NULL
,
251 .gui_idle
= &r100_gui_idle
,
252 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
254 .tlb_flush
= &r100_pci_gart_tlb_flush
,
255 .set_page
= &r100_pci_gart_set_page
,
258 [RADEON_RING_TYPE_GFX_INDEX
] = {
259 .ib_execute
= &r100_ring_ib_execute
,
260 .emit_fence
= &r100_fence_ring_emit
,
261 .emit_semaphore
= &r100_semaphore_ring_emit
,
262 .cs_parse
= &r100_cs_parse
,
263 .ring_start
= &r100_ring_start
,
264 .ring_test
= &r100_ring_test
,
265 .ib_test
= &r100_ib_test
,
266 .is_lockup
= &r100_gpu_is_lockup
,
270 .set
= &r100_irq_set
,
271 .process
= &r100_irq_process
,
274 .bandwidth_update
= &r100_bandwidth_update
,
275 .get_vblank_counter
= &r100_get_vblank_counter
,
276 .wait_for_vblank
= &r100_wait_for_vblank
,
277 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
278 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
281 .blit
= &r100_copy_blit
,
282 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
283 .dma
= &r200_copy_dma
,
284 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
285 .copy
= &r100_copy_blit
,
286 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
289 .set_reg
= r100_set_surface_reg
,
290 .clear_reg
= r100_clear_surface_reg
,
293 .init
= &r100_hpd_init
,
294 .fini
= &r100_hpd_fini
,
295 .sense
= &r100_hpd_sense
,
296 .set_polarity
= &r100_hpd_set_polarity
,
299 .misc
= &r100_pm_misc
,
300 .prepare
= &r100_pm_prepare
,
301 .finish
= &r100_pm_finish
,
302 .init_profile
= &r100_pm_init_profile
,
303 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
304 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
305 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
306 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
307 .set_memory_clock
= NULL
,
308 .get_pcie_lanes
= NULL
,
309 .set_pcie_lanes
= NULL
,
310 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
313 .pre_page_flip
= &r100_pre_page_flip
,
314 .page_flip
= &r100_page_flip
,
315 .post_page_flip
= &r100_post_page_flip
,
319 static struct radeon_asic r300_asic
= {
322 .suspend
= &r300_suspend
,
323 .resume
= &r300_resume
,
324 .vga_set_state
= &r100_vga_set_state
,
325 .asic_reset
= &r300_asic_reset
,
326 .ioctl_wait_idle
= NULL
,
327 .gui_idle
= &r100_gui_idle
,
328 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
330 .tlb_flush
= &r100_pci_gart_tlb_flush
,
331 .set_page
= &r100_pci_gart_set_page
,
334 [RADEON_RING_TYPE_GFX_INDEX
] = {
335 .ib_execute
= &r100_ring_ib_execute
,
336 .emit_fence
= &r300_fence_ring_emit
,
337 .emit_semaphore
= &r100_semaphore_ring_emit
,
338 .cs_parse
= &r300_cs_parse
,
339 .ring_start
= &r300_ring_start
,
340 .ring_test
= &r100_ring_test
,
341 .ib_test
= &r100_ib_test
,
342 .is_lockup
= &r100_gpu_is_lockup
,
346 .set
= &r100_irq_set
,
347 .process
= &r100_irq_process
,
350 .bandwidth_update
= &r100_bandwidth_update
,
351 .get_vblank_counter
= &r100_get_vblank_counter
,
352 .wait_for_vblank
= &r100_wait_for_vblank
,
353 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
354 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
357 .blit
= &r100_copy_blit
,
358 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
359 .dma
= &r200_copy_dma
,
360 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
361 .copy
= &r100_copy_blit
,
362 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
365 .set_reg
= r100_set_surface_reg
,
366 .clear_reg
= r100_clear_surface_reg
,
369 .init
= &r100_hpd_init
,
370 .fini
= &r100_hpd_fini
,
371 .sense
= &r100_hpd_sense
,
372 .set_polarity
= &r100_hpd_set_polarity
,
375 .misc
= &r100_pm_misc
,
376 .prepare
= &r100_pm_prepare
,
377 .finish
= &r100_pm_finish
,
378 .init_profile
= &r100_pm_init_profile
,
379 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
380 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
381 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
382 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
383 .set_memory_clock
= NULL
,
384 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
385 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
386 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
389 .pre_page_flip
= &r100_pre_page_flip
,
390 .page_flip
= &r100_page_flip
,
391 .post_page_flip
= &r100_post_page_flip
,
395 static struct radeon_asic r300_asic_pcie
= {
398 .suspend
= &r300_suspend
,
399 .resume
= &r300_resume
,
400 .vga_set_state
= &r100_vga_set_state
,
401 .asic_reset
= &r300_asic_reset
,
402 .ioctl_wait_idle
= NULL
,
403 .gui_idle
= &r100_gui_idle
,
404 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
406 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
407 .set_page
= &rv370_pcie_gart_set_page
,
410 [RADEON_RING_TYPE_GFX_INDEX
] = {
411 .ib_execute
= &r100_ring_ib_execute
,
412 .emit_fence
= &r300_fence_ring_emit
,
413 .emit_semaphore
= &r100_semaphore_ring_emit
,
414 .cs_parse
= &r300_cs_parse
,
415 .ring_start
= &r300_ring_start
,
416 .ring_test
= &r100_ring_test
,
417 .ib_test
= &r100_ib_test
,
418 .is_lockup
= &r100_gpu_is_lockup
,
422 .set
= &r100_irq_set
,
423 .process
= &r100_irq_process
,
426 .bandwidth_update
= &r100_bandwidth_update
,
427 .get_vblank_counter
= &r100_get_vblank_counter
,
428 .wait_for_vblank
= &r100_wait_for_vblank
,
429 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
430 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
433 .blit
= &r100_copy_blit
,
434 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
435 .dma
= &r200_copy_dma
,
436 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
437 .copy
= &r100_copy_blit
,
438 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
441 .set_reg
= r100_set_surface_reg
,
442 .clear_reg
= r100_clear_surface_reg
,
445 .init
= &r100_hpd_init
,
446 .fini
= &r100_hpd_fini
,
447 .sense
= &r100_hpd_sense
,
448 .set_polarity
= &r100_hpd_set_polarity
,
451 .misc
= &r100_pm_misc
,
452 .prepare
= &r100_pm_prepare
,
453 .finish
= &r100_pm_finish
,
454 .init_profile
= &r100_pm_init_profile
,
455 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
456 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
457 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
458 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
459 .set_memory_clock
= NULL
,
460 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
461 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
462 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
465 .pre_page_flip
= &r100_pre_page_flip
,
466 .page_flip
= &r100_page_flip
,
467 .post_page_flip
= &r100_post_page_flip
,
471 static struct radeon_asic r420_asic
= {
474 .suspend
= &r420_suspend
,
475 .resume
= &r420_resume
,
476 .vga_set_state
= &r100_vga_set_state
,
477 .asic_reset
= &r300_asic_reset
,
478 .ioctl_wait_idle
= NULL
,
479 .gui_idle
= &r100_gui_idle
,
480 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
482 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
483 .set_page
= &rv370_pcie_gart_set_page
,
486 [RADEON_RING_TYPE_GFX_INDEX
] = {
487 .ib_execute
= &r100_ring_ib_execute
,
488 .emit_fence
= &r300_fence_ring_emit
,
489 .emit_semaphore
= &r100_semaphore_ring_emit
,
490 .cs_parse
= &r300_cs_parse
,
491 .ring_start
= &r300_ring_start
,
492 .ring_test
= &r100_ring_test
,
493 .ib_test
= &r100_ib_test
,
494 .is_lockup
= &r100_gpu_is_lockup
,
498 .set
= &r100_irq_set
,
499 .process
= &r100_irq_process
,
502 .bandwidth_update
= &r100_bandwidth_update
,
503 .get_vblank_counter
= &r100_get_vblank_counter
,
504 .wait_for_vblank
= &r100_wait_for_vblank
,
505 .set_backlight_level
= &atombios_set_backlight_level
,
506 .get_backlight_level
= &atombios_get_backlight_level
,
509 .blit
= &r100_copy_blit
,
510 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
511 .dma
= &r200_copy_dma
,
512 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
513 .copy
= &r100_copy_blit
,
514 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
517 .set_reg
= r100_set_surface_reg
,
518 .clear_reg
= r100_clear_surface_reg
,
521 .init
= &r100_hpd_init
,
522 .fini
= &r100_hpd_fini
,
523 .sense
= &r100_hpd_sense
,
524 .set_polarity
= &r100_hpd_set_polarity
,
527 .misc
= &r100_pm_misc
,
528 .prepare
= &r100_pm_prepare
,
529 .finish
= &r100_pm_finish
,
530 .init_profile
= &r420_pm_init_profile
,
531 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
532 .get_engine_clock
= &radeon_atom_get_engine_clock
,
533 .set_engine_clock
= &radeon_atom_set_engine_clock
,
534 .get_memory_clock
= &radeon_atom_get_memory_clock
,
535 .set_memory_clock
= &radeon_atom_set_memory_clock
,
536 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
537 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
538 .set_clock_gating
= &radeon_atom_set_clock_gating
,
541 .pre_page_flip
= &r100_pre_page_flip
,
542 .page_flip
= &r100_page_flip
,
543 .post_page_flip
= &r100_post_page_flip
,
547 static struct radeon_asic rs400_asic
= {
550 .suspend
= &rs400_suspend
,
551 .resume
= &rs400_resume
,
552 .vga_set_state
= &r100_vga_set_state
,
553 .asic_reset
= &r300_asic_reset
,
554 .ioctl_wait_idle
= NULL
,
555 .gui_idle
= &r100_gui_idle
,
556 .mc_wait_for_idle
= &rs400_mc_wait_for_idle
,
558 .tlb_flush
= &rs400_gart_tlb_flush
,
559 .set_page
= &rs400_gart_set_page
,
562 [RADEON_RING_TYPE_GFX_INDEX
] = {
563 .ib_execute
= &r100_ring_ib_execute
,
564 .emit_fence
= &r300_fence_ring_emit
,
565 .emit_semaphore
= &r100_semaphore_ring_emit
,
566 .cs_parse
= &r300_cs_parse
,
567 .ring_start
= &r300_ring_start
,
568 .ring_test
= &r100_ring_test
,
569 .ib_test
= &r100_ib_test
,
570 .is_lockup
= &r100_gpu_is_lockup
,
574 .set
= &r100_irq_set
,
575 .process
= &r100_irq_process
,
578 .bandwidth_update
= &r100_bandwidth_update
,
579 .get_vblank_counter
= &r100_get_vblank_counter
,
580 .wait_for_vblank
= &r100_wait_for_vblank
,
581 .set_backlight_level
= &radeon_legacy_set_backlight_level
,
582 .get_backlight_level
= &radeon_legacy_get_backlight_level
,
585 .blit
= &r100_copy_blit
,
586 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
587 .dma
= &r200_copy_dma
,
588 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
589 .copy
= &r100_copy_blit
,
590 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
593 .set_reg
= r100_set_surface_reg
,
594 .clear_reg
= r100_clear_surface_reg
,
597 .init
= &r100_hpd_init
,
598 .fini
= &r100_hpd_fini
,
599 .sense
= &r100_hpd_sense
,
600 .set_polarity
= &r100_hpd_set_polarity
,
603 .misc
= &r100_pm_misc
,
604 .prepare
= &r100_pm_prepare
,
605 .finish
= &r100_pm_finish
,
606 .init_profile
= &r100_pm_init_profile
,
607 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
608 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
609 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
610 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
611 .set_memory_clock
= NULL
,
612 .get_pcie_lanes
= NULL
,
613 .set_pcie_lanes
= NULL
,
614 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
617 .pre_page_flip
= &r100_pre_page_flip
,
618 .page_flip
= &r100_page_flip
,
619 .post_page_flip
= &r100_post_page_flip
,
623 static struct radeon_asic rs600_asic
= {
626 .suspend
= &rs600_suspend
,
627 .resume
= &rs600_resume
,
628 .vga_set_state
= &r100_vga_set_state
,
629 .asic_reset
= &rs600_asic_reset
,
630 .ioctl_wait_idle
= NULL
,
631 .gui_idle
= &r100_gui_idle
,
632 .mc_wait_for_idle
= &rs600_mc_wait_for_idle
,
634 .tlb_flush
= &rs600_gart_tlb_flush
,
635 .set_page
= &rs600_gart_set_page
,
638 [RADEON_RING_TYPE_GFX_INDEX
] = {
639 .ib_execute
= &r100_ring_ib_execute
,
640 .emit_fence
= &r300_fence_ring_emit
,
641 .emit_semaphore
= &r100_semaphore_ring_emit
,
642 .cs_parse
= &r300_cs_parse
,
643 .ring_start
= &r300_ring_start
,
644 .ring_test
= &r100_ring_test
,
645 .ib_test
= &r100_ib_test
,
646 .is_lockup
= &r100_gpu_is_lockup
,
650 .set
= &rs600_irq_set
,
651 .process
= &rs600_irq_process
,
654 .bandwidth_update
= &rs600_bandwidth_update
,
655 .get_vblank_counter
= &rs600_get_vblank_counter
,
656 .wait_for_vblank
= &avivo_wait_for_vblank
,
657 .set_backlight_level
= &atombios_set_backlight_level
,
658 .get_backlight_level
= &atombios_get_backlight_level
,
661 .blit
= &r100_copy_blit
,
662 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
663 .dma
= &r200_copy_dma
,
664 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
665 .copy
= &r100_copy_blit
,
666 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
669 .set_reg
= r100_set_surface_reg
,
670 .clear_reg
= r100_clear_surface_reg
,
673 .init
= &rs600_hpd_init
,
674 .fini
= &rs600_hpd_fini
,
675 .sense
= &rs600_hpd_sense
,
676 .set_polarity
= &rs600_hpd_set_polarity
,
679 .misc
= &rs600_pm_misc
,
680 .prepare
= &rs600_pm_prepare
,
681 .finish
= &rs600_pm_finish
,
682 .init_profile
= &r420_pm_init_profile
,
683 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
684 .get_engine_clock
= &radeon_atom_get_engine_clock
,
685 .set_engine_clock
= &radeon_atom_set_engine_clock
,
686 .get_memory_clock
= &radeon_atom_get_memory_clock
,
687 .set_memory_clock
= &radeon_atom_set_memory_clock
,
688 .get_pcie_lanes
= NULL
,
689 .set_pcie_lanes
= NULL
,
690 .set_clock_gating
= &radeon_atom_set_clock_gating
,
693 .pre_page_flip
= &rs600_pre_page_flip
,
694 .page_flip
= &rs600_page_flip
,
695 .post_page_flip
= &rs600_post_page_flip
,
699 static struct radeon_asic rs690_asic
= {
702 .suspend
= &rs690_suspend
,
703 .resume
= &rs690_resume
,
704 .vga_set_state
= &r100_vga_set_state
,
705 .asic_reset
= &rs600_asic_reset
,
706 .ioctl_wait_idle
= NULL
,
707 .gui_idle
= &r100_gui_idle
,
708 .mc_wait_for_idle
= &rs690_mc_wait_for_idle
,
710 .tlb_flush
= &rs400_gart_tlb_flush
,
711 .set_page
= &rs400_gart_set_page
,
714 [RADEON_RING_TYPE_GFX_INDEX
] = {
715 .ib_execute
= &r100_ring_ib_execute
,
716 .emit_fence
= &r300_fence_ring_emit
,
717 .emit_semaphore
= &r100_semaphore_ring_emit
,
718 .cs_parse
= &r300_cs_parse
,
719 .ring_start
= &r300_ring_start
,
720 .ring_test
= &r100_ring_test
,
721 .ib_test
= &r100_ib_test
,
722 .is_lockup
= &r100_gpu_is_lockup
,
726 .set
= &rs600_irq_set
,
727 .process
= &rs600_irq_process
,
730 .get_vblank_counter
= &rs600_get_vblank_counter
,
731 .bandwidth_update
= &rs690_bandwidth_update
,
732 .wait_for_vblank
= &avivo_wait_for_vblank
,
733 .set_backlight_level
= &atombios_set_backlight_level
,
734 .get_backlight_level
= &atombios_get_backlight_level
,
737 .blit
= &r100_copy_blit
,
738 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
739 .dma
= &r200_copy_dma
,
740 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
741 .copy
= &r200_copy_dma
,
742 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
745 .set_reg
= r100_set_surface_reg
,
746 .clear_reg
= r100_clear_surface_reg
,
749 .init
= &rs600_hpd_init
,
750 .fini
= &rs600_hpd_fini
,
751 .sense
= &rs600_hpd_sense
,
752 .set_polarity
= &rs600_hpd_set_polarity
,
755 .misc
= &rs600_pm_misc
,
756 .prepare
= &rs600_pm_prepare
,
757 .finish
= &rs600_pm_finish
,
758 .init_profile
= &r420_pm_init_profile
,
759 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
760 .get_engine_clock
= &radeon_atom_get_engine_clock
,
761 .set_engine_clock
= &radeon_atom_set_engine_clock
,
762 .get_memory_clock
= &radeon_atom_get_memory_clock
,
763 .set_memory_clock
= &radeon_atom_set_memory_clock
,
764 .get_pcie_lanes
= NULL
,
765 .set_pcie_lanes
= NULL
,
766 .set_clock_gating
= &radeon_atom_set_clock_gating
,
769 .pre_page_flip
= &rs600_pre_page_flip
,
770 .page_flip
= &rs600_page_flip
,
771 .post_page_flip
= &rs600_post_page_flip
,
775 static struct radeon_asic rv515_asic
= {
778 .suspend
= &rv515_suspend
,
779 .resume
= &rv515_resume
,
780 .vga_set_state
= &r100_vga_set_state
,
781 .asic_reset
= &rs600_asic_reset
,
782 .ioctl_wait_idle
= NULL
,
783 .gui_idle
= &r100_gui_idle
,
784 .mc_wait_for_idle
= &rv515_mc_wait_for_idle
,
786 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
787 .set_page
= &rv370_pcie_gart_set_page
,
790 [RADEON_RING_TYPE_GFX_INDEX
] = {
791 .ib_execute
= &r100_ring_ib_execute
,
792 .emit_fence
= &r300_fence_ring_emit
,
793 .emit_semaphore
= &r100_semaphore_ring_emit
,
794 .cs_parse
= &r300_cs_parse
,
795 .ring_start
= &rv515_ring_start
,
796 .ring_test
= &r100_ring_test
,
797 .ib_test
= &r100_ib_test
,
798 .is_lockup
= &r100_gpu_is_lockup
,
802 .set
= &rs600_irq_set
,
803 .process
= &rs600_irq_process
,
806 .get_vblank_counter
= &rs600_get_vblank_counter
,
807 .bandwidth_update
= &rv515_bandwidth_update
,
808 .wait_for_vblank
= &avivo_wait_for_vblank
,
809 .set_backlight_level
= &atombios_set_backlight_level
,
810 .get_backlight_level
= &atombios_get_backlight_level
,
813 .blit
= &r100_copy_blit
,
814 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
815 .dma
= &r200_copy_dma
,
816 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
817 .copy
= &r100_copy_blit
,
818 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
821 .set_reg
= r100_set_surface_reg
,
822 .clear_reg
= r100_clear_surface_reg
,
825 .init
= &rs600_hpd_init
,
826 .fini
= &rs600_hpd_fini
,
827 .sense
= &rs600_hpd_sense
,
828 .set_polarity
= &rs600_hpd_set_polarity
,
831 .misc
= &rs600_pm_misc
,
832 .prepare
= &rs600_pm_prepare
,
833 .finish
= &rs600_pm_finish
,
834 .init_profile
= &r420_pm_init_profile
,
835 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
836 .get_engine_clock
= &radeon_atom_get_engine_clock
,
837 .set_engine_clock
= &radeon_atom_set_engine_clock
,
838 .get_memory_clock
= &radeon_atom_get_memory_clock
,
839 .set_memory_clock
= &radeon_atom_set_memory_clock
,
840 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
841 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
842 .set_clock_gating
= &radeon_atom_set_clock_gating
,
845 .pre_page_flip
= &rs600_pre_page_flip
,
846 .page_flip
= &rs600_page_flip
,
847 .post_page_flip
= &rs600_post_page_flip
,
851 static struct radeon_asic r520_asic
= {
854 .suspend
= &rv515_suspend
,
855 .resume
= &r520_resume
,
856 .vga_set_state
= &r100_vga_set_state
,
857 .asic_reset
= &rs600_asic_reset
,
858 .ioctl_wait_idle
= NULL
,
859 .gui_idle
= &r100_gui_idle
,
860 .mc_wait_for_idle
= &r520_mc_wait_for_idle
,
862 .tlb_flush
= &rv370_pcie_gart_tlb_flush
,
863 .set_page
= &rv370_pcie_gart_set_page
,
866 [RADEON_RING_TYPE_GFX_INDEX
] = {
867 .ib_execute
= &r100_ring_ib_execute
,
868 .emit_fence
= &r300_fence_ring_emit
,
869 .emit_semaphore
= &r100_semaphore_ring_emit
,
870 .cs_parse
= &r300_cs_parse
,
871 .ring_start
= &rv515_ring_start
,
872 .ring_test
= &r100_ring_test
,
873 .ib_test
= &r100_ib_test
,
874 .is_lockup
= &r100_gpu_is_lockup
,
878 .set
= &rs600_irq_set
,
879 .process
= &rs600_irq_process
,
882 .bandwidth_update
= &rv515_bandwidth_update
,
883 .get_vblank_counter
= &rs600_get_vblank_counter
,
884 .wait_for_vblank
= &avivo_wait_for_vblank
,
885 .set_backlight_level
= &atombios_set_backlight_level
,
886 .get_backlight_level
= &atombios_get_backlight_level
,
889 .blit
= &r100_copy_blit
,
890 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
891 .dma
= &r200_copy_dma
,
892 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
893 .copy
= &r100_copy_blit
,
894 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
897 .set_reg
= r100_set_surface_reg
,
898 .clear_reg
= r100_clear_surface_reg
,
901 .init
= &rs600_hpd_init
,
902 .fini
= &rs600_hpd_fini
,
903 .sense
= &rs600_hpd_sense
,
904 .set_polarity
= &rs600_hpd_set_polarity
,
907 .misc
= &rs600_pm_misc
,
908 .prepare
= &rs600_pm_prepare
,
909 .finish
= &rs600_pm_finish
,
910 .init_profile
= &r420_pm_init_profile
,
911 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
912 .get_engine_clock
= &radeon_atom_get_engine_clock
,
913 .set_engine_clock
= &radeon_atom_set_engine_clock
,
914 .get_memory_clock
= &radeon_atom_get_memory_clock
,
915 .set_memory_clock
= &radeon_atom_set_memory_clock
,
916 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
917 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
918 .set_clock_gating
= &radeon_atom_set_clock_gating
,
921 .pre_page_flip
= &rs600_pre_page_flip
,
922 .page_flip
= &rs600_page_flip
,
923 .post_page_flip
= &rs600_post_page_flip
,
927 static struct radeon_asic r600_asic
= {
930 .suspend
= &r600_suspend
,
931 .resume
= &r600_resume
,
932 .vga_set_state
= &r600_vga_set_state
,
933 .asic_reset
= &r600_asic_reset
,
934 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
935 .gui_idle
= &r600_gui_idle
,
936 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
937 .get_xclk
= &r600_get_xclk
,
938 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
940 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
941 .set_page
= &rs600_gart_set_page
,
944 [RADEON_RING_TYPE_GFX_INDEX
] = {
945 .ib_execute
= &r600_ring_ib_execute
,
946 .emit_fence
= &r600_fence_ring_emit
,
947 .emit_semaphore
= &r600_semaphore_ring_emit
,
948 .cs_parse
= &r600_cs_parse
,
949 .ring_test
= &r600_ring_test
,
950 .ib_test
= &r600_ib_test
,
951 .is_lockup
= &r600_gfx_is_lockup
,
953 [R600_RING_TYPE_DMA_INDEX
] = {
954 .ib_execute
= &r600_dma_ring_ib_execute
,
955 .emit_fence
= &r600_dma_fence_ring_emit
,
956 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
957 .cs_parse
= &r600_dma_cs_parse
,
958 .ring_test
= &r600_dma_ring_test
,
959 .ib_test
= &r600_dma_ib_test
,
960 .is_lockup
= &r600_dma_is_lockup
,
964 .set
= &r600_irq_set
,
965 .process
= &r600_irq_process
,
968 .bandwidth_update
= &rv515_bandwidth_update
,
969 .get_vblank_counter
= &rs600_get_vblank_counter
,
970 .wait_for_vblank
= &avivo_wait_for_vblank
,
971 .set_backlight_level
= &atombios_set_backlight_level
,
972 .get_backlight_level
= &atombios_get_backlight_level
,
975 .blit
= &r600_copy_blit
,
976 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
977 .dma
= &r600_copy_dma
,
978 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
979 .copy
= &r600_copy_dma
,
980 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
983 .set_reg
= r600_set_surface_reg
,
984 .clear_reg
= r600_clear_surface_reg
,
987 .init
= &r600_hpd_init
,
988 .fini
= &r600_hpd_fini
,
989 .sense
= &r600_hpd_sense
,
990 .set_polarity
= &r600_hpd_set_polarity
,
993 .misc
= &r600_pm_misc
,
994 .prepare
= &rs600_pm_prepare
,
995 .finish
= &rs600_pm_finish
,
996 .init_profile
= &r600_pm_init_profile
,
997 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
998 .get_engine_clock
= &radeon_atom_get_engine_clock
,
999 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1000 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1001 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1002 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1003 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1004 .set_clock_gating
= NULL
,
1007 .pre_page_flip
= &rs600_pre_page_flip
,
1008 .page_flip
= &rs600_page_flip
,
1009 .post_page_flip
= &rs600_post_page_flip
,
1013 static struct radeon_asic rs780_asic
= {
1016 .suspend
= &r600_suspend
,
1017 .resume
= &r600_resume
,
1018 .vga_set_state
= &r600_vga_set_state
,
1019 .asic_reset
= &r600_asic_reset
,
1020 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1021 .gui_idle
= &r600_gui_idle
,
1022 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1023 .get_xclk
= &r600_get_xclk
,
1024 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1026 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1027 .set_page
= &rs600_gart_set_page
,
1030 [RADEON_RING_TYPE_GFX_INDEX
] = {
1031 .ib_execute
= &r600_ring_ib_execute
,
1032 .emit_fence
= &r600_fence_ring_emit
,
1033 .emit_semaphore
= &r600_semaphore_ring_emit
,
1034 .cs_parse
= &r600_cs_parse
,
1035 .ring_test
= &r600_ring_test
,
1036 .ib_test
= &r600_ib_test
,
1037 .is_lockup
= &r600_gfx_is_lockup
,
1039 [R600_RING_TYPE_DMA_INDEX
] = {
1040 .ib_execute
= &r600_dma_ring_ib_execute
,
1041 .emit_fence
= &r600_dma_fence_ring_emit
,
1042 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1043 .cs_parse
= &r600_dma_cs_parse
,
1044 .ring_test
= &r600_dma_ring_test
,
1045 .ib_test
= &r600_dma_ib_test
,
1046 .is_lockup
= &r600_dma_is_lockup
,
1050 .set
= &r600_irq_set
,
1051 .process
= &r600_irq_process
,
1054 .bandwidth_update
= &rs690_bandwidth_update
,
1055 .get_vblank_counter
= &rs600_get_vblank_counter
,
1056 .wait_for_vblank
= &avivo_wait_for_vblank
,
1057 .set_backlight_level
= &atombios_set_backlight_level
,
1058 .get_backlight_level
= &atombios_get_backlight_level
,
1061 .blit
= &r600_copy_blit
,
1062 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1063 .dma
= &r600_copy_dma
,
1064 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1065 .copy
= &r600_copy_dma
,
1066 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1069 .set_reg
= r600_set_surface_reg
,
1070 .clear_reg
= r600_clear_surface_reg
,
1073 .init
= &r600_hpd_init
,
1074 .fini
= &r600_hpd_fini
,
1075 .sense
= &r600_hpd_sense
,
1076 .set_polarity
= &r600_hpd_set_polarity
,
1079 .misc
= &r600_pm_misc
,
1080 .prepare
= &rs600_pm_prepare
,
1081 .finish
= &rs600_pm_finish
,
1082 .init_profile
= &rs780_pm_init_profile
,
1083 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1084 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1085 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1086 .get_memory_clock
= NULL
,
1087 .set_memory_clock
= NULL
,
1088 .get_pcie_lanes
= NULL
,
1089 .set_pcie_lanes
= NULL
,
1090 .set_clock_gating
= NULL
,
1093 .pre_page_flip
= &rs600_pre_page_flip
,
1094 .page_flip
= &rs600_page_flip
,
1095 .post_page_flip
= &rs600_post_page_flip
,
1099 static struct radeon_asic rv770_asic
= {
1100 .init
= &rv770_init
,
1101 .fini
= &rv770_fini
,
1102 .suspend
= &rv770_suspend
,
1103 .resume
= &rv770_resume
,
1104 .asic_reset
= &r600_asic_reset
,
1105 .vga_set_state
= &r600_vga_set_state
,
1106 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1107 .gui_idle
= &r600_gui_idle
,
1108 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
1109 .get_xclk
= &rv770_get_xclk
,
1110 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1112 .tlb_flush
= &r600_pcie_gart_tlb_flush
,
1113 .set_page
= &rs600_gart_set_page
,
1116 [RADEON_RING_TYPE_GFX_INDEX
] = {
1117 .ib_execute
= &r600_ring_ib_execute
,
1118 .emit_fence
= &r600_fence_ring_emit
,
1119 .emit_semaphore
= &r600_semaphore_ring_emit
,
1120 .cs_parse
= &r600_cs_parse
,
1121 .ring_test
= &r600_ring_test
,
1122 .ib_test
= &r600_ib_test
,
1123 .is_lockup
= &r600_gfx_is_lockup
,
1125 [R600_RING_TYPE_DMA_INDEX
] = {
1126 .ib_execute
= &r600_dma_ring_ib_execute
,
1127 .emit_fence
= &r600_dma_fence_ring_emit
,
1128 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1129 .cs_parse
= &r600_dma_cs_parse
,
1130 .ring_test
= &r600_dma_ring_test
,
1131 .ib_test
= &r600_dma_ib_test
,
1132 .is_lockup
= &r600_dma_is_lockup
,
1134 [R600_RING_TYPE_UVD_INDEX
] = {
1135 .ib_execute
= &r600_uvd_ib_execute
,
1136 .emit_fence
= &r600_uvd_fence_emit
,
1137 .emit_semaphore
= &r600_uvd_semaphore_emit
,
1138 .cs_parse
= &radeon_uvd_cs_parse
,
1139 .ring_test
= &r600_uvd_ring_test
,
1140 .ib_test
= &r600_uvd_ib_test
,
1141 .is_lockup
= &radeon_ring_test_lockup
,
1145 .set
= &r600_irq_set
,
1146 .process
= &r600_irq_process
,
1149 .bandwidth_update
= &rv515_bandwidth_update
,
1150 .get_vblank_counter
= &rs600_get_vblank_counter
,
1151 .wait_for_vblank
= &avivo_wait_for_vblank
,
1152 .set_backlight_level
= &atombios_set_backlight_level
,
1153 .get_backlight_level
= &atombios_get_backlight_level
,
1156 .blit
= &r600_copy_blit
,
1157 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1158 .dma
= &rv770_copy_dma
,
1159 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1160 .copy
= &rv770_copy_dma
,
1161 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1164 .set_reg
= r600_set_surface_reg
,
1165 .clear_reg
= r600_clear_surface_reg
,
1168 .init
= &r600_hpd_init
,
1169 .fini
= &r600_hpd_fini
,
1170 .sense
= &r600_hpd_sense
,
1171 .set_polarity
= &r600_hpd_set_polarity
,
1174 .misc
= &rv770_pm_misc
,
1175 .prepare
= &rs600_pm_prepare
,
1176 .finish
= &rs600_pm_finish
,
1177 .init_profile
= &r600_pm_init_profile
,
1178 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1179 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1180 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1181 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1182 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1183 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1184 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1185 .set_clock_gating
= &radeon_atom_set_clock_gating
,
1188 .pre_page_flip
= &rs600_pre_page_flip
,
1189 .page_flip
= &rv770_page_flip
,
1190 .post_page_flip
= &rs600_post_page_flip
,
1194 static struct radeon_asic evergreen_asic
= {
1195 .init
= &evergreen_init
,
1196 .fini
= &evergreen_fini
,
1197 .suspend
= &evergreen_suspend
,
1198 .resume
= &evergreen_resume
,
1199 .asic_reset
= &evergreen_asic_reset
,
1200 .vga_set_state
= &r600_vga_set_state
,
1201 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1202 .gui_idle
= &r600_gui_idle
,
1203 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1204 .get_xclk
= &rv770_get_xclk
,
1205 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1207 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1208 .set_page
= &rs600_gart_set_page
,
1211 [RADEON_RING_TYPE_GFX_INDEX
] = {
1212 .ib_execute
= &evergreen_ring_ib_execute
,
1213 .emit_fence
= &r600_fence_ring_emit
,
1214 .emit_semaphore
= &r600_semaphore_ring_emit
,
1215 .cs_parse
= &evergreen_cs_parse
,
1216 .ring_test
= &r600_ring_test
,
1217 .ib_test
= &r600_ib_test
,
1218 .is_lockup
= &evergreen_gfx_is_lockup
,
1220 [R600_RING_TYPE_DMA_INDEX
] = {
1221 .ib_execute
= &evergreen_dma_ring_ib_execute
,
1222 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1223 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1224 .cs_parse
= &evergreen_dma_cs_parse
,
1225 .ring_test
= &r600_dma_ring_test
,
1226 .ib_test
= &r600_dma_ib_test
,
1227 .is_lockup
= &evergreen_dma_is_lockup
,
1229 [R600_RING_TYPE_UVD_INDEX
] = {
1230 .ib_execute
= &r600_uvd_ib_execute
,
1231 .emit_fence
= &r600_uvd_fence_emit
,
1232 .emit_semaphore
= &r600_uvd_semaphore_emit
,
1233 .cs_parse
= &radeon_uvd_cs_parse
,
1234 .ring_test
= &r600_uvd_ring_test
,
1235 .ib_test
= &r600_uvd_ib_test
,
1236 .is_lockup
= &radeon_ring_test_lockup
,
1240 .set
= &evergreen_irq_set
,
1241 .process
= &evergreen_irq_process
,
1244 .bandwidth_update
= &evergreen_bandwidth_update
,
1245 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1246 .wait_for_vblank
= &dce4_wait_for_vblank
,
1247 .set_backlight_level
= &atombios_set_backlight_level
,
1248 .get_backlight_level
= &atombios_get_backlight_level
,
1251 .blit
= &r600_copy_blit
,
1252 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1253 .dma
= &evergreen_copy_dma
,
1254 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1255 .copy
= &evergreen_copy_dma
,
1256 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1259 .set_reg
= r600_set_surface_reg
,
1260 .clear_reg
= r600_clear_surface_reg
,
1263 .init
= &evergreen_hpd_init
,
1264 .fini
= &evergreen_hpd_fini
,
1265 .sense
= &evergreen_hpd_sense
,
1266 .set_polarity
= &evergreen_hpd_set_polarity
,
1269 .misc
= &evergreen_pm_misc
,
1270 .prepare
= &evergreen_pm_prepare
,
1271 .finish
= &evergreen_pm_finish
,
1272 .init_profile
= &r600_pm_init_profile
,
1273 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1274 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1275 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1276 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1277 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1278 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1279 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1280 .set_clock_gating
= NULL
,
1283 .pre_page_flip
= &evergreen_pre_page_flip
,
1284 .page_flip
= &evergreen_page_flip
,
1285 .post_page_flip
= &evergreen_post_page_flip
,
1289 static struct radeon_asic sumo_asic
= {
1290 .init
= &evergreen_init
,
1291 .fini
= &evergreen_fini
,
1292 .suspend
= &evergreen_suspend
,
1293 .resume
= &evergreen_resume
,
1294 .asic_reset
= &evergreen_asic_reset
,
1295 .vga_set_state
= &r600_vga_set_state
,
1296 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1297 .gui_idle
= &r600_gui_idle
,
1298 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1299 .get_xclk
= &r600_get_xclk
,
1300 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1302 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1303 .set_page
= &rs600_gart_set_page
,
1306 [RADEON_RING_TYPE_GFX_INDEX
] = {
1307 .ib_execute
= &evergreen_ring_ib_execute
,
1308 .emit_fence
= &r600_fence_ring_emit
,
1309 .emit_semaphore
= &r600_semaphore_ring_emit
,
1310 .cs_parse
= &evergreen_cs_parse
,
1311 .ring_test
= &r600_ring_test
,
1312 .ib_test
= &r600_ib_test
,
1313 .is_lockup
= &evergreen_gfx_is_lockup
,
1315 [R600_RING_TYPE_DMA_INDEX
] = {
1316 .ib_execute
= &evergreen_dma_ring_ib_execute
,
1317 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1318 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1319 .cs_parse
= &evergreen_dma_cs_parse
,
1320 .ring_test
= &r600_dma_ring_test
,
1321 .ib_test
= &r600_dma_ib_test
,
1322 .is_lockup
= &evergreen_dma_is_lockup
,
1324 [R600_RING_TYPE_UVD_INDEX
] = {
1325 .ib_execute
= &r600_uvd_ib_execute
,
1326 .emit_fence
= &r600_uvd_fence_emit
,
1327 .emit_semaphore
= &r600_uvd_semaphore_emit
,
1328 .cs_parse
= &radeon_uvd_cs_parse
,
1329 .ring_test
= &r600_uvd_ring_test
,
1330 .ib_test
= &r600_uvd_ib_test
,
1331 .is_lockup
= &radeon_ring_test_lockup
,
1335 .set
= &evergreen_irq_set
,
1336 .process
= &evergreen_irq_process
,
1339 .bandwidth_update
= &evergreen_bandwidth_update
,
1340 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1341 .wait_for_vblank
= &dce4_wait_for_vblank
,
1342 .set_backlight_level
= &atombios_set_backlight_level
,
1343 .get_backlight_level
= &atombios_get_backlight_level
,
1346 .blit
= &r600_copy_blit
,
1347 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1348 .dma
= &evergreen_copy_dma
,
1349 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1350 .copy
= &evergreen_copy_dma
,
1351 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1354 .set_reg
= r600_set_surface_reg
,
1355 .clear_reg
= r600_clear_surface_reg
,
1358 .init
= &evergreen_hpd_init
,
1359 .fini
= &evergreen_hpd_fini
,
1360 .sense
= &evergreen_hpd_sense
,
1361 .set_polarity
= &evergreen_hpd_set_polarity
,
1364 .misc
= &evergreen_pm_misc
,
1365 .prepare
= &evergreen_pm_prepare
,
1366 .finish
= &evergreen_pm_finish
,
1367 .init_profile
= &sumo_pm_init_profile
,
1368 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1369 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1370 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1371 .get_memory_clock
= NULL
,
1372 .set_memory_clock
= NULL
,
1373 .get_pcie_lanes
= NULL
,
1374 .set_pcie_lanes
= NULL
,
1375 .set_clock_gating
= NULL
,
1378 .pre_page_flip
= &evergreen_pre_page_flip
,
1379 .page_flip
= &evergreen_page_flip
,
1380 .post_page_flip
= &evergreen_post_page_flip
,
1384 static struct radeon_asic btc_asic
= {
1385 .init
= &evergreen_init
,
1386 .fini
= &evergreen_fini
,
1387 .suspend
= &evergreen_suspend
,
1388 .resume
= &evergreen_resume
,
1389 .asic_reset
= &evergreen_asic_reset
,
1390 .vga_set_state
= &r600_vga_set_state
,
1391 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1392 .gui_idle
= &r600_gui_idle
,
1393 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1394 .get_xclk
= &rv770_get_xclk
,
1395 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1397 .tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1398 .set_page
= &rs600_gart_set_page
,
1401 [RADEON_RING_TYPE_GFX_INDEX
] = {
1402 .ib_execute
= &evergreen_ring_ib_execute
,
1403 .emit_fence
= &r600_fence_ring_emit
,
1404 .emit_semaphore
= &r600_semaphore_ring_emit
,
1405 .cs_parse
= &evergreen_cs_parse
,
1406 .ring_test
= &r600_ring_test
,
1407 .ib_test
= &r600_ib_test
,
1408 .is_lockup
= &evergreen_gfx_is_lockup
,
1410 [R600_RING_TYPE_DMA_INDEX
] = {
1411 .ib_execute
= &evergreen_dma_ring_ib_execute
,
1412 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1413 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1414 .cs_parse
= &evergreen_dma_cs_parse
,
1415 .ring_test
= &r600_dma_ring_test
,
1416 .ib_test
= &r600_dma_ib_test
,
1417 .is_lockup
= &evergreen_dma_is_lockup
,
1419 [R600_RING_TYPE_UVD_INDEX
] = {
1420 .ib_execute
= &r600_uvd_ib_execute
,
1421 .emit_fence
= &r600_uvd_fence_emit
,
1422 .emit_semaphore
= &r600_uvd_semaphore_emit
,
1423 .cs_parse
= &radeon_uvd_cs_parse
,
1424 .ring_test
= &r600_uvd_ring_test
,
1425 .ib_test
= &r600_uvd_ib_test
,
1426 .is_lockup
= &radeon_ring_test_lockup
,
1430 .set
= &evergreen_irq_set
,
1431 .process
= &evergreen_irq_process
,
1434 .bandwidth_update
= &evergreen_bandwidth_update
,
1435 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1436 .wait_for_vblank
= &dce4_wait_for_vblank
,
1437 .set_backlight_level
= &atombios_set_backlight_level
,
1438 .get_backlight_level
= &atombios_get_backlight_level
,
1441 .blit
= &r600_copy_blit
,
1442 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1443 .dma
= &evergreen_copy_dma
,
1444 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1445 .copy
= &evergreen_copy_dma
,
1446 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1449 .set_reg
= r600_set_surface_reg
,
1450 .clear_reg
= r600_clear_surface_reg
,
1453 .init
= &evergreen_hpd_init
,
1454 .fini
= &evergreen_hpd_fini
,
1455 .sense
= &evergreen_hpd_sense
,
1456 .set_polarity
= &evergreen_hpd_set_polarity
,
1459 .misc
= &evergreen_pm_misc
,
1460 .prepare
= &evergreen_pm_prepare
,
1461 .finish
= &evergreen_pm_finish
,
1462 .init_profile
= &btc_pm_init_profile
,
1463 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1464 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1465 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1466 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1467 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1468 .get_pcie_lanes
= NULL
,
1469 .set_pcie_lanes
= NULL
,
1470 .set_clock_gating
= NULL
,
1473 .pre_page_flip
= &evergreen_pre_page_flip
,
1474 .page_flip
= &evergreen_page_flip
,
1475 .post_page_flip
= &evergreen_post_page_flip
,
1479 static struct radeon_asic cayman_asic
= {
1480 .init
= &cayman_init
,
1481 .fini
= &cayman_fini
,
1482 .suspend
= &cayman_suspend
,
1483 .resume
= &cayman_resume
,
1484 .asic_reset
= &cayman_asic_reset
,
1485 .vga_set_state
= &r600_vga_set_state
,
1486 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1487 .gui_idle
= &r600_gui_idle
,
1488 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1489 .get_xclk
= &rv770_get_xclk
,
1490 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1492 .tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1493 .set_page
= &rs600_gart_set_page
,
1496 .init
= &cayman_vm_init
,
1497 .fini
= &cayman_vm_fini
,
1498 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1499 .set_page
= &cayman_vm_set_page
,
1502 [RADEON_RING_TYPE_GFX_INDEX
] = {
1503 .ib_execute
= &cayman_ring_ib_execute
,
1504 .ib_parse
= &evergreen_ib_parse
,
1505 .emit_fence
= &cayman_fence_ring_emit
,
1506 .emit_semaphore
= &r600_semaphore_ring_emit
,
1507 .cs_parse
= &evergreen_cs_parse
,
1508 .ring_test
= &r600_ring_test
,
1509 .ib_test
= &r600_ib_test
,
1510 .is_lockup
= &cayman_gfx_is_lockup
,
1511 .vm_flush
= &cayman_vm_flush
,
1513 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
1514 .ib_execute
= &cayman_ring_ib_execute
,
1515 .ib_parse
= &evergreen_ib_parse
,
1516 .emit_fence
= &cayman_fence_ring_emit
,
1517 .emit_semaphore
= &r600_semaphore_ring_emit
,
1518 .cs_parse
= &evergreen_cs_parse
,
1519 .ring_test
= &r600_ring_test
,
1520 .ib_test
= &r600_ib_test
,
1521 .is_lockup
= &cayman_gfx_is_lockup
,
1522 .vm_flush
= &cayman_vm_flush
,
1524 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
1525 .ib_execute
= &cayman_ring_ib_execute
,
1526 .ib_parse
= &evergreen_ib_parse
,
1527 .emit_fence
= &cayman_fence_ring_emit
,
1528 .emit_semaphore
= &r600_semaphore_ring_emit
,
1529 .cs_parse
= &evergreen_cs_parse
,
1530 .ring_test
= &r600_ring_test
,
1531 .ib_test
= &r600_ib_test
,
1532 .is_lockup
= &cayman_gfx_is_lockup
,
1533 .vm_flush
= &cayman_vm_flush
,
1535 [R600_RING_TYPE_DMA_INDEX
] = {
1536 .ib_execute
= &cayman_dma_ring_ib_execute
,
1537 .ib_parse
= &evergreen_dma_ib_parse
,
1538 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1539 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1540 .cs_parse
= &evergreen_dma_cs_parse
,
1541 .ring_test
= &r600_dma_ring_test
,
1542 .ib_test
= &r600_dma_ib_test
,
1543 .is_lockup
= &cayman_dma_is_lockup
,
1544 .vm_flush
= &cayman_dma_vm_flush
,
1546 [CAYMAN_RING_TYPE_DMA1_INDEX
] = {
1547 .ib_execute
= &cayman_dma_ring_ib_execute
,
1548 .ib_parse
= &evergreen_dma_ib_parse
,
1549 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1550 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1551 .cs_parse
= &evergreen_dma_cs_parse
,
1552 .ring_test
= &r600_dma_ring_test
,
1553 .ib_test
= &r600_dma_ib_test
,
1554 .is_lockup
= &cayman_dma_is_lockup
,
1555 .vm_flush
= &cayman_dma_vm_flush
,
1557 [R600_RING_TYPE_UVD_INDEX
] = {
1558 .ib_execute
= &r600_uvd_ib_execute
,
1559 .emit_fence
= &r600_uvd_fence_emit
,
1560 .emit_semaphore
= &cayman_uvd_semaphore_emit
,
1561 .cs_parse
= &radeon_uvd_cs_parse
,
1562 .ring_test
= &r600_uvd_ring_test
,
1563 .ib_test
= &r600_uvd_ib_test
,
1564 .is_lockup
= &radeon_ring_test_lockup
,
1568 .set
= &evergreen_irq_set
,
1569 .process
= &evergreen_irq_process
,
1572 .bandwidth_update
= &evergreen_bandwidth_update
,
1573 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1574 .wait_for_vblank
= &dce4_wait_for_vblank
,
1575 .set_backlight_level
= &atombios_set_backlight_level
,
1576 .get_backlight_level
= &atombios_get_backlight_level
,
1579 .blit
= &r600_copy_blit
,
1580 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1581 .dma
= &evergreen_copy_dma
,
1582 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1583 .copy
= &evergreen_copy_dma
,
1584 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1587 .set_reg
= r600_set_surface_reg
,
1588 .clear_reg
= r600_clear_surface_reg
,
1591 .init
= &evergreen_hpd_init
,
1592 .fini
= &evergreen_hpd_fini
,
1593 .sense
= &evergreen_hpd_sense
,
1594 .set_polarity
= &evergreen_hpd_set_polarity
,
1597 .misc
= &evergreen_pm_misc
,
1598 .prepare
= &evergreen_pm_prepare
,
1599 .finish
= &evergreen_pm_finish
,
1600 .init_profile
= &btc_pm_init_profile
,
1601 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1602 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1603 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1604 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1605 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1606 .get_pcie_lanes
= NULL
,
1607 .set_pcie_lanes
= NULL
,
1608 .set_clock_gating
= NULL
,
1611 .pre_page_flip
= &evergreen_pre_page_flip
,
1612 .page_flip
= &evergreen_page_flip
,
1613 .post_page_flip
= &evergreen_post_page_flip
,
1617 static struct radeon_asic trinity_asic
= {
1618 .init
= &cayman_init
,
1619 .fini
= &cayman_fini
,
1620 .suspend
= &cayman_suspend
,
1621 .resume
= &cayman_resume
,
1622 .asic_reset
= &cayman_asic_reset
,
1623 .vga_set_state
= &r600_vga_set_state
,
1624 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1625 .gui_idle
= &r600_gui_idle
,
1626 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1627 .get_xclk
= &r600_get_xclk
,
1628 .get_gpu_clock_counter
= &r600_get_gpu_clock_counter
,
1630 .tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1631 .set_page
= &rs600_gart_set_page
,
1634 .init
= &cayman_vm_init
,
1635 .fini
= &cayman_vm_fini
,
1636 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1637 .set_page
= &cayman_vm_set_page
,
1640 [RADEON_RING_TYPE_GFX_INDEX
] = {
1641 .ib_execute
= &cayman_ring_ib_execute
,
1642 .ib_parse
= &evergreen_ib_parse
,
1643 .emit_fence
= &cayman_fence_ring_emit
,
1644 .emit_semaphore
= &r600_semaphore_ring_emit
,
1645 .cs_parse
= &evergreen_cs_parse
,
1646 .ring_test
= &r600_ring_test
,
1647 .ib_test
= &r600_ib_test
,
1648 .is_lockup
= &cayman_gfx_is_lockup
,
1649 .vm_flush
= &cayman_vm_flush
,
1651 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
1652 .ib_execute
= &cayman_ring_ib_execute
,
1653 .ib_parse
= &evergreen_ib_parse
,
1654 .emit_fence
= &cayman_fence_ring_emit
,
1655 .emit_semaphore
= &r600_semaphore_ring_emit
,
1656 .cs_parse
= &evergreen_cs_parse
,
1657 .ring_test
= &r600_ring_test
,
1658 .ib_test
= &r600_ib_test
,
1659 .is_lockup
= &cayman_gfx_is_lockup
,
1660 .vm_flush
= &cayman_vm_flush
,
1662 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
1663 .ib_execute
= &cayman_ring_ib_execute
,
1664 .ib_parse
= &evergreen_ib_parse
,
1665 .emit_fence
= &cayman_fence_ring_emit
,
1666 .emit_semaphore
= &r600_semaphore_ring_emit
,
1667 .cs_parse
= &evergreen_cs_parse
,
1668 .ring_test
= &r600_ring_test
,
1669 .ib_test
= &r600_ib_test
,
1670 .is_lockup
= &cayman_gfx_is_lockup
,
1671 .vm_flush
= &cayman_vm_flush
,
1673 [R600_RING_TYPE_DMA_INDEX
] = {
1674 .ib_execute
= &cayman_dma_ring_ib_execute
,
1675 .ib_parse
= &evergreen_dma_ib_parse
,
1676 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1677 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1678 .cs_parse
= &evergreen_dma_cs_parse
,
1679 .ring_test
= &r600_dma_ring_test
,
1680 .ib_test
= &r600_dma_ib_test
,
1681 .is_lockup
= &cayman_dma_is_lockup
,
1682 .vm_flush
= &cayman_dma_vm_flush
,
1684 [CAYMAN_RING_TYPE_DMA1_INDEX
] = {
1685 .ib_execute
= &cayman_dma_ring_ib_execute
,
1686 .ib_parse
= &evergreen_dma_ib_parse
,
1687 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1688 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1689 .cs_parse
= &evergreen_dma_cs_parse
,
1690 .ring_test
= &r600_dma_ring_test
,
1691 .ib_test
= &r600_dma_ib_test
,
1692 .is_lockup
= &cayman_dma_is_lockup
,
1693 .vm_flush
= &cayman_dma_vm_flush
,
1695 [R600_RING_TYPE_UVD_INDEX
] = {
1696 .ib_execute
= &r600_uvd_ib_execute
,
1697 .emit_fence
= &r600_uvd_fence_emit
,
1698 .emit_semaphore
= &cayman_uvd_semaphore_emit
,
1699 .cs_parse
= &radeon_uvd_cs_parse
,
1700 .ring_test
= &r600_uvd_ring_test
,
1701 .ib_test
= &r600_uvd_ib_test
,
1702 .is_lockup
= &radeon_ring_test_lockup
,
1706 .set
= &evergreen_irq_set
,
1707 .process
= &evergreen_irq_process
,
1710 .bandwidth_update
= &dce6_bandwidth_update
,
1711 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1712 .wait_for_vblank
= &dce4_wait_for_vblank
,
1713 .set_backlight_level
= &atombios_set_backlight_level
,
1714 .get_backlight_level
= &atombios_get_backlight_level
,
1717 .blit
= &r600_copy_blit
,
1718 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1719 .dma
= &evergreen_copy_dma
,
1720 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1721 .copy
= &evergreen_copy_dma
,
1722 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1725 .set_reg
= r600_set_surface_reg
,
1726 .clear_reg
= r600_clear_surface_reg
,
1729 .init
= &evergreen_hpd_init
,
1730 .fini
= &evergreen_hpd_fini
,
1731 .sense
= &evergreen_hpd_sense
,
1732 .set_polarity
= &evergreen_hpd_set_polarity
,
1735 .misc
= &evergreen_pm_misc
,
1736 .prepare
= &evergreen_pm_prepare
,
1737 .finish
= &evergreen_pm_finish
,
1738 .init_profile
= &sumo_pm_init_profile
,
1739 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1740 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1741 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1742 .get_memory_clock
= NULL
,
1743 .set_memory_clock
= NULL
,
1744 .get_pcie_lanes
= NULL
,
1745 .set_pcie_lanes
= NULL
,
1746 .set_clock_gating
= NULL
,
1749 .pre_page_flip
= &evergreen_pre_page_flip
,
1750 .page_flip
= &evergreen_page_flip
,
1751 .post_page_flip
= &evergreen_post_page_flip
,
1755 static struct radeon_asic si_asic
= {
1758 .suspend
= &si_suspend
,
1759 .resume
= &si_resume
,
1760 .asic_reset
= &si_asic_reset
,
1761 .vga_set_state
= &r600_vga_set_state
,
1762 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1763 .gui_idle
= &r600_gui_idle
,
1764 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1765 .get_xclk
= &si_get_xclk
,
1766 .get_gpu_clock_counter
= &si_get_gpu_clock_counter
,
1768 .tlb_flush
= &si_pcie_gart_tlb_flush
,
1769 .set_page
= &rs600_gart_set_page
,
1772 .init
= &si_vm_init
,
1773 .fini
= &si_vm_fini
,
1774 .pt_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1775 .set_page
= &si_vm_set_page
,
1778 [RADEON_RING_TYPE_GFX_INDEX
] = {
1779 .ib_execute
= &si_ring_ib_execute
,
1780 .ib_parse
= &si_ib_parse
,
1781 .emit_fence
= &si_fence_ring_emit
,
1782 .emit_semaphore
= &r600_semaphore_ring_emit
,
1784 .ring_test
= &r600_ring_test
,
1785 .ib_test
= &r600_ib_test
,
1786 .is_lockup
= &si_gfx_is_lockup
,
1787 .vm_flush
= &si_vm_flush
,
1789 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
1790 .ib_execute
= &si_ring_ib_execute
,
1791 .ib_parse
= &si_ib_parse
,
1792 .emit_fence
= &si_fence_ring_emit
,
1793 .emit_semaphore
= &r600_semaphore_ring_emit
,
1795 .ring_test
= &r600_ring_test
,
1796 .ib_test
= &r600_ib_test
,
1797 .is_lockup
= &si_gfx_is_lockup
,
1798 .vm_flush
= &si_vm_flush
,
1800 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
1801 .ib_execute
= &si_ring_ib_execute
,
1802 .ib_parse
= &si_ib_parse
,
1803 .emit_fence
= &si_fence_ring_emit
,
1804 .emit_semaphore
= &r600_semaphore_ring_emit
,
1806 .ring_test
= &r600_ring_test
,
1807 .ib_test
= &r600_ib_test
,
1808 .is_lockup
= &si_gfx_is_lockup
,
1809 .vm_flush
= &si_vm_flush
,
1811 [R600_RING_TYPE_DMA_INDEX
] = {
1812 .ib_execute
= &cayman_dma_ring_ib_execute
,
1813 .ib_parse
= &evergreen_dma_ib_parse
,
1814 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1815 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1817 .ring_test
= &r600_dma_ring_test
,
1818 .ib_test
= &r600_dma_ib_test
,
1819 .is_lockup
= &si_dma_is_lockup
,
1820 .vm_flush
= &si_dma_vm_flush
,
1822 [CAYMAN_RING_TYPE_DMA1_INDEX
] = {
1823 .ib_execute
= &cayman_dma_ring_ib_execute
,
1824 .ib_parse
= &evergreen_dma_ib_parse
,
1825 .emit_fence
= &evergreen_dma_fence_ring_emit
,
1826 .emit_semaphore
= &r600_dma_semaphore_ring_emit
,
1828 .ring_test
= &r600_dma_ring_test
,
1829 .ib_test
= &r600_dma_ib_test
,
1830 .is_lockup
= &si_dma_is_lockup
,
1831 .vm_flush
= &si_dma_vm_flush
,
1833 [R600_RING_TYPE_UVD_INDEX
] = {
1834 .ib_execute
= &r600_uvd_ib_execute
,
1835 .emit_fence
= &r600_uvd_fence_emit
,
1836 .emit_semaphore
= &cayman_uvd_semaphore_emit
,
1837 .cs_parse
= &radeon_uvd_cs_parse
,
1838 .ring_test
= &r600_uvd_ring_test
,
1839 .ib_test
= &r600_uvd_ib_test
,
1840 .is_lockup
= &radeon_ring_test_lockup
,
1845 .process
= &si_irq_process
,
1848 .bandwidth_update
= &dce6_bandwidth_update
,
1849 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1850 .wait_for_vblank
= &dce4_wait_for_vblank
,
1851 .set_backlight_level
= &atombios_set_backlight_level
,
1852 .get_backlight_level
= &atombios_get_backlight_level
,
1856 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1857 .dma
= &si_copy_dma
,
1858 .dma_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1859 .copy
= &si_copy_dma
,
1860 .copy_ring_index
= R600_RING_TYPE_DMA_INDEX
,
1863 .set_reg
= r600_set_surface_reg
,
1864 .clear_reg
= r600_clear_surface_reg
,
1867 .init
= &evergreen_hpd_init
,
1868 .fini
= &evergreen_hpd_fini
,
1869 .sense
= &evergreen_hpd_sense
,
1870 .set_polarity
= &evergreen_hpd_set_polarity
,
1873 .misc
= &evergreen_pm_misc
,
1874 .prepare
= &evergreen_pm_prepare
,
1875 .finish
= &evergreen_pm_finish
,
1876 .init_profile
= &sumo_pm_init_profile
,
1877 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1878 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1879 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1880 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1881 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1882 .get_pcie_lanes
= NULL
,
1883 .set_pcie_lanes
= NULL
,
1884 .set_clock_gating
= NULL
,
1887 .pre_page_flip
= &evergreen_pre_page_flip
,
1888 .page_flip
= &evergreen_page_flip
,
1889 .post_page_flip
= &evergreen_post_page_flip
,
1894 * radeon_asic_init - register asic specific callbacks
1896 * @rdev: radeon device pointer
1898 * Registers the appropriate asic specific callbacks for each
1899 * chip family. Also sets other asics specific info like the number
1900 * of crtcs and the register aperture accessors (all asics).
1901 * Returns 0 for success.
1903 int radeon_asic_init(struct radeon_device
*rdev
)
1905 radeon_register_accessor_init(rdev
);
1907 /* set the number of crtcs */
1908 if (rdev
->flags
& RADEON_SINGLE_CRTC
)
1913 switch (rdev
->family
) {
1919 rdev
->asic
= &r100_asic
;
1925 rdev
->asic
= &r200_asic
;
1931 if (rdev
->flags
& RADEON_IS_PCIE
)
1932 rdev
->asic
= &r300_asic_pcie
;
1934 rdev
->asic
= &r300_asic
;
1939 rdev
->asic
= &r420_asic
;
1941 if (rdev
->bios
== NULL
) {
1942 rdev
->asic
->pm
.get_engine_clock
= &radeon_legacy_get_engine_clock
;
1943 rdev
->asic
->pm
.set_engine_clock
= &radeon_legacy_set_engine_clock
;
1944 rdev
->asic
->pm
.get_memory_clock
= &radeon_legacy_get_memory_clock
;
1945 rdev
->asic
->pm
.set_memory_clock
= NULL
;
1946 rdev
->asic
->display
.set_backlight_level
= &radeon_legacy_set_backlight_level
;
1951 rdev
->asic
= &rs400_asic
;
1954 rdev
->asic
= &rs600_asic
;
1958 rdev
->asic
= &rs690_asic
;
1961 rdev
->asic
= &rv515_asic
;
1968 rdev
->asic
= &r520_asic
;
1976 rdev
->asic
= &r600_asic
;
1980 rdev
->asic
= &rs780_asic
;
1986 rdev
->asic
= &rv770_asic
;
1994 if (rdev
->family
== CHIP_CEDAR
)
1998 rdev
->asic
= &evergreen_asic
;
2003 rdev
->asic
= &sumo_asic
;
2009 if (rdev
->family
== CHIP_CAICOS
)
2013 rdev
->asic
= &btc_asic
;
2016 rdev
->asic
= &cayman_asic
;
2021 rdev
->asic
= &trinity_asic
;
2029 rdev
->asic
= &si_asic
;
2031 if (rdev
->family
== CHIP_OLAND
)
2037 /* FIXME: not supported yet */
2041 if (rdev
->flags
& RADEON_IS_IGP
) {
2042 rdev
->asic
->pm
.get_memory_clock
= NULL
;
2043 rdev
->asic
->pm
.set_memory_clock
= NULL
;