drivers/gpu/drm/radeon/radeon_asic.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_ASIC_H__
  29 #define __RADEON_ASIC_H__
  30
  31 /*
  32  * common functions
  33  */
  34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
  35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
  37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  38
  39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
  40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
  42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
  43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  44
  45 /*
  46  * r100,rv100,rs100,rv200,rs200
  47  */
  48 struct r100_mc_save {
  49         u32     GENMO_WT;
  50         u32     CRTC_EXT_CNTL;
  51         u32     CRTC_GEN_CNTL;
  52         u32     CRTC2_GEN_CNTL;
  53         u32     CUR_OFFSET;
  54         u32     CUR2_OFFSET;
  55 };
  56 int r100_init(struct radeon_device *rdev);
  57 void r100_fini(struct radeon_device *rdev);
  58 int r100_suspend(struct radeon_device *rdev);
  59 int r100_resume(struct radeon_device *rdev);
  60 void r100_vga_set_state(struct radeon_device *rdev, bool state);
  61 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  62 int r100_asic_reset(struct radeon_device *rdev);
  63 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
  64 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  65 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  66 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
  67 int r100_irq_set(struct radeon_device *rdev);
  68 int r100_irq_process(struct radeon_device *rdev);
  69 void r100_fence_ring_emit(struct radeon_device *rdev,
  70                           struct radeon_fence *fence);
  71 void r100_semaphore_ring_emit(struct radeon_device *rdev,
  72                               struct radeon_ring *cp,
  73                               struct radeon_semaphore *semaphore,
  74                               bool emit_wait);
  75 int r100_cs_parse(struct radeon_cs_parser *p);
  76 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  77 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
  78 int r100_copy_blit(struct radeon_device *rdev,
  79                    uint64_t src_offset,
  80                    uint64_t dst_offset,
  81                    unsigned num_gpu_pages,
  82                    struct radeon_fence **fence);
  83 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
  84                          uint32_t tiling_flags, uint32_t pitch,
  85                          uint32_t offset, uint32_t obj_size);
  86 void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
  87 void r100_bandwidth_update(struct radeon_device *rdev);
  88 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  89 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  90 void r100_hpd_init(struct radeon_device *rdev);
  91 void r100_hpd_fini(struct radeon_device *rdev);
  92 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  93 void r100_hpd_set_polarity(struct radeon_device *rdev,
  94                            enum radeon_hpd_id hpd);
  95 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
  96 int r100_debugfs_cp_init(struct radeon_device *rdev);
  97 void r100_cp_disable(struct radeon_device *rdev);
  98 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  99 void r100_cp_fini(struct radeon_device *rdev);
 100 int r100_pci_gart_init(struct radeon_device *rdev);
 101 void r100_pci_gart_fini(struct radeon_device *rdev);
 102 int r100_pci_gart_enable(struct radeon_device *rdev);
 103 void r100_pci_gart_disable(struct radeon_device *rdev);
 104 int r100_debugfs_mc_info_init(struct radeon_device *rdev);
 105 int r100_gui_wait_for_idle(struct radeon_device *rdev);
 106 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 107 void r100_irq_disable(struct radeon_device *rdev);
 108 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
 109 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
 110 void r100_vram_init_sizes(struct radeon_device *rdev);
 111 int r100_cp_reset(struct radeon_device *rdev);
 112 void r100_vga_render_disable(struct radeon_device *rdev);
 113 void r100_restore_sanity(struct radeon_device *rdev);
 114 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
 115                                          struct radeon_cs_packet *pkt,
 116                                          struct radeon_bo *robj);
 117 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 118                           struct radeon_cs_packet *pkt,
 119                           const unsigned *auth, unsigned n,
 120                           radeon_packet0_check_t check);
 121 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 122                          struct radeon_cs_packet *pkt,
 123                          unsigned idx);
 124 void r100_enable_bm(struct radeon_device *rdev);
 125 void r100_set_common_regs(struct radeon_device *rdev);
 126 void r100_bm_disable(struct radeon_device *rdev);
 127 extern bool r100_gui_idle(struct radeon_device *rdev);
 128 extern void r100_pm_misc(struct radeon_device *rdev);
 129 extern void r100_pm_prepare(struct radeon_device *rdev);
 130 extern void r100_pm_finish(struct radeon_device *rdev);
 131 extern void r100_pm_init_profile(struct radeon_device *rdev);
 132 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
 133 extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
 134 extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 135 extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
 136 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
 137 extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
 138
 139 /*
 140  * r200,rv250,rs300,rv280
 141  */
 142 extern int r200_copy_dma(struct radeon_device *rdev,
 143                          uint64_t src_offset,
 144                          uint64_t dst_offset,
 145                          unsigned num_gpu_pages,
 146                          struct radeon_fence **fence);
 147 void r200_set_safe_registers(struct radeon_device *rdev);
 148
 149 /*
 150  * r300,r350,rv350,rv380
 151  */
 152 extern int r300_init(struct radeon_device *rdev);
 153 extern void r300_fini(struct radeon_device *rdev);
 154 extern int r300_suspend(struct radeon_device *rdev);
 155 extern int r300_resume(struct radeon_device *rdev);
 156 extern int r300_asic_reset(struct radeon_device *rdev);
 157 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
 158 extern void r300_fence_ring_emit(struct radeon_device *rdev,
 159                                 struct radeon_fence *fence);
 160 extern int r300_cs_parse(struct radeon_cs_parser *p);
 161 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
 162 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 163 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 164 extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
 165 extern void r300_set_reg_safe(struct radeon_device *rdev);
 166 extern void r300_mc_program(struct radeon_device *rdev);
 167 extern void r300_mc_init(struct radeon_device *rdev);
 168 extern void r300_clock_startup(struct radeon_device *rdev);
 169 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
 170 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
 171 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
 172 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
 173 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
 174 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
 175
 176 /*
 177  * r420,r423,rv410
 178  */
 179 extern int r420_init(struct radeon_device *rdev);
 180 extern void r420_fini(struct radeon_device *rdev);
 181 extern int r420_suspend(struct radeon_device *rdev);
 182 extern int r420_resume(struct radeon_device *rdev);
 183 extern void r420_pm_init_profile(struct radeon_device *rdev);
 184 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
 185 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
 186 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
 187 extern void r420_pipes_init(struct radeon_device *rdev);
 188
 189 /*
 190  * rs400,rs480
 191  */
 192 extern int rs400_init(struct radeon_device *rdev);
 193 extern void rs400_fini(struct radeon_device *rdev);
 194 extern int rs400_suspend(struct radeon_device *rdev);
 195 extern int rs400_resume(struct radeon_device *rdev);
 196 void rs400_gart_tlb_flush(struct radeon_device *rdev);
 197 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 198 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 199 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 200 int rs400_gart_init(struct radeon_device *rdev);
 201 int rs400_gart_enable(struct radeon_device *rdev);
 202 void rs400_gart_adjust_size(struct radeon_device *rdev);
 203 void rs400_gart_disable(struct radeon_device *rdev);
 204 void rs400_gart_fini(struct radeon_device *rdev);
 205 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
 206
 207 /*
 208  * rs600.
 209  */
 210 extern int rs600_asic_reset(struct radeon_device *rdev);
 211 extern int rs600_init(struct radeon_device *rdev);
 212 extern void rs600_fini(struct radeon_device *rdev);
 213 extern int rs600_suspend(struct radeon_device *rdev);
 214 extern int rs600_resume(struct radeon_device *rdev);
 215 int rs600_irq_set(struct radeon_device *rdev);
 216 int rs600_irq_process(struct radeon_device *rdev);
 217 void rs600_irq_disable(struct radeon_device *rdev);
 218 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
 219 void rs600_gart_tlb_flush(struct radeon_device *rdev);
 220 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 221 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 222 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 223 void rs600_bandwidth_update(struct radeon_device *rdev);
 224 void rs600_hpd_init(struct radeon_device *rdev);
 225 void rs600_hpd_fini(struct radeon_device *rdev);
 226 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 227 void rs600_hpd_set_polarity(struct radeon_device *rdev,
 228                             enum radeon_hpd_id hpd);
 229 extern void rs600_pm_misc(struct radeon_device *rdev);
 230 extern void rs600_pm_prepare(struct radeon_device *rdev);
 231 extern void rs600_pm_finish(struct radeon_device *rdev);
 232 extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
 233 extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 234 extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
 235 void rs600_set_safe_registers(struct radeon_device *rdev);
 236 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
 237 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
 238
 239 /*
 240  * rs690,rs740
 241  */
 242 int rs690_init(struct radeon_device *rdev);
 243 void rs690_fini(struct radeon_device *rdev);
 244 int rs690_resume(struct radeon_device *rdev);
 245 int rs690_suspend(struct radeon_device *rdev);
 246 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 247 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 248 void rs690_bandwidth_update(struct radeon_device *rdev);
 249 void rs690_line_buffer_adjust(struct radeon_device *rdev,
 250                                         struct drm_display_mode *mode1,
 251                                         struct drm_display_mode *mode2);
 252 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
 253
 254 /*
 255  * rv515
 256  */
 257 struct rv515_mc_save {
 258         u32 vga_render_control;
 259         u32 vga_hdp_control;
 260 };
 261
 262 int rv515_init(struct radeon_device *rdev);
 263 void rv515_fini(struct radeon_device *rdev);
 264 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 265 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 266 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
 267 void rv515_bandwidth_update(struct radeon_device *rdev);
 268 int rv515_resume(struct radeon_device *rdev);
 269 int rv515_suspend(struct radeon_device *rdev);
 270 void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
 271 void rv515_vga_render_disable(struct radeon_device *rdev);
 272 void rv515_set_safe_registers(struct radeon_device *rdev);
 273 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
 274 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
 275 void rv515_clock_startup(struct radeon_device *rdev);
 276 void rv515_debugfs(struct radeon_device *rdev);
 277 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
 278
 279 /*
 280  * r520,rv530,rv560,rv570,r580
 281  */
 282 int r520_init(struct radeon_device *rdev);
 283 int r520_resume(struct radeon_device *rdev);
 284 int r520_mc_wait_for_idle(struct radeon_device *rdev);
 285
 286 /*
 287  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
 288  */
 289 int r600_init(struct radeon_device *rdev);
 290 void r600_fini(struct radeon_device *rdev);
 291 int r600_suspend(struct radeon_device *rdev);
 292 int r600_resume(struct radeon_device *rdev);
 293 void r600_vga_set_state(struct radeon_device *rdev, bool state);
 294 int r600_wb_init(struct radeon_device *rdev);
 295 void r600_wb_fini(struct radeon_device *rdev);
 296 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
 297 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 298 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 299 int r600_cs_parse(struct radeon_cs_parser *p);
 300 void r600_fence_ring_emit(struct radeon_device *rdev,
 301                           struct radeon_fence *fence);
 302 void r600_semaphore_ring_emit(struct radeon_device *rdev,
 303                               struct radeon_ring *cp,
 304                               struct radeon_semaphore *semaphore,
 305                               bool emit_wait);
 306 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 307 int r600_asic_reset(struct radeon_device *rdev);
 308 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
 309                          uint32_t tiling_flags, uint32_t pitch,
 310                          uint32_t offset, uint32_t obj_size);
 311 void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
 312 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 313 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 314 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 315 int r600_copy_blit(struct radeon_device *rdev,
 316                    uint64_t src_offset, uint64_t dst_offset,
 317                    unsigned num_gpu_pages, struct radeon_fence **fence);
 318 void r600_hpd_init(struct radeon_device *rdev);
 319 void r600_hpd_fini(struct radeon_device *rdev);
 320 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 321 void r600_hpd_set_polarity(struct radeon_device *rdev,
 322                            enum radeon_hpd_id hpd);
 323 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
 324 extern bool r600_gui_idle(struct radeon_device *rdev);
 325 extern void r600_pm_misc(struct radeon_device *rdev);
 326 extern void r600_pm_init_profile(struct radeon_device *rdev);
 327 extern void rs780_pm_init_profile(struct radeon_device *rdev);
 328 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
 329 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 330 extern int r600_get_pcie_lanes(struct radeon_device *rdev);
 331 bool r600_card_posted(struct radeon_device *rdev);
 332 void r600_cp_stop(struct radeon_device *rdev);
 333 int r600_cp_start(struct radeon_device *rdev);
 334 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
 335 int r600_cp_resume(struct radeon_device *rdev);
 336 void r600_cp_fini(struct radeon_device *rdev);
 337 int r600_count_pipe_bits(uint32_t val);
 338 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 339 int r600_pcie_gart_init(struct radeon_device *rdev);
 340 void r600_scratch_init(struct radeon_device *rdev);
 341 int r600_blit_init(struct radeon_device *rdev);
 342 void r600_blit_fini(struct radeon_device *rdev);
 343 int r600_init_microcode(struct radeon_device *rdev);
 344 /* r600 irq */
 345 int r600_irq_process(struct radeon_device *rdev);
 346 int r600_irq_init(struct radeon_device *rdev);
 347 void r600_irq_fini(struct radeon_device *rdev);
 348 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
 349 int r600_irq_set(struct radeon_device *rdev);
 350 void r600_irq_suspend(struct radeon_device *rdev);
 351 void r600_disable_interrupts(struct radeon_device *rdev);
 352 void r600_rlc_stop(struct radeon_device *rdev);
 353 /* r600 audio */
 354 int r600_audio_init(struct radeon_device *rdev);
 355 void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
 356 struct r600_audio r600_audio_status(struct radeon_device *rdev);
 357 void r600_audio_fini(struct radeon_device *rdev);
 358 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
 359 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
 360 /* r600 blit */
 361 int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
 362                            struct radeon_fence **fence, struct radeon_sa_bo **vb,
 363                            struct radeon_semaphore **sem);
 364 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
 365                          struct radeon_sa_bo *vb, struct radeon_semaphore *sem);
 366 void r600_kms_blit_copy(struct radeon_device *rdev,
 367                         u64 src_gpu_addr, u64 dst_gpu_addr,
 368                         unsigned num_gpu_pages,
 369                         struct radeon_sa_bo *vb);
 370 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 371 uint64_t r600_get_gpu_clock(struct radeon_device *rdev);
 372
 373 /*
 374  * rv770,rv730,rv710,rv740
 375  */
 376 int rv770_init(struct radeon_device *rdev);
 377 void rv770_fini(struct radeon_device *rdev);
 378 int rv770_suspend(struct radeon_device *rdev);
 379 int rv770_resume(struct radeon_device *rdev);
 380 void rv770_pm_misc(struct radeon_device *rdev);
 381 u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 382 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
 383 void r700_cp_stop(struct radeon_device *rdev);
 384 void r700_cp_fini(struct radeon_device *rdev);
 385
 386 /*
 387  * evergreen
 388  */
 389 struct evergreen_mc_save {
 390         u32 vga_render_control;
 391         u32 vga_hdp_control;
 392 };
 393
 394 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
 395 int evergreen_init(struct radeon_device *rdev);
 396 void evergreen_fini(struct radeon_device *rdev);
 397 int evergreen_suspend(struct radeon_device *rdev);
 398 int evergreen_resume(struct radeon_device *rdev);
 399 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 400 int evergreen_asic_reset(struct radeon_device *rdev);
 401 void evergreen_bandwidth_update(struct radeon_device *rdev);
 402 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 403 void evergreen_hpd_init(struct radeon_device *rdev);
 404 void evergreen_hpd_fini(struct radeon_device *rdev);
 405 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 406 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 407                                 enum radeon_hpd_id hpd);
 408 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
 409 int evergreen_irq_set(struct radeon_device *rdev);
 410 int evergreen_irq_process(struct radeon_device *rdev);
 411 extern int evergreen_cs_parse(struct radeon_cs_parser *p);
 412 extern void evergreen_pm_misc(struct radeon_device *rdev);
 413 extern void evergreen_pm_prepare(struct radeon_device *rdev);
 414 extern void evergreen_pm_finish(struct radeon_device *rdev);
 415 extern void sumo_pm_init_profile(struct radeon_device *rdev);
 416 extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
 417 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 418 extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
 419 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
 420 void evergreen_disable_interrupt_state(struct radeon_device *rdev);
 421 int evergreen_blit_init(struct radeon_device *rdev);
 422 int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
 423
 424 /*
 425  * cayman
 426  */
 427 void cayman_fence_ring_emit(struct radeon_device *rdev,
 428                             struct radeon_fence *fence);
 429 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
 430 int cayman_init(struct radeon_device *rdev);
 431 void cayman_fini(struct radeon_device *rdev);
 432 int cayman_suspend(struct radeon_device *rdev);
 433 int cayman_resume(struct radeon_device *rdev);
 434 int cayman_asic_reset(struct radeon_device *rdev);
 435 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 436 int cayman_vm_init(struct radeon_device *rdev);
 437 void cayman_vm_fini(struct radeon_device *rdev);
 438 int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id);
 439 void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
 440 void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm);
 441 uint32_t cayman_vm_page_flags(struct radeon_device *rdev,
 442                               struct radeon_vm *vm,
 443                               uint32_t flags);
 444 void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
 445                         unsigned pfn, uint64_t addr, uint32_t flags);
 446 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 447
 448 /* DCE6 - SI */
 449 void dce6_bandwidth_update(struct radeon_device *rdev);
 450
 451 /*
 452  * si
 453  */
 454 void si_fence_ring_emit(struct radeon_device *rdev,
 455                         struct radeon_fence *fence);
 456 void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
 457 int si_init(struct radeon_device *rdev);
 458 void si_fini(struct radeon_device *rdev);
 459 int si_suspend(struct radeon_device *rdev);
 460 int si_resume(struct radeon_device *rdev);
 461 bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 462 int si_asic_reset(struct radeon_device *rdev);
 463 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 464 int si_irq_set(struct radeon_device *rdev);
 465 int si_irq_process(struct radeon_device *rdev);
 466 int si_vm_init(struct radeon_device *rdev);
 467 void si_vm_fini(struct radeon_device *rdev);
 468 int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id);
 469 void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
 470 void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm);
 471 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 472 uint64_t si_get_gpu_clock(struct radeon_device *rdev);
 473
 474 #endif