drivers/gpu/drm/radeon/radeon_asic.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_ASIC_H__
  29 #define __RADEON_ASIC_H__
  30
  31 /*
  32  * common functions
  33  */
  34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
  35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
  37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  38
  39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
  40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
  42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
  43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  44
  45 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
  46 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
  47 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
  48 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
  49
  50 /*
  51  * r100,rv100,rs100,rv200,rs200
  52  */
  53 struct r100_mc_save {
  54         u32     GENMO_WT;
  55         u32     CRTC_EXT_CNTL;
  56         u32     CRTC_GEN_CNTL;
  57         u32     CRTC2_GEN_CNTL;
  58         u32     CUR_OFFSET;
  59         u32     CUR2_OFFSET;
  60 };
  61 int r100_init(struct radeon_device *rdev);
  62 void r100_fini(struct radeon_device *rdev);
  63 int r100_suspend(struct radeon_device *rdev);
  64 int r100_resume(struct radeon_device *rdev);
  65 void r100_vga_set_state(struct radeon_device *rdev, bool state);
  66 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  67 int r100_asic_reset(struct radeon_device *rdev);
  68 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
  69 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  70 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  71 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
  72 int r100_irq_set(struct radeon_device *rdev);
  73 int r100_irq_process(struct radeon_device *rdev);
  74 void r100_fence_ring_emit(struct radeon_device *rdev,
  75                           struct radeon_fence *fence);
  76 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
  77                               struct radeon_ring *cp,
  78                               struct radeon_semaphore *semaphore,
  79                               bool emit_wait);
  80 int r100_cs_parse(struct radeon_cs_parser *p);
  81 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  82 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
  83 int r100_copy_blit(struct radeon_device *rdev,
  84                    uint64_t src_offset,
  85                    uint64_t dst_offset,
  86                    unsigned num_gpu_pages,
  87                    struct radeon_fence **fence);
  88 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
  89                          uint32_t tiling_flags, uint32_t pitch,
  90                          uint32_t offset, uint32_t obj_size);
  91 void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
  92 void r100_bandwidth_update(struct radeon_device *rdev);
  93 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  94 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  95 void r100_hpd_init(struct radeon_device *rdev);
  96 void r100_hpd_fini(struct radeon_device *rdev);
  97 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  98 void r100_hpd_set_polarity(struct radeon_device *rdev,
  99                            enum radeon_hpd_id hpd);
 100 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
 101 int r100_debugfs_cp_init(struct radeon_device *rdev);
 102 void r100_cp_disable(struct radeon_device *rdev);
 103 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
 104 void r100_cp_fini(struct radeon_device *rdev);
 105 int r100_pci_gart_init(struct radeon_device *rdev);
 106 void r100_pci_gart_fini(struct radeon_device *rdev);
 107 int r100_pci_gart_enable(struct radeon_device *rdev);
 108 void r100_pci_gart_disable(struct radeon_device *rdev);
 109 int r100_debugfs_mc_info_init(struct radeon_device *rdev);
 110 int r100_gui_wait_for_idle(struct radeon_device *rdev);
 111 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 112 void r100_irq_disable(struct radeon_device *rdev);
 113 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
 114 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
 115 void r100_vram_init_sizes(struct radeon_device *rdev);
 116 int r100_cp_reset(struct radeon_device *rdev);
 117 void r100_vga_render_disable(struct radeon_device *rdev);
 118 void r100_restore_sanity(struct radeon_device *rdev);
 119 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
 120                                          struct radeon_cs_packet *pkt,
 121                                          struct radeon_bo *robj);
 122 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 123                           struct radeon_cs_packet *pkt,
 124                           const unsigned *auth, unsigned n,
 125                           radeon_packet0_check_t check);
 126 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 127                          struct radeon_cs_packet *pkt,
 128                          unsigned idx);
 129 void r100_enable_bm(struct radeon_device *rdev);
 130 void r100_set_common_regs(struct radeon_device *rdev);
 131 void r100_bm_disable(struct radeon_device *rdev);
 132 extern bool r100_gui_idle(struct radeon_device *rdev);
 133 extern void r100_pm_misc(struct radeon_device *rdev);
 134 extern void r100_pm_prepare(struct radeon_device *rdev);
 135 extern void r100_pm_finish(struct radeon_device *rdev);
 136 extern void r100_pm_init_profile(struct radeon_device *rdev);
 137 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
 138 extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
 139 extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 140 extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
 141 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
 142 extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
 143
 144 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
 145                       struct radeon_ring *ring);
 146 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
 147                       struct radeon_ring *ring);
 148 void r100_gfx_set_wptr(struct radeon_device *rdev,
 149                        struct radeon_ring *ring);
 150
 151 /*
 152  * r200,rv250,rs300,rv280
 153  */
 154 extern int r200_copy_dma(struct radeon_device *rdev,
 155                          uint64_t src_offset,
 156                          uint64_t dst_offset,
 157                          unsigned num_gpu_pages,
 158                          struct radeon_fence **fence);
 159 void r200_set_safe_registers(struct radeon_device *rdev);
 160
 161 /*
 162  * r300,r350,rv350,rv380
 163  */
 164 extern int r300_init(struct radeon_device *rdev);
 165 extern void r300_fini(struct radeon_device *rdev);
 166 extern int r300_suspend(struct radeon_device *rdev);
 167 extern int r300_resume(struct radeon_device *rdev);
 168 extern int r300_asic_reset(struct radeon_device *rdev);
 169 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
 170 extern void r300_fence_ring_emit(struct radeon_device *rdev,
 171                                 struct radeon_fence *fence);
 172 extern int r300_cs_parse(struct radeon_cs_parser *p);
 173 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
 174 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 175 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 176 extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
 177 extern void r300_set_reg_safe(struct radeon_device *rdev);
 178 extern void r300_mc_program(struct radeon_device *rdev);
 179 extern void r300_mc_init(struct radeon_device *rdev);
 180 extern void r300_clock_startup(struct radeon_device *rdev);
 181 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
 182 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
 183 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
 184 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
 185 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
 186 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
 187
 188 /*
 189  * r420,r423,rv410
 190  */
 191 extern int r420_init(struct radeon_device *rdev);
 192 extern void r420_fini(struct radeon_device *rdev);
 193 extern int r420_suspend(struct radeon_device *rdev);
 194 extern int r420_resume(struct radeon_device *rdev);
 195 extern void r420_pm_init_profile(struct radeon_device *rdev);
 196 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
 197 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
 198 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
 199 extern void r420_pipes_init(struct radeon_device *rdev);
 200
 201 /*
 202  * rs400,rs480
 203  */
 204 extern int rs400_init(struct radeon_device *rdev);
 205 extern void rs400_fini(struct radeon_device *rdev);
 206 extern int rs400_suspend(struct radeon_device *rdev);
 207 extern int rs400_resume(struct radeon_device *rdev);
 208 void rs400_gart_tlb_flush(struct radeon_device *rdev);
 209 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 210 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 211 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 212 int rs400_gart_init(struct radeon_device *rdev);
 213 int rs400_gart_enable(struct radeon_device *rdev);
 214 void rs400_gart_adjust_size(struct radeon_device *rdev);
 215 void rs400_gart_disable(struct radeon_device *rdev);
 216 void rs400_gart_fini(struct radeon_device *rdev);
 217 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
 218
 219 /*
 220  * rs600.
 221  */
 222 extern int rs600_asic_reset(struct radeon_device *rdev);
 223 extern int rs600_init(struct radeon_device *rdev);
 224 extern void rs600_fini(struct radeon_device *rdev);
 225 extern int rs600_suspend(struct radeon_device *rdev);
 226 extern int rs600_resume(struct radeon_device *rdev);
 227 int rs600_irq_set(struct radeon_device *rdev);
 228 int rs600_irq_process(struct radeon_device *rdev);
 229 void rs600_irq_disable(struct radeon_device *rdev);
 230 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
 231 void rs600_gart_tlb_flush(struct radeon_device *rdev);
 232 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 233 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 234 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 235 void rs600_bandwidth_update(struct radeon_device *rdev);
 236 void rs600_hpd_init(struct radeon_device *rdev);
 237 void rs600_hpd_fini(struct radeon_device *rdev);
 238 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 239 void rs600_hpd_set_polarity(struct radeon_device *rdev,
 240                             enum radeon_hpd_id hpd);
 241 extern void rs600_pm_misc(struct radeon_device *rdev);
 242 extern void rs600_pm_prepare(struct radeon_device *rdev);
 243 extern void rs600_pm_finish(struct radeon_device *rdev);
 244 extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
 245 extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 246 extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
 247 void rs600_set_safe_registers(struct radeon_device *rdev);
 248 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
 249 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
 250
 251 /*
 252  * rs690,rs740
 253  */
 254 int rs690_init(struct radeon_device *rdev);
 255 void rs690_fini(struct radeon_device *rdev);
 256 int rs690_resume(struct radeon_device *rdev);
 257 int rs690_suspend(struct radeon_device *rdev);
 258 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 259 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 260 void rs690_bandwidth_update(struct radeon_device *rdev);
 261 void rs690_line_buffer_adjust(struct radeon_device *rdev,
 262                                         struct drm_display_mode *mode1,
 263                                         struct drm_display_mode *mode2);
 264 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
 265
 266 /*
 267  * rv515
 268  */
 269 struct rv515_mc_save {
 270         u32 vga_render_control;
 271         u32 vga_hdp_control;
 272         bool crtc_enabled[2];
 273 };
 274
 275 int rv515_init(struct radeon_device *rdev);
 276 void rv515_fini(struct radeon_device *rdev);
 277 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 278 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 279 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
 280 void rv515_bandwidth_update(struct radeon_device *rdev);
 281 int rv515_resume(struct radeon_device *rdev);
 282 int rv515_suspend(struct radeon_device *rdev);
 283 void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
 284 void rv515_vga_render_disable(struct radeon_device *rdev);
 285 void rv515_set_safe_registers(struct radeon_device *rdev);
 286 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
 287 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
 288 void rv515_clock_startup(struct radeon_device *rdev);
 289 void rv515_debugfs(struct radeon_device *rdev);
 290 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
 291
 292 /*
 293  * r520,rv530,rv560,rv570,r580
 294  */
 295 int r520_init(struct radeon_device *rdev);
 296 int r520_resume(struct radeon_device *rdev);
 297 int r520_mc_wait_for_idle(struct radeon_device *rdev);
 298
 299 /*
 300  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
 301  */
 302 int r600_init(struct radeon_device *rdev);
 303 void r600_fini(struct radeon_device *rdev);
 304 int r600_suspend(struct radeon_device *rdev);
 305 int r600_resume(struct radeon_device *rdev);
 306 void r600_vga_set_state(struct radeon_device *rdev, bool state);
 307 int r600_wb_init(struct radeon_device *rdev);
 308 void r600_wb_fini(struct radeon_device *rdev);
 309 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
 310 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 311 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 312 int r600_cs_parse(struct radeon_cs_parser *p);
 313 int r600_dma_cs_parse(struct radeon_cs_parser *p);
 314 void r600_fence_ring_emit(struct radeon_device *rdev,
 315                           struct radeon_fence *fence);
 316 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
 317                               struct radeon_ring *cp,
 318                               struct radeon_semaphore *semaphore,
 319                               bool emit_wait);
 320 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
 321                               struct radeon_fence *fence);
 322 bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
 323                                   struct radeon_ring *ring,
 324                                   struct radeon_semaphore *semaphore,
 325                                   bool emit_wait);
 326 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 327 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 328 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 329 int r600_asic_reset(struct radeon_device *rdev);
 330 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
 331                          uint32_t tiling_flags, uint32_t pitch,
 332                          uint32_t offset, uint32_t obj_size);
 333 void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
 334 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 335 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 336 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 337 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 338 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 339 int r600_copy_cpdma(struct radeon_device *rdev,
 340                     uint64_t src_offset, uint64_t dst_offset,
 341                     unsigned num_gpu_pages, struct radeon_fence **fence);
 342 int r600_copy_dma(struct radeon_device *rdev,
 343                   uint64_t src_offset, uint64_t dst_offset,
 344                   unsigned num_gpu_pages, struct radeon_fence **fence);
 345 void r600_hpd_init(struct radeon_device *rdev);
 346 void r600_hpd_fini(struct radeon_device *rdev);
 347 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 348 void r600_hpd_set_polarity(struct radeon_device *rdev,
 349                            enum radeon_hpd_id hpd);
 350 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
 351 extern bool r600_gui_idle(struct radeon_device *rdev);
 352 extern void r600_pm_misc(struct radeon_device *rdev);
 353 extern void r600_pm_init_profile(struct radeon_device *rdev);
 354 extern void rs780_pm_init_profile(struct radeon_device *rdev);
 355 extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 356 extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 357 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
 358 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 359 extern int r600_get_pcie_lanes(struct radeon_device *rdev);
 360 bool r600_card_posted(struct radeon_device *rdev);
 361 void r600_cp_stop(struct radeon_device *rdev);
 362 int r600_cp_start(struct radeon_device *rdev);
 363 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
 364 int r600_cp_resume(struct radeon_device *rdev);
 365 void r600_cp_fini(struct radeon_device *rdev);
 366 int r600_count_pipe_bits(uint32_t val);
 367 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 368 int r600_pcie_gart_init(struct radeon_device *rdev);
 369 void r600_scratch_init(struct radeon_device *rdev);
 370 int r600_init_microcode(struct radeon_device *rdev);
 371 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
 372                       struct radeon_ring *ring);
 373 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
 374                       struct radeon_ring *ring);
 375 void r600_gfx_set_wptr(struct radeon_device *rdev,
 376                        struct radeon_ring *ring);
 377 /* r600 irq */
 378 int r600_irq_process(struct radeon_device *rdev);
 379 int r600_irq_init(struct radeon_device *rdev);
 380 void r600_irq_fini(struct radeon_device *rdev);
 381 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
 382 int r600_irq_set(struct radeon_device *rdev);
 383 void r600_irq_suspend(struct radeon_device *rdev);
 384 void r600_disable_interrupts(struct radeon_device *rdev);
 385 void r600_rlc_stop(struct radeon_device *rdev);
 386 /* r600 audio */
 387 int r600_audio_init(struct radeon_device *rdev);
 388 struct r600_audio_pin r600_audio_status(struct radeon_device *rdev);
 389 void r600_audio_fini(struct radeon_device *rdev);
 390 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
 391 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
 392 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
 393 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
 394 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 395 u32 r600_get_xclk(struct radeon_device *rdev);
 396 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
 397 int rv6xx_get_temp(struct radeon_device *rdev);
 398 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 399 int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
 400 void r600_dpm_post_set_power_state(struct radeon_device *rdev);
 401 int r600_dpm_late_enable(struct radeon_device *rdev);
 402 /* r600 dma */
 403 uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
 404                            struct radeon_ring *ring);
 405 uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
 406                            struct radeon_ring *ring);
 407 void r600_dma_set_wptr(struct radeon_device *rdev,
 408                        struct radeon_ring *ring);
 409 /* rv6xx dpm */
 410 int rv6xx_dpm_init(struct radeon_device *rdev);
 411 int rv6xx_dpm_enable(struct radeon_device *rdev);
 412 void rv6xx_dpm_disable(struct radeon_device *rdev);
 413 int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
 414 void rv6xx_setup_asic(struct radeon_device *rdev);
 415 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
 416 void rv6xx_dpm_fini(struct radeon_device *rdev);
 417 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
 418 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
 419 void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
 420                                  struct radeon_ps *ps);
 421 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 422                                                        struct seq_file *m);
 423 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
 424                                       enum radeon_dpm_forced_level level);
 425 /* rs780 dpm */
 426 int rs780_dpm_init(struct radeon_device *rdev);
 427 int rs780_dpm_enable(struct radeon_device *rdev);
 428 void rs780_dpm_disable(struct radeon_device *rdev);
 429 int rs780_dpm_set_power_state(struct radeon_device *rdev);
 430 void rs780_dpm_setup_asic(struct radeon_device *rdev);
 431 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
 432 void rs780_dpm_fini(struct radeon_device *rdev);
 433 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
 434 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
 435 void rs780_dpm_print_power_state(struct radeon_device *rdev,
 436                                  struct radeon_ps *ps);
 437 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 438                                                        struct seq_file *m);
 439 int rs780_dpm_force_performance_level(struct radeon_device *rdev,
 440                                       enum radeon_dpm_forced_level level);
 441
 442 /*
 443  * rv770,rv730,rv710,rv740
 444  */
 445 int rv770_init(struct radeon_device *rdev);
 446 void rv770_fini(struct radeon_device *rdev);
 447 int rv770_suspend(struct radeon_device *rdev);
 448 int rv770_resume(struct radeon_device *rdev);
 449 void rv770_pm_misc(struct radeon_device *rdev);
 450 u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 451 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
 452 void r700_cp_stop(struct radeon_device *rdev);
 453 void r700_cp_fini(struct radeon_device *rdev);
 454 int rv770_copy_dma(struct radeon_device *rdev,
 455                   uint64_t src_offset, uint64_t dst_offset,
 456                   unsigned num_gpu_pages,
 457                    struct radeon_fence **fence);
 458 u32 rv770_get_xclk(struct radeon_device *rdev);
 459 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 460 int rv770_get_temp(struct radeon_device *rdev);
 461 /* rv7xx pm */
 462 int rv770_dpm_init(struct radeon_device *rdev);
 463 int rv770_dpm_enable(struct radeon_device *rdev);
 464 int rv770_dpm_late_enable(struct radeon_device *rdev);
 465 void rv770_dpm_disable(struct radeon_device *rdev);
 466 int rv770_dpm_set_power_state(struct radeon_device *rdev);
 467 void rv770_dpm_setup_asic(struct radeon_device *rdev);
 468 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
 469 void rv770_dpm_fini(struct radeon_device *rdev);
 470 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
 471 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
 472 void rv770_dpm_print_power_state(struct radeon_device *rdev,
 473                                  struct radeon_ps *ps);
 474 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 475                                                        struct seq_file *m);
 476 int rv770_dpm_force_performance_level(struct radeon_device *rdev,
 477                                       enum radeon_dpm_forced_level level);
 478 bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
 479
 480 /*
 481  * evergreen
 482  */
 483 struct evergreen_mc_save {
 484         u32 vga_render_control;
 485         u32 vga_hdp_control;
 486         bool crtc_enabled[RADEON_MAX_CRTCS];
 487 };
 488
 489 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
 490 int evergreen_init(struct radeon_device *rdev);
 491 void evergreen_fini(struct radeon_device *rdev);
 492 int evergreen_suspend(struct radeon_device *rdev);
 493 int evergreen_resume(struct radeon_device *rdev);
 494 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 495 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 496 int evergreen_asic_reset(struct radeon_device *rdev);
 497 void evergreen_bandwidth_update(struct radeon_device *rdev);
 498 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 499 void evergreen_hpd_init(struct radeon_device *rdev);
 500 void evergreen_hpd_fini(struct radeon_device *rdev);
 501 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 502 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 503                                 enum radeon_hpd_id hpd);
 504 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
 505 int evergreen_irq_set(struct radeon_device *rdev);
 506 int evergreen_irq_process(struct radeon_device *rdev);
 507 extern int evergreen_cs_parse(struct radeon_cs_parser *p);
 508 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
 509 extern void evergreen_pm_misc(struct radeon_device *rdev);
 510 extern void evergreen_pm_prepare(struct radeon_device *rdev);
 511 extern void evergreen_pm_finish(struct radeon_device *rdev);
 512 extern void sumo_pm_init_profile(struct radeon_device *rdev);
 513 extern void btc_pm_init_profile(struct radeon_device *rdev);
 514 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 515 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 516 extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
 517 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 518 extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
 519 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
 520 void evergreen_disable_interrupt_state(struct radeon_device *rdev);
 521 int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
 522 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
 523                                    struct radeon_fence *fence);
 524 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
 525                                    struct radeon_ib *ib);
 526 int evergreen_copy_dma(struct radeon_device *rdev,
 527                        uint64_t src_offset, uint64_t dst_offset,
 528                        unsigned num_gpu_pages,
 529                        struct radeon_fence **fence);
 530 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
 531 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
 532 int evergreen_get_temp(struct radeon_device *rdev);
 533 int sumo_get_temp(struct radeon_device *rdev);
 534 int tn_get_temp(struct radeon_device *rdev);
 535 int cypress_dpm_init(struct radeon_device *rdev);
 536 void cypress_dpm_setup_asic(struct radeon_device *rdev);
 537 int cypress_dpm_enable(struct radeon_device *rdev);
 538 void cypress_dpm_disable(struct radeon_device *rdev);
 539 int cypress_dpm_set_power_state(struct radeon_device *rdev);
 540 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
 541 void cypress_dpm_fini(struct radeon_device *rdev);
 542 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
 543 int btc_dpm_init(struct radeon_device *rdev);
 544 void btc_dpm_setup_asic(struct radeon_device *rdev);
 545 int btc_dpm_enable(struct radeon_device *rdev);
 546 void btc_dpm_disable(struct radeon_device *rdev);
 547 int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
 548 int btc_dpm_set_power_state(struct radeon_device *rdev);
 549 void btc_dpm_post_set_power_state(struct radeon_device *rdev);
 550 void btc_dpm_fini(struct radeon_device *rdev);
 551 u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
 552 u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
 553 bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
 554 void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 555                                                      struct seq_file *m);
 556 int sumo_dpm_init(struct radeon_device *rdev);
 557 int sumo_dpm_enable(struct radeon_device *rdev);
 558 int sumo_dpm_late_enable(struct radeon_device *rdev);
 559 void sumo_dpm_disable(struct radeon_device *rdev);
 560 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
 561 int sumo_dpm_set_power_state(struct radeon_device *rdev);
 562 void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
 563 void sumo_dpm_setup_asic(struct radeon_device *rdev);
 564 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
 565 void sumo_dpm_fini(struct radeon_device *rdev);
 566 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
 567 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
 568 void sumo_dpm_print_power_state(struct radeon_device *rdev,
 569                                 struct radeon_ps *ps);
 570 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 571                                                       struct seq_file *m);
 572 int sumo_dpm_force_performance_level(struct radeon_device *rdev,
 573                                      enum radeon_dpm_forced_level level);
 574
 575 /*
 576  * cayman
 577  */
 578 void cayman_fence_ring_emit(struct radeon_device *rdev,
 579                             struct radeon_fence *fence);
 580 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
 581 int cayman_init(struct radeon_device *rdev);
 582 void cayman_fini(struct radeon_device *rdev);
 583 int cayman_suspend(struct radeon_device *rdev);
 584 int cayman_resume(struct radeon_device *rdev);
 585 int cayman_asic_reset(struct radeon_device *rdev);
 586 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 587 int cayman_vm_init(struct radeon_device *rdev);
 588 void cayman_vm_fini(struct radeon_device *rdev);
 589 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 590 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
 591 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 592 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 593 void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
 594                                 struct radeon_ib *ib);
 595 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 596 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 597 void cayman_dma_vm_set_page(struct radeon_device *rdev,
 598                             struct radeon_ib *ib,
 599                             uint64_t pe,
 600                             uint64_t addr, unsigned count,
 601                             uint32_t incr, uint32_t flags);
 602
 603 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 604
 605 u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
 606                         struct radeon_ring *ring);
 607 u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
 608                         struct radeon_ring *ring);
 609 void cayman_gfx_set_wptr(struct radeon_device *rdev,
 610                          struct radeon_ring *ring);
 611 uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
 612                              struct radeon_ring *ring);
 613 uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
 614                              struct radeon_ring *ring);
 615 void cayman_dma_set_wptr(struct radeon_device *rdev,
 616                          struct radeon_ring *ring);
 617
 618 int ni_dpm_init(struct radeon_device *rdev);
 619 void ni_dpm_setup_asic(struct radeon_device *rdev);
 620 int ni_dpm_enable(struct radeon_device *rdev);
 621 void ni_dpm_disable(struct radeon_device *rdev);
 622 int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
 623 int ni_dpm_set_power_state(struct radeon_device *rdev);
 624 void ni_dpm_post_set_power_state(struct radeon_device *rdev);
 625 void ni_dpm_fini(struct radeon_device *rdev);
 626 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
 627 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
 628 void ni_dpm_print_power_state(struct radeon_device *rdev,
 629                               struct radeon_ps *ps);
 630 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 631                                                     struct seq_file *m);
 632 int ni_dpm_force_performance_level(struct radeon_device *rdev,
 633                                    enum radeon_dpm_forced_level level);
 634 bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
 635 int trinity_dpm_init(struct radeon_device *rdev);
 636 int trinity_dpm_enable(struct radeon_device *rdev);
 637 int trinity_dpm_late_enable(struct radeon_device *rdev);
 638 void trinity_dpm_disable(struct radeon_device *rdev);
 639 int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
 640 int trinity_dpm_set_power_state(struct radeon_device *rdev);
 641 void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
 642 void trinity_dpm_setup_asic(struct radeon_device *rdev);
 643 void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
 644 void trinity_dpm_fini(struct radeon_device *rdev);
 645 u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
 646 u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
 647 void trinity_dpm_print_power_state(struct radeon_device *rdev,
 648                                    struct radeon_ps *ps);
 649 void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 650                                                          struct seq_file *m);
 651 int trinity_dpm_force_performance_level(struct radeon_device *rdev,
 652                                         enum radeon_dpm_forced_level level);
 653 void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
 654
 655 /* DCE6 - SI */
 656 void dce6_bandwidth_update(struct radeon_device *rdev);
 657 int dce6_audio_init(struct radeon_device *rdev);
 658 void dce6_audio_fini(struct radeon_device *rdev);
 659
 660 /*
 661  * si
 662  */
 663 void si_fence_ring_emit(struct radeon_device *rdev,
 664                         struct radeon_fence *fence);
 665 void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
 666 int si_init(struct radeon_device *rdev);
 667 void si_fini(struct radeon_device *rdev);
 668 int si_suspend(struct radeon_device *rdev);
 669 int si_resume(struct radeon_device *rdev);
 670 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 671 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 672 int si_asic_reset(struct radeon_device *rdev);
 673 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 674 int si_irq_set(struct radeon_device *rdev);
 675 int si_irq_process(struct radeon_device *rdev);
 676 int si_vm_init(struct radeon_device *rdev);
 677 void si_vm_fini(struct radeon_device *rdev);
 678 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 679 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 680 int si_copy_dma(struct radeon_device *rdev,
 681                 uint64_t src_offset, uint64_t dst_offset,
 682                 unsigned num_gpu_pages,
 683                 struct radeon_fence **fence);
 684 void si_dma_vm_set_page(struct radeon_device *rdev,
 685                         struct radeon_ib *ib,
 686                         uint64_t pe,
 687                         uint64_t addr, unsigned count,
 688                         uint32_t incr, uint32_t flags);
 689 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 690 u32 si_get_xclk(struct radeon_device *rdev);
 691 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
 692 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 693 int si_get_temp(struct radeon_device *rdev);
 694 int si_dpm_init(struct radeon_device *rdev);
 695 void si_dpm_setup_asic(struct radeon_device *rdev);
 696 int si_dpm_enable(struct radeon_device *rdev);
 697 int si_dpm_late_enable(struct radeon_device *rdev);
 698 void si_dpm_disable(struct radeon_device *rdev);
 699 int si_dpm_pre_set_power_state(struct radeon_device *rdev);
 700 int si_dpm_set_power_state(struct radeon_device *rdev);
 701 void si_dpm_post_set_power_state(struct radeon_device *rdev);
 702 void si_dpm_fini(struct radeon_device *rdev);
 703 void si_dpm_display_configuration_changed(struct radeon_device *rdev);
 704 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 705                                                     struct seq_file *m);
 706 int si_dpm_force_performance_level(struct radeon_device *rdev,
 707                                    enum radeon_dpm_forced_level level);
 708
 709 /* DCE8 - CIK */
 710 void dce8_bandwidth_update(struct radeon_device *rdev);
 711
 712 /*
 713  * cik
 714  */
 715 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
 716 u32 cik_get_xclk(struct radeon_device *rdev);
 717 uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 718 void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 719 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 720 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
 721 void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
 722                               struct radeon_fence *fence);
 723 bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
 724                                   struct radeon_ring *ring,
 725                                   struct radeon_semaphore *semaphore,
 726                                   bool emit_wait);
 727 void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 728 int cik_copy_dma(struct radeon_device *rdev,
 729                  uint64_t src_offset, uint64_t dst_offset,
 730                  unsigned num_gpu_pages,
 731                  struct radeon_fence **fence);
 732 int cik_copy_cpdma(struct radeon_device *rdev,
 733                    uint64_t src_offset, uint64_t dst_offset,
 734                    unsigned num_gpu_pages,
 735                    struct radeon_fence **fence);
 736 int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
 737 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 738 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 739 void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
 740                              struct radeon_fence *fence);
 741 void cik_fence_compute_ring_emit(struct radeon_device *rdev,
 742                                  struct radeon_fence *fence);
 743 bool cik_semaphore_ring_emit(struct radeon_device *rdev,
 744                              struct radeon_ring *cp,
 745                              struct radeon_semaphore *semaphore,
 746                              bool emit_wait);
 747 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
 748 int cik_init(struct radeon_device *rdev);
 749 void cik_fini(struct radeon_device *rdev);
 750 int cik_suspend(struct radeon_device *rdev);
 751 int cik_resume(struct radeon_device *rdev);
 752 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 753 int cik_asic_reset(struct radeon_device *rdev);
 754 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 755 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
 756 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 757 int cik_irq_set(struct radeon_device *rdev);
 758 int cik_irq_process(struct radeon_device *rdev);
 759 int cik_vm_init(struct radeon_device *rdev);
 760 void cik_vm_fini(struct radeon_device *rdev);
 761 void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 762 void cik_sdma_vm_set_page(struct radeon_device *rdev,
 763                           struct radeon_ib *ib,
 764                           uint64_t pe,
 765                           uint64_t addr, unsigned count,
 766                           uint32_t incr, uint32_t flags);
 767 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 768 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 769 u32 cik_gfx_get_rptr(struct radeon_device *rdev,
 770                      struct radeon_ring *ring);
 771 u32 cik_gfx_get_wptr(struct radeon_device *rdev,
 772                      struct radeon_ring *ring);
 773 void cik_gfx_set_wptr(struct radeon_device *rdev,
 774                       struct radeon_ring *ring);
 775 u32 cik_compute_get_rptr(struct radeon_device *rdev,
 776                          struct radeon_ring *ring);
 777 u32 cik_compute_get_wptr(struct radeon_device *rdev,
 778                          struct radeon_ring *ring);
 779 void cik_compute_set_wptr(struct radeon_device *rdev,
 780                           struct radeon_ring *ring);
 781 u32 cik_sdma_get_rptr(struct radeon_device *rdev,
 782                       struct radeon_ring *ring);
 783 u32 cik_sdma_get_wptr(struct radeon_device *rdev,
 784                       struct radeon_ring *ring);
 785 void cik_sdma_set_wptr(struct radeon_device *rdev,
 786                        struct radeon_ring *ring);
 787 int ci_get_temp(struct radeon_device *rdev);
 788 int kv_get_temp(struct radeon_device *rdev);
 789
 790 int ci_dpm_init(struct radeon_device *rdev);
 791 int ci_dpm_enable(struct radeon_device *rdev);
 792 int ci_dpm_late_enable(struct radeon_device *rdev);
 793 void ci_dpm_disable(struct radeon_device *rdev);
 794 int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
 795 int ci_dpm_set_power_state(struct radeon_device *rdev);
 796 void ci_dpm_post_set_power_state(struct radeon_device *rdev);
 797 void ci_dpm_setup_asic(struct radeon_device *rdev);
 798 void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
 799 void ci_dpm_fini(struct radeon_device *rdev);
 800 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
 801 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
 802 void ci_dpm_print_power_state(struct radeon_device *rdev,
 803                               struct radeon_ps *ps);
 804 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 805                                                     struct seq_file *m);
 806 int ci_dpm_force_performance_level(struct radeon_device *rdev,
 807                                    enum radeon_dpm_forced_level level);
 808 bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
 809 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
 810
 811 int kv_dpm_init(struct radeon_device *rdev);
 812 int kv_dpm_enable(struct radeon_device *rdev);
 813 int kv_dpm_late_enable(struct radeon_device *rdev);
 814 void kv_dpm_disable(struct radeon_device *rdev);
 815 int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
 816 int kv_dpm_set_power_state(struct radeon_device *rdev);
 817 void kv_dpm_post_set_power_state(struct radeon_device *rdev);
 818 void kv_dpm_setup_asic(struct radeon_device *rdev);
 819 void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
 820 void kv_dpm_fini(struct radeon_device *rdev);
 821 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
 822 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
 823 void kv_dpm_print_power_state(struct radeon_device *rdev,
 824                               struct radeon_ps *ps);
 825 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 826                                                     struct seq_file *m);
 827 int kv_dpm_force_performance_level(struct radeon_device *rdev,
 828                                    enum radeon_dpm_forced_level level);
 829 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
 830 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
 831
 832 /* uvd v1.0 */
 833 uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
 834                            struct radeon_ring *ring);
 835 uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
 836                            struct radeon_ring *ring);
 837 void uvd_v1_0_set_wptr(struct radeon_device *rdev,
 838                        struct radeon_ring *ring);
 839
 840 int uvd_v1_0_init(struct radeon_device *rdev);
 841 void uvd_v1_0_fini(struct radeon_device *rdev);
 842 int uvd_v1_0_start(struct radeon_device *rdev);
 843 void uvd_v1_0_stop(struct radeon_device *rdev);
 844
 845 int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
 846 int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 847 bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
 848                              struct radeon_ring *ring,
 849                              struct radeon_semaphore *semaphore,
 850                              bool emit_wait);
 851 void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 852
 853 /* uvd v2.2 */
 854 int uvd_v2_2_resume(struct radeon_device *rdev);
 855 void uvd_v2_2_fence_emit(struct radeon_device *rdev,
 856                          struct radeon_fence *fence);
 857
 858 /* uvd v3.1 */
 859 bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
 860                              struct radeon_ring *ring,
 861                              struct radeon_semaphore *semaphore,
 862                              bool emit_wait);
 863
 864 /* uvd v4.2 */
 865 int uvd_v4_2_resume(struct radeon_device *rdev);
 866
 867 /* vce v1.0 */
 868 uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
 869                            struct radeon_ring *ring);
 870 uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
 871                            struct radeon_ring *ring);
 872 void vce_v1_0_set_wptr(struct radeon_device *rdev,
 873                        struct radeon_ring *ring);
 874 int vce_v1_0_init(struct radeon_device *rdev);
 875 int vce_v1_0_start(struct radeon_device *rdev);
 876
 877 /* vce v2.0 */
 878 int vce_v2_0_resume(struct radeon_device *rdev);
 879
 880 #endif