2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #ifndef __RADEON_ASIC_H__
29 #define __RADEON_ASIC_H__
34 void radeon_legacy_set_engine_clock(struct radeon_device
*rdev
, uint32_t eng_clock
);
35 void radeon_legacy_set_clock_gating(struct radeon_device
*rdev
, int enable
);
37 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
, uint32_t eng_clock
);
38 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
, uint32_t mem_clock
);
39 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
);
42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
44 int r100_init(struct radeon_device
*rdev
);
45 int r200_init(struct radeon_device
*rdev
);
46 uint32_t r100_mm_rreg(struct radeon_device
*rdev
, uint32_t reg
);
47 void r100_mm_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
48 void r100_errata(struct radeon_device
*rdev
);
49 void r100_vram_info(struct radeon_device
*rdev
);
50 int r100_gpu_reset(struct radeon_device
*rdev
);
51 int r100_mc_init(struct radeon_device
*rdev
);
52 void r100_mc_fini(struct radeon_device
*rdev
);
53 u32
r100_get_vblank_counter(struct radeon_device
*rdev
, int crtc
);
54 int r100_wb_init(struct radeon_device
*rdev
);
55 void r100_wb_fini(struct radeon_device
*rdev
);
56 int r100_gart_enable(struct radeon_device
*rdev
);
57 void r100_pci_gart_disable(struct radeon_device
*rdev
);
58 void r100_pci_gart_tlb_flush(struct radeon_device
*rdev
);
59 int r100_pci_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
60 int r100_cp_init(struct radeon_device
*rdev
, unsigned ring_size
);
61 void r100_cp_fini(struct radeon_device
*rdev
);
62 void r100_cp_disable(struct radeon_device
*rdev
);
63 void r100_cp_commit(struct radeon_device
*rdev
);
64 void r100_ring_start(struct radeon_device
*rdev
);
65 int r100_irq_set(struct radeon_device
*rdev
);
66 int r100_irq_process(struct radeon_device
*rdev
);
67 void r100_fence_ring_emit(struct radeon_device
*rdev
,
68 struct radeon_fence
*fence
);
69 int r100_cs_parse(struct radeon_cs_parser
*p
);
70 void r100_pll_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
71 uint32_t r100_pll_rreg(struct radeon_device
*rdev
, uint32_t reg
);
72 int r100_copy_blit(struct radeon_device
*rdev
,
76 struct radeon_fence
*fence
);
77 int r100_set_surface_reg(struct radeon_device
*rdev
, int reg
,
78 uint32_t tiling_flags
, uint32_t pitch
,
79 uint32_t offset
, uint32_t obj_size
);
80 int r100_clear_surface_reg(struct radeon_device
*rdev
, int reg
);
81 void r100_bandwidth_update(struct radeon_device
*rdev
);
82 void r100_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
83 int r100_ib_test(struct radeon_device
*rdev
);
84 int r100_ring_test(struct radeon_device
*rdev
);
86 static struct radeon_asic r100_asic
= {
88 .errata
= &r100_errata
,
89 .vram_info
= &r100_vram_info
,
90 .gpu_reset
= &r100_gpu_reset
,
91 .mc_init
= &r100_mc_init
,
92 .mc_fini
= &r100_mc_fini
,
93 .wb_init
= &r100_wb_init
,
94 .wb_fini
= &r100_wb_fini
,
95 .gart_enable
= &r100_gart_enable
,
96 .gart_disable
= &r100_pci_gart_disable
,
97 .gart_tlb_flush
= &r100_pci_gart_tlb_flush
,
98 .gart_set_page
= &r100_pci_gart_set_page
,
99 .cp_init
= &r100_cp_init
,
100 .cp_fini
= &r100_cp_fini
,
101 .cp_disable
= &r100_cp_disable
,
102 .cp_commit
= &r100_cp_commit
,
103 .ring_start
= &r100_ring_start
,
104 .ring_test
= &r100_ring_test
,
105 .ring_ib_execute
= &r100_ring_ib_execute
,
106 .ib_test
= &r100_ib_test
,
107 .irq_set
= &r100_irq_set
,
108 .irq_process
= &r100_irq_process
,
109 .get_vblank_counter
= &r100_get_vblank_counter
,
110 .fence_ring_emit
= &r100_fence_ring_emit
,
111 .cs_parse
= &r100_cs_parse
,
112 .copy_blit
= &r100_copy_blit
,
114 .copy
= &r100_copy_blit
,
115 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
116 .set_memory_clock
= NULL
,
117 .set_pcie_lanes
= NULL
,
118 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
119 .set_surface_reg
= r100_set_surface_reg
,
120 .clear_surface_reg
= r100_clear_surface_reg
,
121 .bandwidth_update
= &r100_bandwidth_update
,
126 * r300,r350,rv350,rv380
128 int r300_init(struct radeon_device
*rdev
);
129 void r300_errata(struct radeon_device
*rdev
);
130 void r300_vram_info(struct radeon_device
*rdev
);
131 int r300_gpu_reset(struct radeon_device
*rdev
);
132 int r300_mc_init(struct radeon_device
*rdev
);
133 void r300_mc_fini(struct radeon_device
*rdev
);
134 void r300_ring_start(struct radeon_device
*rdev
);
135 void r300_fence_ring_emit(struct radeon_device
*rdev
,
136 struct radeon_fence
*fence
);
137 int r300_cs_parse(struct radeon_cs_parser
*p
);
138 int r300_gart_enable(struct radeon_device
*rdev
);
139 void rv370_pcie_gart_disable(struct radeon_device
*rdev
);
140 void rv370_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
141 int rv370_pcie_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
142 uint32_t rv370_pcie_rreg(struct radeon_device
*rdev
, uint32_t reg
);
143 void rv370_pcie_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
144 void rv370_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
);
145 int r300_copy_dma(struct radeon_device
*rdev
,
149 struct radeon_fence
*fence
);
151 static struct radeon_asic r300_asic
= {
153 .errata
= &r300_errata
,
154 .vram_info
= &r300_vram_info
,
155 .gpu_reset
= &r300_gpu_reset
,
156 .mc_init
= &r300_mc_init
,
157 .mc_fini
= &r300_mc_fini
,
158 .wb_init
= &r100_wb_init
,
159 .wb_fini
= &r100_wb_fini
,
160 .gart_enable
= &r300_gart_enable
,
161 .gart_disable
= &r100_pci_gart_disable
,
162 .gart_tlb_flush
= &r100_pci_gart_tlb_flush
,
163 .gart_set_page
= &r100_pci_gart_set_page
,
164 .cp_init
= &r100_cp_init
,
165 .cp_fini
= &r100_cp_fini
,
166 .cp_disable
= &r100_cp_disable
,
167 .cp_commit
= &r100_cp_commit
,
168 .ring_start
= &r300_ring_start
,
169 .ring_test
= &r100_ring_test
,
170 .ring_ib_execute
= &r100_ring_ib_execute
,
171 .ib_test
= &r100_ib_test
,
172 .irq_set
= &r100_irq_set
,
173 .irq_process
= &r100_irq_process
,
174 .get_vblank_counter
= &r100_get_vblank_counter
,
175 .fence_ring_emit
= &r300_fence_ring_emit
,
176 .cs_parse
= &r300_cs_parse
,
177 .copy_blit
= &r100_copy_blit
,
178 .copy_dma
= &r300_copy_dma
,
179 .copy
= &r100_copy_blit
,
180 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
181 .set_memory_clock
= NULL
,
182 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
183 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
184 .set_surface_reg
= r100_set_surface_reg
,
185 .clear_surface_reg
= r100_clear_surface_reg
,
186 .bandwidth_update
= &r100_bandwidth_update
,
192 void r420_errata(struct radeon_device
*rdev
);
193 void r420_vram_info(struct radeon_device
*rdev
);
194 int r420_mc_init(struct radeon_device
*rdev
);
195 void r420_mc_fini(struct radeon_device
*rdev
);
196 static struct radeon_asic r420_asic
= {
198 .errata
= &r420_errata
,
199 .vram_info
= &r420_vram_info
,
200 .gpu_reset
= &r300_gpu_reset
,
201 .mc_init
= &r420_mc_init
,
202 .mc_fini
= &r420_mc_fini
,
203 .wb_init
= &r100_wb_init
,
204 .wb_fini
= &r100_wb_fini
,
205 .gart_enable
= &r300_gart_enable
,
206 .gart_disable
= &rv370_pcie_gart_disable
,
207 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
208 .gart_set_page
= &rv370_pcie_gart_set_page
,
209 .cp_init
= &r100_cp_init
,
210 .cp_fini
= &r100_cp_fini
,
211 .cp_disable
= &r100_cp_disable
,
212 .cp_commit
= &r100_cp_commit
,
213 .ring_start
= &r300_ring_start
,
214 .ring_test
= &r100_ring_test
,
215 .ring_ib_execute
= &r100_ring_ib_execute
,
216 .ib_test
= &r100_ib_test
,
217 .irq_set
= &r100_irq_set
,
218 .irq_process
= &r100_irq_process
,
219 .get_vblank_counter
= &r100_get_vblank_counter
,
220 .fence_ring_emit
= &r300_fence_ring_emit
,
221 .cs_parse
= &r300_cs_parse
,
222 .copy_blit
= &r100_copy_blit
,
223 .copy_dma
= &r300_copy_dma
,
224 .copy
= &r100_copy_blit
,
225 .set_engine_clock
= &radeon_atom_set_engine_clock
,
226 .set_memory_clock
= &radeon_atom_set_memory_clock
,
227 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
228 .set_clock_gating
= &radeon_atom_set_clock_gating
,
229 .set_surface_reg
= r100_set_surface_reg
,
230 .clear_surface_reg
= r100_clear_surface_reg
,
231 .bandwidth_update
= &r100_bandwidth_update
,
238 void rs400_errata(struct radeon_device
*rdev
);
239 void rs400_vram_info(struct radeon_device
*rdev
);
240 int rs400_mc_init(struct radeon_device
*rdev
);
241 void rs400_mc_fini(struct radeon_device
*rdev
);
242 int rs400_gart_enable(struct radeon_device
*rdev
);
243 void rs400_gart_disable(struct radeon_device
*rdev
);
244 void rs400_gart_tlb_flush(struct radeon_device
*rdev
);
245 int rs400_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
246 uint32_t rs400_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
247 void rs400_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
248 static struct radeon_asic rs400_asic
= {
250 .errata
= &rs400_errata
,
251 .vram_info
= &rs400_vram_info
,
252 .gpu_reset
= &r300_gpu_reset
,
253 .mc_init
= &rs400_mc_init
,
254 .mc_fini
= &rs400_mc_fini
,
255 .wb_init
= &r100_wb_init
,
256 .wb_fini
= &r100_wb_fini
,
257 .gart_enable
= &rs400_gart_enable
,
258 .gart_disable
= &rs400_gart_disable
,
259 .gart_tlb_flush
= &rs400_gart_tlb_flush
,
260 .gart_set_page
= &rs400_gart_set_page
,
261 .cp_init
= &r100_cp_init
,
262 .cp_fini
= &r100_cp_fini
,
263 .cp_disable
= &r100_cp_disable
,
264 .cp_commit
= &r100_cp_commit
,
265 .ring_start
= &r300_ring_start
,
266 .ring_test
= &r100_ring_test
,
267 .ring_ib_execute
= &r100_ring_ib_execute
,
268 .ib_test
= &r100_ib_test
,
269 .irq_set
= &r100_irq_set
,
270 .irq_process
= &r100_irq_process
,
271 .get_vblank_counter
= &r100_get_vblank_counter
,
272 .fence_ring_emit
= &r300_fence_ring_emit
,
273 .cs_parse
= &r300_cs_parse
,
274 .copy_blit
= &r100_copy_blit
,
275 .copy_dma
= &r300_copy_dma
,
276 .copy
= &r100_copy_blit
,
277 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
278 .set_memory_clock
= NULL
,
279 .set_pcie_lanes
= NULL
,
280 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
281 .set_surface_reg
= r100_set_surface_reg
,
282 .clear_surface_reg
= r100_clear_surface_reg
,
283 .bandwidth_update
= &r100_bandwidth_update
,
290 int rs600_init(struct radeon_device
*rdev
);
291 void rs600_errata(struct radeon_device
*rdev
);
292 void rs600_vram_info(struct radeon_device
*rdev
);
293 int rs600_mc_init(struct radeon_device
*rdev
);
294 void rs600_mc_fini(struct radeon_device
*rdev
);
295 int rs600_irq_set(struct radeon_device
*rdev
);
296 int rs600_irq_process(struct radeon_device
*rdev
);
297 u32
rs600_get_vblank_counter(struct radeon_device
*rdev
, int crtc
);
298 int rs600_gart_enable(struct radeon_device
*rdev
);
299 void rs600_gart_disable(struct radeon_device
*rdev
);
300 void rs600_gart_tlb_flush(struct radeon_device
*rdev
);
301 int rs600_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
302 uint32_t rs600_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
303 void rs600_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
304 void rs600_bandwidth_update(struct radeon_device
*rdev
);
305 static struct radeon_asic rs600_asic
= {
307 .errata
= &rs600_errata
,
308 .vram_info
= &rs600_vram_info
,
309 .gpu_reset
= &r300_gpu_reset
,
310 .mc_init
= &rs600_mc_init
,
311 .mc_fini
= &rs600_mc_fini
,
312 .wb_init
= &r100_wb_init
,
313 .wb_fini
= &r100_wb_fini
,
314 .gart_enable
= &rs600_gart_enable
,
315 .gart_disable
= &rs600_gart_disable
,
316 .gart_tlb_flush
= &rs600_gart_tlb_flush
,
317 .gart_set_page
= &rs600_gart_set_page
,
318 .cp_init
= &r100_cp_init
,
319 .cp_fini
= &r100_cp_fini
,
320 .cp_disable
= &r100_cp_disable
,
321 .cp_commit
= &r100_cp_commit
,
322 .ring_start
= &r300_ring_start
,
323 .ring_test
= &r100_ring_test
,
324 .ring_ib_execute
= &r100_ring_ib_execute
,
325 .ib_test
= &r100_ib_test
,
326 .irq_set
= &rs600_irq_set
,
327 .irq_process
= &rs600_irq_process
,
328 .get_vblank_counter
= &rs600_get_vblank_counter
,
329 .fence_ring_emit
= &r300_fence_ring_emit
,
330 .cs_parse
= &r300_cs_parse
,
331 .copy_blit
= &r100_copy_blit
,
332 .copy_dma
= &r300_copy_dma
,
333 .copy
= &r100_copy_blit
,
334 .set_engine_clock
= &radeon_atom_set_engine_clock
,
335 .set_memory_clock
= &radeon_atom_set_memory_clock
,
336 .set_pcie_lanes
= NULL
,
337 .set_clock_gating
= &radeon_atom_set_clock_gating
,
338 .bandwidth_update
= &rs600_bandwidth_update
,
345 void rs690_errata(struct radeon_device
*rdev
);
346 void rs690_vram_info(struct radeon_device
*rdev
);
347 int rs690_mc_init(struct radeon_device
*rdev
);
348 void rs690_mc_fini(struct radeon_device
*rdev
);
349 uint32_t rs690_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
350 void rs690_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
351 void rs690_bandwidth_update(struct radeon_device
*rdev
);
352 static struct radeon_asic rs690_asic
= {
354 .errata
= &rs690_errata
,
355 .vram_info
= &rs690_vram_info
,
356 .gpu_reset
= &r300_gpu_reset
,
357 .mc_init
= &rs690_mc_init
,
358 .mc_fini
= &rs690_mc_fini
,
359 .wb_init
= &r100_wb_init
,
360 .wb_fini
= &r100_wb_fini
,
361 .gart_enable
= &rs400_gart_enable
,
362 .gart_disable
= &rs400_gart_disable
,
363 .gart_tlb_flush
= &rs400_gart_tlb_flush
,
364 .gart_set_page
= &rs400_gart_set_page
,
365 .cp_init
= &r100_cp_init
,
366 .cp_fini
= &r100_cp_fini
,
367 .cp_disable
= &r100_cp_disable
,
368 .cp_commit
= &r100_cp_commit
,
369 .ring_start
= &r300_ring_start
,
370 .ring_test
= &r100_ring_test
,
371 .ring_ib_execute
= &r100_ring_ib_execute
,
372 .ib_test
= &r100_ib_test
,
373 .irq_set
= &rs600_irq_set
,
374 .irq_process
= &rs600_irq_process
,
375 .get_vblank_counter
= &rs600_get_vblank_counter
,
376 .fence_ring_emit
= &r300_fence_ring_emit
,
377 .cs_parse
= &r300_cs_parse
,
378 .copy_blit
= &r100_copy_blit
,
379 .copy_dma
= &r300_copy_dma
,
380 .copy
= &r300_copy_dma
,
381 .set_engine_clock
= &radeon_atom_set_engine_clock
,
382 .set_memory_clock
= &radeon_atom_set_memory_clock
,
383 .set_pcie_lanes
= NULL
,
384 .set_clock_gating
= &radeon_atom_set_clock_gating
,
385 .set_surface_reg
= r100_set_surface_reg
,
386 .clear_surface_reg
= r100_clear_surface_reg
,
387 .bandwidth_update
= &rs690_bandwidth_update
,
394 int rv515_init(struct radeon_device
*rdev
);
395 void rv515_errata(struct radeon_device
*rdev
);
396 void rv515_vram_info(struct radeon_device
*rdev
);
397 int rv515_gpu_reset(struct radeon_device
*rdev
);
398 int rv515_mc_init(struct radeon_device
*rdev
);
399 void rv515_mc_fini(struct radeon_device
*rdev
);
400 uint32_t rv515_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
401 void rv515_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
402 void rv515_ring_start(struct radeon_device
*rdev
);
403 uint32_t rv515_pcie_rreg(struct radeon_device
*rdev
, uint32_t reg
);
404 void rv515_pcie_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
405 void rv515_bandwidth_update(struct radeon_device
*rdev
);
406 static struct radeon_asic rv515_asic
= {
408 .errata
= &rv515_errata
,
409 .vram_info
= &rv515_vram_info
,
410 .gpu_reset
= &rv515_gpu_reset
,
411 .mc_init
= &rv515_mc_init
,
412 .mc_fini
= &rv515_mc_fini
,
413 .wb_init
= &r100_wb_init
,
414 .wb_fini
= &r100_wb_fini
,
415 .gart_enable
= &r300_gart_enable
,
416 .gart_disable
= &rv370_pcie_gart_disable
,
417 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
418 .gart_set_page
= &rv370_pcie_gart_set_page
,
419 .cp_init
= &r100_cp_init
,
420 .cp_fini
= &r100_cp_fini
,
421 .cp_disable
= &r100_cp_disable
,
422 .cp_commit
= &r100_cp_commit
,
423 .ring_start
= &rv515_ring_start
,
424 .ring_test
= &r100_ring_test
,
425 .ring_ib_execute
= &r100_ring_ib_execute
,
426 .ib_test
= &r100_ib_test
,
427 .irq_set
= &rs600_irq_set
,
428 .irq_process
= &rs600_irq_process
,
429 .get_vblank_counter
= &rs600_get_vblank_counter
,
430 .fence_ring_emit
= &r300_fence_ring_emit
,
431 .cs_parse
= &r300_cs_parse
,
432 .copy_blit
= &r100_copy_blit
,
433 .copy_dma
= &r300_copy_dma
,
434 .copy
= &r100_copy_blit
,
435 .set_engine_clock
= &radeon_atom_set_engine_clock
,
436 .set_memory_clock
= &radeon_atom_set_memory_clock
,
437 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
438 .set_clock_gating
= &radeon_atom_set_clock_gating
,
439 .set_surface_reg
= r100_set_surface_reg
,
440 .clear_surface_reg
= r100_clear_surface_reg
,
441 .bandwidth_update
= &rv515_bandwidth_update
,
446 * r520,rv530,rv560,rv570,r580
448 void r520_errata(struct radeon_device
*rdev
);
449 void r520_vram_info(struct radeon_device
*rdev
);
450 int r520_mc_init(struct radeon_device
*rdev
);
451 void r520_mc_fini(struct radeon_device
*rdev
);
452 void r520_bandwidth_update(struct radeon_device
*rdev
);
453 static struct radeon_asic r520_asic
= {
455 .errata
= &r520_errata
,
456 .vram_info
= &r520_vram_info
,
457 .gpu_reset
= &rv515_gpu_reset
,
458 .mc_init
= &r520_mc_init
,
459 .mc_fini
= &r520_mc_fini
,
460 .wb_init
= &r100_wb_init
,
461 .wb_fini
= &r100_wb_fini
,
462 .gart_enable
= &r300_gart_enable
,
463 .gart_disable
= &rv370_pcie_gart_disable
,
464 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
465 .gart_set_page
= &rv370_pcie_gart_set_page
,
466 .cp_init
= &r100_cp_init
,
467 .cp_fini
= &r100_cp_fini
,
468 .cp_disable
= &r100_cp_disable
,
469 .cp_commit
= &r100_cp_commit
,
470 .ring_start
= &rv515_ring_start
,
471 .ring_test
= &r100_ring_test
,
472 .ring_ib_execute
= &r100_ring_ib_execute
,
473 .ib_test
= &r100_ib_test
,
474 .irq_set
= &rs600_irq_set
,
475 .irq_process
= &rs600_irq_process
,
476 .get_vblank_counter
= &rs600_get_vblank_counter
,
477 .fence_ring_emit
= &r300_fence_ring_emit
,
478 .cs_parse
= &r300_cs_parse
,
479 .copy_blit
= &r100_copy_blit
,
480 .copy_dma
= &r300_copy_dma
,
481 .copy
= &r100_copy_blit
,
482 .set_engine_clock
= &radeon_atom_set_engine_clock
,
483 .set_memory_clock
= &radeon_atom_set_memory_clock
,
484 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
485 .set_clock_gating
= &radeon_atom_set_clock_gating
,
486 .set_surface_reg
= r100_set_surface_reg
,
487 .clear_surface_reg
= r100_clear_surface_reg
,
488 .bandwidth_update
= &r520_bandwidth_update
,
492 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
494 int r600_init(struct radeon_device
*rdev
);
495 void r600_fini(struct radeon_device
*rdev
);
496 int r600_suspend(struct radeon_device
*rdev
);
497 int r600_resume(struct radeon_device
*rdev
);
498 int r600_wb_init(struct radeon_device
*rdev
);
499 void r600_wb_fini(struct radeon_device
*rdev
);
500 void r600_cp_commit(struct radeon_device
*rdev
);
501 void r600_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
502 uint32_t r600_pciep_rreg(struct radeon_device
*rdev
, uint32_t reg
);
503 void r600_pciep_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
504 int r600_cs_parse(struct radeon_cs_parser
*p
);
505 void r600_fence_ring_emit(struct radeon_device
*rdev
,
506 struct radeon_fence
*fence
);
507 int r600_copy_dma(struct radeon_device
*rdev
,
511 struct radeon_fence
*fence
);
512 int r600_irq_process(struct radeon_device
*rdev
);
513 int r600_irq_set(struct radeon_device
*rdev
);
514 int r600_gpu_reset(struct radeon_device
*rdev
);
515 int r600_set_surface_reg(struct radeon_device
*rdev
, int reg
,
516 uint32_t tiling_flags
, uint32_t pitch
,
517 uint32_t offset
, uint32_t obj_size
);
518 int r600_clear_surface_reg(struct radeon_device
*rdev
, int reg
);
519 void r600_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
520 int r600_ib_test(struct radeon_device
*rdev
);
521 int r600_ring_test(struct radeon_device
*rdev
);
522 int r600_copy_blit(struct radeon_device
*rdev
,
523 uint64_t src_offset
, uint64_t dst_offset
,
524 unsigned num_pages
, struct radeon_fence
*fence
);
526 static struct radeon_asic r600_asic
= {
530 .suspend
= &r600_suspend
,
531 .resume
= &r600_resume
,
532 .cp_commit
= &r600_cp_commit
,
534 .gpu_reset
= &r600_gpu_reset
,
537 .wb_init
= &r600_wb_init
,
538 .wb_fini
= &r600_wb_fini
,
540 .gart_disable
= NULL
,
541 .gart_tlb_flush
= &r600_pcie_gart_tlb_flush
,
542 .gart_set_page
= &rs600_gart_set_page
,
547 .ring_test
= &r600_ring_test
,
548 .ring_ib_execute
= &r600_ring_ib_execute
,
549 .ib_test
= &r600_ib_test
,
550 .irq_set
= &r600_irq_set
,
551 .irq_process
= &r600_irq_process
,
552 .fence_ring_emit
= &r600_fence_ring_emit
,
553 .cs_parse
= &r600_cs_parse
,
554 .copy_blit
= &r600_copy_blit
,
555 .copy_dma
= &r600_copy_blit
,
557 .set_engine_clock
= &radeon_atom_set_engine_clock
,
558 .set_memory_clock
= &radeon_atom_set_memory_clock
,
559 .set_pcie_lanes
= NULL
,
560 .set_clock_gating
= &radeon_atom_set_clock_gating
,
561 .set_surface_reg
= r600_set_surface_reg
,
562 .clear_surface_reg
= r600_clear_surface_reg
,
563 .bandwidth_update
= &r520_bandwidth_update
,
567 * rv770,rv730,rv710,rv740
569 int rv770_init(struct radeon_device
*rdev
);
570 void rv770_fini(struct radeon_device
*rdev
);
571 int rv770_suspend(struct radeon_device
*rdev
);
572 int rv770_resume(struct radeon_device
*rdev
);
573 int rv770_gpu_reset(struct radeon_device
*rdev
);
575 static struct radeon_asic rv770_asic
= {
579 .suspend
= &rv770_suspend
,
580 .resume
= &rv770_resume
,
581 .cp_commit
= &r600_cp_commit
,
583 .gpu_reset
= &rv770_gpu_reset
,
586 .wb_init
= &r600_wb_init
,
587 .wb_fini
= &r600_wb_fini
,
589 .gart_disable
= NULL
,
590 .gart_tlb_flush
= &r600_pcie_gart_tlb_flush
,
591 .gart_set_page
= &rs600_gart_set_page
,
596 .ring_test
= &r600_ring_test
,
597 .ring_ib_execute
= &r600_ring_ib_execute
,
598 .ib_test
= &r600_ib_test
,
599 .irq_set
= &r600_irq_set
,
600 .irq_process
= &r600_irq_process
,
601 .fence_ring_emit
= &r600_fence_ring_emit
,
602 .cs_parse
= &r600_cs_parse
,
603 .copy_blit
= &r600_copy_blit
,
604 .copy_dma
= &r600_copy_blit
,
606 .set_engine_clock
= &radeon_atom_set_engine_clock
,
607 .set_memory_clock
= &radeon_atom_set_memory_clock
,
608 .set_pcie_lanes
= NULL
,
609 .set_clock_gating
= &radeon_atom_set_clock_gating
,
610 .set_surface_reg
= r600_set_surface_reg
,
611 .clear_surface_reg
= r600_clear_surface_reg
,
612 .bandwidth_update
= &r520_bandwidth_update
,