2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #ifndef __RADEON_ASIC_H__
29 #define __RADEON_ASIC_H__
34 void radeon_legacy_set_engine_clock(struct radeon_device
*rdev
, uint32_t eng_clock
);
35 void radeon_legacy_set_clock_gating(struct radeon_device
*rdev
, int enable
);
37 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
, uint32_t eng_clock
);
38 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
, uint32_t mem_clock
);
39 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
);
42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
44 int r100_init(struct radeon_device
*rdev
);
45 int r200_init(struct radeon_device
*rdev
);
46 uint32_t r100_mm_rreg(struct radeon_device
*rdev
, uint32_t reg
);
47 void r100_mm_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
48 void r100_errata(struct radeon_device
*rdev
);
49 void r100_vram_info(struct radeon_device
*rdev
);
50 int r100_gpu_reset(struct radeon_device
*rdev
);
51 int r100_mc_init(struct radeon_device
*rdev
);
52 void r100_mc_fini(struct radeon_device
*rdev
);
53 u32
r100_get_vblank_counter(struct radeon_device
*rdev
, int crtc
);
54 int r100_wb_init(struct radeon_device
*rdev
);
55 void r100_wb_fini(struct radeon_device
*rdev
);
56 int r100_gart_enable(struct radeon_device
*rdev
);
57 void r100_pci_gart_disable(struct radeon_device
*rdev
);
58 void r100_pci_gart_tlb_flush(struct radeon_device
*rdev
);
59 int r100_pci_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
60 int r100_cp_init(struct radeon_device
*rdev
, unsigned ring_size
);
61 void r100_cp_fini(struct radeon_device
*rdev
);
62 void r100_cp_disable(struct radeon_device
*rdev
);
63 void r100_ring_start(struct radeon_device
*rdev
);
64 int r100_irq_set(struct radeon_device
*rdev
);
65 int r100_irq_process(struct radeon_device
*rdev
);
66 void r100_fence_ring_emit(struct radeon_device
*rdev
,
67 struct radeon_fence
*fence
);
68 int r100_cs_parse(struct radeon_cs_parser
*p
);
69 void r100_pll_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
70 uint32_t r100_pll_rreg(struct radeon_device
*rdev
, uint32_t reg
);
71 int r100_copy_blit(struct radeon_device
*rdev
,
75 struct radeon_fence
*fence
);
76 int r100_set_surface_reg(struct radeon_device
*rdev
, int reg
,
77 uint32_t tiling_flags
, uint32_t pitch
,
78 uint32_t offset
, uint32_t obj_size
);
79 int r100_clear_surface_reg(struct radeon_device
*rdev
, int reg
);
80 void r100_bandwidth_update(struct radeon_device
*rdev
);
82 static struct radeon_asic r100_asic
= {
84 .errata
= &r100_errata
,
85 .vram_info
= &r100_vram_info
,
86 .gpu_reset
= &r100_gpu_reset
,
87 .mc_init
= &r100_mc_init
,
88 .mc_fini
= &r100_mc_fini
,
89 .wb_init
= &r100_wb_init
,
90 .wb_fini
= &r100_wb_fini
,
91 .gart_enable
= &r100_gart_enable
,
92 .gart_disable
= &r100_pci_gart_disable
,
93 .gart_tlb_flush
= &r100_pci_gart_tlb_flush
,
94 .gart_set_page
= &r100_pci_gart_set_page
,
95 .cp_init
= &r100_cp_init
,
96 .cp_fini
= &r100_cp_fini
,
97 .cp_disable
= &r100_cp_disable
,
98 .ring_start
= &r100_ring_start
,
99 .irq_set
= &r100_irq_set
,
100 .irq_process
= &r100_irq_process
,
101 .get_vblank_counter
= &r100_get_vblank_counter
,
102 .fence_ring_emit
= &r100_fence_ring_emit
,
103 .cs_parse
= &r100_cs_parse
,
104 .copy_blit
= &r100_copy_blit
,
106 .copy
= &r100_copy_blit
,
107 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
108 .set_memory_clock
= NULL
,
109 .set_pcie_lanes
= NULL
,
110 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
111 .set_surface_reg
= r100_set_surface_reg
,
112 .clear_surface_reg
= r100_clear_surface_reg
,
113 .bandwidth_update
= &r100_bandwidth_update
,
118 * r300,r350,rv350,rv380
120 int r300_init(struct radeon_device
*rdev
);
121 void r300_errata(struct radeon_device
*rdev
);
122 void r300_vram_info(struct radeon_device
*rdev
);
123 int r300_gpu_reset(struct radeon_device
*rdev
);
124 int r300_mc_init(struct radeon_device
*rdev
);
125 void r300_mc_fini(struct radeon_device
*rdev
);
126 void r300_ring_start(struct radeon_device
*rdev
);
127 void r300_fence_ring_emit(struct radeon_device
*rdev
,
128 struct radeon_fence
*fence
);
129 int r300_cs_parse(struct radeon_cs_parser
*p
);
130 int r300_gart_enable(struct radeon_device
*rdev
);
131 void rv370_pcie_gart_disable(struct radeon_device
*rdev
);
132 void rv370_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
133 int rv370_pcie_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
134 uint32_t rv370_pcie_rreg(struct radeon_device
*rdev
, uint32_t reg
);
135 void rv370_pcie_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
136 void rv370_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
);
137 int r300_copy_dma(struct radeon_device
*rdev
,
141 struct radeon_fence
*fence
);
143 static struct radeon_asic r300_asic
= {
145 .errata
= &r300_errata
,
146 .vram_info
= &r300_vram_info
,
147 .gpu_reset
= &r300_gpu_reset
,
148 .mc_init
= &r300_mc_init
,
149 .mc_fini
= &r300_mc_fini
,
150 .wb_init
= &r100_wb_init
,
151 .wb_fini
= &r100_wb_fini
,
152 .gart_enable
= &r300_gart_enable
,
153 .gart_disable
= &r100_pci_gart_disable
,
154 .gart_tlb_flush
= &r100_pci_gart_tlb_flush
,
155 .gart_set_page
= &r100_pci_gart_set_page
,
156 .cp_init
= &r100_cp_init
,
157 .cp_fini
= &r100_cp_fini
,
158 .cp_disable
= &r100_cp_disable
,
159 .ring_start
= &r300_ring_start
,
160 .irq_set
= &r100_irq_set
,
161 .irq_process
= &r100_irq_process
,
162 .get_vblank_counter
= &r100_get_vblank_counter
,
163 .fence_ring_emit
= &r300_fence_ring_emit
,
164 .cs_parse
= &r300_cs_parse
,
165 .copy_blit
= &r100_copy_blit
,
166 .copy_dma
= &r300_copy_dma
,
167 .copy
= &r100_copy_blit
,
168 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
169 .set_memory_clock
= NULL
,
170 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
171 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
172 .set_surface_reg
= r100_set_surface_reg
,
173 .clear_surface_reg
= r100_clear_surface_reg
,
174 .bandwidth_update
= &r100_bandwidth_update
,
180 void r420_errata(struct radeon_device
*rdev
);
181 void r420_vram_info(struct radeon_device
*rdev
);
182 int r420_mc_init(struct radeon_device
*rdev
);
183 void r420_mc_fini(struct radeon_device
*rdev
);
184 static struct radeon_asic r420_asic
= {
186 .errata
= &r420_errata
,
187 .vram_info
= &r420_vram_info
,
188 .gpu_reset
= &r300_gpu_reset
,
189 .mc_init
= &r420_mc_init
,
190 .mc_fini
= &r420_mc_fini
,
191 .wb_init
= &r100_wb_init
,
192 .wb_fini
= &r100_wb_fini
,
193 .gart_enable
= &r300_gart_enable
,
194 .gart_disable
= &rv370_pcie_gart_disable
,
195 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
196 .gart_set_page
= &rv370_pcie_gart_set_page
,
197 .cp_init
= &r100_cp_init
,
198 .cp_fini
= &r100_cp_fini
,
199 .cp_disable
= &r100_cp_disable
,
200 .ring_start
= &r300_ring_start
,
201 .irq_set
= &r100_irq_set
,
202 .irq_process
= &r100_irq_process
,
203 .get_vblank_counter
= &r100_get_vblank_counter
,
204 .fence_ring_emit
= &r300_fence_ring_emit
,
205 .cs_parse
= &r300_cs_parse
,
206 .copy_blit
= &r100_copy_blit
,
207 .copy_dma
= &r300_copy_dma
,
208 .copy
= &r100_copy_blit
,
209 .set_engine_clock
= &radeon_atom_set_engine_clock
,
210 .set_memory_clock
= &radeon_atom_set_memory_clock
,
211 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
212 .set_clock_gating
= &radeon_atom_set_clock_gating
,
213 .set_surface_reg
= r100_set_surface_reg
,
214 .clear_surface_reg
= r100_clear_surface_reg
,
215 .bandwidth_update
= &r100_bandwidth_update
,
222 void rs400_errata(struct radeon_device
*rdev
);
223 void rs400_vram_info(struct radeon_device
*rdev
);
224 int rs400_mc_init(struct radeon_device
*rdev
);
225 void rs400_mc_fini(struct radeon_device
*rdev
);
226 int rs400_gart_enable(struct radeon_device
*rdev
);
227 void rs400_gart_disable(struct radeon_device
*rdev
);
228 void rs400_gart_tlb_flush(struct radeon_device
*rdev
);
229 int rs400_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
230 uint32_t rs400_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
231 void rs400_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
232 static struct radeon_asic rs400_asic
= {
234 .errata
= &rs400_errata
,
235 .vram_info
= &rs400_vram_info
,
236 .gpu_reset
= &r300_gpu_reset
,
237 .mc_init
= &rs400_mc_init
,
238 .mc_fini
= &rs400_mc_fini
,
239 .wb_init
= &r100_wb_init
,
240 .wb_fini
= &r100_wb_fini
,
241 .gart_enable
= &rs400_gart_enable
,
242 .gart_disable
= &rs400_gart_disable
,
243 .gart_tlb_flush
= &rs400_gart_tlb_flush
,
244 .gart_set_page
= &rs400_gart_set_page
,
245 .cp_init
= &r100_cp_init
,
246 .cp_fini
= &r100_cp_fini
,
247 .cp_disable
= &r100_cp_disable
,
248 .ring_start
= &r300_ring_start
,
249 .irq_set
= &r100_irq_set
,
250 .irq_process
= &r100_irq_process
,
251 .get_vblank_counter
= &r100_get_vblank_counter
,
252 .fence_ring_emit
= &r300_fence_ring_emit
,
253 .cs_parse
= &r300_cs_parse
,
254 .copy_blit
= &r100_copy_blit
,
255 .copy_dma
= &r300_copy_dma
,
256 .copy
= &r100_copy_blit
,
257 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
258 .set_memory_clock
= NULL
,
259 .set_pcie_lanes
= NULL
,
260 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
261 .set_surface_reg
= r100_set_surface_reg
,
262 .clear_surface_reg
= r100_clear_surface_reg
,
263 .bandwidth_update
= &r100_bandwidth_update
,
270 int rs600_init(struct radeon_device
*rdev
);
271 void rs600_errata(struct radeon_device
*rdev
);
272 void rs600_vram_info(struct radeon_device
*rdev
);
273 int rs600_mc_init(struct radeon_device
*rdev
);
274 void rs600_mc_fini(struct radeon_device
*rdev
);
275 int rs600_irq_set(struct radeon_device
*rdev
);
276 int rs600_irq_process(struct radeon_device
*rdev
);
277 u32
rs600_get_vblank_counter(struct radeon_device
*rdev
, int crtc
);
278 int rs600_gart_enable(struct radeon_device
*rdev
);
279 void rs600_gart_disable(struct radeon_device
*rdev
);
280 void rs600_gart_tlb_flush(struct radeon_device
*rdev
);
281 int rs600_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
282 uint32_t rs600_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
283 void rs600_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
284 void rs600_bandwidth_update(struct radeon_device
*rdev
);
285 static struct radeon_asic rs600_asic
= {
287 .errata
= &rs600_errata
,
288 .vram_info
= &rs600_vram_info
,
289 .gpu_reset
= &r300_gpu_reset
,
290 .mc_init
= &rs600_mc_init
,
291 .mc_fini
= &rs600_mc_fini
,
292 .wb_init
= &r100_wb_init
,
293 .wb_fini
= &r100_wb_fini
,
294 .gart_enable
= &rs600_gart_enable
,
295 .gart_disable
= &rs600_gart_disable
,
296 .gart_tlb_flush
= &rs600_gart_tlb_flush
,
297 .gart_set_page
= &rs600_gart_set_page
,
298 .cp_init
= &r100_cp_init
,
299 .cp_fini
= &r100_cp_fini
,
300 .cp_disable
= &r100_cp_disable
,
301 .ring_start
= &r300_ring_start
,
302 .irq_set
= &rs600_irq_set
,
303 .irq_process
= &rs600_irq_process
,
304 .get_vblank_counter
= &rs600_get_vblank_counter
,
305 .fence_ring_emit
= &r300_fence_ring_emit
,
306 .cs_parse
= &r300_cs_parse
,
307 .copy_blit
= &r100_copy_blit
,
308 .copy_dma
= &r300_copy_dma
,
309 .copy
= &r100_copy_blit
,
310 .set_engine_clock
= &radeon_atom_set_engine_clock
,
311 .set_memory_clock
= &radeon_atom_set_memory_clock
,
312 .set_pcie_lanes
= NULL
,
313 .set_clock_gating
= &radeon_atom_set_clock_gating
,
314 .bandwidth_update
= &rs600_bandwidth_update
,
321 void rs690_errata(struct radeon_device
*rdev
);
322 void rs690_vram_info(struct radeon_device
*rdev
);
323 int rs690_mc_init(struct radeon_device
*rdev
);
324 void rs690_mc_fini(struct radeon_device
*rdev
);
325 uint32_t rs690_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
326 void rs690_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
327 void rs690_bandwidth_update(struct radeon_device
*rdev
);
328 static struct radeon_asic rs690_asic
= {
330 .errata
= &rs690_errata
,
331 .vram_info
= &rs690_vram_info
,
332 .gpu_reset
= &r300_gpu_reset
,
333 .mc_init
= &rs690_mc_init
,
334 .mc_fini
= &rs690_mc_fini
,
335 .wb_init
= &r100_wb_init
,
336 .wb_fini
= &r100_wb_fini
,
337 .gart_enable
= &rs400_gart_enable
,
338 .gart_disable
= &rs400_gart_disable
,
339 .gart_tlb_flush
= &rs400_gart_tlb_flush
,
340 .gart_set_page
= &rs400_gart_set_page
,
341 .cp_init
= &r100_cp_init
,
342 .cp_fini
= &r100_cp_fini
,
343 .cp_disable
= &r100_cp_disable
,
344 .ring_start
= &r300_ring_start
,
345 .irq_set
= &rs600_irq_set
,
346 .irq_process
= &rs600_irq_process
,
347 .get_vblank_counter
= &rs600_get_vblank_counter
,
348 .fence_ring_emit
= &r300_fence_ring_emit
,
349 .cs_parse
= &r300_cs_parse
,
350 .copy_blit
= &r100_copy_blit
,
351 .copy_dma
= &r300_copy_dma
,
352 .copy
= &r300_copy_dma
,
353 .set_engine_clock
= &radeon_atom_set_engine_clock
,
354 .set_memory_clock
= &radeon_atom_set_memory_clock
,
355 .set_pcie_lanes
= NULL
,
356 .set_clock_gating
= &radeon_atom_set_clock_gating
,
357 .set_surface_reg
= r100_set_surface_reg
,
358 .clear_surface_reg
= r100_clear_surface_reg
,
359 .bandwidth_update
= &rs690_bandwidth_update
,
366 int rv515_init(struct radeon_device
*rdev
);
367 void rv515_errata(struct radeon_device
*rdev
);
368 void rv515_vram_info(struct radeon_device
*rdev
);
369 int rv515_gpu_reset(struct radeon_device
*rdev
);
370 int rv515_mc_init(struct radeon_device
*rdev
);
371 void rv515_mc_fini(struct radeon_device
*rdev
);
372 uint32_t rv515_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
373 void rv515_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
374 void rv515_ring_start(struct radeon_device
*rdev
);
375 uint32_t rv515_pcie_rreg(struct radeon_device
*rdev
, uint32_t reg
);
376 void rv515_pcie_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
377 void rv515_bandwidth_update(struct radeon_device
*rdev
);
378 static struct radeon_asic rv515_asic
= {
380 .errata
= &rv515_errata
,
381 .vram_info
= &rv515_vram_info
,
382 .gpu_reset
= &rv515_gpu_reset
,
383 .mc_init
= &rv515_mc_init
,
384 .mc_fini
= &rv515_mc_fini
,
385 .wb_init
= &r100_wb_init
,
386 .wb_fini
= &r100_wb_fini
,
387 .gart_enable
= &r300_gart_enable
,
388 .gart_disable
= &rv370_pcie_gart_disable
,
389 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
390 .gart_set_page
= &rv370_pcie_gart_set_page
,
391 .cp_init
= &r100_cp_init
,
392 .cp_fini
= &r100_cp_fini
,
393 .cp_disable
= &r100_cp_disable
,
394 .ring_start
= &rv515_ring_start
,
395 .irq_set
= &rs600_irq_set
,
396 .irq_process
= &rs600_irq_process
,
397 .get_vblank_counter
= &rs600_get_vblank_counter
,
398 .fence_ring_emit
= &r300_fence_ring_emit
,
399 .cs_parse
= &r300_cs_parse
,
400 .copy_blit
= &r100_copy_blit
,
401 .copy_dma
= &r300_copy_dma
,
402 .copy
= &r100_copy_blit
,
403 .set_engine_clock
= &radeon_atom_set_engine_clock
,
404 .set_memory_clock
= &radeon_atom_set_memory_clock
,
405 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
406 .set_clock_gating
= &radeon_atom_set_clock_gating
,
407 .set_surface_reg
= r100_set_surface_reg
,
408 .clear_surface_reg
= r100_clear_surface_reg
,
409 .bandwidth_update
= &rv515_bandwidth_update
,
414 * r520,rv530,rv560,rv570,r580
416 void r520_errata(struct radeon_device
*rdev
);
417 void r520_vram_info(struct radeon_device
*rdev
);
418 int r520_mc_init(struct radeon_device
*rdev
);
419 void r520_mc_fini(struct radeon_device
*rdev
);
420 void r520_bandwidth_update(struct radeon_device
*rdev
);
421 static struct radeon_asic r520_asic
= {
423 .errata
= &r520_errata
,
424 .vram_info
= &r520_vram_info
,
425 .gpu_reset
= &rv515_gpu_reset
,
426 .mc_init
= &r520_mc_init
,
427 .mc_fini
= &r520_mc_fini
,
428 .wb_init
= &r100_wb_init
,
429 .wb_fini
= &r100_wb_fini
,
430 .gart_enable
= &r300_gart_enable
,
431 .gart_disable
= &rv370_pcie_gart_disable
,
432 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
433 .gart_set_page
= &rv370_pcie_gart_set_page
,
434 .cp_init
= &r100_cp_init
,
435 .cp_fini
= &r100_cp_fini
,
436 .cp_disable
= &r100_cp_disable
,
437 .ring_start
= &rv515_ring_start
,
438 .irq_set
= &rs600_irq_set
,
439 .irq_process
= &rs600_irq_process
,
440 .get_vblank_counter
= &rs600_get_vblank_counter
,
441 .fence_ring_emit
= &r300_fence_ring_emit
,
442 .cs_parse
= &r300_cs_parse
,
443 .copy_blit
= &r100_copy_blit
,
444 .copy_dma
= &r300_copy_dma
,
445 .copy
= &r100_copy_blit
,
446 .set_engine_clock
= &radeon_atom_set_engine_clock
,
447 .set_memory_clock
= &radeon_atom_set_memory_clock
,
448 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
449 .set_clock_gating
= &radeon_atom_set_clock_gating
,
450 .set_surface_reg
= r100_set_surface_reg
,
451 .clear_surface_reg
= r100_clear_surface_reg
,
452 .bandwidth_update
= &r520_bandwidth_update
,
456 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710
458 uint32_t r600_pciep_rreg(struct radeon_device
*rdev
, uint32_t reg
);
459 void r600_pciep_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);