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drm/radeon: fix endian handling in radeon_atom_init_mc_reg_table
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_atombios.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 extern void
34 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
35 uint32_t supported_device, u16 caps);
36
37 /* from radeon_legacy_encoder.c */
38 extern void
39 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device);
41
42 union atom_supported_devices {
43 struct _ATOM_SUPPORTED_DEVICES_INFO info;
44 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
45 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
46 };
47
48 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
49 ATOM_GPIO_I2C_ASSIGMENT *gpio,
50 u8 index)
51 {
52 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
53 if ((rdev->family == CHIP_R420) ||
54 (rdev->family == CHIP_R423) ||
55 (rdev->family == CHIP_RV410)) {
56 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
58 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
59 gpio->ucClkMaskShift = 0x19;
60 gpio->ucDataMaskShift = 0x18;
61 }
62 }
63
64 /* some evergreen boards have bad data for this entry */
65 if (ASIC_IS_DCE4(rdev)) {
66 if ((index == 7) &&
67 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
68 (gpio->sucI2cId.ucAccess == 0)) {
69 gpio->sucI2cId.ucAccess = 0x97;
70 gpio->ucDataMaskShift = 8;
71 gpio->ucDataEnShift = 8;
72 gpio->ucDataY_Shift = 8;
73 gpio->ucDataA_Shift = 8;
74 }
75 }
76
77 /* some DCE3 boards have bad data for this entry */
78 if (ASIC_IS_DCE3(rdev)) {
79 if ((index == 4) &&
80 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
81 (gpio->sucI2cId.ucAccess == 0x94))
82 gpio->sucI2cId.ucAccess = 0x14;
83 }
84 }
85
86 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
87 {
88 struct radeon_i2c_bus_rec i2c;
89
90 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
91
92 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
93 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
94 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
95 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
96 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
97 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
98 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
99 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
100 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
101 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
102 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
103 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
104 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
105 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
106 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
107 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
108
109 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
110 i2c.hw_capable = true;
111 else
112 i2c.hw_capable = false;
113
114 if (gpio->sucI2cId.ucAccess == 0xa0)
115 i2c.mm_i2c = true;
116 else
117 i2c.mm_i2c = false;
118
119 i2c.i2c_id = gpio->sucI2cId.ucAccess;
120
121 if (i2c.mask_clk_reg)
122 i2c.valid = true;
123 else
124 i2c.valid = false;
125
126 return i2c;
127 }
128
129 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
130 uint8_t id)
131 {
132 struct atom_context *ctx = rdev->mode_info.atom_context;
133 ATOM_GPIO_I2C_ASSIGMENT *gpio;
134 struct radeon_i2c_bus_rec i2c;
135 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
136 struct _ATOM_GPIO_I2C_INFO *i2c_info;
137 uint16_t data_offset, size;
138 int i, num_indices;
139
140 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
141 i2c.valid = false;
142
143 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
144 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
145
146 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
147 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
148
149 gpio = &i2c_info->asGPIO_Info[0];
150 for (i = 0; i < num_indices; i++) {
151
152 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
153
154 if (gpio->sucI2cId.ucAccess == id) {
155 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
156 break;
157 }
158 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
159 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
160 }
161 }
162
163 return i2c;
164 }
165
166 void radeon_atombios_i2c_init(struct radeon_device *rdev)
167 {
168 struct atom_context *ctx = rdev->mode_info.atom_context;
169 ATOM_GPIO_I2C_ASSIGMENT *gpio;
170 struct radeon_i2c_bus_rec i2c;
171 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
172 struct _ATOM_GPIO_I2C_INFO *i2c_info;
173 uint16_t data_offset, size;
174 int i, num_indices;
175 char stmp[32];
176
177 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
178 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
179
180 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
181 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
182
183 gpio = &i2c_info->asGPIO_Info[0];
184 for (i = 0; i < num_indices; i++) {
185 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
186
187 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
188
189 if (i2c.valid) {
190 sprintf(stmp, "0x%x", i2c.i2c_id);
191 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
192 }
193 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
194 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
195 }
196 }
197 }
198
199 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
200 u8 id)
201 {
202 struct atom_context *ctx = rdev->mode_info.atom_context;
203 struct radeon_gpio_rec gpio;
204 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
205 struct _ATOM_GPIO_PIN_LUT *gpio_info;
206 ATOM_GPIO_PIN_ASSIGNMENT *pin;
207 u16 data_offset, size;
208 int i, num_indices;
209
210 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
211 gpio.valid = false;
212
213 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
214 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
215
216 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
217 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
218
219 pin = gpio_info->asGPIO_Pin;
220 for (i = 0; i < num_indices; i++) {
221 if (id == pin->ucGPIO_ID) {
222 gpio.id = pin->ucGPIO_ID;
223 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
224 gpio.mask = (1 << pin->ucGpioPinBitShift);
225 gpio.valid = true;
226 break;
227 }
228 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
229 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
230 }
231 }
232
233 return gpio;
234 }
235
236 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
237 struct radeon_gpio_rec *gpio)
238 {
239 struct radeon_hpd hpd;
240 u32 reg;
241
242 memset(&hpd, 0, sizeof(struct radeon_hpd));
243
244 if (ASIC_IS_DCE6(rdev))
245 reg = SI_DC_GPIO_HPD_A;
246 else if (ASIC_IS_DCE4(rdev))
247 reg = EVERGREEN_DC_GPIO_HPD_A;
248 else
249 reg = AVIVO_DC_GPIO_HPD_A;
250
251 hpd.gpio = *gpio;
252 if (gpio->reg == reg) {
253 switch(gpio->mask) {
254 case (1 << 0):
255 hpd.hpd = RADEON_HPD_1;
256 break;
257 case (1 << 8):
258 hpd.hpd = RADEON_HPD_2;
259 break;
260 case (1 << 16):
261 hpd.hpd = RADEON_HPD_3;
262 break;
263 case (1 << 24):
264 hpd.hpd = RADEON_HPD_4;
265 break;
266 case (1 << 26):
267 hpd.hpd = RADEON_HPD_5;
268 break;
269 case (1 << 28):
270 hpd.hpd = RADEON_HPD_6;
271 break;
272 default:
273 hpd.hpd = RADEON_HPD_NONE;
274 break;
275 }
276 } else
277 hpd.hpd = RADEON_HPD_NONE;
278 return hpd;
279 }
280
281 static bool radeon_atom_apply_quirks(struct drm_device *dev,
282 uint32_t supported_device,
283 int *connector_type,
284 struct radeon_i2c_bus_rec *i2c_bus,
285 uint16_t *line_mux,
286 struct radeon_hpd *hpd)
287 {
288
289 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
290 if ((dev->pdev->device == 0x791e) &&
291 (dev->pdev->subsystem_vendor == 0x1043) &&
292 (dev->pdev->subsystem_device == 0x826d)) {
293 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
294 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
295 *connector_type = DRM_MODE_CONNECTOR_DVID;
296 }
297
298 /* Asrock RS600 board lists the DVI port as HDMI */
299 if ((dev->pdev->device == 0x7941) &&
300 (dev->pdev->subsystem_vendor == 0x1849) &&
301 (dev->pdev->subsystem_device == 0x7941)) {
302 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
303 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
304 *connector_type = DRM_MODE_CONNECTOR_DVID;
305 }
306
307 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
308 if ((dev->pdev->device == 0x796e) &&
309 (dev->pdev->subsystem_vendor == 0x1462) &&
310 (dev->pdev->subsystem_device == 0x7302)) {
311 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
312 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
313 return false;
314 }
315
316 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
317 if ((dev->pdev->device == 0x7941) &&
318 (dev->pdev->subsystem_vendor == 0x147b) &&
319 (dev->pdev->subsystem_device == 0x2412)) {
320 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
321 return false;
322 }
323
324 /* Falcon NW laptop lists vga ddc line for LVDS */
325 if ((dev->pdev->device == 0x5653) &&
326 (dev->pdev->subsystem_vendor == 0x1462) &&
327 (dev->pdev->subsystem_device == 0x0291)) {
328 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
329 i2c_bus->valid = false;
330 *line_mux = 53;
331 }
332 }
333
334 /* HIS X1300 is DVI+VGA, not DVI+DVI */
335 if ((dev->pdev->device == 0x7146) &&
336 (dev->pdev->subsystem_vendor == 0x17af) &&
337 (dev->pdev->subsystem_device == 0x2058)) {
338 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
339 return false;
340 }
341
342 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
343 if ((dev->pdev->device == 0x7142) &&
344 (dev->pdev->subsystem_vendor == 0x1458) &&
345 (dev->pdev->subsystem_device == 0x2134)) {
346 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
347 return false;
348 }
349
350
351 /* Funky macbooks */
352 if ((dev->pdev->device == 0x71C5) &&
353 (dev->pdev->subsystem_vendor == 0x106b) &&
354 (dev->pdev->subsystem_device == 0x0080)) {
355 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
356 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
357 return false;
358 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
359 *line_mux = 0x90;
360 }
361
362 /* mac rv630, rv730, others */
363 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
364 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
365 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
366 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
367 }
368
369 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
370 if ((dev->pdev->device == 0x9598) &&
371 (dev->pdev->subsystem_vendor == 0x1043) &&
372 (dev->pdev->subsystem_device == 0x01da)) {
373 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
374 *connector_type = DRM_MODE_CONNECTOR_DVII;
375 }
376 }
377
378 /* ASUS HD 3600 board lists the DVI port as HDMI */
379 if ((dev->pdev->device == 0x9598) &&
380 (dev->pdev->subsystem_vendor == 0x1043) &&
381 (dev->pdev->subsystem_device == 0x01e4)) {
382 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
383 *connector_type = DRM_MODE_CONNECTOR_DVII;
384 }
385 }
386
387 /* ASUS HD 3450 board lists the DVI port as HDMI */
388 if ((dev->pdev->device == 0x95C5) &&
389 (dev->pdev->subsystem_vendor == 0x1043) &&
390 (dev->pdev->subsystem_device == 0x01e2)) {
391 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
392 *connector_type = DRM_MODE_CONNECTOR_DVII;
393 }
394 }
395
396 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
397 * HDMI + VGA reporting as HDMI
398 */
399 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
400 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
401 *connector_type = DRM_MODE_CONNECTOR_VGA;
402 *line_mux = 0;
403 }
404 }
405
406 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
407 * on the laptop and a DVI port on the docking station and
408 * both share the same encoder, hpd pin, and ddc line.
409 * So while the bios table is technically correct,
410 * we drop the DVI port here since xrandr has no concept of
411 * encoders and will try and drive both connectors
412 * with different crtcs which isn't possible on the hardware
413 * side and leaves no crtcs for LVDS or VGA.
414 */
415 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
416 (dev->pdev->subsystem_vendor == 0x1025) &&
417 (dev->pdev->subsystem_device == 0x013c)) {
418 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
419 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
420 /* actually it's a DVI-D port not DVI-I */
421 *connector_type = DRM_MODE_CONNECTOR_DVID;
422 return false;
423 }
424 }
425
426 /* XFX Pine Group device rv730 reports no VGA DDC lines
427 * even though they are wired up to record 0x93
428 */
429 if ((dev->pdev->device == 0x9498) &&
430 (dev->pdev->subsystem_vendor == 0x1682) &&
431 (dev->pdev->subsystem_device == 0x2452) &&
432 (i2c_bus->valid == false) &&
433 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
434 struct radeon_device *rdev = dev->dev_private;
435 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
436 }
437
438 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
439 if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
440 (dev->pdev->subsystem_vendor == 0x1734) &&
441 (dev->pdev->subsystem_device == 0x11bd)) {
442 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
443 *connector_type = DRM_MODE_CONNECTOR_DVII;
444 *line_mux = 0x3103;
445 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
446 *connector_type = DRM_MODE_CONNECTOR_DVII;
447 }
448 }
449
450
451 return true;
452 }
453
454 const int supported_devices_connector_convert[] = {
455 DRM_MODE_CONNECTOR_Unknown,
456 DRM_MODE_CONNECTOR_VGA,
457 DRM_MODE_CONNECTOR_DVII,
458 DRM_MODE_CONNECTOR_DVID,
459 DRM_MODE_CONNECTOR_DVIA,
460 DRM_MODE_CONNECTOR_SVIDEO,
461 DRM_MODE_CONNECTOR_Composite,
462 DRM_MODE_CONNECTOR_LVDS,
463 DRM_MODE_CONNECTOR_Unknown,
464 DRM_MODE_CONNECTOR_Unknown,
465 DRM_MODE_CONNECTOR_HDMIA,
466 DRM_MODE_CONNECTOR_HDMIB,
467 DRM_MODE_CONNECTOR_Unknown,
468 DRM_MODE_CONNECTOR_Unknown,
469 DRM_MODE_CONNECTOR_9PinDIN,
470 DRM_MODE_CONNECTOR_DisplayPort
471 };
472
473 const uint16_t supported_devices_connector_object_id_convert[] = {
474 CONNECTOR_OBJECT_ID_NONE,
475 CONNECTOR_OBJECT_ID_VGA,
476 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
477 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
478 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
479 CONNECTOR_OBJECT_ID_COMPOSITE,
480 CONNECTOR_OBJECT_ID_SVIDEO,
481 CONNECTOR_OBJECT_ID_LVDS,
482 CONNECTOR_OBJECT_ID_9PIN_DIN,
483 CONNECTOR_OBJECT_ID_9PIN_DIN,
484 CONNECTOR_OBJECT_ID_DISPLAYPORT,
485 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
486 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
487 CONNECTOR_OBJECT_ID_SVIDEO
488 };
489
490 const int object_connector_convert[] = {
491 DRM_MODE_CONNECTOR_Unknown,
492 DRM_MODE_CONNECTOR_DVII,
493 DRM_MODE_CONNECTOR_DVII,
494 DRM_MODE_CONNECTOR_DVID,
495 DRM_MODE_CONNECTOR_DVID,
496 DRM_MODE_CONNECTOR_VGA,
497 DRM_MODE_CONNECTOR_Composite,
498 DRM_MODE_CONNECTOR_SVIDEO,
499 DRM_MODE_CONNECTOR_Unknown,
500 DRM_MODE_CONNECTOR_Unknown,
501 DRM_MODE_CONNECTOR_9PinDIN,
502 DRM_MODE_CONNECTOR_Unknown,
503 DRM_MODE_CONNECTOR_HDMIA,
504 DRM_MODE_CONNECTOR_HDMIB,
505 DRM_MODE_CONNECTOR_LVDS,
506 DRM_MODE_CONNECTOR_9PinDIN,
507 DRM_MODE_CONNECTOR_Unknown,
508 DRM_MODE_CONNECTOR_Unknown,
509 DRM_MODE_CONNECTOR_Unknown,
510 DRM_MODE_CONNECTOR_DisplayPort,
511 DRM_MODE_CONNECTOR_eDP,
512 DRM_MODE_CONNECTOR_Unknown
513 };
514
515 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
516 {
517 struct radeon_device *rdev = dev->dev_private;
518 struct radeon_mode_info *mode_info = &rdev->mode_info;
519 struct atom_context *ctx = mode_info->atom_context;
520 int index = GetIndexIntoMasterTable(DATA, Object_Header);
521 u16 size, data_offset;
522 u8 frev, crev;
523 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
524 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
525 ATOM_OBJECT_TABLE *router_obj;
526 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
527 ATOM_OBJECT_HEADER *obj_header;
528 int i, j, k, path_size, device_support;
529 int connector_type;
530 u16 igp_lane_info, conn_id, connector_object_id;
531 struct radeon_i2c_bus_rec ddc_bus;
532 struct radeon_router router;
533 struct radeon_gpio_rec gpio;
534 struct radeon_hpd hpd;
535
536 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
537 return false;
538
539 if (crev < 2)
540 return false;
541
542 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
543 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
544 (ctx->bios + data_offset +
545 le16_to_cpu(obj_header->usDisplayPathTableOffset));
546 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
547 (ctx->bios + data_offset +
548 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
549 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
550 (ctx->bios + data_offset +
551 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
552 router_obj = (ATOM_OBJECT_TABLE *)
553 (ctx->bios + data_offset +
554 le16_to_cpu(obj_header->usRouterObjectTableOffset));
555 device_support = le16_to_cpu(obj_header->usDeviceSupport);
556
557 path_size = 0;
558 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
559 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
560 ATOM_DISPLAY_OBJECT_PATH *path;
561 addr += path_size;
562 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
563 path_size += le16_to_cpu(path->usSize);
564
565 if (device_support & le16_to_cpu(path->usDeviceTag)) {
566 uint8_t con_obj_id, con_obj_num, con_obj_type;
567
568 con_obj_id =
569 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
570 >> OBJECT_ID_SHIFT;
571 con_obj_num =
572 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
573 >> ENUM_ID_SHIFT;
574 con_obj_type =
575 (le16_to_cpu(path->usConnObjectId) &
576 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
577
578 /* TODO CV support */
579 if (le16_to_cpu(path->usDeviceTag) ==
580 ATOM_DEVICE_CV_SUPPORT)
581 continue;
582
583 /* IGP chips */
584 if ((rdev->flags & RADEON_IS_IGP) &&
585 (con_obj_id ==
586 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
587 uint16_t igp_offset = 0;
588 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
589
590 index =
591 GetIndexIntoMasterTable(DATA,
592 IntegratedSystemInfo);
593
594 if (atom_parse_data_header(ctx, index, &size, &frev,
595 &crev, &igp_offset)) {
596
597 if (crev >= 2) {
598 igp_obj =
599 (ATOM_INTEGRATED_SYSTEM_INFO_V2
600 *) (ctx->bios + igp_offset);
601
602 if (igp_obj) {
603 uint32_t slot_config, ct;
604
605 if (con_obj_num == 1)
606 slot_config =
607 igp_obj->
608 ulDDISlot1Config;
609 else
610 slot_config =
611 igp_obj->
612 ulDDISlot2Config;
613
614 ct = (slot_config >> 16) & 0xff;
615 connector_type =
616 object_connector_convert
617 [ct];
618 connector_object_id = ct;
619 igp_lane_info =
620 slot_config & 0xffff;
621 } else
622 continue;
623 } else
624 continue;
625 } else {
626 igp_lane_info = 0;
627 connector_type =
628 object_connector_convert[con_obj_id];
629 connector_object_id = con_obj_id;
630 }
631 } else {
632 igp_lane_info = 0;
633 connector_type =
634 object_connector_convert[con_obj_id];
635 connector_object_id = con_obj_id;
636 }
637
638 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
639 continue;
640
641 router.ddc_valid = false;
642 router.cd_valid = false;
643 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
644 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
645
646 grph_obj_id =
647 (le16_to_cpu(path->usGraphicObjIds[j]) &
648 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
649 grph_obj_num =
650 (le16_to_cpu(path->usGraphicObjIds[j]) &
651 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
652 grph_obj_type =
653 (le16_to_cpu(path->usGraphicObjIds[j]) &
654 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
655
656 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
657 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
658 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
659 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
660 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
661 (ctx->bios + data_offset +
662 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
663 ATOM_ENCODER_CAP_RECORD *cap_record;
664 u16 caps = 0;
665
666 while (record->ucRecordSize > 0 &&
667 record->ucRecordType > 0 &&
668 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
669 switch (record->ucRecordType) {
670 case ATOM_ENCODER_CAP_RECORD_TYPE:
671 cap_record =(ATOM_ENCODER_CAP_RECORD *)
672 record;
673 caps = le16_to_cpu(cap_record->usEncoderCap);
674 break;
675 }
676 record = (ATOM_COMMON_RECORD_HEADER *)
677 ((char *)record + record->ucRecordSize);
678 }
679 radeon_add_atom_encoder(dev,
680 encoder_obj,
681 le16_to_cpu
682 (path->
683 usDeviceTag),
684 caps);
685 }
686 }
687 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
688 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
689 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
690 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
691 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
692 (ctx->bios + data_offset +
693 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
694 ATOM_I2C_RECORD *i2c_record;
695 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
696 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
697 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
698 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
699 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
700 (ctx->bios + data_offset +
701 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
702 u8 *num_dst_objs = (u8 *)
703 ((u8 *)router_src_dst_table + 1 +
704 (router_src_dst_table->ucNumberOfSrc * 2));
705 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
706 int enum_id;
707
708 router.router_id = router_obj_id;
709 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
710 if (le16_to_cpu(path->usConnObjectId) ==
711 le16_to_cpu(dst_objs[enum_id]))
712 break;
713 }
714
715 while (record->ucRecordSize > 0 &&
716 record->ucRecordType > 0 &&
717 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
718 switch (record->ucRecordType) {
719 case ATOM_I2C_RECORD_TYPE:
720 i2c_record =
721 (ATOM_I2C_RECORD *)
722 record;
723 i2c_config =
724 (ATOM_I2C_ID_CONFIG_ACCESS *)
725 &i2c_record->sucI2cId;
726 router.i2c_info =
727 radeon_lookup_i2c_gpio(rdev,
728 i2c_config->
729 ucAccess);
730 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
731 break;
732 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
733 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
734 record;
735 router.ddc_valid = true;
736 router.ddc_mux_type = ddc_path->ucMuxType;
737 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
738 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
739 break;
740 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
741 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
742 record;
743 router.cd_valid = true;
744 router.cd_mux_type = cd_path->ucMuxType;
745 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
746 router.cd_mux_state = cd_path->ucMuxState[enum_id];
747 break;
748 }
749 record = (ATOM_COMMON_RECORD_HEADER *)
750 ((char *)record + record->ucRecordSize);
751 }
752 }
753 }
754 }
755 }
756
757 /* look up gpio for ddc, hpd */
758 ddc_bus.valid = false;
759 hpd.hpd = RADEON_HPD_NONE;
760 if ((le16_to_cpu(path->usDeviceTag) &
761 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
762 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
763 if (le16_to_cpu(path->usConnObjectId) ==
764 le16_to_cpu(con_obj->asObjects[j].
765 usObjectID)) {
766 ATOM_COMMON_RECORD_HEADER
767 *record =
768 (ATOM_COMMON_RECORD_HEADER
769 *)
770 (ctx->bios + data_offset +
771 le16_to_cpu(con_obj->
772 asObjects[j].
773 usRecordOffset));
774 ATOM_I2C_RECORD *i2c_record;
775 ATOM_HPD_INT_RECORD *hpd_record;
776 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
777
778 while (record->ucRecordSize > 0 &&
779 record->ucRecordType > 0 &&
780 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
781 switch (record->ucRecordType) {
782 case ATOM_I2C_RECORD_TYPE:
783 i2c_record =
784 (ATOM_I2C_RECORD *)
785 record;
786 i2c_config =
787 (ATOM_I2C_ID_CONFIG_ACCESS *)
788 &i2c_record->sucI2cId;
789 ddc_bus = radeon_lookup_i2c_gpio(rdev,
790 i2c_config->
791 ucAccess);
792 break;
793 case ATOM_HPD_INT_RECORD_TYPE:
794 hpd_record =
795 (ATOM_HPD_INT_RECORD *)
796 record;
797 gpio = radeon_lookup_gpio(rdev,
798 hpd_record->ucHPDIntGPIOID);
799 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
800 hpd.plugged_state = hpd_record->ucPlugged_PinState;
801 break;
802 }
803 record =
804 (ATOM_COMMON_RECORD_HEADER
805 *) ((char *)record
806 +
807 record->
808 ucRecordSize);
809 }
810 break;
811 }
812 }
813 }
814
815 /* needed for aux chan transactions */
816 ddc_bus.hpd = hpd.hpd;
817
818 conn_id = le16_to_cpu(path->usConnObjectId);
819
820 if (!radeon_atom_apply_quirks
821 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
822 &ddc_bus, &conn_id, &hpd))
823 continue;
824
825 radeon_add_atom_connector(dev,
826 conn_id,
827 le16_to_cpu(path->
828 usDeviceTag),
829 connector_type, &ddc_bus,
830 igp_lane_info,
831 connector_object_id,
832 &hpd,
833 &router);
834
835 }
836 }
837
838 radeon_link_encoder_connector(dev);
839
840 return true;
841 }
842
843 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
844 int connector_type,
845 uint16_t devices)
846 {
847 struct radeon_device *rdev = dev->dev_private;
848
849 if (rdev->flags & RADEON_IS_IGP) {
850 return supported_devices_connector_object_id_convert
851 [connector_type];
852 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
853 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
854 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
855 struct radeon_mode_info *mode_info = &rdev->mode_info;
856 struct atom_context *ctx = mode_info->atom_context;
857 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
858 uint16_t size, data_offset;
859 uint8_t frev, crev;
860 ATOM_XTMDS_INFO *xtmds;
861
862 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
863 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
864
865 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
866 if (connector_type == DRM_MODE_CONNECTOR_DVII)
867 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
868 else
869 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
870 } else {
871 if (connector_type == DRM_MODE_CONNECTOR_DVII)
872 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
873 else
874 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
875 }
876 } else
877 return supported_devices_connector_object_id_convert
878 [connector_type];
879 } else {
880 return supported_devices_connector_object_id_convert
881 [connector_type];
882 }
883 }
884
885 struct bios_connector {
886 bool valid;
887 uint16_t line_mux;
888 uint16_t devices;
889 int connector_type;
890 struct radeon_i2c_bus_rec ddc_bus;
891 struct radeon_hpd hpd;
892 };
893
894 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
895 drm_device
896 *dev)
897 {
898 struct radeon_device *rdev = dev->dev_private;
899 struct radeon_mode_info *mode_info = &rdev->mode_info;
900 struct atom_context *ctx = mode_info->atom_context;
901 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
902 uint16_t size, data_offset;
903 uint8_t frev, crev;
904 uint16_t device_support;
905 uint8_t dac;
906 union atom_supported_devices *supported_devices;
907 int i, j, max_device;
908 struct bios_connector *bios_connectors;
909 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
910 struct radeon_router router;
911
912 router.ddc_valid = false;
913 router.cd_valid = false;
914
915 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
916 if (!bios_connectors)
917 return false;
918
919 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
920 &data_offset)) {
921 kfree(bios_connectors);
922 return false;
923 }
924
925 supported_devices =
926 (union atom_supported_devices *)(ctx->bios + data_offset);
927
928 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
929
930 if (frev > 1)
931 max_device = ATOM_MAX_SUPPORTED_DEVICE;
932 else
933 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
934
935 for (i = 0; i < max_device; i++) {
936 ATOM_CONNECTOR_INFO_I2C ci =
937 supported_devices->info.asConnInfo[i];
938
939 bios_connectors[i].valid = false;
940
941 if (!(device_support & (1 << i))) {
942 continue;
943 }
944
945 if (i == ATOM_DEVICE_CV_INDEX) {
946 DRM_DEBUG_KMS("Skipping Component Video\n");
947 continue;
948 }
949
950 bios_connectors[i].connector_type =
951 supported_devices_connector_convert[ci.sucConnectorInfo.
952 sbfAccess.
953 bfConnectorType];
954
955 if (bios_connectors[i].connector_type ==
956 DRM_MODE_CONNECTOR_Unknown)
957 continue;
958
959 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
960
961 bios_connectors[i].line_mux =
962 ci.sucI2cId.ucAccess;
963
964 /* give tv unique connector ids */
965 if (i == ATOM_DEVICE_TV1_INDEX) {
966 bios_connectors[i].ddc_bus.valid = false;
967 bios_connectors[i].line_mux = 50;
968 } else if (i == ATOM_DEVICE_TV2_INDEX) {
969 bios_connectors[i].ddc_bus.valid = false;
970 bios_connectors[i].line_mux = 51;
971 } else if (i == ATOM_DEVICE_CV_INDEX) {
972 bios_connectors[i].ddc_bus.valid = false;
973 bios_connectors[i].line_mux = 52;
974 } else
975 bios_connectors[i].ddc_bus =
976 radeon_lookup_i2c_gpio(rdev,
977 bios_connectors[i].line_mux);
978
979 if ((crev > 1) && (frev > 1)) {
980 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
981 switch (isb) {
982 case 0x4:
983 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
984 break;
985 case 0xa:
986 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
987 break;
988 default:
989 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
990 break;
991 }
992 } else {
993 if (i == ATOM_DEVICE_DFP1_INDEX)
994 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
995 else if (i == ATOM_DEVICE_DFP2_INDEX)
996 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
997 else
998 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
999 }
1000
1001 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1002 * shared with a DVI port, we'll pick up the DVI connector when we
1003 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1004 */
1005 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1006 bios_connectors[i].connector_type =
1007 DRM_MODE_CONNECTOR_VGA;
1008
1009 if (!radeon_atom_apply_quirks
1010 (dev, (1 << i), &bios_connectors[i].connector_type,
1011 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1012 &bios_connectors[i].hpd))
1013 continue;
1014
1015 bios_connectors[i].valid = true;
1016 bios_connectors[i].devices = (1 << i);
1017
1018 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1019 radeon_add_atom_encoder(dev,
1020 radeon_get_encoder_enum(dev,
1021 (1 << i),
1022 dac),
1023 (1 << i),
1024 0);
1025 else
1026 radeon_add_legacy_encoder(dev,
1027 radeon_get_encoder_enum(dev,
1028 (1 << i),
1029 dac),
1030 (1 << i));
1031 }
1032
1033 /* combine shared connectors */
1034 for (i = 0; i < max_device; i++) {
1035 if (bios_connectors[i].valid) {
1036 for (j = 0; j < max_device; j++) {
1037 if (bios_connectors[j].valid && (i != j)) {
1038 if (bios_connectors[i].line_mux ==
1039 bios_connectors[j].line_mux) {
1040 /* make sure not to combine LVDS */
1041 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1042 bios_connectors[i].line_mux = 53;
1043 bios_connectors[i].ddc_bus.valid = false;
1044 continue;
1045 }
1046 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1047 bios_connectors[j].line_mux = 53;
1048 bios_connectors[j].ddc_bus.valid = false;
1049 continue;
1050 }
1051 /* combine analog and digital for DVI-I */
1052 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1053 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1054 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1055 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1056 bios_connectors[i].devices |=
1057 bios_connectors[j].devices;
1058 bios_connectors[i].connector_type =
1059 DRM_MODE_CONNECTOR_DVII;
1060 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1061 bios_connectors[i].hpd =
1062 bios_connectors[j].hpd;
1063 bios_connectors[j].valid = false;
1064 }
1065 }
1066 }
1067 }
1068 }
1069 }
1070
1071 /* add the connectors */
1072 for (i = 0; i < max_device; i++) {
1073 if (bios_connectors[i].valid) {
1074 uint16_t connector_object_id =
1075 atombios_get_connector_object_id(dev,
1076 bios_connectors[i].connector_type,
1077 bios_connectors[i].devices);
1078 radeon_add_atom_connector(dev,
1079 bios_connectors[i].line_mux,
1080 bios_connectors[i].devices,
1081 bios_connectors[i].
1082 connector_type,
1083 &bios_connectors[i].ddc_bus,
1084 0,
1085 connector_object_id,
1086 &bios_connectors[i].hpd,
1087 &router);
1088 }
1089 }
1090
1091 radeon_link_encoder_connector(dev);
1092
1093 kfree(bios_connectors);
1094 return true;
1095 }
1096
1097 union firmware_info {
1098 ATOM_FIRMWARE_INFO info;
1099 ATOM_FIRMWARE_INFO_V1_2 info_12;
1100 ATOM_FIRMWARE_INFO_V1_3 info_13;
1101 ATOM_FIRMWARE_INFO_V1_4 info_14;
1102 ATOM_FIRMWARE_INFO_V2_1 info_21;
1103 ATOM_FIRMWARE_INFO_V2_2 info_22;
1104 };
1105
1106 bool radeon_atom_get_clock_info(struct drm_device *dev)
1107 {
1108 struct radeon_device *rdev = dev->dev_private;
1109 struct radeon_mode_info *mode_info = &rdev->mode_info;
1110 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1111 union firmware_info *firmware_info;
1112 uint8_t frev, crev;
1113 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1114 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1115 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1116 struct radeon_pll *spll = &rdev->clock.spll;
1117 struct radeon_pll *mpll = &rdev->clock.mpll;
1118 uint16_t data_offset;
1119
1120 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1121 &frev, &crev, &data_offset)) {
1122 firmware_info =
1123 (union firmware_info *)(mode_info->atom_context->bios +
1124 data_offset);
1125 /* pixel clocks */
1126 p1pll->reference_freq =
1127 le16_to_cpu(firmware_info->info.usReferenceClock);
1128 p1pll->reference_div = 0;
1129
1130 if (crev < 2)
1131 p1pll->pll_out_min =
1132 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1133 else
1134 p1pll->pll_out_min =
1135 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1136 p1pll->pll_out_max =
1137 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1138
1139 if (crev >= 4) {
1140 p1pll->lcd_pll_out_min =
1141 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1142 if (p1pll->lcd_pll_out_min == 0)
1143 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1144 p1pll->lcd_pll_out_max =
1145 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1146 if (p1pll->lcd_pll_out_max == 0)
1147 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1148 } else {
1149 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1150 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1151 }
1152
1153 if (p1pll->pll_out_min == 0) {
1154 if (ASIC_IS_AVIVO(rdev))
1155 p1pll->pll_out_min = 64800;
1156 else
1157 p1pll->pll_out_min = 20000;
1158 }
1159
1160 p1pll->pll_in_min =
1161 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1162 p1pll->pll_in_max =
1163 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1164
1165 *p2pll = *p1pll;
1166
1167 /* system clock */
1168 if (ASIC_IS_DCE4(rdev))
1169 spll->reference_freq =
1170 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1171 else
1172 spll->reference_freq =
1173 le16_to_cpu(firmware_info->info.usReferenceClock);
1174 spll->reference_div = 0;
1175
1176 spll->pll_out_min =
1177 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1178 spll->pll_out_max =
1179 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1180
1181 /* ??? */
1182 if (spll->pll_out_min == 0) {
1183 if (ASIC_IS_AVIVO(rdev))
1184 spll->pll_out_min = 64800;
1185 else
1186 spll->pll_out_min = 20000;
1187 }
1188
1189 spll->pll_in_min =
1190 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1191 spll->pll_in_max =
1192 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1193
1194 /* memory clock */
1195 if (ASIC_IS_DCE4(rdev))
1196 mpll->reference_freq =
1197 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1198 else
1199 mpll->reference_freq =
1200 le16_to_cpu(firmware_info->info.usReferenceClock);
1201 mpll->reference_div = 0;
1202
1203 mpll->pll_out_min =
1204 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1205 mpll->pll_out_max =
1206 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1207
1208 /* ??? */
1209 if (mpll->pll_out_min == 0) {
1210 if (ASIC_IS_AVIVO(rdev))
1211 mpll->pll_out_min = 64800;
1212 else
1213 mpll->pll_out_min = 20000;
1214 }
1215
1216 mpll->pll_in_min =
1217 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1218 mpll->pll_in_max =
1219 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1220
1221 rdev->clock.default_sclk =
1222 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1223 rdev->clock.default_mclk =
1224 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1225
1226 if (ASIC_IS_DCE4(rdev)) {
1227 rdev->clock.default_dispclk =
1228 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1229 if (rdev->clock.default_dispclk == 0) {
1230 if (ASIC_IS_DCE5(rdev))
1231 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1232 else
1233 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1234 }
1235 rdev->clock.dp_extclk =
1236 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1237 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1238 }
1239 *dcpll = *p1pll;
1240
1241 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1242 if (rdev->clock.max_pixel_clock == 0)
1243 rdev->clock.max_pixel_clock = 40000;
1244
1245 /* not technically a clock, but... */
1246 rdev->mode_info.firmware_flags =
1247 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1248
1249 return true;
1250 }
1251
1252 return false;
1253 }
1254
1255 union igp_info {
1256 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1257 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1258 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1259 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1260 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1261 };
1262
1263 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1264 {
1265 struct radeon_mode_info *mode_info = &rdev->mode_info;
1266 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1267 union igp_info *igp_info;
1268 u8 frev, crev;
1269 u16 data_offset;
1270
1271 /* sideport is AMD only */
1272 if (rdev->family == CHIP_RS600)
1273 return false;
1274
1275 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1276 &frev, &crev, &data_offset)) {
1277 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1278 data_offset);
1279 switch (crev) {
1280 case 1:
1281 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1282 return true;
1283 break;
1284 case 2:
1285 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1286 return true;
1287 break;
1288 default:
1289 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1290 break;
1291 }
1292 }
1293 return false;
1294 }
1295
1296 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1297 struct radeon_encoder_int_tmds *tmds)
1298 {
1299 struct drm_device *dev = encoder->base.dev;
1300 struct radeon_device *rdev = dev->dev_private;
1301 struct radeon_mode_info *mode_info = &rdev->mode_info;
1302 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1303 uint16_t data_offset;
1304 struct _ATOM_TMDS_INFO *tmds_info;
1305 uint8_t frev, crev;
1306 uint16_t maxfreq;
1307 int i;
1308
1309 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1310 &frev, &crev, &data_offset)) {
1311 tmds_info =
1312 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1313 data_offset);
1314
1315 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1316 for (i = 0; i < 4; i++) {
1317 tmds->tmds_pll[i].freq =
1318 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1319 tmds->tmds_pll[i].value =
1320 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1321 tmds->tmds_pll[i].value |=
1322 (tmds_info->asMiscInfo[i].
1323 ucPLL_VCO_Gain & 0x3f) << 6;
1324 tmds->tmds_pll[i].value |=
1325 (tmds_info->asMiscInfo[i].
1326 ucPLL_DutyCycle & 0xf) << 12;
1327 tmds->tmds_pll[i].value |=
1328 (tmds_info->asMiscInfo[i].
1329 ucPLL_VoltageSwing & 0xf) << 16;
1330
1331 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1332 tmds->tmds_pll[i].freq,
1333 tmds->tmds_pll[i].value);
1334
1335 if (maxfreq == tmds->tmds_pll[i].freq) {
1336 tmds->tmds_pll[i].freq = 0xffffffff;
1337 break;
1338 }
1339 }
1340 return true;
1341 }
1342 return false;
1343 }
1344
1345 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1346 struct radeon_atom_ss *ss,
1347 int id)
1348 {
1349 struct radeon_mode_info *mode_info = &rdev->mode_info;
1350 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1351 uint16_t data_offset, size;
1352 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1353 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1354 uint8_t frev, crev;
1355 int i, num_indices;
1356
1357 memset(ss, 0, sizeof(struct radeon_atom_ss));
1358 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1359 &frev, &crev, &data_offset)) {
1360 ss_info =
1361 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1362
1363 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1364 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1365 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1366 ((u8 *)&ss_info->asSS_Info[0]);
1367 for (i = 0; i < num_indices; i++) {
1368 if (ss_assign->ucSS_Id == id) {
1369 ss->percentage =
1370 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1371 ss->type = ss_assign->ucSpreadSpectrumType;
1372 ss->step = ss_assign->ucSS_Step;
1373 ss->delay = ss_assign->ucSS_Delay;
1374 ss->range = ss_assign->ucSS_Range;
1375 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1376 return true;
1377 }
1378 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1379 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1380 }
1381 }
1382 return false;
1383 }
1384
1385 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1386 struct radeon_atom_ss *ss,
1387 int id)
1388 {
1389 struct radeon_mode_info *mode_info = &rdev->mode_info;
1390 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1391 u16 data_offset, size;
1392 union igp_info *igp_info;
1393 u8 frev, crev;
1394 u16 percentage = 0, rate = 0;
1395
1396 /* get any igp specific overrides */
1397 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1398 &frev, &crev, &data_offset)) {
1399 igp_info = (union igp_info *)
1400 (mode_info->atom_context->bios + data_offset);
1401 switch (crev) {
1402 case 6:
1403 switch (id) {
1404 case ASIC_INTERNAL_SS_ON_TMDS:
1405 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1406 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1407 break;
1408 case ASIC_INTERNAL_SS_ON_HDMI:
1409 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1410 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1411 break;
1412 case ASIC_INTERNAL_SS_ON_LVDS:
1413 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1414 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1415 break;
1416 }
1417 break;
1418 case 7:
1419 switch (id) {
1420 case ASIC_INTERNAL_SS_ON_TMDS:
1421 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1422 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1423 break;
1424 case ASIC_INTERNAL_SS_ON_HDMI:
1425 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1426 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1427 break;
1428 case ASIC_INTERNAL_SS_ON_LVDS:
1429 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1430 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1431 break;
1432 }
1433 break;
1434 case 8:
1435 switch (id) {
1436 case ASIC_INTERNAL_SS_ON_TMDS:
1437 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1438 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1439 break;
1440 case ASIC_INTERNAL_SS_ON_HDMI:
1441 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1442 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1443 break;
1444 case ASIC_INTERNAL_SS_ON_LVDS:
1445 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1446 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1447 break;
1448 }
1449 break;
1450 default:
1451 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1452 break;
1453 }
1454 if (percentage)
1455 ss->percentage = percentage;
1456 if (rate)
1457 ss->rate = rate;
1458 }
1459 }
1460
1461 union asic_ss_info {
1462 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1463 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1464 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1465 };
1466
1467 union asic_ss_assignment {
1468 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1469 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1470 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1471 };
1472
1473 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1474 struct radeon_atom_ss *ss,
1475 int id, u32 clock)
1476 {
1477 struct radeon_mode_info *mode_info = &rdev->mode_info;
1478 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1479 uint16_t data_offset, size;
1480 union asic_ss_info *ss_info;
1481 union asic_ss_assignment *ss_assign;
1482 uint8_t frev, crev;
1483 int i, num_indices;
1484
1485 if (id == ASIC_INTERNAL_MEMORY_SS) {
1486 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1487 return false;
1488 }
1489 if (id == ASIC_INTERNAL_ENGINE_SS) {
1490 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1491 return false;
1492 }
1493
1494 memset(ss, 0, sizeof(struct radeon_atom_ss));
1495 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1496 &frev, &crev, &data_offset)) {
1497
1498 ss_info =
1499 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1500
1501 switch (frev) {
1502 case 1:
1503 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1504 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1505
1506 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1507 for (i = 0; i < num_indices; i++) {
1508 if ((ss_assign->v1.ucClockIndication == id) &&
1509 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1510 ss->percentage =
1511 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1512 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1513 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1514 ss->percentage_divider = 100;
1515 return true;
1516 }
1517 ss_assign = (union asic_ss_assignment *)
1518 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1519 }
1520 break;
1521 case 2:
1522 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1523 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1524 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1525 for (i = 0; i < num_indices; i++) {
1526 if ((ss_assign->v2.ucClockIndication == id) &&
1527 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1528 ss->percentage =
1529 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1530 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1531 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1532 ss->percentage_divider = 100;
1533 if ((crev == 2) &&
1534 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1535 (id == ASIC_INTERNAL_MEMORY_SS)))
1536 ss->rate /= 100;
1537 return true;
1538 }
1539 ss_assign = (union asic_ss_assignment *)
1540 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1541 }
1542 break;
1543 case 3:
1544 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1545 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1546 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1547 for (i = 0; i < num_indices; i++) {
1548 if ((ss_assign->v3.ucClockIndication == id) &&
1549 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1550 ss->percentage =
1551 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1552 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1553 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1554 if (ss_assign->v3.ucSpreadSpectrumMode &
1555 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1556 ss->percentage_divider = 1000;
1557 else
1558 ss->percentage_divider = 100;
1559 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1560 (id == ASIC_INTERNAL_MEMORY_SS))
1561 ss->rate /= 100;
1562 if (rdev->flags & RADEON_IS_IGP)
1563 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1564 return true;
1565 }
1566 ss_assign = (union asic_ss_assignment *)
1567 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1568 }
1569 break;
1570 default:
1571 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1572 break;
1573 }
1574
1575 }
1576 return false;
1577 }
1578
1579 union lvds_info {
1580 struct _ATOM_LVDS_INFO info;
1581 struct _ATOM_LVDS_INFO_V12 info_12;
1582 };
1583
1584 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1585 radeon_encoder
1586 *encoder)
1587 {
1588 struct drm_device *dev = encoder->base.dev;
1589 struct radeon_device *rdev = dev->dev_private;
1590 struct radeon_mode_info *mode_info = &rdev->mode_info;
1591 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1592 uint16_t data_offset, misc;
1593 union lvds_info *lvds_info;
1594 uint8_t frev, crev;
1595 struct radeon_encoder_atom_dig *lvds = NULL;
1596 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1597
1598 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1599 &frev, &crev, &data_offset)) {
1600 lvds_info =
1601 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1602 lvds =
1603 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1604
1605 if (!lvds)
1606 return NULL;
1607
1608 lvds->native_mode.clock =
1609 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1610 lvds->native_mode.hdisplay =
1611 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1612 lvds->native_mode.vdisplay =
1613 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1614 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1615 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1616 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1617 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1618 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1619 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1620 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1621 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1622 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1623 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1624 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1625 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1626 lvds->panel_pwr_delay =
1627 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1628 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1629
1630 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1631 if (misc & ATOM_VSYNC_POLARITY)
1632 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1633 if (misc & ATOM_HSYNC_POLARITY)
1634 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1635 if (misc & ATOM_COMPOSITESYNC)
1636 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1637 if (misc & ATOM_INTERLACE)
1638 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1639 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1640 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1641
1642 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1643 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1644
1645 /* set crtc values */
1646 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1647
1648 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1649
1650 encoder->native_mode = lvds->native_mode;
1651
1652 if (encoder_enum == 2)
1653 lvds->linkb = true;
1654 else
1655 lvds->linkb = false;
1656
1657 /* parse the lcd record table */
1658 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1659 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1660 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1661 bool bad_record = false;
1662 u8 *record;
1663
1664 if ((frev == 1) && (crev < 2))
1665 /* absolute */
1666 record = (u8 *)(mode_info->atom_context->bios +
1667 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1668 else
1669 /* relative */
1670 record = (u8 *)(mode_info->atom_context->bios +
1671 data_offset +
1672 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1673 while (*record != ATOM_RECORD_END_TYPE) {
1674 switch (*record) {
1675 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1676 record += sizeof(ATOM_PATCH_RECORD_MODE);
1677 break;
1678 case LCD_RTS_RECORD_TYPE:
1679 record += sizeof(ATOM_LCD_RTS_RECORD);
1680 break;
1681 case LCD_CAP_RECORD_TYPE:
1682 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1683 break;
1684 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1685 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1686 if (fake_edid_record->ucFakeEDIDLength) {
1687 struct edid *edid;
1688 int edid_size =
1689 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1690 edid = kmalloc(edid_size, GFP_KERNEL);
1691 if (edid) {
1692 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1693 fake_edid_record->ucFakeEDIDLength);
1694
1695 if (drm_edid_is_valid(edid)) {
1696 rdev->mode_info.bios_hardcoded_edid = edid;
1697 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1698 } else
1699 kfree(edid);
1700 }
1701 }
1702 record += fake_edid_record->ucFakeEDIDLength ?
1703 fake_edid_record->ucFakeEDIDLength + 2 :
1704 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1705 break;
1706 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1707 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1708 lvds->native_mode.width_mm = panel_res_record->usHSize;
1709 lvds->native_mode.height_mm = panel_res_record->usVSize;
1710 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1711 break;
1712 default:
1713 DRM_ERROR("Bad LCD record %d\n", *record);
1714 bad_record = true;
1715 break;
1716 }
1717 if (bad_record)
1718 break;
1719 }
1720 }
1721 }
1722 return lvds;
1723 }
1724
1725 struct radeon_encoder_primary_dac *
1726 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1727 {
1728 struct drm_device *dev = encoder->base.dev;
1729 struct radeon_device *rdev = dev->dev_private;
1730 struct radeon_mode_info *mode_info = &rdev->mode_info;
1731 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1732 uint16_t data_offset;
1733 struct _COMPASSIONATE_DATA *dac_info;
1734 uint8_t frev, crev;
1735 uint8_t bg, dac;
1736 struct radeon_encoder_primary_dac *p_dac = NULL;
1737
1738 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1739 &frev, &crev, &data_offset)) {
1740 dac_info = (struct _COMPASSIONATE_DATA *)
1741 (mode_info->atom_context->bios + data_offset);
1742
1743 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1744
1745 if (!p_dac)
1746 return NULL;
1747
1748 bg = dac_info->ucDAC1_BG_Adjustment;
1749 dac = dac_info->ucDAC1_DAC_Adjustment;
1750 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1751
1752 }
1753 return p_dac;
1754 }
1755
1756 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1757 struct drm_display_mode *mode)
1758 {
1759 struct radeon_mode_info *mode_info = &rdev->mode_info;
1760 ATOM_ANALOG_TV_INFO *tv_info;
1761 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1762 ATOM_DTD_FORMAT *dtd_timings;
1763 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1764 u8 frev, crev;
1765 u16 data_offset, misc;
1766
1767 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1768 &frev, &crev, &data_offset))
1769 return false;
1770
1771 switch (crev) {
1772 case 1:
1773 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1774 if (index >= MAX_SUPPORTED_TV_TIMING)
1775 return false;
1776
1777 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1778 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1779 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1780 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1781 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1782
1783 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1784 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1785 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1786 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1787 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1788
1789 mode->flags = 0;
1790 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1791 if (misc & ATOM_VSYNC_POLARITY)
1792 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1793 if (misc & ATOM_HSYNC_POLARITY)
1794 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1795 if (misc & ATOM_COMPOSITESYNC)
1796 mode->flags |= DRM_MODE_FLAG_CSYNC;
1797 if (misc & ATOM_INTERLACE)
1798 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1799 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1800 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1801
1802 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1803
1804 if (index == 1) {
1805 /* PAL timings appear to have wrong values for totals */
1806 mode->crtc_htotal -= 1;
1807 mode->crtc_vtotal -= 1;
1808 }
1809 break;
1810 case 2:
1811 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1812 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1813 return false;
1814
1815 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1816 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1817 le16_to_cpu(dtd_timings->usHBlanking_Time);
1818 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1819 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1820 le16_to_cpu(dtd_timings->usHSyncOffset);
1821 mode->crtc_hsync_end = mode->crtc_hsync_start +
1822 le16_to_cpu(dtd_timings->usHSyncWidth);
1823
1824 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1825 le16_to_cpu(dtd_timings->usVBlanking_Time);
1826 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1827 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1828 le16_to_cpu(dtd_timings->usVSyncOffset);
1829 mode->crtc_vsync_end = mode->crtc_vsync_start +
1830 le16_to_cpu(dtd_timings->usVSyncWidth);
1831
1832 mode->flags = 0;
1833 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1834 if (misc & ATOM_VSYNC_POLARITY)
1835 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1836 if (misc & ATOM_HSYNC_POLARITY)
1837 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1838 if (misc & ATOM_COMPOSITESYNC)
1839 mode->flags |= DRM_MODE_FLAG_CSYNC;
1840 if (misc & ATOM_INTERLACE)
1841 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1842 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1843 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1844
1845 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1846 break;
1847 }
1848 return true;
1849 }
1850
1851 enum radeon_tv_std
1852 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1853 {
1854 struct radeon_mode_info *mode_info = &rdev->mode_info;
1855 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1856 uint16_t data_offset;
1857 uint8_t frev, crev;
1858 struct _ATOM_ANALOG_TV_INFO *tv_info;
1859 enum radeon_tv_std tv_std = TV_STD_NTSC;
1860
1861 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1862 &frev, &crev, &data_offset)) {
1863
1864 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1865 (mode_info->atom_context->bios + data_offset);
1866
1867 switch (tv_info->ucTV_BootUpDefaultStandard) {
1868 case ATOM_TV_NTSC:
1869 tv_std = TV_STD_NTSC;
1870 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1871 break;
1872 case ATOM_TV_NTSCJ:
1873 tv_std = TV_STD_NTSC_J;
1874 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1875 break;
1876 case ATOM_TV_PAL:
1877 tv_std = TV_STD_PAL;
1878 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1879 break;
1880 case ATOM_TV_PALM:
1881 tv_std = TV_STD_PAL_M;
1882 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1883 break;
1884 case ATOM_TV_PALN:
1885 tv_std = TV_STD_PAL_N;
1886 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1887 break;
1888 case ATOM_TV_PALCN:
1889 tv_std = TV_STD_PAL_CN;
1890 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1891 break;
1892 case ATOM_TV_PAL60:
1893 tv_std = TV_STD_PAL_60;
1894 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1895 break;
1896 case ATOM_TV_SECAM:
1897 tv_std = TV_STD_SECAM;
1898 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1899 break;
1900 default:
1901 tv_std = TV_STD_NTSC;
1902 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1903 break;
1904 }
1905 }
1906 return tv_std;
1907 }
1908
1909 struct radeon_encoder_tv_dac *
1910 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1911 {
1912 struct drm_device *dev = encoder->base.dev;
1913 struct radeon_device *rdev = dev->dev_private;
1914 struct radeon_mode_info *mode_info = &rdev->mode_info;
1915 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1916 uint16_t data_offset;
1917 struct _COMPASSIONATE_DATA *dac_info;
1918 uint8_t frev, crev;
1919 uint8_t bg, dac;
1920 struct radeon_encoder_tv_dac *tv_dac = NULL;
1921
1922 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1923 &frev, &crev, &data_offset)) {
1924
1925 dac_info = (struct _COMPASSIONATE_DATA *)
1926 (mode_info->atom_context->bios + data_offset);
1927
1928 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1929
1930 if (!tv_dac)
1931 return NULL;
1932
1933 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1934 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1935 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1936
1937 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1938 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1939 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1940
1941 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1942 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1943 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1944
1945 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1946 }
1947 return tv_dac;
1948 }
1949
1950 static const char *thermal_controller_names[] = {
1951 "NONE",
1952 "lm63",
1953 "adm1032",
1954 "adm1030",
1955 "max6649",
1956 "lm64",
1957 "f75375",
1958 "asc7xxx",
1959 };
1960
1961 static const char *pp_lib_thermal_controller_names[] = {
1962 "NONE",
1963 "lm63",
1964 "adm1032",
1965 "adm1030",
1966 "max6649",
1967 "lm64",
1968 "f75375",
1969 "RV6xx",
1970 "RV770",
1971 "adt7473",
1972 "NONE",
1973 "External GPIO",
1974 "Evergreen",
1975 "emc2103",
1976 "Sumo",
1977 "Northern Islands",
1978 "Southern Islands",
1979 "lm96163",
1980 "Sea Islands",
1981 };
1982
1983 union power_info {
1984 struct _ATOM_POWERPLAY_INFO info;
1985 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1986 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1987 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1988 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1989 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1990 };
1991
1992 union pplib_clock_info {
1993 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1994 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1995 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1996 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1997 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
1998 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
1999 };
2000
2001 union pplib_power_state {
2002 struct _ATOM_PPLIB_STATE v1;
2003 struct _ATOM_PPLIB_STATE_V2 v2;
2004 };
2005
2006 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2007 int state_index,
2008 u32 misc, u32 misc2)
2009 {
2010 rdev->pm.power_state[state_index].misc = misc;
2011 rdev->pm.power_state[state_index].misc2 = misc2;
2012 /* order matters! */
2013 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2014 rdev->pm.power_state[state_index].type =
2015 POWER_STATE_TYPE_POWERSAVE;
2016 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2017 rdev->pm.power_state[state_index].type =
2018 POWER_STATE_TYPE_BATTERY;
2019 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2020 rdev->pm.power_state[state_index].type =
2021 POWER_STATE_TYPE_BATTERY;
2022 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2023 rdev->pm.power_state[state_index].type =
2024 POWER_STATE_TYPE_BALANCED;
2025 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2026 rdev->pm.power_state[state_index].type =
2027 POWER_STATE_TYPE_PERFORMANCE;
2028 rdev->pm.power_state[state_index].flags &=
2029 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2030 }
2031 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2032 rdev->pm.power_state[state_index].type =
2033 POWER_STATE_TYPE_BALANCED;
2034 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2035 rdev->pm.power_state[state_index].type =
2036 POWER_STATE_TYPE_DEFAULT;
2037 rdev->pm.default_power_state_index = state_index;
2038 rdev->pm.power_state[state_index].default_clock_mode =
2039 &rdev->pm.power_state[state_index].clock_info[0];
2040 } else if (state_index == 0) {
2041 rdev->pm.power_state[state_index].clock_info[0].flags |=
2042 RADEON_PM_MODE_NO_DISPLAY;
2043 }
2044 }
2045
2046 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2047 {
2048 struct radeon_mode_info *mode_info = &rdev->mode_info;
2049 u32 misc, misc2 = 0;
2050 int num_modes = 0, i;
2051 int state_index = 0;
2052 struct radeon_i2c_bus_rec i2c_bus;
2053 union power_info *power_info;
2054 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2055 u16 data_offset;
2056 u8 frev, crev;
2057
2058 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2059 &frev, &crev, &data_offset))
2060 return state_index;
2061 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2062
2063 /* add the i2c bus for thermal/fan chip */
2064 if ((power_info->info.ucOverdriveThermalController > 0) &&
2065 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2066 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2067 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2068 power_info->info.ucOverdriveControllerAddress >> 1);
2069 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2070 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2071 if (rdev->pm.i2c_bus) {
2072 struct i2c_board_info info = { };
2073 const char *name = thermal_controller_names[power_info->info.
2074 ucOverdriveThermalController];
2075 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2076 strlcpy(info.type, name, sizeof(info.type));
2077 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2078 }
2079 }
2080 num_modes = power_info->info.ucNumOfPowerModeEntries;
2081 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2082 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2083 if (num_modes == 0)
2084 return state_index;
2085 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2086 if (!rdev->pm.power_state)
2087 return state_index;
2088 /* last mode is usually default, array is low to high */
2089 for (i = 0; i < num_modes; i++) {
2090 rdev->pm.power_state[state_index].clock_info =
2091 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2092 if (!rdev->pm.power_state[state_index].clock_info)
2093 return state_index;
2094 rdev->pm.power_state[state_index].num_clock_modes = 1;
2095 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2096 switch (frev) {
2097 case 1:
2098 rdev->pm.power_state[state_index].clock_info[0].mclk =
2099 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2100 rdev->pm.power_state[state_index].clock_info[0].sclk =
2101 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2102 /* skip invalid modes */
2103 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2104 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2105 continue;
2106 rdev->pm.power_state[state_index].pcie_lanes =
2107 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2108 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2109 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2110 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2111 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2112 VOLTAGE_GPIO;
2113 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2114 radeon_lookup_gpio(rdev,
2115 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2116 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2117 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2118 true;
2119 else
2120 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2121 false;
2122 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2123 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2124 VOLTAGE_VDDC;
2125 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2126 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2127 }
2128 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2129 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2130 state_index++;
2131 break;
2132 case 2:
2133 rdev->pm.power_state[state_index].clock_info[0].mclk =
2134 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2135 rdev->pm.power_state[state_index].clock_info[0].sclk =
2136 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2137 /* skip invalid modes */
2138 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2139 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2140 continue;
2141 rdev->pm.power_state[state_index].pcie_lanes =
2142 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2143 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2144 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2145 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2146 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2147 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2148 VOLTAGE_GPIO;
2149 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2150 radeon_lookup_gpio(rdev,
2151 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2152 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2153 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2154 true;
2155 else
2156 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2157 false;
2158 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2159 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2160 VOLTAGE_VDDC;
2161 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2162 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2163 }
2164 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2165 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2166 state_index++;
2167 break;
2168 case 3:
2169 rdev->pm.power_state[state_index].clock_info[0].mclk =
2170 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2171 rdev->pm.power_state[state_index].clock_info[0].sclk =
2172 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2173 /* skip invalid modes */
2174 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2175 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2176 continue;
2177 rdev->pm.power_state[state_index].pcie_lanes =
2178 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2179 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2180 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2181 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2182 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2183 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2184 VOLTAGE_GPIO;
2185 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2186 radeon_lookup_gpio(rdev,
2187 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2188 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2189 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2190 true;
2191 else
2192 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2193 false;
2194 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2195 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2196 VOLTAGE_VDDC;
2197 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2198 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2199 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2200 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2201 true;
2202 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2203 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2204 }
2205 }
2206 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2207 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2208 state_index++;
2209 break;
2210 }
2211 }
2212 /* last mode is usually default */
2213 if (rdev->pm.default_power_state_index == -1) {
2214 rdev->pm.power_state[state_index - 1].type =
2215 POWER_STATE_TYPE_DEFAULT;
2216 rdev->pm.default_power_state_index = state_index - 1;
2217 rdev->pm.power_state[state_index - 1].default_clock_mode =
2218 &rdev->pm.power_state[state_index - 1].clock_info[0];
2219 rdev->pm.power_state[state_index].flags &=
2220 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2221 rdev->pm.power_state[state_index].misc = 0;
2222 rdev->pm.power_state[state_index].misc2 = 0;
2223 }
2224 return state_index;
2225 }
2226
2227 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2228 ATOM_PPLIB_THERMALCONTROLLER *controller)
2229 {
2230 struct radeon_i2c_bus_rec i2c_bus;
2231
2232 /* add the i2c bus for thermal/fan chip */
2233 if (controller->ucType > 0) {
2234 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2235 DRM_INFO("Internal thermal controller %s fan control\n",
2236 (controller->ucFanParameters &
2237 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2238 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2239 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2240 DRM_INFO("Internal thermal controller %s fan control\n",
2241 (controller->ucFanParameters &
2242 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2243 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2244 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2245 DRM_INFO("Internal thermal controller %s fan control\n",
2246 (controller->ucFanParameters &
2247 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2248 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2249 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2250 DRM_INFO("Internal thermal controller %s fan control\n",
2251 (controller->ucFanParameters &
2252 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2253 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2254 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2255 DRM_INFO("Internal thermal controller %s fan control\n",
2256 (controller->ucFanParameters &
2257 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2258 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2259 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2260 DRM_INFO("Internal thermal controller %s fan control\n",
2261 (controller->ucFanParameters &
2262 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2263 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2264 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2265 DRM_INFO("Internal thermal controller %s fan control\n",
2266 (controller->ucFanParameters &
2267 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2268 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2269 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2270 DRM_INFO("Internal thermal controller %s fan control\n",
2271 (controller->ucFanParameters &
2272 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2273 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2274 } else if ((controller->ucType ==
2275 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2276 (controller->ucType ==
2277 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2278 (controller->ucType ==
2279 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2280 DRM_INFO("Special thermal controller config\n");
2281 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2282 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2283 pp_lib_thermal_controller_names[controller->ucType],
2284 controller->ucI2cAddress >> 1,
2285 (controller->ucFanParameters &
2286 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2287 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2288 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2289 if (rdev->pm.i2c_bus) {
2290 struct i2c_board_info info = { };
2291 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2292 info.addr = controller->ucI2cAddress >> 1;
2293 strlcpy(info.type, name, sizeof(info.type));
2294 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2295 }
2296 } else {
2297 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2298 controller->ucType,
2299 controller->ucI2cAddress >> 1,
2300 (controller->ucFanParameters &
2301 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2302 }
2303 }
2304 }
2305
2306 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2307 u16 *vddc, u16 *vddci, u16 *mvdd)
2308 {
2309 struct radeon_mode_info *mode_info = &rdev->mode_info;
2310 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2311 u8 frev, crev;
2312 u16 data_offset;
2313 union firmware_info *firmware_info;
2314
2315 *vddc = 0;
2316 *vddci = 0;
2317 *mvdd = 0;
2318
2319 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2320 &frev, &crev, &data_offset)) {
2321 firmware_info =
2322 (union firmware_info *)(mode_info->atom_context->bios +
2323 data_offset);
2324 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2325 if ((frev == 2) && (crev >= 2)) {
2326 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2327 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2328 }
2329 }
2330 }
2331
2332 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2333 int state_index, int mode_index,
2334 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2335 {
2336 int j;
2337 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2338 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2339 u16 vddc, vddci, mvdd;
2340
2341 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2342
2343 rdev->pm.power_state[state_index].misc = misc;
2344 rdev->pm.power_state[state_index].misc2 = misc2;
2345 rdev->pm.power_state[state_index].pcie_lanes =
2346 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2347 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2348 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2349 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2350 rdev->pm.power_state[state_index].type =
2351 POWER_STATE_TYPE_BATTERY;
2352 break;
2353 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2354 rdev->pm.power_state[state_index].type =
2355 POWER_STATE_TYPE_BALANCED;
2356 break;
2357 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2358 rdev->pm.power_state[state_index].type =
2359 POWER_STATE_TYPE_PERFORMANCE;
2360 break;
2361 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2362 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2363 rdev->pm.power_state[state_index].type =
2364 POWER_STATE_TYPE_PERFORMANCE;
2365 break;
2366 }
2367 rdev->pm.power_state[state_index].flags = 0;
2368 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2369 rdev->pm.power_state[state_index].flags |=
2370 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2371 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2372 rdev->pm.power_state[state_index].type =
2373 POWER_STATE_TYPE_DEFAULT;
2374 rdev->pm.default_power_state_index = state_index;
2375 rdev->pm.power_state[state_index].default_clock_mode =
2376 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2377 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2378 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2379 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2380 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2381 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2382 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2383 } else {
2384 u16 max_vddci = 0;
2385
2386 if (ASIC_IS_DCE4(rdev))
2387 radeon_atom_get_max_voltage(rdev,
2388 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2389 &max_vddci);
2390 /* patch the table values with the default sclk/mclk from firmware info */
2391 for (j = 0; j < mode_index; j++) {
2392 rdev->pm.power_state[state_index].clock_info[j].mclk =
2393 rdev->clock.default_mclk;
2394 rdev->pm.power_state[state_index].clock_info[j].sclk =
2395 rdev->clock.default_sclk;
2396 if (vddc)
2397 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2398 vddc;
2399 if (max_vddci)
2400 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2401 max_vddci;
2402 }
2403 }
2404 }
2405 }
2406
2407 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2408 int state_index, int mode_index,
2409 union pplib_clock_info *clock_info)
2410 {
2411 u32 sclk, mclk;
2412 u16 vddc;
2413
2414 if (rdev->flags & RADEON_IS_IGP) {
2415 if (rdev->family >= CHIP_PALM) {
2416 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2417 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2418 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2419 } else {
2420 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2421 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2422 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2423 }
2424 } else if (rdev->family >= CHIP_BONAIRE) {
2425 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2426 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2427 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2428 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2429 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2430 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2431 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2432 VOLTAGE_NONE;
2433 } else if (rdev->family >= CHIP_TAHITI) {
2434 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2435 sclk |= clock_info->si.ucEngineClockHigh << 16;
2436 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2437 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2438 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2439 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2440 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2441 VOLTAGE_SW;
2442 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2443 le16_to_cpu(clock_info->si.usVDDC);
2444 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2445 le16_to_cpu(clock_info->si.usVDDCI);
2446 } else if (rdev->family >= CHIP_CEDAR) {
2447 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2448 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2449 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2450 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2451 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2452 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2453 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2454 VOLTAGE_SW;
2455 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2456 le16_to_cpu(clock_info->evergreen.usVDDC);
2457 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2458 le16_to_cpu(clock_info->evergreen.usVDDCI);
2459 } else {
2460 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2461 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2462 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2463 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2464 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2465 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2466 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2467 VOLTAGE_SW;
2468 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2469 le16_to_cpu(clock_info->r600.usVDDC);
2470 }
2471
2472 /* patch up vddc if necessary */
2473 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2474 case ATOM_VIRTUAL_VOLTAGE_ID0:
2475 case ATOM_VIRTUAL_VOLTAGE_ID1:
2476 case ATOM_VIRTUAL_VOLTAGE_ID2:
2477 case ATOM_VIRTUAL_VOLTAGE_ID3:
2478 case ATOM_VIRTUAL_VOLTAGE_ID4:
2479 case ATOM_VIRTUAL_VOLTAGE_ID5:
2480 case ATOM_VIRTUAL_VOLTAGE_ID6:
2481 case ATOM_VIRTUAL_VOLTAGE_ID7:
2482 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2483 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2484 &vddc) == 0)
2485 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2486 break;
2487 default:
2488 break;
2489 }
2490
2491 if (rdev->flags & RADEON_IS_IGP) {
2492 /* skip invalid modes */
2493 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2494 return false;
2495 } else {
2496 /* skip invalid modes */
2497 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2498 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2499 return false;
2500 }
2501 return true;
2502 }
2503
2504 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2505 {
2506 struct radeon_mode_info *mode_info = &rdev->mode_info;
2507 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2508 union pplib_power_state *power_state;
2509 int i, j;
2510 int state_index = 0, mode_index = 0;
2511 union pplib_clock_info *clock_info;
2512 bool valid;
2513 union power_info *power_info;
2514 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2515 u16 data_offset;
2516 u8 frev, crev;
2517
2518 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2519 &frev, &crev, &data_offset))
2520 return state_index;
2521 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2522
2523 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2524 if (power_info->pplib.ucNumStates == 0)
2525 return state_index;
2526 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2527 power_info->pplib.ucNumStates, GFP_KERNEL);
2528 if (!rdev->pm.power_state)
2529 return state_index;
2530 /* first mode is usually default, followed by low to high */
2531 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2532 mode_index = 0;
2533 power_state = (union pplib_power_state *)
2534 (mode_info->atom_context->bios + data_offset +
2535 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2536 i * power_info->pplib.ucStateEntrySize);
2537 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2538 (mode_info->atom_context->bios + data_offset +
2539 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2540 (power_state->v1.ucNonClockStateIndex *
2541 power_info->pplib.ucNonClockSize));
2542 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2543 ((power_info->pplib.ucStateEntrySize - 1) ?
2544 (power_info->pplib.ucStateEntrySize - 1) : 1),
2545 GFP_KERNEL);
2546 if (!rdev->pm.power_state[i].clock_info)
2547 return state_index;
2548 if (power_info->pplib.ucStateEntrySize - 1) {
2549 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2550 clock_info = (union pplib_clock_info *)
2551 (mode_info->atom_context->bios + data_offset +
2552 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2553 (power_state->v1.ucClockStateIndices[j] *
2554 power_info->pplib.ucClockInfoSize));
2555 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2556 state_index, mode_index,
2557 clock_info);
2558 if (valid)
2559 mode_index++;
2560 }
2561 } else {
2562 rdev->pm.power_state[state_index].clock_info[0].mclk =
2563 rdev->clock.default_mclk;
2564 rdev->pm.power_state[state_index].clock_info[0].sclk =
2565 rdev->clock.default_sclk;
2566 mode_index++;
2567 }
2568 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2569 if (mode_index) {
2570 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2571 non_clock_info);
2572 state_index++;
2573 }
2574 }
2575 /* if multiple clock modes, mark the lowest as no display */
2576 for (i = 0; i < state_index; i++) {
2577 if (rdev->pm.power_state[i].num_clock_modes > 1)
2578 rdev->pm.power_state[i].clock_info[0].flags |=
2579 RADEON_PM_MODE_NO_DISPLAY;
2580 }
2581 /* first mode is usually default */
2582 if (rdev->pm.default_power_state_index == -1) {
2583 rdev->pm.power_state[0].type =
2584 POWER_STATE_TYPE_DEFAULT;
2585 rdev->pm.default_power_state_index = 0;
2586 rdev->pm.power_state[0].default_clock_mode =
2587 &rdev->pm.power_state[0].clock_info[0];
2588 }
2589 return state_index;
2590 }
2591
2592 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2593 {
2594 struct radeon_mode_info *mode_info = &rdev->mode_info;
2595 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2596 union pplib_power_state *power_state;
2597 int i, j, non_clock_array_index, clock_array_index;
2598 int state_index = 0, mode_index = 0;
2599 union pplib_clock_info *clock_info;
2600 struct _StateArray *state_array;
2601 struct _ClockInfoArray *clock_info_array;
2602 struct _NonClockInfoArray *non_clock_info_array;
2603 bool valid;
2604 union power_info *power_info;
2605 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2606 u16 data_offset;
2607 u8 frev, crev;
2608 u8 *power_state_offset;
2609
2610 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2611 &frev, &crev, &data_offset))
2612 return state_index;
2613 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2614
2615 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2616 state_array = (struct _StateArray *)
2617 (mode_info->atom_context->bios + data_offset +
2618 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2619 clock_info_array = (struct _ClockInfoArray *)
2620 (mode_info->atom_context->bios + data_offset +
2621 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2622 non_clock_info_array = (struct _NonClockInfoArray *)
2623 (mode_info->atom_context->bios + data_offset +
2624 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2625 if (state_array->ucNumEntries == 0)
2626 return state_index;
2627 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2628 state_array->ucNumEntries, GFP_KERNEL);
2629 if (!rdev->pm.power_state)
2630 return state_index;
2631 power_state_offset = (u8 *)state_array->states;
2632 for (i = 0; i < state_array->ucNumEntries; i++) {
2633 mode_index = 0;
2634 power_state = (union pplib_power_state *)power_state_offset;
2635 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2636 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2637 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2638 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2639 (power_state->v2.ucNumDPMLevels ?
2640 power_state->v2.ucNumDPMLevels : 1),
2641 GFP_KERNEL);
2642 if (!rdev->pm.power_state[i].clock_info)
2643 return state_index;
2644 if (power_state->v2.ucNumDPMLevels) {
2645 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2646 clock_array_index = power_state->v2.clockInfoIndex[j];
2647 clock_info = (union pplib_clock_info *)
2648 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2649 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2650 state_index, mode_index,
2651 clock_info);
2652 if (valid)
2653 mode_index++;
2654 }
2655 } else {
2656 rdev->pm.power_state[state_index].clock_info[0].mclk =
2657 rdev->clock.default_mclk;
2658 rdev->pm.power_state[state_index].clock_info[0].sclk =
2659 rdev->clock.default_sclk;
2660 mode_index++;
2661 }
2662 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2663 if (mode_index) {
2664 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2665 non_clock_info);
2666 state_index++;
2667 }
2668 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2669 }
2670 /* if multiple clock modes, mark the lowest as no display */
2671 for (i = 0; i < state_index; i++) {
2672 if (rdev->pm.power_state[i].num_clock_modes > 1)
2673 rdev->pm.power_state[i].clock_info[0].flags |=
2674 RADEON_PM_MODE_NO_DISPLAY;
2675 }
2676 /* first mode is usually default */
2677 if (rdev->pm.default_power_state_index == -1) {
2678 rdev->pm.power_state[0].type =
2679 POWER_STATE_TYPE_DEFAULT;
2680 rdev->pm.default_power_state_index = 0;
2681 rdev->pm.power_state[0].default_clock_mode =
2682 &rdev->pm.power_state[0].clock_info[0];
2683 }
2684 return state_index;
2685 }
2686
2687 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2688 {
2689 struct radeon_mode_info *mode_info = &rdev->mode_info;
2690 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2691 u16 data_offset;
2692 u8 frev, crev;
2693 int state_index = 0;
2694
2695 rdev->pm.default_power_state_index = -1;
2696
2697 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2698 &frev, &crev, &data_offset)) {
2699 switch (frev) {
2700 case 1:
2701 case 2:
2702 case 3:
2703 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2704 break;
2705 case 4:
2706 case 5:
2707 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2708 break;
2709 case 6:
2710 state_index = radeon_atombios_parse_power_table_6(rdev);
2711 break;
2712 default:
2713 break;
2714 }
2715 }
2716
2717 if (state_index == 0) {
2718 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2719 if (rdev->pm.power_state) {
2720 rdev->pm.power_state[0].clock_info =
2721 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2722 if (rdev->pm.power_state[0].clock_info) {
2723 /* add the default mode */
2724 rdev->pm.power_state[state_index].type =
2725 POWER_STATE_TYPE_DEFAULT;
2726 rdev->pm.power_state[state_index].num_clock_modes = 1;
2727 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2728 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2729 rdev->pm.power_state[state_index].default_clock_mode =
2730 &rdev->pm.power_state[state_index].clock_info[0];
2731 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2732 rdev->pm.power_state[state_index].pcie_lanes = 16;
2733 rdev->pm.default_power_state_index = state_index;
2734 rdev->pm.power_state[state_index].flags = 0;
2735 state_index++;
2736 }
2737 }
2738 }
2739
2740 rdev->pm.num_power_states = state_index;
2741
2742 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2743 rdev->pm.current_clock_mode_index = 0;
2744 if (rdev->pm.default_power_state_index >= 0)
2745 rdev->pm.current_vddc =
2746 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2747 else
2748 rdev->pm.current_vddc = 0;
2749 }
2750
2751 union get_clock_dividers {
2752 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2753 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2754 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2755 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2756 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2757 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2758 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2759 };
2760
2761 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2762 u8 clock_type,
2763 u32 clock,
2764 bool strobe_mode,
2765 struct atom_clock_dividers *dividers)
2766 {
2767 union get_clock_dividers args;
2768 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2769 u8 frev, crev;
2770
2771 memset(&args, 0, sizeof(args));
2772 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2773
2774 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2775 return -EINVAL;
2776
2777 switch (crev) {
2778 case 1:
2779 /* r4xx, r5xx */
2780 args.v1.ucAction = clock_type;
2781 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2782
2783 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2784
2785 dividers->post_div = args.v1.ucPostDiv;
2786 dividers->fb_div = args.v1.ucFbDiv;
2787 dividers->enable_post_div = true;
2788 break;
2789 case 2:
2790 case 3:
2791 case 5:
2792 /* r6xx, r7xx, evergreen, ni, si */
2793 if (rdev->family <= CHIP_RV770) {
2794 args.v2.ucAction = clock_type;
2795 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2796
2797 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2798
2799 dividers->post_div = args.v2.ucPostDiv;
2800 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2801 dividers->ref_div = args.v2.ucAction;
2802 if (rdev->family == CHIP_RV770) {
2803 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2804 true : false;
2805 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2806 } else
2807 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2808 } else {
2809 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2810 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2811
2812 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2813
2814 dividers->post_div = args.v3.ucPostDiv;
2815 dividers->enable_post_div = (args.v3.ucCntlFlag &
2816 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2817 dividers->enable_dithen = (args.v3.ucCntlFlag &
2818 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2819 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2820 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2821 dividers->ref_div = args.v3.ucRefDiv;
2822 dividers->vco_mode = (args.v3.ucCntlFlag &
2823 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2824 } else {
2825 /* for SI we use ComputeMemoryClockParam for memory plls */
2826 if (rdev->family >= CHIP_TAHITI)
2827 return -EINVAL;
2828 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2829 if (strobe_mode)
2830 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2831
2832 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2833
2834 dividers->post_div = args.v5.ucPostDiv;
2835 dividers->enable_post_div = (args.v5.ucCntlFlag &
2836 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2837 dividers->enable_dithen = (args.v5.ucCntlFlag &
2838 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2839 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2840 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2841 dividers->ref_div = args.v5.ucRefDiv;
2842 dividers->vco_mode = (args.v5.ucCntlFlag &
2843 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2844 }
2845 }
2846 break;
2847 case 4:
2848 /* fusion */
2849 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2850
2851 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2852
2853 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2854 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2855 break;
2856 case 6:
2857 /* CI */
2858 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2859 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2860 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2861
2862 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2863
2864 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2865 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2866 dividers->ref_div = args.v6_out.ucPllRefDiv;
2867 dividers->post_div = args.v6_out.ucPllPostDiv;
2868 dividers->flags = args.v6_out.ucPllCntlFlag;
2869 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2870 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2871 break;
2872 default:
2873 return -EINVAL;
2874 }
2875 return 0;
2876 }
2877
2878 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2879 u32 clock,
2880 bool strobe_mode,
2881 struct atom_mpll_param *mpll_param)
2882 {
2883 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2884 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2885 u8 frev, crev;
2886
2887 memset(&args, 0, sizeof(args));
2888 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2889
2890 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2891 return -EINVAL;
2892
2893 switch (frev) {
2894 case 2:
2895 switch (crev) {
2896 case 1:
2897 /* SI */
2898 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2899 args.ucInputFlag = 0;
2900 if (strobe_mode)
2901 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2902
2903 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2904
2905 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2906 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2907 mpll_param->post_div = args.ucPostDiv;
2908 mpll_param->dll_speed = args.ucDllSpeed;
2909 mpll_param->bwcntl = args.ucBWCntl;
2910 mpll_param->vco_mode =
2911 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2912 mpll_param->yclk_sel =
2913 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2914 mpll_param->qdr =
2915 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2916 mpll_param->half_rate =
2917 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2918 break;
2919 default:
2920 return -EINVAL;
2921 }
2922 break;
2923 default:
2924 return -EINVAL;
2925 }
2926 return 0;
2927 }
2928
2929 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2930 {
2931 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2932 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2933
2934 args.ucEnable = enable;
2935
2936 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2937 }
2938
2939 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2940 {
2941 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2942 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2943
2944 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2945 return le32_to_cpu(args.ulReturnEngineClock);
2946 }
2947
2948 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2949 {
2950 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2951 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2952
2953 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2954 return le32_to_cpu(args.ulReturnMemoryClock);
2955 }
2956
2957 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2958 uint32_t eng_clock)
2959 {
2960 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2961 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2962
2963 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2964
2965 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2966 }
2967
2968 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2969 uint32_t mem_clock)
2970 {
2971 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2972 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2973
2974 if (rdev->flags & RADEON_IS_IGP)
2975 return;
2976
2977 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2978
2979 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2980 }
2981
2982 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
2983 u32 eng_clock, u32 mem_clock)
2984 {
2985 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2986 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
2987 u32 tmp;
2988
2989 memset(&args, 0, sizeof(args));
2990
2991 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
2992 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
2993
2994 args.ulTargetEngineClock = cpu_to_le32(tmp);
2995 if (mem_clock)
2996 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
2997
2998 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2999 }
3000
3001 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3002 u32 mem_clock)
3003 {
3004 u32 args;
3005 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3006
3007 args = cpu_to_le32(mem_clock); /* 10 khz */
3008
3009 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3010 }
3011
3012 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3013 u32 mem_clock)
3014 {
3015 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3016 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3017 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3018
3019 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3020
3021 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3022 }
3023
3024 union set_voltage {
3025 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3026 struct _SET_VOLTAGE_PARAMETERS v1;
3027 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3028 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3029 };
3030
3031 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3032 {
3033 union set_voltage args;
3034 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3035 u8 frev, crev, volt_index = voltage_level;
3036
3037 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3038 return;
3039
3040 /* 0xff01 is a flag rather then an actual voltage */
3041 if (voltage_level == 0xff01)
3042 return;
3043
3044 switch (crev) {
3045 case 1:
3046 args.v1.ucVoltageType = voltage_type;
3047 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3048 args.v1.ucVoltageIndex = volt_index;
3049 break;
3050 case 2:
3051 args.v2.ucVoltageType = voltage_type;
3052 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3053 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3054 break;
3055 case 3:
3056 args.v3.ucVoltageType = voltage_type;
3057 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3058 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3059 break;
3060 default:
3061 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3062 return;
3063 }
3064
3065 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3066 }
3067
3068 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3069 u16 voltage_id, u16 *voltage)
3070 {
3071 union set_voltage args;
3072 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3073 u8 frev, crev;
3074
3075 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3076 return -EINVAL;
3077
3078 switch (crev) {
3079 case 1:
3080 return -EINVAL;
3081 case 2:
3082 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3083 args.v2.ucVoltageMode = 0;
3084 args.v2.usVoltageLevel = 0;
3085
3086 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3087
3088 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3089 break;
3090 case 3:
3091 args.v3.ucVoltageType = voltage_type;
3092 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3093 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3094
3095 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3096
3097 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3098 break;
3099 default:
3100 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3101 return -EINVAL;
3102 }
3103
3104 return 0;
3105 }
3106
3107 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3108 u16 *voltage,
3109 u16 leakage_idx)
3110 {
3111 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3112 }
3113
3114 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3115 u16 *leakage_id)
3116 {
3117 union set_voltage args;
3118 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3119 u8 frev, crev;
3120
3121 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3122 return -EINVAL;
3123
3124 switch (crev) {
3125 case 3:
3126 case 4:
3127 args.v3.ucVoltageType = 0;
3128 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3129 args.v3.usVoltageLevel = 0;
3130
3131 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3132
3133 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3134 break;
3135 default:
3136 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3137 return -EINVAL;
3138 }
3139
3140 return 0;
3141 }
3142
3143 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3144 u16 *vddc, u16 *vddci,
3145 u16 virtual_voltage_id,
3146 u16 vbios_voltage_id)
3147 {
3148 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3149 u8 frev, crev;
3150 u16 data_offset, size;
3151 int i, j;
3152 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3153 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3154
3155 *vddc = 0;
3156 *vddci = 0;
3157
3158 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3159 &frev, &crev, &data_offset))
3160 return -EINVAL;
3161
3162 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3163 (rdev->mode_info.atom_context->bios + data_offset);
3164
3165 switch (frev) {
3166 case 1:
3167 return -EINVAL;
3168 case 2:
3169 switch (crev) {
3170 case 1:
3171 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3172 return -EINVAL;
3173 leakage_bin = (u16 *)
3174 (rdev->mode_info.atom_context->bios + data_offset +
3175 le16_to_cpu(profile->usLeakageBinArrayOffset));
3176 vddc_id_buf = (u16 *)
3177 (rdev->mode_info.atom_context->bios + data_offset +
3178 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3179 vddc_buf = (u16 *)
3180 (rdev->mode_info.atom_context->bios + data_offset +
3181 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3182 vddci_id_buf = (u16 *)
3183 (rdev->mode_info.atom_context->bios + data_offset +
3184 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3185 vddci_buf = (u16 *)
3186 (rdev->mode_info.atom_context->bios + data_offset +
3187 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3188
3189 if (profile->ucElbVDDC_Num > 0) {
3190 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3191 if (vddc_id_buf[i] == virtual_voltage_id) {
3192 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3193 if (vbios_voltage_id <= leakage_bin[j]) {
3194 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3195 break;
3196 }
3197 }
3198 break;
3199 }
3200 }
3201 }
3202 if (profile->ucElbVDDCI_Num > 0) {
3203 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3204 if (vddci_id_buf[i] == virtual_voltage_id) {
3205 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3206 if (vbios_voltage_id <= leakage_bin[j]) {
3207 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3208 break;
3209 }
3210 }
3211 break;
3212 }
3213 }
3214 }
3215 break;
3216 default:
3217 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3218 return -EINVAL;
3219 }
3220 break;
3221 default:
3222 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3223 return -EINVAL;
3224 }
3225
3226 return 0;
3227 }
3228
3229 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3230 u16 voltage_level, u8 voltage_type,
3231 u32 *gpio_value, u32 *gpio_mask)
3232 {
3233 union set_voltage args;
3234 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3235 u8 frev, crev;
3236
3237 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3238 return -EINVAL;
3239
3240 switch (crev) {
3241 case 1:
3242 return -EINVAL;
3243 case 2:
3244 args.v2.ucVoltageType = voltage_type;
3245 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3246 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3247
3248 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3249
3250 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3251
3252 args.v2.ucVoltageType = voltage_type;
3253 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3254 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3255
3256 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3257
3258 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3259 break;
3260 default:
3261 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3262 return -EINVAL;
3263 }
3264
3265 return 0;
3266 }
3267
3268 union voltage_object_info {
3269 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3270 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3271 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3272 };
3273
3274 union voltage_object {
3275 struct _ATOM_VOLTAGE_OBJECT v1;
3276 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3277 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3278 };
3279
3280 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3281 u8 voltage_type)
3282 {
3283 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3284 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3285 u8 *start = (u8 *)v1;
3286
3287 while (offset < size) {
3288 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3289 if (vo->ucVoltageType == voltage_type)
3290 return vo;
3291 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3292 vo->asFormula.ucNumOfVoltageEntries;
3293 }
3294 return NULL;
3295 }
3296
3297 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3298 u8 voltage_type)
3299 {
3300 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3301 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3302 u8 *start = (u8*)v2;
3303
3304 while (offset < size) {
3305 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3306 if (vo->ucVoltageType == voltage_type)
3307 return vo;
3308 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3309 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3310 }
3311 return NULL;
3312 }
3313
3314 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3315 u8 voltage_type, u8 voltage_mode)
3316 {
3317 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3318 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3319 u8 *start = (u8*)v3;
3320
3321 while (offset < size) {
3322 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3323 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3324 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3325 return vo;
3326 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3327 }
3328 return NULL;
3329 }
3330
3331 bool
3332 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3333 u8 voltage_type, u8 voltage_mode)
3334 {
3335 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3336 u8 frev, crev;
3337 u16 data_offset, size;
3338 union voltage_object_info *voltage_info;
3339 union voltage_object *voltage_object = NULL;
3340
3341 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3342 &frev, &crev, &data_offset)) {
3343 voltage_info = (union voltage_object_info *)
3344 (rdev->mode_info.atom_context->bios + data_offset);
3345
3346 switch (frev) {
3347 case 1:
3348 case 2:
3349 switch (crev) {
3350 case 1:
3351 voltage_object = (union voltage_object *)
3352 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3353 if (voltage_object &&
3354 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3355 return true;
3356 break;
3357 case 2:
3358 voltage_object = (union voltage_object *)
3359 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3360 if (voltage_object &&
3361 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3362 return true;
3363 break;
3364 default:
3365 DRM_ERROR("unknown voltage object table\n");
3366 return false;
3367 }
3368 break;
3369 case 3:
3370 switch (crev) {
3371 case 1:
3372 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3373 voltage_type, voltage_mode))
3374 return true;
3375 break;
3376 default:
3377 DRM_ERROR("unknown voltage object table\n");
3378 return false;
3379 }
3380 break;
3381 default:
3382 DRM_ERROR("unknown voltage object table\n");
3383 return false;
3384 }
3385
3386 }
3387 return false;
3388 }
3389
3390 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3391 u8 voltage_type, u16 *max_voltage)
3392 {
3393 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3394 u8 frev, crev;
3395 u16 data_offset, size;
3396 union voltage_object_info *voltage_info;
3397 union voltage_object *voltage_object = NULL;
3398
3399 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3400 &frev, &crev, &data_offset)) {
3401 voltage_info = (union voltage_object_info *)
3402 (rdev->mode_info.atom_context->bios + data_offset);
3403
3404 switch (crev) {
3405 case 1:
3406 voltage_object = (union voltage_object *)
3407 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3408 if (voltage_object) {
3409 ATOM_VOLTAGE_FORMULA *formula =
3410 &voltage_object->v1.asFormula;
3411 if (formula->ucFlag & 1)
3412 *max_voltage =
3413 le16_to_cpu(formula->usVoltageBaseLevel) +
3414 formula->ucNumOfVoltageEntries / 2 *
3415 le16_to_cpu(formula->usVoltageStep);
3416 else
3417 *max_voltage =
3418 le16_to_cpu(formula->usVoltageBaseLevel) +
3419 (formula->ucNumOfVoltageEntries - 1) *
3420 le16_to_cpu(formula->usVoltageStep);
3421 return 0;
3422 }
3423 break;
3424 case 2:
3425 voltage_object = (union voltage_object *)
3426 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3427 if (voltage_object) {
3428 ATOM_VOLTAGE_FORMULA_V2 *formula =
3429 &voltage_object->v2.asFormula;
3430 if (formula->ucNumOfVoltageEntries) {
3431 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3432 ((u8 *)&formula->asVIDAdjustEntries[0] +
3433 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3434 *max_voltage =
3435 le16_to_cpu(lut->usVoltageValue);
3436 return 0;
3437 }
3438 }
3439 break;
3440 default:
3441 DRM_ERROR("unknown voltage object table\n");
3442 return -EINVAL;
3443 }
3444
3445 }
3446 return -EINVAL;
3447 }
3448
3449 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3450 u8 voltage_type, u16 *min_voltage)
3451 {
3452 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3453 u8 frev, crev;
3454 u16 data_offset, size;
3455 union voltage_object_info *voltage_info;
3456 union voltage_object *voltage_object = NULL;
3457
3458 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3459 &frev, &crev, &data_offset)) {
3460 voltage_info = (union voltage_object_info *)
3461 (rdev->mode_info.atom_context->bios + data_offset);
3462
3463 switch (crev) {
3464 case 1:
3465 voltage_object = (union voltage_object *)
3466 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3467 if (voltage_object) {
3468 ATOM_VOLTAGE_FORMULA *formula =
3469 &voltage_object->v1.asFormula;
3470 *min_voltage =
3471 le16_to_cpu(formula->usVoltageBaseLevel);
3472 return 0;
3473 }
3474 break;
3475 case 2:
3476 voltage_object = (union voltage_object *)
3477 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3478 if (voltage_object) {
3479 ATOM_VOLTAGE_FORMULA_V2 *formula =
3480 &voltage_object->v2.asFormula;
3481 if (formula->ucNumOfVoltageEntries) {
3482 *min_voltage =
3483 le16_to_cpu(formula->asVIDAdjustEntries[
3484 0
3485 ].usVoltageValue);
3486 return 0;
3487 }
3488 }
3489 break;
3490 default:
3491 DRM_ERROR("unknown voltage object table\n");
3492 return -EINVAL;
3493 }
3494
3495 }
3496 return -EINVAL;
3497 }
3498
3499 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3500 u8 voltage_type, u16 *voltage_step)
3501 {
3502 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3503 u8 frev, crev;
3504 u16 data_offset, size;
3505 union voltage_object_info *voltage_info;
3506 union voltage_object *voltage_object = NULL;
3507
3508 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3509 &frev, &crev, &data_offset)) {
3510 voltage_info = (union voltage_object_info *)
3511 (rdev->mode_info.atom_context->bios + data_offset);
3512
3513 switch (crev) {
3514 case 1:
3515 voltage_object = (union voltage_object *)
3516 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3517 if (voltage_object) {
3518 ATOM_VOLTAGE_FORMULA *formula =
3519 &voltage_object->v1.asFormula;
3520 if (formula->ucFlag & 1)
3521 *voltage_step =
3522 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3523 else
3524 *voltage_step =
3525 le16_to_cpu(formula->usVoltageStep);
3526 return 0;
3527 }
3528 break;
3529 case 2:
3530 return -EINVAL;
3531 default:
3532 DRM_ERROR("unknown voltage object table\n");
3533 return -EINVAL;
3534 }
3535
3536 }
3537 return -EINVAL;
3538 }
3539
3540 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3541 u8 voltage_type,
3542 u16 nominal_voltage,
3543 u16 *true_voltage)
3544 {
3545 u16 min_voltage, max_voltage, voltage_step;
3546
3547 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3548 return -EINVAL;
3549 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3550 return -EINVAL;
3551 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3552 return -EINVAL;
3553
3554 if (nominal_voltage <= min_voltage)
3555 *true_voltage = min_voltage;
3556 else if (nominal_voltage >= max_voltage)
3557 *true_voltage = max_voltage;
3558 else
3559 *true_voltage = min_voltage +
3560 ((nominal_voltage - min_voltage) / voltage_step) *
3561 voltage_step;
3562
3563 return 0;
3564 }
3565
3566 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3567 u8 voltage_type, u8 voltage_mode,
3568 struct atom_voltage_table *voltage_table)
3569 {
3570 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3571 u8 frev, crev;
3572 u16 data_offset, size;
3573 int i, ret;
3574 union voltage_object_info *voltage_info;
3575 union voltage_object *voltage_object = NULL;
3576
3577 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3578 &frev, &crev, &data_offset)) {
3579 voltage_info = (union voltage_object_info *)
3580 (rdev->mode_info.atom_context->bios + data_offset);
3581
3582 switch (frev) {
3583 case 1:
3584 case 2:
3585 switch (crev) {
3586 case 1:
3587 DRM_ERROR("old table version %d, %d\n", frev, crev);
3588 return -EINVAL;
3589 case 2:
3590 voltage_object = (union voltage_object *)
3591 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3592 if (voltage_object) {
3593 ATOM_VOLTAGE_FORMULA_V2 *formula =
3594 &voltage_object->v2.asFormula;
3595 VOLTAGE_LUT_ENTRY *lut;
3596 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3597 return -EINVAL;
3598 lut = &formula->asVIDAdjustEntries[0];
3599 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3600 voltage_table->entries[i].value =
3601 le16_to_cpu(lut->usVoltageValue);
3602 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3603 voltage_table->entries[i].value,
3604 voltage_type,
3605 &voltage_table->entries[i].smio_low,
3606 &voltage_table->mask_low);
3607 if (ret)
3608 return ret;
3609 lut = (VOLTAGE_LUT_ENTRY *)
3610 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3611 }
3612 voltage_table->count = formula->ucNumOfVoltageEntries;
3613 return 0;
3614 }
3615 break;
3616 default:
3617 DRM_ERROR("unknown voltage object table\n");
3618 return -EINVAL;
3619 }
3620 break;
3621 case 3:
3622 switch (crev) {
3623 case 1:
3624 voltage_object = (union voltage_object *)
3625 atom_lookup_voltage_object_v3(&voltage_info->v3,
3626 voltage_type, voltage_mode);
3627 if (voltage_object) {
3628 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3629 &voltage_object->v3.asGpioVoltageObj;
3630 VOLTAGE_LUT_ENTRY_V2 *lut;
3631 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3632 return -EINVAL;
3633 lut = &gpio->asVolGpioLut[0];
3634 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3635 voltage_table->entries[i].value =
3636 le16_to_cpu(lut->usVoltageValue);
3637 voltage_table->entries[i].smio_low =
3638 le32_to_cpu(lut->ulVoltageId);
3639 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3640 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3641 }
3642 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3643 voltage_table->count = gpio->ucGpioEntryNum;
3644 voltage_table->phase_delay = gpio->ucPhaseDelay;
3645 return 0;
3646 }
3647 break;
3648 default:
3649 DRM_ERROR("unknown voltage object table\n");
3650 return -EINVAL;
3651 }
3652 break;
3653 default:
3654 DRM_ERROR("unknown voltage object table\n");
3655 return -EINVAL;
3656 }
3657 }
3658 return -EINVAL;
3659 }
3660
3661 union vram_info {
3662 struct _ATOM_VRAM_INFO_V3 v1_3;
3663 struct _ATOM_VRAM_INFO_V4 v1_4;
3664 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3665 };
3666
3667 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3668 u8 module_index, struct atom_memory_info *mem_info)
3669 {
3670 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3671 u8 frev, crev, i;
3672 u16 data_offset, size;
3673 union vram_info *vram_info;
3674
3675 memset(mem_info, 0, sizeof(struct atom_memory_info));
3676
3677 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3678 &frev, &crev, &data_offset)) {
3679 vram_info = (union vram_info *)
3680 (rdev->mode_info.atom_context->bios + data_offset);
3681 switch (frev) {
3682 case 1:
3683 switch (crev) {
3684 case 3:
3685 /* r6xx */
3686 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3687 ATOM_VRAM_MODULE_V3 *vram_module =
3688 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3689
3690 for (i = 0; i < module_index; i++) {
3691 if (le16_to_cpu(vram_module->usSize) == 0)
3692 return -EINVAL;
3693 vram_module = (ATOM_VRAM_MODULE_V3 *)
3694 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3695 }
3696 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3697 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3698 } else
3699 return -EINVAL;
3700 break;
3701 case 4:
3702 /* r7xx, evergreen */
3703 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3704 ATOM_VRAM_MODULE_V4 *vram_module =
3705 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3706
3707 for (i = 0; i < module_index; i++) {
3708 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3709 return -EINVAL;
3710 vram_module = (ATOM_VRAM_MODULE_V4 *)
3711 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3712 }
3713 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3714 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3715 } else
3716 return -EINVAL;
3717 break;
3718 default:
3719 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3720 return -EINVAL;
3721 }
3722 break;
3723 case 2:
3724 switch (crev) {
3725 case 1:
3726 /* ni */
3727 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3728 ATOM_VRAM_MODULE_V7 *vram_module =
3729 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3730
3731 for (i = 0; i < module_index; i++) {
3732 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3733 return -EINVAL;
3734 vram_module = (ATOM_VRAM_MODULE_V7 *)
3735 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3736 }
3737 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3738 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3739 } else
3740 return -EINVAL;
3741 break;
3742 default:
3743 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3744 return -EINVAL;
3745 }
3746 break;
3747 default:
3748 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3749 return -EINVAL;
3750 }
3751 return 0;
3752 }
3753 return -EINVAL;
3754 }
3755
3756 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3757 bool gddr5, u8 module_index,
3758 struct atom_memory_clock_range_table *mclk_range_table)
3759 {
3760 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3761 u8 frev, crev, i;
3762 u16 data_offset, size;
3763 union vram_info *vram_info;
3764 u32 mem_timing_size = gddr5 ?
3765 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3766
3767 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3768
3769 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3770 &frev, &crev, &data_offset)) {
3771 vram_info = (union vram_info *)
3772 (rdev->mode_info.atom_context->bios + data_offset);
3773 switch (frev) {
3774 case 1:
3775 switch (crev) {
3776 case 3:
3777 DRM_ERROR("old table version %d, %d\n", frev, crev);
3778 return -EINVAL;
3779 case 4:
3780 /* r7xx, evergreen */
3781 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3782 ATOM_VRAM_MODULE_V4 *vram_module =
3783 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3784 ATOM_MEMORY_TIMING_FORMAT *format;
3785
3786 for (i = 0; i < module_index; i++) {
3787 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3788 return -EINVAL;
3789 vram_module = (ATOM_VRAM_MODULE_V4 *)
3790 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3791 }
3792 mclk_range_table->num_entries = (u8)
3793 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3794 mem_timing_size);
3795 format = &vram_module->asMemTiming[0];
3796 for (i = 0; i < mclk_range_table->num_entries; i++) {
3797 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3798 format = (ATOM_MEMORY_TIMING_FORMAT *)
3799 ((u8 *)format + mem_timing_size);
3800 }
3801 } else
3802 return -EINVAL;
3803 break;
3804 default:
3805 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3806 return -EINVAL;
3807 }
3808 break;
3809 case 2:
3810 DRM_ERROR("new table version %d, %d\n", frev, crev);
3811 return -EINVAL;
3812 default:
3813 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3814 return -EINVAL;
3815 }
3816 return 0;
3817 }
3818 return -EINVAL;
3819 }
3820
3821 #define MEM_ID_MASK 0xff000000
3822 #define MEM_ID_SHIFT 24
3823 #define CLOCK_RANGE_MASK 0x00ffffff
3824 #define CLOCK_RANGE_SHIFT 0
3825 #define LOW_NIBBLE_MASK 0xf
3826 #define DATA_EQU_PREV 0
3827 #define DATA_FROM_TABLE 4
3828
3829 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3830 u8 module_index,
3831 struct atom_mc_reg_table *reg_table)
3832 {
3833 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3834 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3835 u32 i = 0, j;
3836 u16 data_offset, size;
3837 union vram_info *vram_info;
3838
3839 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3840
3841 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3842 &frev, &crev, &data_offset)) {
3843 vram_info = (union vram_info *)
3844 (rdev->mode_info.atom_context->bios + data_offset);
3845 switch (frev) {
3846 case 1:
3847 DRM_ERROR("old table version %d, %d\n", frev, crev);
3848 return -EINVAL;
3849 case 2:
3850 switch (crev) {
3851 case 1:
3852 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3853 ATOM_INIT_REG_BLOCK *reg_block =
3854 (ATOM_INIT_REG_BLOCK *)
3855 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
3856 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
3857 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3858 ((u8 *)reg_block + (2 * sizeof(u16)) +
3859 le16_to_cpu(reg_block->usRegIndexTblSize));
3860 ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
3861 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
3862 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
3863 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
3864 return -EINVAL;
3865 while (i < num_entries) {
3866 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
3867 break;
3868 reg_table->mc_reg_address[i].s1 =
3869 (u16)(le16_to_cpu(format->usRegIndex));
3870 reg_table->mc_reg_address[i].pre_reg_data =
3871 (u8)(format->ucPreRegDataLength);
3872 i++;
3873 format = (ATOM_INIT_REG_INDEX_FORMAT *)
3874 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
3875 }
3876 reg_table->last = i;
3877 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
3878 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
3879 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
3880 >> MEM_ID_SHIFT);
3881 if (module_index == t_mem_id) {
3882 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
3883 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
3884 >> CLOCK_RANGE_SHIFT);
3885 for (i = 0, j = 1; i < reg_table->last; i++) {
3886 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
3887 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
3888 (u32)le32_to_cpu(*((u32 *)reg_data + j));
3889 j++;
3890 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
3891 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
3892 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
3893 }
3894 }
3895 num_ranges++;
3896 }
3897 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3898 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
3899 }
3900 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
3901 return -EINVAL;
3902 reg_table->num_entries = num_ranges;
3903 } else
3904 return -EINVAL;
3905 break;
3906 default:
3907 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3908 return -EINVAL;
3909 }
3910 break;
3911 default:
3912 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3913 return -EINVAL;
3914 }
3915 return 0;
3916 }
3917 return -EINVAL;
3918 }
3919
3920 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
3921 {
3922 struct radeon_device *rdev = dev->dev_private;
3923 uint32_t bios_2_scratch, bios_6_scratch;
3924
3925 if (rdev->family >= CHIP_R600) {
3926 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3927 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
3928 } else {
3929 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3930 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3931 }
3932
3933 /* let the bios control the backlight */
3934 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
3935
3936 /* tell the bios not to handle mode switching */
3937 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
3938
3939 if (rdev->family >= CHIP_R600) {
3940 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3941 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3942 } else {
3943 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3944 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3945 }
3946
3947 }
3948
3949 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
3950 {
3951 uint32_t scratch_reg;
3952 int i;
3953
3954 if (rdev->family >= CHIP_R600)
3955 scratch_reg = R600_BIOS_0_SCRATCH;
3956 else
3957 scratch_reg = RADEON_BIOS_0_SCRATCH;
3958
3959 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
3960 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
3961 }
3962
3963 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
3964 {
3965 uint32_t scratch_reg;
3966 int i;
3967
3968 if (rdev->family >= CHIP_R600)
3969 scratch_reg = R600_BIOS_0_SCRATCH;
3970 else
3971 scratch_reg = RADEON_BIOS_0_SCRATCH;
3972
3973 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
3974 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
3975 }
3976
3977 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
3978 {
3979 struct drm_device *dev = encoder->dev;
3980 struct radeon_device *rdev = dev->dev_private;
3981 uint32_t bios_6_scratch;
3982
3983 if (rdev->family >= CHIP_R600)
3984 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
3985 else
3986 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3987
3988 if (lock) {
3989 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
3990 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
3991 } else {
3992 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
3993 bios_6_scratch |= ATOM_S6_ACC_MODE;
3994 }
3995
3996 if (rdev->family >= CHIP_R600)
3997 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3998 else
3999 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4000 }
4001
4002 /* at some point we may want to break this out into individual functions */
4003 void
4004 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4005 struct drm_encoder *encoder,
4006 bool connected)
4007 {
4008 struct drm_device *dev = connector->dev;
4009 struct radeon_device *rdev = dev->dev_private;
4010 struct radeon_connector *radeon_connector =
4011 to_radeon_connector(connector);
4012 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4013 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4014
4015 if (rdev->family >= CHIP_R600) {
4016 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4017 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4018 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4019 } else {
4020 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4021 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4022 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4023 }
4024
4025 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4026 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4027 if (connected) {
4028 DRM_DEBUG_KMS("TV1 connected\n");
4029 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4030 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4031 } else {
4032 DRM_DEBUG_KMS("TV1 disconnected\n");
4033 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4034 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4035 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4036 }
4037 }
4038 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4039 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4040 if (connected) {
4041 DRM_DEBUG_KMS("CV connected\n");
4042 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4043 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4044 } else {
4045 DRM_DEBUG_KMS("CV disconnected\n");
4046 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4047 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4048 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4049 }
4050 }
4051 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4052 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4053 if (connected) {
4054 DRM_DEBUG_KMS("LCD1 connected\n");
4055 bios_0_scratch |= ATOM_S0_LCD1;
4056 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4057 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4058 } else {
4059 DRM_DEBUG_KMS("LCD1 disconnected\n");
4060 bios_0_scratch &= ~ATOM_S0_LCD1;
4061 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4062 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4063 }
4064 }
4065 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4066 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4067 if (connected) {
4068 DRM_DEBUG_KMS("CRT1 connected\n");
4069 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4070 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4071 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4072 } else {
4073 DRM_DEBUG_KMS("CRT1 disconnected\n");
4074 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4075 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4076 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4077 }
4078 }
4079 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4080 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4081 if (connected) {
4082 DRM_DEBUG_KMS("CRT2 connected\n");
4083 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4084 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4085 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4086 } else {
4087 DRM_DEBUG_KMS("CRT2 disconnected\n");
4088 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4089 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4090 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4091 }
4092 }
4093 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4094 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4095 if (connected) {
4096 DRM_DEBUG_KMS("DFP1 connected\n");
4097 bios_0_scratch |= ATOM_S0_DFP1;
4098 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4099 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4100 } else {
4101 DRM_DEBUG_KMS("DFP1 disconnected\n");
4102 bios_0_scratch &= ~ATOM_S0_DFP1;
4103 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4104 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4105 }
4106 }
4107 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4108 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4109 if (connected) {
4110 DRM_DEBUG_KMS("DFP2 connected\n");
4111 bios_0_scratch |= ATOM_S0_DFP2;
4112 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4113 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4114 } else {
4115 DRM_DEBUG_KMS("DFP2 disconnected\n");
4116 bios_0_scratch &= ~ATOM_S0_DFP2;
4117 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4118 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4119 }
4120 }
4121 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4122 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4123 if (connected) {
4124 DRM_DEBUG_KMS("DFP3 connected\n");
4125 bios_0_scratch |= ATOM_S0_DFP3;
4126 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4127 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4128 } else {
4129 DRM_DEBUG_KMS("DFP3 disconnected\n");
4130 bios_0_scratch &= ~ATOM_S0_DFP3;
4131 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4132 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4133 }
4134 }
4135 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4136 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4137 if (connected) {
4138 DRM_DEBUG_KMS("DFP4 connected\n");
4139 bios_0_scratch |= ATOM_S0_DFP4;
4140 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4141 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4142 } else {
4143 DRM_DEBUG_KMS("DFP4 disconnected\n");
4144 bios_0_scratch &= ~ATOM_S0_DFP4;
4145 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4146 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4147 }
4148 }
4149 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4150 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4151 if (connected) {
4152 DRM_DEBUG_KMS("DFP5 connected\n");
4153 bios_0_scratch |= ATOM_S0_DFP5;
4154 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4155 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4156 } else {
4157 DRM_DEBUG_KMS("DFP5 disconnected\n");
4158 bios_0_scratch &= ~ATOM_S0_DFP5;
4159 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4160 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4161 }
4162 }
4163 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4164 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4165 if (connected) {
4166 DRM_DEBUG_KMS("DFP6 connected\n");
4167 bios_0_scratch |= ATOM_S0_DFP6;
4168 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4169 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4170 } else {
4171 DRM_DEBUG_KMS("DFP6 disconnected\n");
4172 bios_0_scratch &= ~ATOM_S0_DFP6;
4173 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4174 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4175 }
4176 }
4177
4178 if (rdev->family >= CHIP_R600) {
4179 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4180 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4181 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4182 } else {
4183 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4184 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4185 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4186 }
4187 }
4188
4189 void
4190 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4191 {
4192 struct drm_device *dev = encoder->dev;
4193 struct radeon_device *rdev = dev->dev_private;
4194 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4195 uint32_t bios_3_scratch;
4196
4197 if (ASIC_IS_DCE4(rdev))
4198 return;
4199
4200 if (rdev->family >= CHIP_R600)
4201 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4202 else
4203 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4204
4205 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4206 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4207 bios_3_scratch |= (crtc << 18);
4208 }
4209 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4210 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4211 bios_3_scratch |= (crtc << 24);
4212 }
4213 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4214 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4215 bios_3_scratch |= (crtc << 16);
4216 }
4217 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4218 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4219 bios_3_scratch |= (crtc << 20);
4220 }
4221 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4222 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4223 bios_3_scratch |= (crtc << 17);
4224 }
4225 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4226 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4227 bios_3_scratch |= (crtc << 19);
4228 }
4229 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4230 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4231 bios_3_scratch |= (crtc << 23);
4232 }
4233 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4234 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4235 bios_3_scratch |= (crtc << 25);
4236 }
4237
4238 if (rdev->family >= CHIP_R600)
4239 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4240 else
4241 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4242 }
4243
4244 void
4245 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4246 {
4247 struct drm_device *dev = encoder->dev;
4248 struct radeon_device *rdev = dev->dev_private;
4249 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4250 uint32_t bios_2_scratch;
4251
4252 if (ASIC_IS_DCE4(rdev))
4253 return;
4254
4255 if (rdev->family >= CHIP_R600)
4256 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4257 else
4258 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4259
4260 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4261 if (on)
4262 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4263 else
4264 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4265 }
4266 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4267 if (on)
4268 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4269 else
4270 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4271 }
4272 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4273 if (on)
4274 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4275 else
4276 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4277 }
4278 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4279 if (on)
4280 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4281 else
4282 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4283 }
4284 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4285 if (on)
4286 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4287 else
4288 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4289 }
4290 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4291 if (on)
4292 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4293 else
4294 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4295 }
4296 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4297 if (on)
4298 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4299 else
4300 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4301 }
4302 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4303 if (on)
4304 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4305 else
4306 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4307 }
4308 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4309 if (on)
4310 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4311 else
4312 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4313 }
4314 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4315 if (on)
4316 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4317 else
4318 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4319 }
4320
4321 if (rdev->family >= CHIP_R600)
4322 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4323 else
4324 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4325 }
Linux kernel - Deliverables
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