2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_enum(struct drm_device
*dev
, uint32_t supported_device
,
37 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
39 radeon_add_atom_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
40 uint32_t supported_device
, u16 caps
);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device
*dev
,
45 uint32_t connector_id
,
46 uint32_t supported_device
,
48 struct radeon_i2c_bus_rec
*i2c_bus
,
49 uint32_t igp_lane_info
,
50 uint16_t connector_object_id
,
51 struct radeon_hpd
*hpd
,
52 struct radeon_router
*router
);
54 /* from radeon_legacy_encoder.c */
56 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
57 uint32_t supported_device
);
59 union atom_supported_devices
{
60 struct _ATOM_SUPPORTED_DEVICES_INFO info
;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2
;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1
;
65 static inline struct radeon_i2c_bus_rec
radeon_lookup_i2c_gpio(struct radeon_device
*rdev
,
68 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
69 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
70 struct radeon_i2c_bus_rec i2c
;
71 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
72 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
73 uint16_t data_offset
, size
;
76 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
79 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
80 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
82 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
85 for (i
= 0; i
< num_indices
; i
++) {
86 gpio
= &i2c_info
->asGPIO_Info
[i
];
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev
)) {
91 (gpio
->usClkMaskRegisterIndex
== 0x1936) &&
92 (gpio
->sucI2cId
.ucAccess
== 0)) {
93 gpio
->sucI2cId
.ucAccess
= 0x97;
94 gpio
->ucDataMaskShift
= 8;
95 gpio
->ucDataEnShift
= 8;
96 gpio
->ucDataY_Shift
= 8;
97 gpio
->ucDataA_Shift
= 8;
101 /* some DCE3 boards have bad data for this entry */
102 if (ASIC_IS_DCE3(rdev
)) {
104 (gpio
->usClkMaskRegisterIndex
== 0x1fda) &&
105 (gpio
->sucI2cId
.ucAccess
== 0x94))
106 gpio
->sucI2cId
.ucAccess
= 0x14;
109 if (gpio
->sucI2cId
.ucAccess
== id
) {
110 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
) * 4;
111 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
) * 4;
112 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
) * 4;
113 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
) * 4;
114 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
) * 4;
115 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
) * 4;
116 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
) * 4;
117 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
) * 4;
118 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
119 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
120 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
121 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
122 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
123 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
124 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
125 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
127 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
128 i2c
.hw_capable
= true;
130 i2c
.hw_capable
= false;
132 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
137 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
139 if (i2c
.mask_clk_reg
)
149 void radeon_atombios_i2c_init(struct radeon_device
*rdev
)
151 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
152 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
153 struct radeon_i2c_bus_rec i2c
;
154 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
155 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
156 uint16_t data_offset
, size
;
160 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
162 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
163 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
165 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
166 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
168 for (i
= 0; i
< num_indices
; i
++) {
169 gpio
= &i2c_info
->asGPIO_Info
[i
];
172 /* some evergreen boards have bad data for this entry */
173 if (ASIC_IS_DCE4(rdev
)) {
175 (gpio
->usClkMaskRegisterIndex
== 0x1936) &&
176 (gpio
->sucI2cId
.ucAccess
== 0)) {
177 gpio
->sucI2cId
.ucAccess
= 0x97;
178 gpio
->ucDataMaskShift
= 8;
179 gpio
->ucDataEnShift
= 8;
180 gpio
->ucDataY_Shift
= 8;
181 gpio
->ucDataA_Shift
= 8;
185 /* some DCE3 boards have bad data for this entry */
186 if (ASIC_IS_DCE3(rdev
)) {
188 (gpio
->usClkMaskRegisterIndex
== 0x1fda) &&
189 (gpio
->sucI2cId
.ucAccess
== 0x94))
190 gpio
->sucI2cId
.ucAccess
= 0x14;
193 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
) * 4;
194 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
) * 4;
195 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
) * 4;
196 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
) * 4;
197 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
) * 4;
198 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
) * 4;
199 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
) * 4;
200 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
) * 4;
201 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
202 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
203 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
204 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
205 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
206 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
207 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
208 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
210 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
211 i2c
.hw_capable
= true;
213 i2c
.hw_capable
= false;
215 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
220 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
222 if (i2c
.mask_clk_reg
) {
224 sprintf(stmp
, "0x%x", i2c
.i2c_id
);
225 rdev
->i2c_bus
[i
] = radeon_i2c_create(rdev
->ddev
, &i2c
, stmp
);
231 static inline struct radeon_gpio_rec
radeon_lookup_gpio(struct radeon_device
*rdev
,
234 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
235 struct radeon_gpio_rec gpio
;
236 int index
= GetIndexIntoMasterTable(DATA
, GPIO_Pin_LUT
);
237 struct _ATOM_GPIO_PIN_LUT
*gpio_info
;
238 ATOM_GPIO_PIN_ASSIGNMENT
*pin
;
239 u16 data_offset
, size
;
242 memset(&gpio
, 0, sizeof(struct radeon_gpio_rec
));
245 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
246 gpio_info
= (struct _ATOM_GPIO_PIN_LUT
*)(ctx
->bios
+ data_offset
);
248 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
249 sizeof(ATOM_GPIO_PIN_ASSIGNMENT
);
251 for (i
= 0; i
< num_indices
; i
++) {
252 pin
= &gpio_info
->asGPIO_Pin
[i
];
253 if (id
== pin
->ucGPIO_ID
) {
254 gpio
.id
= pin
->ucGPIO_ID
;
255 gpio
.reg
= pin
->usGpioPin_AIndex
* 4;
256 gpio
.mask
= (1 << pin
->ucGpioPinBitShift
);
266 static struct radeon_hpd
radeon_atom_get_hpd_info_from_gpio(struct radeon_device
*rdev
,
267 struct radeon_gpio_rec
*gpio
)
269 struct radeon_hpd hpd
;
272 memset(&hpd
, 0, sizeof(struct radeon_hpd
));
274 if (ASIC_IS_DCE4(rdev
))
275 reg
= EVERGREEN_DC_GPIO_HPD_A
;
277 reg
= AVIVO_DC_GPIO_HPD_A
;
280 if (gpio
->reg
== reg
) {
283 hpd
.hpd
= RADEON_HPD_1
;
286 hpd
.hpd
= RADEON_HPD_2
;
289 hpd
.hpd
= RADEON_HPD_3
;
292 hpd
.hpd
= RADEON_HPD_4
;
295 hpd
.hpd
= RADEON_HPD_5
;
298 hpd
.hpd
= RADEON_HPD_6
;
301 hpd
.hpd
= RADEON_HPD_NONE
;
305 hpd
.hpd
= RADEON_HPD_NONE
;
309 static bool radeon_atom_apply_quirks(struct drm_device
*dev
,
310 uint32_t supported_device
,
312 struct radeon_i2c_bus_rec
*i2c_bus
,
314 struct radeon_hpd
*hpd
)
317 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
318 if ((dev
->pdev
->device
== 0x791e) &&
319 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
320 (dev
->pdev
->subsystem_device
== 0x826d)) {
321 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
322 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
323 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
326 /* Asrock RS600 board lists the DVI port as HDMI */
327 if ((dev
->pdev
->device
== 0x7941) &&
328 (dev
->pdev
->subsystem_vendor
== 0x1849) &&
329 (dev
->pdev
->subsystem_device
== 0x7941)) {
330 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
331 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
332 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
335 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
336 if ((dev
->pdev
->device
== 0x796e) &&
337 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
338 (dev
->pdev
->subsystem_device
== 0x7302)) {
339 if ((supported_device
== ATOM_DEVICE_DFP2_SUPPORT
) ||
340 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
344 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
345 if ((dev
->pdev
->device
== 0x7941) &&
346 (dev
->pdev
->subsystem_vendor
== 0x147b) &&
347 (dev
->pdev
->subsystem_device
== 0x2412)) {
348 if (*connector_type
== DRM_MODE_CONNECTOR_DVII
)
352 /* Falcon NW laptop lists vga ddc line for LVDS */
353 if ((dev
->pdev
->device
== 0x5653) &&
354 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
355 (dev
->pdev
->subsystem_device
== 0x0291)) {
356 if (*connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
357 i2c_bus
->valid
= false;
362 /* HIS X1300 is DVI+VGA, not DVI+DVI */
363 if ((dev
->pdev
->device
== 0x7146) &&
364 (dev
->pdev
->subsystem_vendor
== 0x17af) &&
365 (dev
->pdev
->subsystem_device
== 0x2058)) {
366 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
370 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
371 if ((dev
->pdev
->device
== 0x7142) &&
372 (dev
->pdev
->subsystem_vendor
== 0x1458) &&
373 (dev
->pdev
->subsystem_device
== 0x2134)) {
374 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
380 if ((dev
->pdev
->device
== 0x71C5) &&
381 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
382 (dev
->pdev
->subsystem_device
== 0x0080)) {
383 if ((supported_device
== ATOM_DEVICE_CRT1_SUPPORT
) ||
384 (supported_device
== ATOM_DEVICE_DFP2_SUPPORT
))
386 if (supported_device
== ATOM_DEVICE_CRT2_SUPPORT
)
390 /* mac rv630, rv730, others */
391 if ((supported_device
== ATOM_DEVICE_TV1_SUPPORT
) &&
392 (*connector_type
== DRM_MODE_CONNECTOR_DVII
)) {
393 *connector_type
= DRM_MODE_CONNECTOR_9PinDIN
;
394 *line_mux
= CONNECTOR_7PIN_DIN_ENUM_ID1
;
397 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
398 if ((dev
->pdev
->device
== 0x9598) &&
399 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
400 (dev
->pdev
->subsystem_device
== 0x01da)) {
401 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
402 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
406 /* ASUS HD 3600 board lists the DVI port as HDMI */
407 if ((dev
->pdev
->device
== 0x9598) &&
408 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
409 (dev
->pdev
->subsystem_device
== 0x01e4)) {
410 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
411 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
415 /* ASUS HD 3450 board lists the DVI port as HDMI */
416 if ((dev
->pdev
->device
== 0x95C5) &&
417 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
418 (dev
->pdev
->subsystem_device
== 0x01e2)) {
419 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
420 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
424 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
425 * HDMI + VGA reporting as HDMI
427 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
428 if (supported_device
& (ATOM_DEVICE_CRT_SUPPORT
)) {
429 *connector_type
= DRM_MODE_CONNECTOR_VGA
;
434 /* Acer laptop (Acer TravelMate 5730G) has an HDMI port
435 * on the laptop and a DVI port on the docking station and
436 * both share the same encoder, hpd pin, and ddc line.
437 * So while the bios table is technically correct,
438 * we drop the DVI port here since xrandr has no concept of
439 * encoders and will try and drive both connectors
440 * with different crtcs which isn't possible on the hardware
441 * side and leaves no crtcs for LVDS or VGA.
443 if ((dev
->pdev
->device
== 0x95c4) &&
444 (dev
->pdev
->subsystem_vendor
== 0x1025) &&
445 (dev
->pdev
->subsystem_device
== 0x013c)) {
446 if ((*connector_type
== DRM_MODE_CONNECTOR_DVII
) &&
447 (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)) {
448 /* actually it's a DVI-D port not DVI-I */
449 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
454 /* XFX Pine Group device rv730 reports no VGA DDC lines
455 * even though they are wired up to record 0x93
457 if ((dev
->pdev
->device
== 0x9498) &&
458 (dev
->pdev
->subsystem_vendor
== 0x1682) &&
459 (dev
->pdev
->subsystem_device
== 0x2452)) {
460 struct radeon_device
*rdev
= dev
->dev_private
;
461 *i2c_bus
= radeon_lookup_i2c_gpio(rdev
, 0x93);
466 const int supported_devices_connector_convert
[] = {
467 DRM_MODE_CONNECTOR_Unknown
,
468 DRM_MODE_CONNECTOR_VGA
,
469 DRM_MODE_CONNECTOR_DVII
,
470 DRM_MODE_CONNECTOR_DVID
,
471 DRM_MODE_CONNECTOR_DVIA
,
472 DRM_MODE_CONNECTOR_SVIDEO
,
473 DRM_MODE_CONNECTOR_Composite
,
474 DRM_MODE_CONNECTOR_LVDS
,
475 DRM_MODE_CONNECTOR_Unknown
,
476 DRM_MODE_CONNECTOR_Unknown
,
477 DRM_MODE_CONNECTOR_HDMIA
,
478 DRM_MODE_CONNECTOR_HDMIB
,
479 DRM_MODE_CONNECTOR_Unknown
,
480 DRM_MODE_CONNECTOR_Unknown
,
481 DRM_MODE_CONNECTOR_9PinDIN
,
482 DRM_MODE_CONNECTOR_DisplayPort
485 const uint16_t supported_devices_connector_object_id_convert
[] = {
486 CONNECTOR_OBJECT_ID_NONE
,
487 CONNECTOR_OBJECT_ID_VGA
,
488 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
, /* not all boards support DL */
489 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
, /* not all boards support DL */
490 CONNECTOR_OBJECT_ID_VGA
, /* technically DVI-A */
491 CONNECTOR_OBJECT_ID_COMPOSITE
,
492 CONNECTOR_OBJECT_ID_SVIDEO
,
493 CONNECTOR_OBJECT_ID_LVDS
,
494 CONNECTOR_OBJECT_ID_9PIN_DIN
,
495 CONNECTOR_OBJECT_ID_9PIN_DIN
,
496 CONNECTOR_OBJECT_ID_DISPLAYPORT
,
497 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
,
498 CONNECTOR_OBJECT_ID_HDMI_TYPE_B
,
499 CONNECTOR_OBJECT_ID_SVIDEO
502 const int object_connector_convert
[] = {
503 DRM_MODE_CONNECTOR_Unknown
,
504 DRM_MODE_CONNECTOR_DVII
,
505 DRM_MODE_CONNECTOR_DVII
,
506 DRM_MODE_CONNECTOR_DVID
,
507 DRM_MODE_CONNECTOR_DVID
,
508 DRM_MODE_CONNECTOR_VGA
,
509 DRM_MODE_CONNECTOR_Composite
,
510 DRM_MODE_CONNECTOR_SVIDEO
,
511 DRM_MODE_CONNECTOR_Unknown
,
512 DRM_MODE_CONNECTOR_Unknown
,
513 DRM_MODE_CONNECTOR_9PinDIN
,
514 DRM_MODE_CONNECTOR_Unknown
,
515 DRM_MODE_CONNECTOR_HDMIA
,
516 DRM_MODE_CONNECTOR_HDMIB
,
517 DRM_MODE_CONNECTOR_LVDS
,
518 DRM_MODE_CONNECTOR_9PinDIN
,
519 DRM_MODE_CONNECTOR_Unknown
,
520 DRM_MODE_CONNECTOR_Unknown
,
521 DRM_MODE_CONNECTOR_Unknown
,
522 DRM_MODE_CONNECTOR_DisplayPort
,
523 DRM_MODE_CONNECTOR_eDP
,
524 DRM_MODE_CONNECTOR_Unknown
527 bool radeon_get_atom_connector_info_from_object_table(struct drm_device
*dev
)
529 struct radeon_device
*rdev
= dev
->dev_private
;
530 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
531 struct atom_context
*ctx
= mode_info
->atom_context
;
532 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
533 u16 size
, data_offset
;
535 ATOM_CONNECTOR_OBJECT_TABLE
*con_obj
;
536 ATOM_ENCODER_OBJECT_TABLE
*enc_obj
;
537 ATOM_OBJECT_TABLE
*router_obj
;
538 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
539 ATOM_OBJECT_HEADER
*obj_header
;
540 int i
, j
, k
, path_size
, device_support
;
542 u16 igp_lane_info
, conn_id
, connector_object_id
;
543 struct radeon_i2c_bus_rec ddc_bus
;
544 struct radeon_router router
;
545 struct radeon_gpio_rec gpio
;
546 struct radeon_hpd hpd
;
548 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
))
554 obj_header
= (ATOM_OBJECT_HEADER
*) (ctx
->bios
+ data_offset
);
555 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
556 (ctx
->bios
+ data_offset
+
557 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
558 con_obj
= (ATOM_CONNECTOR_OBJECT_TABLE
*)
559 (ctx
->bios
+ data_offset
+
560 le16_to_cpu(obj_header
->usConnectorObjectTableOffset
));
561 enc_obj
= (ATOM_ENCODER_OBJECT_TABLE
*)
562 (ctx
->bios
+ data_offset
+
563 le16_to_cpu(obj_header
->usEncoderObjectTableOffset
));
564 router_obj
= (ATOM_OBJECT_TABLE
*)
565 (ctx
->bios
+ data_offset
+
566 le16_to_cpu(obj_header
->usRouterObjectTableOffset
));
567 device_support
= le16_to_cpu(obj_header
->usDeviceSupport
);
570 for (i
= 0; i
< path_obj
->ucNumOfDispPath
; i
++) {
571 uint8_t *addr
= (uint8_t *) path_obj
->asDispPath
;
572 ATOM_DISPLAY_OBJECT_PATH
*path
;
574 path
= (ATOM_DISPLAY_OBJECT_PATH
*) addr
;
575 path_size
+= le16_to_cpu(path
->usSize
);
577 if (device_support
& le16_to_cpu(path
->usDeviceTag
)) {
578 uint8_t con_obj_id
, con_obj_num
, con_obj_type
;
581 (le16_to_cpu(path
->usConnObjectId
) & OBJECT_ID_MASK
)
584 (le16_to_cpu(path
->usConnObjectId
) & ENUM_ID_MASK
)
587 (le16_to_cpu(path
->usConnObjectId
) &
588 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
590 /* TODO CV support */
591 if (le16_to_cpu(path
->usDeviceTag
) ==
592 ATOM_DEVICE_CV_SUPPORT
)
596 if ((rdev
->flags
& RADEON_IS_IGP
) &&
598 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR
)) {
599 uint16_t igp_offset
= 0;
600 ATOM_INTEGRATED_SYSTEM_INFO_V2
*igp_obj
;
603 GetIndexIntoMasterTable(DATA
,
604 IntegratedSystemInfo
);
606 if (atom_parse_data_header(ctx
, index
, &size
, &frev
,
607 &crev
, &igp_offset
)) {
611 (ATOM_INTEGRATED_SYSTEM_INFO_V2
612 *) (ctx
->bios
+ igp_offset
);
615 uint32_t slot_config
, ct
;
617 if (con_obj_num
== 1)
626 ct
= (slot_config
>> 16) & 0xff;
628 object_connector_convert
630 connector_object_id
= ct
;
632 slot_config
& 0xffff;
640 object_connector_convert
[con_obj_id
];
641 connector_object_id
= con_obj_id
;
646 object_connector_convert
[con_obj_id
];
647 connector_object_id
= con_obj_id
;
650 if (connector_type
== DRM_MODE_CONNECTOR_Unknown
)
653 router
.ddc_valid
= false;
654 router
.cd_valid
= false;
655 for (j
= 0; j
< ((le16_to_cpu(path
->usSize
) - 8) / 2); j
++) {
656 uint8_t grph_obj_id
, grph_obj_num
, grph_obj_type
;
659 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
660 OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
662 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
663 ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
665 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
666 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
668 if (grph_obj_type
== GRAPH_OBJECT_TYPE_ENCODER
) {
669 for (k
= 0; k
< enc_obj
->ucNumberOfObjects
; k
++) {
670 u16 encoder_obj
= le16_to_cpu(enc_obj
->asObjects
[k
].usObjectID
);
671 if (le16_to_cpu(path
->usGraphicObjIds
[j
]) == encoder_obj
) {
672 ATOM_COMMON_RECORD_HEADER
*record
= (ATOM_COMMON_RECORD_HEADER
*)
673 (ctx
->bios
+ data_offset
+
674 le16_to_cpu(enc_obj
->asObjects
[k
].usRecordOffset
));
675 ATOM_ENCODER_CAP_RECORD
*cap_record
;
678 while (record
->ucRecordType
> 0 &&
679 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
680 switch (record
->ucRecordType
) {
681 case ATOM_ENCODER_CAP_RECORD_TYPE
:
682 cap_record
=(ATOM_ENCODER_CAP_RECORD
*)
684 caps
= le16_to_cpu(cap_record
->usEncoderCap
);
687 record
= (ATOM_COMMON_RECORD_HEADER
*)
688 ((char *)record
+ record
->ucRecordSize
);
690 radeon_add_atom_encoder(dev
,
698 } else if (grph_obj_type
== GRAPH_OBJECT_TYPE_ROUTER
) {
699 for (k
= 0; k
< router_obj
->ucNumberOfObjects
; k
++) {
700 u16 router_obj_id
= le16_to_cpu(router_obj
->asObjects
[k
].usObjectID
);
701 if (le16_to_cpu(path
->usGraphicObjIds
[j
]) == router_obj_id
) {
702 ATOM_COMMON_RECORD_HEADER
*record
= (ATOM_COMMON_RECORD_HEADER
*)
703 (ctx
->bios
+ data_offset
+
704 le16_to_cpu(router_obj
->asObjects
[k
].usRecordOffset
));
705 ATOM_I2C_RECORD
*i2c_record
;
706 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
707 ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*ddc_path
;
708 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
*cd_path
;
709 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*router_src_dst_table
=
710 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*)
711 (ctx
->bios
+ data_offset
+
712 le16_to_cpu(router_obj
->asObjects
[k
].usSrcDstTableOffset
));
715 router
.router_id
= router_obj_id
;
716 for (enum_id
= 0; enum_id
< router_src_dst_table
->ucNumberOfDst
;
718 if (le16_to_cpu(path
->usConnObjectId
) ==
719 le16_to_cpu(router_src_dst_table
->usDstObjectID
[enum_id
]))
723 while (record
->ucRecordType
> 0 &&
724 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
725 switch (record
->ucRecordType
) {
726 case ATOM_I2C_RECORD_TYPE
:
731 (ATOM_I2C_ID_CONFIG_ACCESS
*)
732 &i2c_record
->sucI2cId
;
734 radeon_lookup_i2c_gpio(rdev
,
737 router
.i2c_addr
= i2c_record
->ucI2CAddr
>> 1;
739 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE
:
740 ddc_path
= (ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*)
742 router
.ddc_valid
= true;
743 router
.ddc_mux_type
= ddc_path
->ucMuxType
;
744 router
.ddc_mux_control_pin
= ddc_path
->ucMuxControlPin
;
745 router
.ddc_mux_state
= ddc_path
->ucMuxState
[enum_id
];
747 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE
:
748 cd_path
= (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
*)
750 router
.cd_valid
= true;
751 router
.cd_mux_type
= cd_path
->ucMuxType
;
752 router
.cd_mux_control_pin
= cd_path
->ucMuxControlPin
;
753 router
.cd_mux_state
= cd_path
->ucMuxState
[enum_id
];
756 record
= (ATOM_COMMON_RECORD_HEADER
*)
757 ((char *)record
+ record
->ucRecordSize
);
764 /* look up gpio for ddc, hpd */
765 ddc_bus
.valid
= false;
766 hpd
.hpd
= RADEON_HPD_NONE
;
767 if ((le16_to_cpu(path
->usDeviceTag
) &
768 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) == 0) {
769 for (j
= 0; j
< con_obj
->ucNumberOfObjects
; j
++) {
770 if (le16_to_cpu(path
->usConnObjectId
) ==
771 le16_to_cpu(con_obj
->asObjects
[j
].
773 ATOM_COMMON_RECORD_HEADER
775 (ATOM_COMMON_RECORD_HEADER
777 (ctx
->bios
+ data_offset
+
778 le16_to_cpu(con_obj
->
781 ATOM_I2C_RECORD
*i2c_record
;
782 ATOM_HPD_INT_RECORD
*hpd_record
;
783 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
785 while (record
->ucRecordType
> 0
788 ATOM_MAX_OBJECT_RECORD_NUMBER
) {
789 switch (record
->ucRecordType
) {
790 case ATOM_I2C_RECORD_TYPE
:
795 (ATOM_I2C_ID_CONFIG_ACCESS
*)
796 &i2c_record
->sucI2cId
;
797 ddc_bus
= radeon_lookup_i2c_gpio(rdev
,
801 case ATOM_HPD_INT_RECORD_TYPE
:
803 (ATOM_HPD_INT_RECORD
*)
805 gpio
= radeon_lookup_gpio(rdev
,
806 hpd_record
->ucHPDIntGPIOID
);
807 hpd
= radeon_atom_get_hpd_info_from_gpio(rdev
, &gpio
);
808 hpd
.plugged_state
= hpd_record
->ucPlugged_PinState
;
812 (ATOM_COMMON_RECORD_HEADER
823 /* needed for aux chan transactions */
824 ddc_bus
.hpd
= hpd
.hpd
;
826 conn_id
= le16_to_cpu(path
->usConnObjectId
);
828 if (!radeon_atom_apply_quirks
829 (dev
, le16_to_cpu(path
->usDeviceTag
), &connector_type
,
830 &ddc_bus
, &conn_id
, &hpd
))
833 radeon_add_atom_connector(dev
,
837 connector_type
, &ddc_bus
,
846 radeon_link_encoder_connector(dev
);
851 static uint16_t atombios_get_connector_object_id(struct drm_device
*dev
,
855 struct radeon_device
*rdev
= dev
->dev_private
;
857 if (rdev
->flags
& RADEON_IS_IGP
) {
858 return supported_devices_connector_object_id_convert
860 } else if (((connector_type
== DRM_MODE_CONNECTOR_DVII
) ||
861 (connector_type
== DRM_MODE_CONNECTOR_DVID
)) &&
862 (devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
863 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
864 struct atom_context
*ctx
= mode_info
->atom_context
;
865 int index
= GetIndexIntoMasterTable(DATA
, XTMDS_Info
);
866 uint16_t size
, data_offset
;
868 ATOM_XTMDS_INFO
*xtmds
;
870 if (atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
)) {
871 xtmds
= (ATOM_XTMDS_INFO
*)(ctx
->bios
+ data_offset
);
873 if (xtmds
->ucSupportedLink
& ATOM_XTMDS_SUPPORTED_DUALLINK
) {
874 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
875 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
877 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
879 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
880 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
882 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
885 return supported_devices_connector_object_id_convert
888 return supported_devices_connector_object_id_convert
893 struct bios_connector
{
898 struct radeon_i2c_bus_rec ddc_bus
;
899 struct radeon_hpd hpd
;
902 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
906 struct radeon_device
*rdev
= dev
->dev_private
;
907 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
908 struct atom_context
*ctx
= mode_info
->atom_context
;
909 int index
= GetIndexIntoMasterTable(DATA
, SupportedDevicesInfo
);
910 uint16_t size
, data_offset
;
912 uint16_t device_support
;
914 union atom_supported_devices
*supported_devices
;
915 int i
, j
, max_device
;
916 struct bios_connector
*bios_connectors
;
917 size_t bc_size
= sizeof(*bios_connectors
) * ATOM_MAX_SUPPORTED_DEVICE
;
918 struct radeon_router router
;
920 router
.ddc_valid
= false;
921 router
.cd_valid
= false;
923 bios_connectors
= kzalloc(bc_size
, GFP_KERNEL
);
924 if (!bios_connectors
)
927 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
,
929 kfree(bios_connectors
);
934 (union atom_supported_devices
*)(ctx
->bios
+ data_offset
);
936 device_support
= le16_to_cpu(supported_devices
->info
.usDeviceSupport
);
939 max_device
= ATOM_MAX_SUPPORTED_DEVICE
;
941 max_device
= ATOM_MAX_SUPPORTED_DEVICE_INFO
;
943 for (i
= 0; i
< max_device
; i
++) {
944 ATOM_CONNECTOR_INFO_I2C ci
=
945 supported_devices
->info
.asConnInfo
[i
];
947 bios_connectors
[i
].valid
= false;
949 if (!(device_support
& (1 << i
))) {
953 if (i
== ATOM_DEVICE_CV_INDEX
) {
954 DRM_DEBUG_KMS("Skipping Component Video\n");
958 bios_connectors
[i
].connector_type
=
959 supported_devices_connector_convert
[ci
.sucConnectorInfo
.
963 if (bios_connectors
[i
].connector_type
==
964 DRM_MODE_CONNECTOR_Unknown
)
967 dac
= ci
.sucConnectorInfo
.sbfAccess
.bfAssociatedDAC
;
969 bios_connectors
[i
].line_mux
=
970 ci
.sucI2cId
.ucAccess
;
972 /* give tv unique connector ids */
973 if (i
== ATOM_DEVICE_TV1_INDEX
) {
974 bios_connectors
[i
].ddc_bus
.valid
= false;
975 bios_connectors
[i
].line_mux
= 50;
976 } else if (i
== ATOM_DEVICE_TV2_INDEX
) {
977 bios_connectors
[i
].ddc_bus
.valid
= false;
978 bios_connectors
[i
].line_mux
= 51;
979 } else if (i
== ATOM_DEVICE_CV_INDEX
) {
980 bios_connectors
[i
].ddc_bus
.valid
= false;
981 bios_connectors
[i
].line_mux
= 52;
983 bios_connectors
[i
].ddc_bus
=
984 radeon_lookup_i2c_gpio(rdev
,
985 bios_connectors
[i
].line_mux
);
987 if ((crev
> 1) && (frev
> 1)) {
988 u8 isb
= supported_devices
->info_2d1
.asIntSrcInfo
[i
].ucIntSrcBitmap
;
991 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
994 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
997 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
1001 if (i
== ATOM_DEVICE_DFP1_INDEX
)
1002 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
1003 else if (i
== ATOM_DEVICE_DFP2_INDEX
)
1004 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
1006 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
1009 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1010 * shared with a DVI port, we'll pick up the DVI connector when we
1011 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1013 if (i
== ATOM_DEVICE_CRT1_INDEX
|| i
== ATOM_DEVICE_CRT2_INDEX
)
1014 bios_connectors
[i
].connector_type
=
1015 DRM_MODE_CONNECTOR_VGA
;
1017 if (!radeon_atom_apply_quirks
1018 (dev
, (1 << i
), &bios_connectors
[i
].connector_type
,
1019 &bios_connectors
[i
].ddc_bus
, &bios_connectors
[i
].line_mux
,
1020 &bios_connectors
[i
].hpd
))
1023 bios_connectors
[i
].valid
= true;
1024 bios_connectors
[i
].devices
= (1 << i
);
1026 if (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
)
1027 radeon_add_atom_encoder(dev
,
1028 radeon_get_encoder_enum(dev
,
1034 radeon_add_legacy_encoder(dev
,
1035 radeon_get_encoder_enum(dev
,
1041 /* combine shared connectors */
1042 for (i
= 0; i
< max_device
; i
++) {
1043 if (bios_connectors
[i
].valid
) {
1044 for (j
= 0; j
< max_device
; j
++) {
1045 if (bios_connectors
[j
].valid
&& (i
!= j
)) {
1046 if (bios_connectors
[i
].line_mux
==
1047 bios_connectors
[j
].line_mux
) {
1048 /* make sure not to combine LVDS */
1049 if (bios_connectors
[i
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1050 bios_connectors
[i
].line_mux
= 53;
1051 bios_connectors
[i
].ddc_bus
.valid
= false;
1054 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1055 bios_connectors
[j
].line_mux
= 53;
1056 bios_connectors
[j
].ddc_bus
.valid
= false;
1059 /* combine analog and digital for DVI-I */
1060 if (((bios_connectors
[i
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
1061 (bios_connectors
[j
].devices
& (ATOM_DEVICE_CRT_SUPPORT
))) ||
1062 ((bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
1063 (bios_connectors
[i
].devices
& (ATOM_DEVICE_CRT_SUPPORT
)))) {
1064 bios_connectors
[i
].devices
|=
1065 bios_connectors
[j
].devices
;
1066 bios_connectors
[i
].connector_type
=
1067 DRM_MODE_CONNECTOR_DVII
;
1068 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
))
1069 bios_connectors
[i
].hpd
=
1070 bios_connectors
[j
].hpd
;
1071 bios_connectors
[j
].valid
= false;
1079 /* add the connectors */
1080 for (i
= 0; i
< max_device
; i
++) {
1081 if (bios_connectors
[i
].valid
) {
1082 uint16_t connector_object_id
=
1083 atombios_get_connector_object_id(dev
,
1084 bios_connectors
[i
].connector_type
,
1085 bios_connectors
[i
].devices
);
1086 radeon_add_atom_connector(dev
,
1087 bios_connectors
[i
].line_mux
,
1088 bios_connectors
[i
].devices
,
1091 &bios_connectors
[i
].ddc_bus
,
1093 connector_object_id
,
1094 &bios_connectors
[i
].hpd
,
1099 radeon_link_encoder_connector(dev
);
1101 kfree(bios_connectors
);
1105 union firmware_info
{
1106 ATOM_FIRMWARE_INFO info
;
1107 ATOM_FIRMWARE_INFO_V1_2 info_12
;
1108 ATOM_FIRMWARE_INFO_V1_3 info_13
;
1109 ATOM_FIRMWARE_INFO_V1_4 info_14
;
1110 ATOM_FIRMWARE_INFO_V2_1 info_21
;
1111 ATOM_FIRMWARE_INFO_V2_2 info_22
;
1114 bool radeon_atom_get_clock_info(struct drm_device
*dev
)
1116 struct radeon_device
*rdev
= dev
->dev_private
;
1117 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1118 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
1119 union firmware_info
*firmware_info
;
1121 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
1122 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
1123 struct radeon_pll
*dcpll
= &rdev
->clock
.dcpll
;
1124 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
1125 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
1126 uint16_t data_offset
;
1128 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1129 &frev
, &crev
, &data_offset
)) {
1131 (union firmware_info
*)(mode_info
->atom_context
->bios
+
1134 p1pll
->reference_freq
=
1135 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1136 p1pll
->reference_div
= 0;
1139 p1pll
->pll_out_min
=
1140 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Output
);
1142 p1pll
->pll_out_min
=
1143 le32_to_cpu(firmware_info
->info_12
.ulMinPixelClockPLL_Output
);
1144 p1pll
->pll_out_max
=
1145 le32_to_cpu(firmware_info
->info
.ulMaxPixelClockPLL_Output
);
1148 p1pll
->lcd_pll_out_min
=
1149 le16_to_cpu(firmware_info
->info_14
.usLcdMinPixelClockPLL_Output
) * 100;
1150 if (p1pll
->lcd_pll_out_min
== 0)
1151 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1152 p1pll
->lcd_pll_out_max
=
1153 le16_to_cpu(firmware_info
->info_14
.usLcdMaxPixelClockPLL_Output
) * 100;
1154 if (p1pll
->lcd_pll_out_max
== 0)
1155 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1157 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1158 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1161 if (p1pll
->pll_out_min
== 0) {
1162 if (ASIC_IS_AVIVO(rdev
))
1163 p1pll
->pll_out_min
= 64800;
1165 p1pll
->pll_out_min
= 20000;
1166 } else if (p1pll
->pll_out_min
> 64800) {
1167 /* Limiting the pll output range is a good thing generally as
1168 * it limits the number of possible pll combinations for a given
1169 * frequency presumably to the ones that work best on each card.
1170 * However, certain duallink DVI monitors seem to like
1171 * pll combinations that would be limited by this at least on
1172 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1175 p1pll
->pll_out_min
= 64800;
1179 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Input
);
1181 le16_to_cpu(firmware_info
->info
.usMaxPixelClockPLL_Input
);
1186 if (ASIC_IS_DCE4(rdev
))
1187 spll
->reference_freq
=
1188 le16_to_cpu(firmware_info
->info_21
.usCoreReferenceClock
);
1190 spll
->reference_freq
=
1191 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1192 spll
->reference_div
= 0;
1195 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Output
);
1197 le32_to_cpu(firmware_info
->info
.ulMaxEngineClockPLL_Output
);
1200 if (spll
->pll_out_min
== 0) {
1201 if (ASIC_IS_AVIVO(rdev
))
1202 spll
->pll_out_min
= 64800;
1204 spll
->pll_out_min
= 20000;
1208 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Input
);
1210 le16_to_cpu(firmware_info
->info
.usMaxEngineClockPLL_Input
);
1213 if (ASIC_IS_DCE4(rdev
))
1214 mpll
->reference_freq
=
1215 le16_to_cpu(firmware_info
->info_21
.usMemoryReferenceClock
);
1217 mpll
->reference_freq
=
1218 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1219 mpll
->reference_div
= 0;
1222 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Output
);
1224 le32_to_cpu(firmware_info
->info
.ulMaxMemoryClockPLL_Output
);
1227 if (mpll
->pll_out_min
== 0) {
1228 if (ASIC_IS_AVIVO(rdev
))
1229 mpll
->pll_out_min
= 64800;
1231 mpll
->pll_out_min
= 20000;
1235 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Input
);
1237 le16_to_cpu(firmware_info
->info
.usMaxMemoryClockPLL_Input
);
1239 rdev
->clock
.default_sclk
=
1240 le32_to_cpu(firmware_info
->info
.ulDefaultEngineClock
);
1241 rdev
->clock
.default_mclk
=
1242 le32_to_cpu(firmware_info
->info
.ulDefaultMemoryClock
);
1244 if (ASIC_IS_DCE4(rdev
)) {
1245 rdev
->clock
.default_dispclk
=
1246 le32_to_cpu(firmware_info
->info_21
.ulDefaultDispEngineClkFreq
);
1247 if (rdev
->clock
.default_dispclk
== 0) {
1248 if (ASIC_IS_DCE5(rdev
))
1249 rdev
->clock
.default_dispclk
= 54000; /* 540 Mhz */
1251 rdev
->clock
.default_dispclk
= 60000; /* 600 Mhz */
1253 rdev
->clock
.dp_extclk
=
1254 le16_to_cpu(firmware_info
->info_21
.usUniphyDPModeExtClkFreq
);
1265 struct _ATOM_INTEGRATED_SYSTEM_INFO info
;
1266 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2
;
1269 bool radeon_atombios_sideport_present(struct radeon_device
*rdev
)
1271 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1272 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1273 union igp_info
*igp_info
;
1277 /* sideport is AMD only */
1278 if (rdev
->family
== CHIP_RS600
)
1281 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1282 &frev
, &crev
, &data_offset
)) {
1283 igp_info
= (union igp_info
*)(mode_info
->atom_context
->bios
+
1287 if (igp_info
->info
.ulBootUpMemoryClock
)
1291 if (igp_info
->info_2
.ulBootUpSidePortClock
)
1295 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
1302 bool radeon_atombios_get_tmds_info(struct radeon_encoder
*encoder
,
1303 struct radeon_encoder_int_tmds
*tmds
)
1305 struct drm_device
*dev
= encoder
->base
.dev
;
1306 struct radeon_device
*rdev
= dev
->dev_private
;
1307 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1308 int index
= GetIndexIntoMasterTable(DATA
, TMDS_Info
);
1309 uint16_t data_offset
;
1310 struct _ATOM_TMDS_INFO
*tmds_info
;
1315 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1316 &frev
, &crev
, &data_offset
)) {
1318 (struct _ATOM_TMDS_INFO
*)(mode_info
->atom_context
->bios
+
1321 maxfreq
= le16_to_cpu(tmds_info
->usMaxFrequency
);
1322 for (i
= 0; i
< 4; i
++) {
1323 tmds
->tmds_pll
[i
].freq
=
1324 le16_to_cpu(tmds_info
->asMiscInfo
[i
].usFrequency
);
1325 tmds
->tmds_pll
[i
].value
=
1326 tmds_info
->asMiscInfo
[i
].ucPLL_ChargePump
& 0x3f;
1327 tmds
->tmds_pll
[i
].value
|=
1328 (tmds_info
->asMiscInfo
[i
].
1329 ucPLL_VCO_Gain
& 0x3f) << 6;
1330 tmds
->tmds_pll
[i
].value
|=
1331 (tmds_info
->asMiscInfo
[i
].
1332 ucPLL_DutyCycle
& 0xf) << 12;
1333 tmds
->tmds_pll
[i
].value
|=
1334 (tmds_info
->asMiscInfo
[i
].
1335 ucPLL_VoltageSwing
& 0xf) << 16;
1337 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1338 tmds
->tmds_pll
[i
].freq
,
1339 tmds
->tmds_pll
[i
].value
);
1341 if (maxfreq
== tmds
->tmds_pll
[i
].freq
) {
1342 tmds
->tmds_pll
[i
].freq
= 0xffffffff;
1351 bool radeon_atombios_get_ppll_ss_info(struct radeon_device
*rdev
,
1352 struct radeon_atom_ss
*ss
,
1355 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1356 int index
= GetIndexIntoMasterTable(DATA
, PPLL_SS_Info
);
1357 uint16_t data_offset
, size
;
1358 struct _ATOM_SPREAD_SPECTRUM_INFO
*ss_info
;
1362 memset(ss
, 0, sizeof(struct radeon_atom_ss
));
1363 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1364 &frev
, &crev
, &data_offset
)) {
1366 (struct _ATOM_SPREAD_SPECTRUM_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1368 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1369 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT
);
1371 for (i
= 0; i
< num_indices
; i
++) {
1372 if (ss_info
->asSS_Info
[i
].ucSS_Id
== id
) {
1374 le16_to_cpu(ss_info
->asSS_Info
[i
].usSpreadSpectrumPercentage
);
1375 ss
->type
= ss_info
->asSS_Info
[i
].ucSpreadSpectrumType
;
1376 ss
->step
= ss_info
->asSS_Info
[i
].ucSS_Step
;
1377 ss
->delay
= ss_info
->asSS_Info
[i
].ucSS_Delay
;
1378 ss
->range
= ss_info
->asSS_Info
[i
].ucSS_Range
;
1379 ss
->refdiv
= ss_info
->asSS_Info
[i
].ucRecommendedRef_Div
;
1387 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device
*rdev
,
1388 struct radeon_atom_ss
*ss
,
1391 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1392 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1393 u16 data_offset
, size
;
1394 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
*igp_info
;
1396 u16 percentage
= 0, rate
= 0;
1398 /* get any igp specific overrides */
1399 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1400 &frev
, &crev
, &data_offset
)) {
1401 igp_info
= (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
*)
1402 (mode_info
->atom_context
->bios
+ data_offset
);
1404 case ASIC_INTERNAL_SS_ON_TMDS
:
1405 percentage
= le16_to_cpu(igp_info
->usDVISSPercentage
);
1406 rate
= le16_to_cpu(igp_info
->usDVISSpreadRateIn10Hz
);
1408 case ASIC_INTERNAL_SS_ON_HDMI
:
1409 percentage
= le16_to_cpu(igp_info
->usHDMISSPercentage
);
1410 rate
= le16_to_cpu(igp_info
->usHDMISSpreadRateIn10Hz
);
1412 case ASIC_INTERNAL_SS_ON_LVDS
:
1413 percentage
= le16_to_cpu(igp_info
->usLvdsSSPercentage
);
1414 rate
= le16_to_cpu(igp_info
->usLvdsSSpreadRateIn10Hz
);
1418 ss
->percentage
= percentage
;
1424 union asic_ss_info
{
1425 struct _ATOM_ASIC_INTERNAL_SS_INFO info
;
1426 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2
;
1427 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3
;
1430 bool radeon_atombios_get_asic_ss_info(struct radeon_device
*rdev
,
1431 struct radeon_atom_ss
*ss
,
1434 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1435 int index
= GetIndexIntoMasterTable(DATA
, ASIC_InternalSS_Info
);
1436 uint16_t data_offset
, size
;
1437 union asic_ss_info
*ss_info
;
1441 memset(ss
, 0, sizeof(struct radeon_atom_ss
));
1442 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1443 &frev
, &crev
, &data_offset
)) {
1446 (union asic_ss_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1450 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1451 sizeof(ATOM_ASIC_SS_ASSIGNMENT
);
1453 for (i
= 0; i
< num_indices
; i
++) {
1454 if ((ss_info
->info
.asSpreadSpectrum
[i
].ucClockIndication
== id
) &&
1455 (clock
<= ss_info
->info
.asSpreadSpectrum
[i
].ulTargetClockRange
)) {
1457 le16_to_cpu(ss_info
->info
.asSpreadSpectrum
[i
].usSpreadSpectrumPercentage
);
1458 ss
->type
= ss_info
->info
.asSpreadSpectrum
[i
].ucSpreadSpectrumMode
;
1459 ss
->rate
= le16_to_cpu(ss_info
->info
.asSpreadSpectrum
[i
].usSpreadRateInKhz
);
1465 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1466 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2
);
1467 for (i
= 0; i
< num_indices
; i
++) {
1468 if ((ss_info
->info_2
.asSpreadSpectrum
[i
].ucClockIndication
== id
) &&
1469 (clock
<= ss_info
->info_2
.asSpreadSpectrum
[i
].ulTargetClockRange
)) {
1471 le16_to_cpu(ss_info
->info_2
.asSpreadSpectrum
[i
].usSpreadSpectrumPercentage
);
1472 ss
->type
= ss_info
->info_2
.asSpreadSpectrum
[i
].ucSpreadSpectrumMode
;
1473 ss
->rate
= le16_to_cpu(ss_info
->info_2
.asSpreadSpectrum
[i
].usSpreadRateIn10Hz
);
1479 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1480 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3
);
1481 for (i
= 0; i
< num_indices
; i
++) {
1482 if ((ss_info
->info_3
.asSpreadSpectrum
[i
].ucClockIndication
== id
) &&
1483 (clock
<= ss_info
->info_3
.asSpreadSpectrum
[i
].ulTargetClockRange
)) {
1485 le16_to_cpu(ss_info
->info_3
.asSpreadSpectrum
[i
].usSpreadSpectrumPercentage
);
1486 ss
->type
= ss_info
->info_3
.asSpreadSpectrum
[i
].ucSpreadSpectrumMode
;
1487 ss
->rate
= le16_to_cpu(ss_info
->info_3
.asSpreadSpectrum
[i
].usSpreadRateIn10Hz
);
1488 if (rdev
->flags
& RADEON_IS_IGP
)
1489 radeon_atombios_get_igp_ss_overrides(rdev
, ss
, id
);
1495 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev
, crev
);
1504 struct _ATOM_LVDS_INFO info
;
1505 struct _ATOM_LVDS_INFO_V12 info_12
;
1508 struct radeon_encoder_atom_dig
*radeon_atombios_get_lvds_info(struct
1512 struct drm_device
*dev
= encoder
->base
.dev
;
1513 struct radeon_device
*rdev
= dev
->dev_private
;
1514 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1515 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
1516 uint16_t data_offset
, misc
;
1517 union lvds_info
*lvds_info
;
1519 struct radeon_encoder_atom_dig
*lvds
= NULL
;
1520 int encoder_enum
= (encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1522 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1523 &frev
, &crev
, &data_offset
)) {
1525 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1527 kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
1532 lvds
->native_mode
.clock
=
1533 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
1534 lvds
->native_mode
.hdisplay
=
1535 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
1536 lvds
->native_mode
.vdisplay
=
1537 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
1538 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
1539 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
1540 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
1541 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
1542 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
1543 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
1544 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
1545 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
1546 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
1547 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncOffset
);
1548 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
1549 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
1550 lvds
->panel_pwr_delay
=
1551 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
1552 lvds
->lcd_misc
= lvds_info
->info
.ucLVDS_Misc
;
1554 misc
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.susModeMiscInfo
.usAccess
);
1555 if (misc
& ATOM_VSYNC_POLARITY
)
1556 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
1557 if (misc
& ATOM_HSYNC_POLARITY
)
1558 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
1559 if (misc
& ATOM_COMPOSITESYNC
)
1560 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_CSYNC
;
1561 if (misc
& ATOM_INTERLACE
)
1562 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
1563 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1564 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_DBLSCAN
;
1566 lvds
->native_mode
.width_mm
= lvds_info
->info
.sLCDTiming
.usImageHSize
;
1567 lvds
->native_mode
.height_mm
= lvds_info
->info
.sLCDTiming
.usImageVSize
;
1569 /* set crtc values */
1570 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1572 lvds
->lcd_ss_id
= lvds_info
->info
.ucSS_Id
;
1574 encoder
->native_mode
= lvds
->native_mode
;
1576 if (encoder_enum
== 2)
1579 lvds
->linkb
= false;
1581 /* parse the lcd record table */
1582 if (lvds_info
->info
.usModePatchTableOffset
) {
1583 ATOM_FAKE_EDID_PATCH_RECORD
*fake_edid_record
;
1584 ATOM_PANEL_RESOLUTION_PATCH_RECORD
*panel_res_record
;
1585 bool bad_record
= false;
1586 u8
*record
= (u8
*)(mode_info
->atom_context
->bios
+
1588 lvds_info
->info
.usModePatchTableOffset
);
1589 while (*record
!= ATOM_RECORD_END_TYPE
) {
1591 case LCD_MODE_PATCH_RECORD_MODE_TYPE
:
1592 record
+= sizeof(ATOM_PATCH_RECORD_MODE
);
1594 case LCD_RTS_RECORD_TYPE
:
1595 record
+= sizeof(ATOM_LCD_RTS_RECORD
);
1597 case LCD_CAP_RECORD_TYPE
:
1598 record
+= sizeof(ATOM_LCD_MODE_CONTROL_CAP
);
1600 case LCD_FAKE_EDID_PATCH_RECORD_TYPE
:
1601 fake_edid_record
= (ATOM_FAKE_EDID_PATCH_RECORD
*)record
;
1602 if (fake_edid_record
->ucFakeEDIDLength
) {
1605 max((int)EDID_LENGTH
, (int)fake_edid_record
->ucFakeEDIDLength
);
1606 edid
= kmalloc(edid_size
, GFP_KERNEL
);
1608 memcpy((u8
*)edid
, (u8
*)&fake_edid_record
->ucFakeEDIDString
[0],
1609 fake_edid_record
->ucFakeEDIDLength
);
1611 if (drm_edid_is_valid(edid
))
1612 rdev
->mode_info
.bios_hardcoded_edid
= edid
;
1617 record
+= sizeof(ATOM_FAKE_EDID_PATCH_RECORD
);
1619 case LCD_PANEL_RESOLUTION_RECORD_TYPE
:
1620 panel_res_record
= (ATOM_PANEL_RESOLUTION_PATCH_RECORD
*)record
;
1621 lvds
->native_mode
.width_mm
= panel_res_record
->usHSize
;
1622 lvds
->native_mode
.height_mm
= panel_res_record
->usVSize
;
1623 record
+= sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD
);
1626 DRM_ERROR("Bad LCD record %d\n", *record
);
1638 struct radeon_encoder_primary_dac
*
1639 radeon_atombios_get_primary_dac_info(struct radeon_encoder
*encoder
)
1641 struct drm_device
*dev
= encoder
->base
.dev
;
1642 struct radeon_device
*rdev
= dev
->dev_private
;
1643 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1644 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1645 uint16_t data_offset
;
1646 struct _COMPASSIONATE_DATA
*dac_info
;
1649 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
1651 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1652 &frev
, &crev
, &data_offset
)) {
1653 dac_info
= (struct _COMPASSIONATE_DATA
*)
1654 (mode_info
->atom_context
->bios
+ data_offset
);
1656 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
), GFP_KERNEL
);
1661 bg
= dac_info
->ucDAC1_BG_Adjustment
;
1662 dac
= dac_info
->ucDAC1_DAC_Adjustment
;
1663 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
1669 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
1670 struct drm_display_mode
*mode
)
1672 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1673 ATOM_ANALOG_TV_INFO
*tv_info
;
1674 ATOM_ANALOG_TV_INFO_V1_2
*tv_info_v1_2
;
1675 ATOM_DTD_FORMAT
*dtd_timings
;
1676 int data_index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1678 u16 data_offset
, misc
;
1680 if (!atom_parse_data_header(mode_info
->atom_context
, data_index
, NULL
,
1681 &frev
, &crev
, &data_offset
))
1686 tv_info
= (ATOM_ANALOG_TV_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1687 if (index
>= MAX_SUPPORTED_TV_TIMING
)
1690 mode
->crtc_htotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Total
);
1691 mode
->crtc_hdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Disp
);
1692 mode
->crtc_hsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
);
1693 mode
->crtc_hsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
) +
1694 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncWidth
);
1696 mode
->crtc_vtotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Total
);
1697 mode
->crtc_vdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Disp
);
1698 mode
->crtc_vsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
);
1699 mode
->crtc_vsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
) +
1700 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncWidth
);
1703 misc
= le16_to_cpu(tv_info
->aModeTimings
[index
].susModeMiscInfo
.usAccess
);
1704 if (misc
& ATOM_VSYNC_POLARITY
)
1705 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1706 if (misc
& ATOM_HSYNC_POLARITY
)
1707 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1708 if (misc
& ATOM_COMPOSITESYNC
)
1709 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1710 if (misc
& ATOM_INTERLACE
)
1711 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1712 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1713 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1715 mode
->clock
= le16_to_cpu(tv_info
->aModeTimings
[index
].usPixelClock
) * 10;
1718 /* PAL timings appear to have wrong values for totals */
1719 mode
->crtc_htotal
-= 1;
1720 mode
->crtc_vtotal
-= 1;
1724 tv_info_v1_2
= (ATOM_ANALOG_TV_INFO_V1_2
*)(mode_info
->atom_context
->bios
+ data_offset
);
1725 if (index
>= MAX_SUPPORTED_TV_TIMING_V1_2
)
1728 dtd_timings
= &tv_info_v1_2
->aModeTimings
[index
];
1729 mode
->crtc_htotal
= le16_to_cpu(dtd_timings
->usHActive
) +
1730 le16_to_cpu(dtd_timings
->usHBlanking_Time
);
1731 mode
->crtc_hdisplay
= le16_to_cpu(dtd_timings
->usHActive
);
1732 mode
->crtc_hsync_start
= le16_to_cpu(dtd_timings
->usHActive
) +
1733 le16_to_cpu(dtd_timings
->usHSyncOffset
);
1734 mode
->crtc_hsync_end
= mode
->crtc_hsync_start
+
1735 le16_to_cpu(dtd_timings
->usHSyncWidth
);
1737 mode
->crtc_vtotal
= le16_to_cpu(dtd_timings
->usVActive
) +
1738 le16_to_cpu(dtd_timings
->usVBlanking_Time
);
1739 mode
->crtc_vdisplay
= le16_to_cpu(dtd_timings
->usVActive
);
1740 mode
->crtc_vsync_start
= le16_to_cpu(dtd_timings
->usVActive
) +
1741 le16_to_cpu(dtd_timings
->usVSyncOffset
);
1742 mode
->crtc_vsync_end
= mode
->crtc_vsync_start
+
1743 le16_to_cpu(dtd_timings
->usVSyncWidth
);
1746 misc
= le16_to_cpu(dtd_timings
->susModeMiscInfo
.usAccess
);
1747 if (misc
& ATOM_VSYNC_POLARITY
)
1748 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1749 if (misc
& ATOM_HSYNC_POLARITY
)
1750 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1751 if (misc
& ATOM_COMPOSITESYNC
)
1752 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1753 if (misc
& ATOM_INTERLACE
)
1754 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1755 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1756 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1758 mode
->clock
= le16_to_cpu(dtd_timings
->usPixClk
) * 10;
1765 radeon_atombios_get_tv_info(struct radeon_device
*rdev
)
1767 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1768 int index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1769 uint16_t data_offset
;
1771 struct _ATOM_ANALOG_TV_INFO
*tv_info
;
1772 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
1774 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1775 &frev
, &crev
, &data_offset
)) {
1777 tv_info
= (struct _ATOM_ANALOG_TV_INFO
*)
1778 (mode_info
->atom_context
->bios
+ data_offset
);
1780 switch (tv_info
->ucTV_BootUpDefaultStandard
) {
1782 tv_std
= TV_STD_NTSC
;
1783 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1786 tv_std
= TV_STD_NTSC_J
;
1787 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1790 tv_std
= TV_STD_PAL
;
1791 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1794 tv_std
= TV_STD_PAL_M
;
1795 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1798 tv_std
= TV_STD_PAL_N
;
1799 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1802 tv_std
= TV_STD_PAL_CN
;
1803 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1806 tv_std
= TV_STD_PAL_60
;
1807 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1810 tv_std
= TV_STD_SECAM
;
1811 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1814 tv_std
= TV_STD_NTSC
;
1815 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1822 struct radeon_encoder_tv_dac
*
1823 radeon_atombios_get_tv_dac_info(struct radeon_encoder
*encoder
)
1825 struct drm_device
*dev
= encoder
->base
.dev
;
1826 struct radeon_device
*rdev
= dev
->dev_private
;
1827 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1828 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1829 uint16_t data_offset
;
1830 struct _COMPASSIONATE_DATA
*dac_info
;
1833 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1835 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1836 &frev
, &crev
, &data_offset
)) {
1838 dac_info
= (struct _COMPASSIONATE_DATA
*)
1839 (mode_info
->atom_context
->bios
+ data_offset
);
1841 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1846 bg
= dac_info
->ucDAC2_CRT2_BG_Adjustment
;
1847 dac
= dac_info
->ucDAC2_CRT2_DAC_Adjustment
;
1848 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1850 bg
= dac_info
->ucDAC2_PAL_BG_Adjustment
;
1851 dac
= dac_info
->ucDAC2_PAL_DAC_Adjustment
;
1852 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1854 bg
= dac_info
->ucDAC2_NTSC_BG_Adjustment
;
1855 dac
= dac_info
->ucDAC2_NTSC_DAC_Adjustment
;
1856 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1858 tv_dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
1863 static const char *thermal_controller_names
[] = {
1874 static const char *pp_lib_thermal_controller_names
[] = {
1894 struct _ATOM_POWERPLAY_INFO info
;
1895 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
1896 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
1897 struct _ATOM_PPLIB_POWERPLAYTABLE pplib
;
1898 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2
;
1899 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3
;
1902 union pplib_clock_info
{
1903 struct _ATOM_PPLIB_R600_CLOCK_INFO r600
;
1904 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780
;
1905 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen
;
1906 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo
;
1909 union pplib_power_state
{
1910 struct _ATOM_PPLIB_STATE v1
;
1911 struct _ATOM_PPLIB_STATE_V2 v2
;
1914 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device
*rdev
,
1916 u32 misc
, u32 misc2
)
1918 rdev
->pm
.power_state
[state_index
].misc
= misc
;
1919 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
1920 /* order matters! */
1921 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
1922 rdev
->pm
.power_state
[state_index
].type
=
1923 POWER_STATE_TYPE_POWERSAVE
;
1924 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
1925 rdev
->pm
.power_state
[state_index
].type
=
1926 POWER_STATE_TYPE_BATTERY
;
1927 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
1928 rdev
->pm
.power_state
[state_index
].type
=
1929 POWER_STATE_TYPE_BATTERY
;
1930 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
1931 rdev
->pm
.power_state
[state_index
].type
=
1932 POWER_STATE_TYPE_BALANCED
;
1933 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
) {
1934 rdev
->pm
.power_state
[state_index
].type
=
1935 POWER_STATE_TYPE_PERFORMANCE
;
1936 rdev
->pm
.power_state
[state_index
].flags
&=
1937 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1939 if (misc2
& ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE
)
1940 rdev
->pm
.power_state
[state_index
].type
=
1941 POWER_STATE_TYPE_BALANCED
;
1942 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
1943 rdev
->pm
.power_state
[state_index
].type
=
1944 POWER_STATE_TYPE_DEFAULT
;
1945 rdev
->pm
.default_power_state_index
= state_index
;
1946 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
1947 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1948 } else if (state_index
== 0) {
1949 rdev
->pm
.power_state
[state_index
].clock_info
[0].flags
|=
1950 RADEON_PM_MODE_NO_DISPLAY
;
1954 static int radeon_atombios_parse_power_table_1_3(struct radeon_device
*rdev
)
1956 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1957 u32 misc
, misc2
= 0;
1958 int num_modes
= 0, i
;
1959 int state_index
= 0;
1960 struct radeon_i2c_bus_rec i2c_bus
;
1961 union power_info
*power_info
;
1962 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
1966 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1967 &frev
, &crev
, &data_offset
))
1969 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1971 /* add the i2c bus for thermal/fan chip */
1972 if (power_info
->info
.ucOverdriveThermalController
> 0) {
1973 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1974 thermal_controller_names
[power_info
->info
.ucOverdriveThermalController
],
1975 power_info
->info
.ucOverdriveControllerAddress
>> 1);
1976 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, power_info
->info
.ucOverdriveI2cLine
);
1977 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
1978 if (rdev
->pm
.i2c_bus
) {
1979 struct i2c_board_info info
= { };
1980 const char *name
= thermal_controller_names
[power_info
->info
.
1981 ucOverdriveThermalController
];
1982 info
.addr
= power_info
->info
.ucOverdriveControllerAddress
>> 1;
1983 strlcpy(info
.type
, name
, sizeof(info
.type
));
1984 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
1987 num_modes
= power_info
->info
.ucNumOfPowerModeEntries
;
1988 if (num_modes
> ATOM_MAX_NUMBEROF_POWER_BLOCK
)
1989 num_modes
= ATOM_MAX_NUMBEROF_POWER_BLOCK
;
1990 /* last mode is usually default, array is low to high */
1991 for (i
= 0; i
< num_modes
; i
++) {
1992 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
1995 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1996 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
1997 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usMemoryClock
);
1998 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
1999 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usEngineClock
);
2000 /* skip invalid modes */
2001 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2002 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2004 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2005 power_info
->info
.asPowerPlayInfo
[i
].ucNumPciELanes
;
2006 misc
= le32_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].ulMiscInfo
);
2007 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
2008 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
2009 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2011 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
2012 radeon_lookup_gpio(rdev
,
2013 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
2014 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
2015 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2018 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2020 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
2021 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2023 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
2024 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
2026 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2027 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, 0);
2031 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2032 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2033 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMemoryClock
);
2034 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2035 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulEngineClock
);
2036 /* skip invalid modes */
2037 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2038 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2040 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2041 power_info
->info_2
.asPowerPlayInfo
[i
].ucNumPciELanes
;
2042 misc
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo
);
2043 misc2
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo2
);
2044 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
2045 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
2046 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2048 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
2049 radeon_lookup_gpio(rdev
,
2050 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
2051 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
2052 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2055 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2057 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
2058 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2060 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
2061 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
2063 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2064 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, misc2
);
2068 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2069 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2070 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMemoryClock
);
2071 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2072 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulEngineClock
);
2073 /* skip invalid modes */
2074 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2075 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2077 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2078 power_info
->info_3
.asPowerPlayInfo
[i
].ucNumPciELanes
;
2079 misc
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo
);
2080 misc2
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo2
);
2081 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
2082 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
2083 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2085 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
2086 radeon_lookup_gpio(rdev
,
2087 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
2088 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
2089 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2092 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2094 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
2095 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2097 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
2098 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
2099 if (misc2
& ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN
) {
2100 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_enabled
=
2102 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_id
=
2103 power_info
->info_3
.asPowerPlayInfo
[i
].ucVDDCI_VoltageDropIndex
;
2106 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2107 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, misc2
);
2112 /* last mode is usually default */
2113 if (rdev
->pm
.default_power_state_index
== -1) {
2114 rdev
->pm
.power_state
[state_index
- 1].type
=
2115 POWER_STATE_TYPE_DEFAULT
;
2116 rdev
->pm
.default_power_state_index
= state_index
- 1;
2117 rdev
->pm
.power_state
[state_index
- 1].default_clock_mode
=
2118 &rdev
->pm
.power_state
[state_index
- 1].clock_info
[0];
2119 rdev
->pm
.power_state
[state_index
].flags
&=
2120 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2121 rdev
->pm
.power_state
[state_index
].misc
= 0;
2122 rdev
->pm
.power_state
[state_index
].misc2
= 0;
2127 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device
*rdev
,
2128 ATOM_PPLIB_THERMALCONTROLLER
*controller
)
2130 struct radeon_i2c_bus_rec i2c_bus
;
2132 /* add the i2c bus for thermal/fan chip */
2133 if (controller
->ucType
> 0) {
2134 if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV6xx
) {
2135 DRM_INFO("Internal thermal controller %s fan control\n",
2136 (controller
->ucFanParameters
&
2137 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2138 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV6XX
;
2139 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV770
) {
2140 DRM_INFO("Internal thermal controller %s fan control\n",
2141 (controller
->ucFanParameters
&
2142 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2143 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV770
;
2144 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_EVERGREEN
) {
2145 DRM_INFO("Internal thermal controller %s fan control\n",
2146 (controller
->ucFanParameters
&
2147 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2148 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_EVERGREEN
;
2149 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_SUMO
) {
2150 DRM_INFO("Internal thermal controller %s fan control\n",
2151 (controller
->ucFanParameters
&
2152 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2153 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_SUMO
;
2154 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_NISLANDS
) {
2155 DRM_INFO("Internal thermal controller %s fan control\n",
2156 (controller
->ucFanParameters
&
2157 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2158 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NI
;
2159 } else if ((controller
->ucType
==
2160 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO
) ||
2161 (controller
->ucType
==
2162 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL
) ||
2163 (controller
->ucType
==
2164 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL
)) {
2165 DRM_INFO("Special thermal controller config\n");
2167 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2168 pp_lib_thermal_controller_names
[controller
->ucType
],
2169 controller
->ucI2cAddress
>> 1,
2170 (controller
->ucFanParameters
&
2171 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2172 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, controller
->ucI2cLine
);
2173 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
2174 if (rdev
->pm
.i2c_bus
) {
2175 struct i2c_board_info info
= { };
2176 const char *name
= pp_lib_thermal_controller_names
[controller
->ucType
];
2177 info
.addr
= controller
->ucI2cAddress
>> 1;
2178 strlcpy(info
.type
, name
, sizeof(info
.type
));
2179 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
2185 static u16
radeon_atombios_get_default_vddc(struct radeon_device
*rdev
)
2187 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2188 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
2191 union firmware_info
*firmware_info
;
2194 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2195 &frev
, &crev
, &data_offset
)) {
2197 (union firmware_info
*)(mode_info
->atom_context
->bios
+
2199 vddc
= firmware_info
->info_14
.usBootUpVDDCVoltage
;
2205 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device
*rdev
,
2206 int state_index
, int mode_index
,
2207 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
)
2210 u32 misc
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
2211 u32 misc2
= le16_to_cpu(non_clock_info
->usClassification
);
2212 u16 vddc
= radeon_atombios_get_default_vddc(rdev
);
2214 rdev
->pm
.power_state
[state_index
].misc
= misc
;
2215 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
2216 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2217 ((misc
& ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
) >>
2218 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
) + 1;
2219 switch (misc2
& ATOM_PPLIB_CLASSIFICATION_UI_MASK
) {
2220 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
:
2221 rdev
->pm
.power_state
[state_index
].type
=
2222 POWER_STATE_TYPE_BATTERY
;
2224 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
:
2225 rdev
->pm
.power_state
[state_index
].type
=
2226 POWER_STATE_TYPE_BALANCED
;
2228 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
:
2229 rdev
->pm
.power_state
[state_index
].type
=
2230 POWER_STATE_TYPE_PERFORMANCE
;
2232 case ATOM_PPLIB_CLASSIFICATION_UI_NONE
:
2233 if (misc2
& ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
2234 rdev
->pm
.power_state
[state_index
].type
=
2235 POWER_STATE_TYPE_PERFORMANCE
;
2238 rdev
->pm
.power_state
[state_index
].flags
= 0;
2239 if (misc
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
)
2240 rdev
->pm
.power_state
[state_index
].flags
|=
2241 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2242 if (misc2
& ATOM_PPLIB_CLASSIFICATION_BOOT
) {
2243 rdev
->pm
.power_state
[state_index
].type
=
2244 POWER_STATE_TYPE_DEFAULT
;
2245 rdev
->pm
.default_power_state_index
= state_index
;
2246 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2247 &rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
- 1];
2248 if (ASIC_IS_DCE5(rdev
)) {
2249 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2250 rdev
->pm
.default_sclk
= rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
;
2251 rdev
->pm
.default_mclk
= rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
;
2252 rdev
->pm
.default_vddc
= rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.voltage
;
2254 /* patch the table values with the default slck/mclk from firmware info */
2255 for (j
= 0; j
< mode_index
; j
++) {
2256 rdev
->pm
.power_state
[state_index
].clock_info
[j
].mclk
=
2257 rdev
->clock
.default_mclk
;
2258 rdev
->pm
.power_state
[state_index
].clock_info
[j
].sclk
=
2259 rdev
->clock
.default_sclk
;
2261 rdev
->pm
.power_state
[state_index
].clock_info
[j
].voltage
.voltage
=
2268 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device
*rdev
,
2269 int state_index
, int mode_index
,
2270 union pplib_clock_info
*clock_info
)
2274 if (rdev
->flags
& RADEON_IS_IGP
) {
2275 if (rdev
->family
>= CHIP_PALM
) {
2276 sclk
= le16_to_cpu(clock_info
->sumo
.usEngineClockLow
);
2277 sclk
|= clock_info
->sumo
.ucEngineClockHigh
<< 16;
2278 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2280 sclk
= le16_to_cpu(clock_info
->rs780
.usLowEngineClockLow
);
2281 sclk
|= clock_info
->rs780
.ucLowEngineClockHigh
<< 16;
2282 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2284 } else if (ASIC_IS_DCE4(rdev
)) {
2285 sclk
= le16_to_cpu(clock_info
->evergreen
.usEngineClockLow
);
2286 sclk
|= clock_info
->evergreen
.ucEngineClockHigh
<< 16;
2287 mclk
= le16_to_cpu(clock_info
->evergreen
.usMemoryClockLow
);
2288 mclk
|= clock_info
->evergreen
.ucMemoryClockHigh
<< 16;
2289 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2290 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2291 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2293 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2294 clock_info
->evergreen
.usVDDC
;
2296 sclk
= le16_to_cpu(clock_info
->r600
.usEngineClockLow
);
2297 sclk
|= clock_info
->r600
.ucEngineClockHigh
<< 16;
2298 mclk
= le16_to_cpu(clock_info
->r600
.usMemoryClockLow
);
2299 mclk
|= clock_info
->r600
.ucMemoryClockHigh
<< 16;
2300 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2301 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2302 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2304 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2305 clock_info
->r600
.usVDDC
;
2308 if (rdev
->flags
& RADEON_IS_IGP
) {
2309 /* skip invalid modes */
2310 if (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0)
2313 /* skip invalid modes */
2314 if ((rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
== 0) ||
2315 (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0))
2321 static int radeon_atombios_parse_power_table_4_5(struct radeon_device
*rdev
)
2323 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2324 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
2325 union pplib_power_state
*power_state
;
2327 int state_index
= 0, mode_index
= 0;
2328 union pplib_clock_info
*clock_info
;
2330 union power_info
*power_info
;
2331 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2335 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2336 &frev
, &crev
, &data_offset
))
2338 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
2340 radeon_atombios_add_pplib_thermal_controller(rdev
, &power_info
->pplib
.sThermalController
);
2341 /* first mode is usually default, followed by low to high */
2342 for (i
= 0; i
< power_info
->pplib
.ucNumStates
; i
++) {
2344 power_state
= (union pplib_power_state
*)
2345 (mode_info
->atom_context
->bios
+ data_offset
+
2346 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
) +
2347 i
* power_info
->pplib
.ucStateEntrySize
);
2348 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2349 (mode_info
->atom_context
->bios
+ data_offset
+
2350 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
) +
2351 (power_state
->v1
.ucNonClockStateIndex
*
2352 power_info
->pplib
.ucNonClockSize
));
2353 for (j
= 0; j
< (power_info
->pplib
.ucStateEntrySize
- 1); j
++) {
2354 clock_info
= (union pplib_clock_info
*)
2355 (mode_info
->atom_context
->bios
+ data_offset
+
2356 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
) +
2357 (power_state
->v1
.ucClockStateIndices
[j
] *
2358 power_info
->pplib
.ucClockInfoSize
));
2359 valid
= radeon_atombios_parse_pplib_clock_info(rdev
,
2360 state_index
, mode_index
,
2365 rdev
->pm
.power_state
[state_index
].num_clock_modes
= mode_index
;
2367 radeon_atombios_parse_pplib_non_clock_info(rdev
, state_index
, mode_index
,
2372 /* if multiple clock modes, mark the lowest as no display */
2373 for (i
= 0; i
< state_index
; i
++) {
2374 if (rdev
->pm
.power_state
[i
].num_clock_modes
> 1)
2375 rdev
->pm
.power_state
[i
].clock_info
[0].flags
|=
2376 RADEON_PM_MODE_NO_DISPLAY
;
2378 /* first mode is usually default */
2379 if (rdev
->pm
.default_power_state_index
== -1) {
2380 rdev
->pm
.power_state
[0].type
=
2381 POWER_STATE_TYPE_DEFAULT
;
2382 rdev
->pm
.default_power_state_index
= 0;
2383 rdev
->pm
.power_state
[0].default_clock_mode
=
2384 &rdev
->pm
.power_state
[0].clock_info
[0];
2389 static int radeon_atombios_parse_power_table_6(struct radeon_device
*rdev
)
2391 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2392 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
2393 union pplib_power_state
*power_state
;
2394 int i
, j
, non_clock_array_index
, clock_array_index
;
2395 int state_index
= 0, mode_index
= 0;
2396 union pplib_clock_info
*clock_info
;
2397 struct StateArray
*state_array
;
2398 struct ClockInfoArray
*clock_info_array
;
2399 struct NonClockInfoArray
*non_clock_info_array
;
2401 union power_info
*power_info
;
2402 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2406 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2407 &frev
, &crev
, &data_offset
))
2409 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
2411 radeon_atombios_add_pplib_thermal_controller(rdev
, &power_info
->pplib
.sThermalController
);
2412 state_array
= (struct StateArray
*)
2413 (mode_info
->atom_context
->bios
+ data_offset
+
2414 power_info
->pplib
.usStateArrayOffset
);
2415 clock_info_array
= (struct ClockInfoArray
*)
2416 (mode_info
->atom_context
->bios
+ data_offset
+
2417 power_info
->pplib
.usClockInfoArrayOffset
);
2418 non_clock_info_array
= (struct NonClockInfoArray
*)
2419 (mode_info
->atom_context
->bios
+ data_offset
+
2420 power_info
->pplib
.usNonClockInfoArrayOffset
);
2421 for (i
= 0; i
< state_array
->ucNumEntries
; i
++) {
2423 power_state
= (union pplib_power_state
*)&state_array
->states
[i
];
2424 /* XXX this might be an inagua bug... */
2425 non_clock_array_index
= i
; /* power_state->v2.nonClockInfoIndex */
2426 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2427 &non_clock_info_array
->nonClockInfo
[non_clock_array_index
];
2428 for (j
= 0; j
< power_state
->v2
.ucNumDPMLevels
; j
++) {
2429 clock_array_index
= power_state
->v2
.clockInfoIndex
[j
];
2430 /* XXX this might be an inagua bug... */
2431 if (clock_array_index
>= clock_info_array
->ucNumEntries
)
2433 clock_info
= (union pplib_clock_info
*)
2434 &clock_info_array
->clockInfo
[clock_array_index
];
2435 valid
= radeon_atombios_parse_pplib_clock_info(rdev
,
2436 state_index
, mode_index
,
2441 rdev
->pm
.power_state
[state_index
].num_clock_modes
= mode_index
;
2443 radeon_atombios_parse_pplib_non_clock_info(rdev
, state_index
, mode_index
,
2448 /* if multiple clock modes, mark the lowest as no display */
2449 for (i
= 0; i
< state_index
; i
++) {
2450 if (rdev
->pm
.power_state
[i
].num_clock_modes
> 1)
2451 rdev
->pm
.power_state
[i
].clock_info
[0].flags
|=
2452 RADEON_PM_MODE_NO_DISPLAY
;
2454 /* first mode is usually default */
2455 if (rdev
->pm
.default_power_state_index
== -1) {
2456 rdev
->pm
.power_state
[0].type
=
2457 POWER_STATE_TYPE_DEFAULT
;
2458 rdev
->pm
.default_power_state_index
= 0;
2459 rdev
->pm
.power_state
[0].default_clock_mode
=
2460 &rdev
->pm
.power_state
[0].clock_info
[0];
2465 void radeon_atombios_get_power_modes(struct radeon_device
*rdev
)
2467 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2468 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2471 int state_index
= 0;
2473 rdev
->pm
.default_power_state_index
= -1;
2475 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2476 &frev
, &crev
, &data_offset
)) {
2481 state_index
= radeon_atombios_parse_power_table_1_3(rdev
);
2485 state_index
= radeon_atombios_parse_power_table_4_5(rdev
);
2488 state_index
= radeon_atombios_parse_power_table_6(rdev
);
2494 /* add the default mode */
2495 rdev
->pm
.power_state
[state_index
].type
=
2496 POWER_STATE_TYPE_DEFAULT
;
2497 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2498 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= rdev
->clock
.default_mclk
;
2499 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= rdev
->clock
.default_sclk
;
2500 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2501 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2502 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2503 rdev
->pm
.power_state
[state_index
].pcie_lanes
= 16;
2504 rdev
->pm
.default_power_state_index
= state_index
;
2505 rdev
->pm
.power_state
[state_index
].flags
= 0;
2509 rdev
->pm
.num_power_states
= state_index
;
2511 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
2512 rdev
->pm
.current_clock_mode_index
= 0;
2513 rdev
->pm
.current_vddc
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
2516 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
)
2518 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args
;
2519 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicClockGating
);
2521 args
.ucEnable
= enable
;
2523 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2526 uint32_t radeon_atom_get_engine_clock(struct radeon_device
*rdev
)
2528 GET_ENGINE_CLOCK_PS_ALLOCATION args
;
2529 int index
= GetIndexIntoMasterTable(COMMAND
, GetEngineClock
);
2531 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2532 return args
.ulReturnEngineClock
;
2535 uint32_t radeon_atom_get_memory_clock(struct radeon_device
*rdev
)
2537 GET_MEMORY_CLOCK_PS_ALLOCATION args
;
2538 int index
= GetIndexIntoMasterTable(COMMAND
, GetMemoryClock
);
2540 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2541 return args
.ulReturnMemoryClock
;
2544 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
,
2547 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
2548 int index
= GetIndexIntoMasterTable(COMMAND
, SetEngineClock
);
2550 args
.ulTargetEngineClock
= eng_clock
; /* 10 khz */
2552 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2555 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
,
2558 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
2559 int index
= GetIndexIntoMasterTable(COMMAND
, SetMemoryClock
);
2561 if (rdev
->flags
& RADEON_IS_IGP
)
2564 args
.ulTargetMemoryClock
= mem_clock
; /* 10 khz */
2566 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2570 struct _SET_VOLTAGE_PS_ALLOCATION alloc
;
2571 struct _SET_VOLTAGE_PARAMETERS v1
;
2572 struct _SET_VOLTAGE_PARAMETERS_V2 v2
;
2575 void radeon_atom_set_voltage(struct radeon_device
*rdev
, u16 level
)
2577 union set_voltage args
;
2578 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
2579 u8 frev
, crev
, volt_index
= level
;
2581 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2586 args
.v1
.ucVoltageType
= SET_VOLTAGE_TYPE_ASIC_VDDC
;
2587 args
.v1
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_ALL_SOURCE
;
2588 args
.v1
.ucVoltageIndex
= volt_index
;
2591 args
.v2
.ucVoltageType
= SET_VOLTAGE_TYPE_ASIC_VDDC
;
2592 args
.v2
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE
;
2593 args
.v2
.usVoltageLevel
= cpu_to_le16(level
);
2596 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
2600 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2605 void radeon_atom_initialize_bios_scratch_regs(struct drm_device
*dev
)
2607 struct radeon_device
*rdev
= dev
->dev_private
;
2608 uint32_t bios_2_scratch
, bios_6_scratch
;
2610 if (rdev
->family
>= CHIP_R600
) {
2611 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
2612 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
2614 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
2615 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2618 /* let the bios control the backlight */
2619 bios_2_scratch
&= ~ATOM_S2_VRI_BRIGHT_ENABLE
;
2621 /* tell the bios not to handle mode switching */
2622 bios_6_scratch
|= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
| ATOM_S6_ACC_MODE
);
2624 if (rdev
->family
>= CHIP_R600
) {
2625 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
2626 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2628 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
2629 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2634 void radeon_save_bios_scratch_regs(struct radeon_device
*rdev
)
2636 uint32_t scratch_reg
;
2639 if (rdev
->family
>= CHIP_R600
)
2640 scratch_reg
= R600_BIOS_0_SCRATCH
;
2642 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
2644 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
2645 rdev
->bios_scratch
[i
] = RREG32(scratch_reg
+ (i
* 4));
2648 void radeon_restore_bios_scratch_regs(struct radeon_device
*rdev
)
2650 uint32_t scratch_reg
;
2653 if (rdev
->family
>= CHIP_R600
)
2654 scratch_reg
= R600_BIOS_0_SCRATCH
;
2656 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
2658 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
2659 WREG32(scratch_reg
+ (i
* 4), rdev
->bios_scratch
[i
]);
2662 void radeon_atom_output_lock(struct drm_encoder
*encoder
, bool lock
)
2664 struct drm_device
*dev
= encoder
->dev
;
2665 struct radeon_device
*rdev
= dev
->dev_private
;
2666 uint32_t bios_6_scratch
;
2668 if (rdev
->family
>= CHIP_R600
)
2669 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
2671 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2674 bios_6_scratch
|= ATOM_S6_CRITICAL_STATE
;
2676 bios_6_scratch
&= ~ATOM_S6_CRITICAL_STATE
;
2678 if (rdev
->family
>= CHIP_R600
)
2679 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2681 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2684 /* at some point we may want to break this out into individual functions */
2686 radeon_atombios_connected_scratch_regs(struct drm_connector
*connector
,
2687 struct drm_encoder
*encoder
,
2690 struct drm_device
*dev
= connector
->dev
;
2691 struct radeon_device
*rdev
= dev
->dev_private
;
2692 struct radeon_connector
*radeon_connector
=
2693 to_radeon_connector(connector
);
2694 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2695 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
2697 if (rdev
->family
>= CHIP_R600
) {
2698 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2699 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
2700 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
2702 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
2703 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
2704 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2707 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
2708 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
2710 DRM_DEBUG_KMS("TV1 connected\n");
2711 bios_3_scratch
|= ATOM_S3_TV1_ACTIVE
;
2712 bios_6_scratch
|= ATOM_S6_ACC_REQ_TV1
;
2714 DRM_DEBUG_KMS("TV1 disconnected\n");
2715 bios_0_scratch
&= ~ATOM_S0_TV1_MASK
;
2716 bios_3_scratch
&= ~ATOM_S3_TV1_ACTIVE
;
2717 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_TV1
;
2720 if ((radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) &&
2721 (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
)) {
2723 DRM_DEBUG_KMS("CV connected\n");
2724 bios_3_scratch
|= ATOM_S3_CV_ACTIVE
;
2725 bios_6_scratch
|= ATOM_S6_ACC_REQ_CV
;
2727 DRM_DEBUG_KMS("CV disconnected\n");
2728 bios_0_scratch
&= ~ATOM_S0_CV_MASK
;
2729 bios_3_scratch
&= ~ATOM_S3_CV_ACTIVE
;
2730 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CV
;
2733 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
2734 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
2736 DRM_DEBUG_KMS("LCD1 connected\n");
2737 bios_0_scratch
|= ATOM_S0_LCD1
;
2738 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
2739 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
2741 DRM_DEBUG_KMS("LCD1 disconnected\n");
2742 bios_0_scratch
&= ~ATOM_S0_LCD1
;
2743 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
2744 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
2747 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
2748 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
2750 DRM_DEBUG_KMS("CRT1 connected\n");
2751 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
2752 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
2753 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
2755 DRM_DEBUG_KMS("CRT1 disconnected\n");
2756 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
2757 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
2758 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
2761 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
2762 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
2764 DRM_DEBUG_KMS("CRT2 connected\n");
2765 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
2766 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
2767 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
2769 DRM_DEBUG_KMS("CRT2 disconnected\n");
2770 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
2771 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
2772 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
2775 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
2776 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
2778 DRM_DEBUG_KMS("DFP1 connected\n");
2779 bios_0_scratch
|= ATOM_S0_DFP1
;
2780 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
2781 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
2783 DRM_DEBUG_KMS("DFP1 disconnected\n");
2784 bios_0_scratch
&= ~ATOM_S0_DFP1
;
2785 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
2786 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
2789 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
2790 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
2792 DRM_DEBUG_KMS("DFP2 connected\n");
2793 bios_0_scratch
|= ATOM_S0_DFP2
;
2794 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
2795 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
2797 DRM_DEBUG_KMS("DFP2 disconnected\n");
2798 bios_0_scratch
&= ~ATOM_S0_DFP2
;
2799 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
2800 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
2803 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
2804 (radeon_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
2806 DRM_DEBUG_KMS("DFP3 connected\n");
2807 bios_0_scratch
|= ATOM_S0_DFP3
;
2808 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
2809 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
2811 DRM_DEBUG_KMS("DFP3 disconnected\n");
2812 bios_0_scratch
&= ~ATOM_S0_DFP3
;
2813 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
2814 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
2817 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
2818 (radeon_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
2820 DRM_DEBUG_KMS("DFP4 connected\n");
2821 bios_0_scratch
|= ATOM_S0_DFP4
;
2822 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
2823 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
2825 DRM_DEBUG_KMS("DFP4 disconnected\n");
2826 bios_0_scratch
&= ~ATOM_S0_DFP4
;
2827 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
2828 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
2831 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
2832 (radeon_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
2834 DRM_DEBUG_KMS("DFP5 connected\n");
2835 bios_0_scratch
|= ATOM_S0_DFP5
;
2836 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
2837 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
2839 DRM_DEBUG_KMS("DFP5 disconnected\n");
2840 bios_0_scratch
&= ~ATOM_S0_DFP5
;
2841 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
2842 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
2846 if (rdev
->family
>= CHIP_R600
) {
2847 WREG32(R600_BIOS_0_SCRATCH
, bios_0_scratch
);
2848 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
2849 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2851 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
2852 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
2853 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2858 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
2860 struct drm_device
*dev
= encoder
->dev
;
2861 struct radeon_device
*rdev
= dev
->dev_private
;
2862 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2863 uint32_t bios_3_scratch
;
2865 if (rdev
->family
>= CHIP_R600
)
2866 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
2868 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
2870 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2871 bios_3_scratch
&= ~ATOM_S3_TV1_CRTC_ACTIVE
;
2872 bios_3_scratch
|= (crtc
<< 18);
2874 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2875 bios_3_scratch
&= ~ATOM_S3_CV_CRTC_ACTIVE
;
2876 bios_3_scratch
|= (crtc
<< 24);
2878 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2879 bios_3_scratch
&= ~ATOM_S3_CRT1_CRTC_ACTIVE
;
2880 bios_3_scratch
|= (crtc
<< 16);
2882 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2883 bios_3_scratch
&= ~ATOM_S3_CRT2_CRTC_ACTIVE
;
2884 bios_3_scratch
|= (crtc
<< 20);
2886 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
2887 bios_3_scratch
&= ~ATOM_S3_LCD1_CRTC_ACTIVE
;
2888 bios_3_scratch
|= (crtc
<< 17);
2890 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
2891 bios_3_scratch
&= ~ATOM_S3_DFP1_CRTC_ACTIVE
;
2892 bios_3_scratch
|= (crtc
<< 19);
2894 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
2895 bios_3_scratch
&= ~ATOM_S3_DFP2_CRTC_ACTIVE
;
2896 bios_3_scratch
|= (crtc
<< 23);
2898 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
2899 bios_3_scratch
&= ~ATOM_S3_DFP3_CRTC_ACTIVE
;
2900 bios_3_scratch
|= (crtc
<< 25);
2903 if (rdev
->family
>= CHIP_R600
)
2904 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
2906 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
2910 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
2912 struct drm_device
*dev
= encoder
->dev
;
2913 struct radeon_device
*rdev
= dev
->dev_private
;
2914 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2915 uint32_t bios_2_scratch
;
2917 if (rdev
->family
>= CHIP_R600
)
2918 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
2920 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
2922 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2924 bios_2_scratch
&= ~ATOM_S2_TV1_DPMS_STATE
;
2926 bios_2_scratch
|= ATOM_S2_TV1_DPMS_STATE
;
2928 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2930 bios_2_scratch
&= ~ATOM_S2_CV_DPMS_STATE
;
2932 bios_2_scratch
|= ATOM_S2_CV_DPMS_STATE
;
2934 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2936 bios_2_scratch
&= ~ATOM_S2_CRT1_DPMS_STATE
;
2938 bios_2_scratch
|= ATOM_S2_CRT1_DPMS_STATE
;
2940 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2942 bios_2_scratch
&= ~ATOM_S2_CRT2_DPMS_STATE
;
2944 bios_2_scratch
|= ATOM_S2_CRT2_DPMS_STATE
;
2946 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
2948 bios_2_scratch
&= ~ATOM_S2_LCD1_DPMS_STATE
;
2950 bios_2_scratch
|= ATOM_S2_LCD1_DPMS_STATE
;
2952 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
2954 bios_2_scratch
&= ~ATOM_S2_DFP1_DPMS_STATE
;
2956 bios_2_scratch
|= ATOM_S2_DFP1_DPMS_STATE
;
2958 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
2960 bios_2_scratch
&= ~ATOM_S2_DFP2_DPMS_STATE
;
2962 bios_2_scratch
|= ATOM_S2_DFP2_DPMS_STATE
;
2964 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
2966 bios_2_scratch
&= ~ATOM_S2_DFP3_DPMS_STATE
;
2968 bios_2_scratch
|= ATOM_S2_DFP3_DPMS_STATE
;
2970 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) {
2972 bios_2_scratch
&= ~ATOM_S2_DFP4_DPMS_STATE
;
2974 bios_2_scratch
|= ATOM_S2_DFP4_DPMS_STATE
;
2976 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) {
2978 bios_2_scratch
&= ~ATOM_S2_DFP5_DPMS_STATE
;
2980 bios_2_scratch
|= ATOM_S2_DFP5_DPMS_STATE
;
2983 if (rdev
->family
>= CHIP_R600
)
2984 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
2986 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);