2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_id(struct drm_device
*dev
, uint32_t supported_device
,
37 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
39 radeon_add_atom_encoder(struct drm_device
*dev
, uint32_t encoder_id
,
40 uint32_t supported_device
);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device
*dev
,
45 uint32_t connector_id
,
46 uint32_t supported_device
,
48 struct radeon_i2c_bus_rec
*i2c_bus
,
49 bool linkb
, uint32_t igp_lane_info
,
50 uint16_t connector_object_id
);
52 /* from radeon_legacy_encoder.c */
54 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_id
,
55 uint32_t supported_device
);
57 union atom_supported_devices
{
58 struct _ATOM_SUPPORTED_DEVICES_INFO info
;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2
;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1
;
63 static inline struct radeon_i2c_bus_rec
radeon_lookup_gpio(struct drm_device
66 struct radeon_device
*rdev
= dev
->dev_private
;
67 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
68 ATOM_GPIO_I2C_ASSIGMENT gpio
;
69 struct radeon_i2c_bus_rec i2c
;
70 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
71 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
74 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
77 atom_parse_data_header(ctx
, index
, NULL
, NULL
, NULL
, &data_offset
);
79 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
81 gpio
= i2c_info
->asGPIO_Info
[id
];
83 i2c
.mask_clk_reg
= le16_to_cpu(gpio
.usClkMaskRegisterIndex
) * 4;
84 i2c
.mask_data_reg
= le16_to_cpu(gpio
.usDataMaskRegisterIndex
) * 4;
85 i2c
.en_clk_reg
= le16_to_cpu(gpio
.usClkEnRegisterIndex
) * 4;
86 i2c
.en_data_reg
= le16_to_cpu(gpio
.usDataEnRegisterIndex
) * 4;
87 i2c
.y_clk_reg
= le16_to_cpu(gpio
.usClkY_RegisterIndex
) * 4;
88 i2c
.y_data_reg
= le16_to_cpu(gpio
.usDataY_RegisterIndex
) * 4;
89 i2c
.a_clk_reg
= le16_to_cpu(gpio
.usClkA_RegisterIndex
) * 4;
90 i2c
.a_data_reg
= le16_to_cpu(gpio
.usDataA_RegisterIndex
) * 4;
91 i2c
.mask_clk_mask
= (1 << gpio
.ucClkMaskShift
);
92 i2c
.mask_data_mask
= (1 << gpio
.ucDataMaskShift
);
93 i2c
.en_clk_mask
= (1 << gpio
.ucClkEnShift
);
94 i2c
.en_data_mask
= (1 << gpio
.ucDataEnShift
);
95 i2c
.y_clk_mask
= (1 << gpio
.ucClkY_Shift
);
96 i2c
.y_data_mask
= (1 << gpio
.ucDataY_Shift
);
97 i2c
.a_clk_mask
= (1 << gpio
.ucClkA_Shift
);
98 i2c
.a_data_mask
= (1 << gpio
.ucDataA_Shift
);
104 static bool radeon_atom_apply_quirks(struct drm_device
*dev
,
105 uint32_t supported_device
,
107 struct radeon_i2c_bus_rec
*i2c_bus
,
111 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
112 if ((dev
->pdev
->device
== 0x791e) &&
113 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
114 (dev
->pdev
->subsystem_device
== 0x826d)) {
115 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
116 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
117 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
120 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
121 if ((dev
->pdev
->device
== 0x7941) &&
122 (dev
->pdev
->subsystem_vendor
== 0x147b) &&
123 (dev
->pdev
->subsystem_device
== 0x2412)) {
124 if (*connector_type
== DRM_MODE_CONNECTOR_DVII
)
128 /* Falcon NW laptop lists vga ddc line for LVDS */
129 if ((dev
->pdev
->device
== 0x5653) &&
130 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
131 (dev
->pdev
->subsystem_device
== 0x0291)) {
132 if (*connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
133 i2c_bus
->valid
= false;
139 if ((dev
->pdev
->device
== 0x71C5) &&
140 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
141 (dev
->pdev
->subsystem_device
== 0x0080)) {
142 if ((supported_device
== ATOM_DEVICE_CRT1_SUPPORT
) ||
143 (supported_device
== ATOM_DEVICE_DFP2_SUPPORT
))
147 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
148 if ((dev
->pdev
->device
== 0x9598) &&
149 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
150 (dev
->pdev
->subsystem_device
== 0x01da)) {
151 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
152 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
156 /* ASUS HD 3450 board lists the DVI port as HDMI */
157 if ((dev
->pdev
->device
== 0x95C5) &&
158 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
159 (dev
->pdev
->subsystem_device
== 0x01e2)) {
160 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
161 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
165 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
166 * HDMI + VGA reporting as HDMI
168 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
169 if (supported_device
& (ATOM_DEVICE_CRT_SUPPORT
)) {
170 *connector_type
= DRM_MODE_CONNECTOR_VGA
;
175 /* Acer laptop reports DVI-D as DVI-I */
176 if ((dev
->pdev
->device
== 0x95c4) &&
177 (dev
->pdev
->subsystem_vendor
== 0x1025) &&
178 (dev
->pdev
->subsystem_device
== 0x013c)) {
179 if ((*connector_type
== DRM_MODE_CONNECTOR_DVII
) &&
180 (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
))
181 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
187 const int supported_devices_connector_convert
[] = {
188 DRM_MODE_CONNECTOR_Unknown
,
189 DRM_MODE_CONNECTOR_VGA
,
190 DRM_MODE_CONNECTOR_DVII
,
191 DRM_MODE_CONNECTOR_DVID
,
192 DRM_MODE_CONNECTOR_DVIA
,
193 DRM_MODE_CONNECTOR_SVIDEO
,
194 DRM_MODE_CONNECTOR_Composite
,
195 DRM_MODE_CONNECTOR_LVDS
,
196 DRM_MODE_CONNECTOR_Unknown
,
197 DRM_MODE_CONNECTOR_Unknown
,
198 DRM_MODE_CONNECTOR_HDMIA
,
199 DRM_MODE_CONNECTOR_HDMIB
,
200 DRM_MODE_CONNECTOR_Unknown
,
201 DRM_MODE_CONNECTOR_Unknown
,
202 DRM_MODE_CONNECTOR_9PinDIN
,
203 DRM_MODE_CONNECTOR_DisplayPort
206 const uint16_t supported_devices_connector_object_id_convert
[] = {
207 CONNECTOR_OBJECT_ID_NONE
,
208 CONNECTOR_OBJECT_ID_VGA
,
209 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
, /* not all boards support DL */
210 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
, /* not all boards support DL */
211 CONNECTOR_OBJECT_ID_VGA
, /* technically DVI-A */
212 CONNECTOR_OBJECT_ID_COMPOSITE
,
213 CONNECTOR_OBJECT_ID_SVIDEO
,
214 CONNECTOR_OBJECT_ID_LVDS
,
215 CONNECTOR_OBJECT_ID_9PIN_DIN
,
216 CONNECTOR_OBJECT_ID_9PIN_DIN
,
217 CONNECTOR_OBJECT_ID_DISPLAYPORT
,
218 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
,
219 CONNECTOR_OBJECT_ID_HDMI_TYPE_B
,
220 CONNECTOR_OBJECT_ID_SVIDEO
223 const int object_connector_convert
[] = {
224 DRM_MODE_CONNECTOR_Unknown
,
225 DRM_MODE_CONNECTOR_DVII
,
226 DRM_MODE_CONNECTOR_DVII
,
227 DRM_MODE_CONNECTOR_DVID
,
228 DRM_MODE_CONNECTOR_DVID
,
229 DRM_MODE_CONNECTOR_VGA
,
230 DRM_MODE_CONNECTOR_Composite
,
231 DRM_MODE_CONNECTOR_SVIDEO
,
232 DRM_MODE_CONNECTOR_Unknown
,
233 DRM_MODE_CONNECTOR_Unknown
,
234 DRM_MODE_CONNECTOR_9PinDIN
,
235 DRM_MODE_CONNECTOR_Unknown
,
236 DRM_MODE_CONNECTOR_HDMIA
,
237 DRM_MODE_CONNECTOR_HDMIB
,
238 DRM_MODE_CONNECTOR_LVDS
,
239 DRM_MODE_CONNECTOR_9PinDIN
,
240 DRM_MODE_CONNECTOR_Unknown
,
241 DRM_MODE_CONNECTOR_Unknown
,
242 DRM_MODE_CONNECTOR_Unknown
,
243 DRM_MODE_CONNECTOR_DisplayPort
246 bool radeon_get_atom_connector_info_from_object_table(struct drm_device
*dev
)
248 struct radeon_device
*rdev
= dev
->dev_private
;
249 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
250 struct atom_context
*ctx
= mode_info
->atom_context
;
251 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
252 uint16_t size
, data_offset
;
253 uint8_t frev
, crev
, line_mux
= 0;
254 ATOM_CONNECTOR_OBJECT_TABLE
*con_obj
;
255 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
256 ATOM_OBJECT_HEADER
*obj_header
;
257 int i
, j
, path_size
, device_support
;
259 uint16_t igp_lane_info
, conn_id
, connector_object_id
;
261 struct radeon_i2c_bus_rec ddc_bus
;
263 atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
);
265 if (data_offset
== 0)
271 obj_header
= (ATOM_OBJECT_HEADER
*) (ctx
->bios
+ data_offset
);
272 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
273 (ctx
->bios
+ data_offset
+
274 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
275 con_obj
= (ATOM_CONNECTOR_OBJECT_TABLE
*)
276 (ctx
->bios
+ data_offset
+
277 le16_to_cpu(obj_header
->usConnectorObjectTableOffset
));
278 device_support
= le16_to_cpu(obj_header
->usDeviceSupport
);
281 for (i
= 0; i
< path_obj
->ucNumOfDispPath
; i
++) {
282 uint8_t *addr
= (uint8_t *) path_obj
->asDispPath
;
283 ATOM_DISPLAY_OBJECT_PATH
*path
;
285 path
= (ATOM_DISPLAY_OBJECT_PATH
*) addr
;
286 path_size
+= le16_to_cpu(path
->usSize
);
289 if (device_support
& le16_to_cpu(path
->usDeviceTag
)) {
290 uint8_t con_obj_id
, con_obj_num
, con_obj_type
;
293 (le16_to_cpu(path
->usConnObjectId
) & OBJECT_ID_MASK
)
296 (le16_to_cpu(path
->usConnObjectId
) & ENUM_ID_MASK
)
299 (le16_to_cpu(path
->usConnObjectId
) &
300 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
302 /* TODO CV support */
303 if (le16_to_cpu(path
->usDeviceTag
) ==
304 ATOM_DEVICE_CV_SUPPORT
)
308 if ((rdev
->flags
& RADEON_IS_IGP
) &&
310 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR
)) {
311 uint16_t igp_offset
= 0;
312 ATOM_INTEGRATED_SYSTEM_INFO_V2
*igp_obj
;
315 GetIndexIntoMasterTable(DATA
,
316 IntegratedSystemInfo
);
318 atom_parse_data_header(ctx
, index
, &size
, &frev
,
323 (ATOM_INTEGRATED_SYSTEM_INFO_V2
324 *) (ctx
->bios
+ igp_offset
);
327 uint32_t slot_config
, ct
;
329 if (con_obj_num
== 1)
338 ct
= (slot_config
>> 16) & 0xff;
340 object_connector_convert
342 connector_object_id
= ct
;
344 slot_config
& 0xffff;
352 object_connector_convert
[con_obj_id
];
353 connector_object_id
= con_obj_id
;
356 if (connector_type
== DRM_MODE_CONNECTOR_Unknown
)
359 for (j
= 0; j
< ((le16_to_cpu(path
->usSize
) - 8) / 2);
361 uint8_t enc_obj_id
, enc_obj_num
, enc_obj_type
;
364 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
365 OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
367 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
368 ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
370 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
371 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
373 /* FIXME: add support for router objects */
374 if (enc_obj_type
== GRAPH_OBJECT_TYPE_ENCODER
) {
375 if (enc_obj_num
== 2)
380 radeon_add_atom_encoder(dev
,
389 /* look up gpio for ddc */
390 if ((le16_to_cpu(path
->usDeviceTag
) &
391 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
393 for (j
= 0; j
< con_obj
->ucNumberOfObjects
; j
++) {
394 if (le16_to_cpu(path
->usConnObjectId
) ==
395 le16_to_cpu(con_obj
->asObjects
[j
].
397 ATOM_COMMON_RECORD_HEADER
399 (ATOM_COMMON_RECORD_HEADER
401 (ctx
->bios
+ data_offset
+
402 le16_to_cpu(con_obj
->
405 ATOM_I2C_RECORD
*i2c_record
;
407 while (record
->ucRecordType
> 0
410 ATOM_MAX_OBJECT_RECORD_NUMBER
) {
413 case ATOM_I2C_RECORD_TYPE
:
424 (ATOM_COMMON_RECORD_HEADER
436 if ((le16_to_cpu(path
->usDeviceTag
) ==
437 ATOM_DEVICE_TV1_SUPPORT
)
438 || (le16_to_cpu(path
->usDeviceTag
) ==
439 ATOM_DEVICE_TV2_SUPPORT
)
440 || (le16_to_cpu(path
->usDeviceTag
) ==
441 ATOM_DEVICE_CV_SUPPORT
))
442 ddc_bus
.valid
= false;
444 ddc_bus
= radeon_lookup_gpio(dev
, line_mux
);
446 conn_id
= le16_to_cpu(path
->usConnObjectId
);
448 if (!radeon_atom_apply_quirks
449 (dev
, le16_to_cpu(path
->usDeviceTag
), &connector_type
,
453 radeon_add_atom_connector(dev
,
457 connector_type
, &ddc_bus
,
458 linkb
, igp_lane_info
,
459 connector_object_id
);
464 radeon_link_encoder_connector(dev
);
469 static uint16_t atombios_get_connector_object_id(struct drm_device
*dev
,
473 struct radeon_device
*rdev
= dev
->dev_private
;
475 if (rdev
->flags
& RADEON_IS_IGP
) {
476 return supported_devices_connector_object_id_convert
478 } else if (((connector_type
== DRM_MODE_CONNECTOR_DVII
) ||
479 (connector_type
== DRM_MODE_CONNECTOR_DVID
)) &&
480 (devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
481 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
482 struct atom_context
*ctx
= mode_info
->atom_context
;
483 int index
= GetIndexIntoMasterTable(DATA
, XTMDS_Info
);
484 uint16_t size
, data_offset
;
486 ATOM_XTMDS_INFO
*xtmds
;
488 atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
);
489 xtmds
= (ATOM_XTMDS_INFO
*)(ctx
->bios
+ data_offset
);
491 if (xtmds
->ucSupportedLink
& ATOM_XTMDS_SUPPORTED_DUALLINK
) {
492 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
493 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
495 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
497 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
498 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
500 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
503 return supported_devices_connector_object_id_convert
508 struct bios_connector
{
513 struct radeon_i2c_bus_rec ddc_bus
;
516 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
520 struct radeon_device
*rdev
= dev
->dev_private
;
521 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
522 struct atom_context
*ctx
= mode_info
->atom_context
;
523 int index
= GetIndexIntoMasterTable(DATA
, SupportedDevicesInfo
);
524 uint16_t size
, data_offset
;
526 uint16_t device_support
;
528 union atom_supported_devices
*supported_devices
;
530 struct bios_connector bios_connectors
[ATOM_MAX_SUPPORTED_DEVICE
];
532 atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
);
535 (union atom_supported_devices
*)(ctx
->bios
+ data_offset
);
537 device_support
= le16_to_cpu(supported_devices
->info
.usDeviceSupport
);
539 for (i
= 0; i
< ATOM_MAX_SUPPORTED_DEVICE
; i
++) {
540 ATOM_CONNECTOR_INFO_I2C ci
=
541 supported_devices
->info
.asConnInfo
[i
];
543 bios_connectors
[i
].valid
= false;
545 if (!(device_support
& (1 << i
))) {
549 if (i
== ATOM_DEVICE_CV_INDEX
) {
550 DRM_DEBUG("Skipping Component Video\n");
554 bios_connectors
[i
].connector_type
=
555 supported_devices_connector_convert
[ci
.sucConnectorInfo
.
559 if (bios_connectors
[i
].connector_type
==
560 DRM_MODE_CONNECTOR_Unknown
)
563 dac
= ci
.sucConnectorInfo
.sbfAccess
.bfAssociatedDAC
;
565 if ((rdev
->family
== CHIP_RS690
) ||
566 (rdev
->family
== CHIP_RS740
)) {
567 if ((i
== ATOM_DEVICE_DFP2_INDEX
)
568 && (ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
== 2))
569 bios_connectors
[i
].line_mux
=
570 ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
+ 1;
571 else if ((i
== ATOM_DEVICE_DFP3_INDEX
)
572 && (ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
== 1))
573 bios_connectors
[i
].line_mux
=
574 ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
+ 1;
576 bios_connectors
[i
].line_mux
=
577 ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
;
579 bios_connectors
[i
].line_mux
=
580 ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
;
582 /* give tv unique connector ids */
583 if (i
== ATOM_DEVICE_TV1_INDEX
) {
584 bios_connectors
[i
].ddc_bus
.valid
= false;
585 bios_connectors
[i
].line_mux
= 50;
586 } else if (i
== ATOM_DEVICE_TV2_INDEX
) {
587 bios_connectors
[i
].ddc_bus
.valid
= false;
588 bios_connectors
[i
].line_mux
= 51;
589 } else if (i
== ATOM_DEVICE_CV_INDEX
) {
590 bios_connectors
[i
].ddc_bus
.valid
= false;
591 bios_connectors
[i
].line_mux
= 52;
593 bios_connectors
[i
].ddc_bus
=
594 radeon_lookup_gpio(dev
,
595 bios_connectors
[i
].line_mux
);
597 /* Always set the connector type to VGA for CRT1/CRT2. if they are
598 * shared with a DVI port, we'll pick up the DVI connector when we
599 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
601 if (i
== ATOM_DEVICE_CRT1_INDEX
|| i
== ATOM_DEVICE_CRT2_INDEX
)
602 bios_connectors
[i
].connector_type
=
603 DRM_MODE_CONNECTOR_VGA
;
605 if (!radeon_atom_apply_quirks
606 (dev
, (1 << i
), &bios_connectors
[i
].connector_type
,
607 &bios_connectors
[i
].ddc_bus
, &bios_connectors
[i
].line_mux
))
610 bios_connectors
[i
].valid
= true;
611 bios_connectors
[i
].devices
= (1 << i
);
613 if (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
)
614 radeon_add_atom_encoder(dev
,
615 radeon_get_encoder_id(dev
,
620 radeon_add_legacy_encoder(dev
,
621 radeon_get_encoder_id(dev
,
628 /* combine shared connectors */
629 for (i
= 0; i
< ATOM_MAX_SUPPORTED_DEVICE
; i
++) {
630 if (bios_connectors
[i
].valid
) {
631 for (j
= 0; j
< ATOM_MAX_SUPPORTED_DEVICE
; j
++) {
632 if (bios_connectors
[j
].valid
&& (i
!= j
)) {
633 if (bios_connectors
[i
].line_mux
==
634 bios_connectors
[j
].line_mux
) {
635 if (((bios_connectors
[i
].
637 (ATOM_DEVICE_DFP_SUPPORT
))
638 && (bios_connectors
[j
].
640 (ATOM_DEVICE_CRT_SUPPORT
)))
642 ((bios_connectors
[j
].
644 (ATOM_DEVICE_DFP_SUPPORT
))
645 && (bios_connectors
[i
].
647 (ATOM_DEVICE_CRT_SUPPORT
)))) {
654 DRM_MODE_CONNECTOR_DVII
;
664 /* add the connectors */
665 for (i
= 0; i
< ATOM_MAX_SUPPORTED_DEVICE
; i
++) {
666 if (bios_connectors
[i
].valid
) {
667 uint16_t connector_object_id
=
668 atombios_get_connector_object_id(dev
,
669 bios_connectors
[i
].connector_type
,
670 bios_connectors
[i
].devices
);
671 radeon_add_atom_connector(dev
,
672 bios_connectors
[i
].line_mux
,
673 bios_connectors
[i
].devices
,
676 &bios_connectors
[i
].ddc_bus
,
678 connector_object_id
);
682 radeon_link_encoder_connector(dev
);
687 union firmware_info
{
688 ATOM_FIRMWARE_INFO info
;
689 ATOM_FIRMWARE_INFO_V1_2 info_12
;
690 ATOM_FIRMWARE_INFO_V1_3 info_13
;
691 ATOM_FIRMWARE_INFO_V1_4 info_14
;
694 bool radeon_atom_get_clock_info(struct drm_device
*dev
)
696 struct radeon_device
*rdev
= dev
->dev_private
;
697 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
698 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
699 union firmware_info
*firmware_info
;
701 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
702 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
703 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
704 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
705 uint16_t data_offset
;
707 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
708 &crev
, &data_offset
);
711 (union firmware_info
*)(mode_info
->atom_context
->bios
+
716 p1pll
->reference_freq
=
717 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
718 p1pll
->reference_div
= 0;
722 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Output
);
725 le32_to_cpu(firmware_info
->info_12
.ulMinPixelClockPLL_Output
);
727 le32_to_cpu(firmware_info
->info
.ulMaxPixelClockPLL_Output
);
729 if (p1pll
->pll_out_min
== 0) {
730 if (ASIC_IS_AVIVO(rdev
))
731 p1pll
->pll_out_min
= 64800;
733 p1pll
->pll_out_min
= 20000;
734 } else if (p1pll
->pll_out_min
> 64800) {
735 /* Limiting the pll output range is a good thing generally as
736 * it limits the number of possible pll combinations for a given
737 * frequency presumably to the ones that work best on each card.
738 * However, certain duallink DVI monitors seem to like
739 * pll combinations that would be limited by this at least on
740 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
743 p1pll
->pll_out_min
= 64800;
747 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Input
);
749 le16_to_cpu(firmware_info
->info
.usMaxPixelClockPLL_Input
);
754 spll
->reference_freq
=
755 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
756 spll
->reference_div
= 0;
759 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Output
);
761 le32_to_cpu(firmware_info
->info
.ulMaxEngineClockPLL_Output
);
764 if (spll
->pll_out_min
== 0) {
765 if (ASIC_IS_AVIVO(rdev
))
766 spll
->pll_out_min
= 64800;
768 spll
->pll_out_min
= 20000;
772 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Input
);
774 le16_to_cpu(firmware_info
->info
.usMaxEngineClockPLL_Input
);
777 mpll
->reference_freq
=
778 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
779 mpll
->reference_div
= 0;
782 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Output
);
784 le32_to_cpu(firmware_info
->info
.ulMaxMemoryClockPLL_Output
);
787 if (mpll
->pll_out_min
== 0) {
788 if (ASIC_IS_AVIVO(rdev
))
789 mpll
->pll_out_min
= 64800;
791 mpll
->pll_out_min
= 20000;
795 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Input
);
797 le16_to_cpu(firmware_info
->info
.usMaxMemoryClockPLL_Input
);
799 rdev
->clock
.default_sclk
=
800 le32_to_cpu(firmware_info
->info
.ulDefaultEngineClock
);
801 rdev
->clock
.default_mclk
=
802 le32_to_cpu(firmware_info
->info
.ulDefaultMemoryClock
);
809 bool radeon_atombios_get_tmds_info(struct radeon_encoder
*encoder
,
810 struct radeon_encoder_int_tmds
*tmds
)
812 struct drm_device
*dev
= encoder
->base
.dev
;
813 struct radeon_device
*rdev
= dev
->dev_private
;
814 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
815 int index
= GetIndexIntoMasterTable(DATA
, TMDS_Info
);
816 uint16_t data_offset
;
817 struct _ATOM_TMDS_INFO
*tmds_info
;
822 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
823 &crev
, &data_offset
);
826 (struct _ATOM_TMDS_INFO
*)(mode_info
->atom_context
->bios
+
830 maxfreq
= le16_to_cpu(tmds_info
->usMaxFrequency
);
831 for (i
= 0; i
< 4; i
++) {
832 tmds
->tmds_pll
[i
].freq
=
833 le16_to_cpu(tmds_info
->asMiscInfo
[i
].usFrequency
);
834 tmds
->tmds_pll
[i
].value
=
835 tmds_info
->asMiscInfo
[i
].ucPLL_ChargePump
& 0x3f;
836 tmds
->tmds_pll
[i
].value
|=
837 (tmds_info
->asMiscInfo
[i
].
838 ucPLL_VCO_Gain
& 0x3f) << 6;
839 tmds
->tmds_pll
[i
].value
|=
840 (tmds_info
->asMiscInfo
[i
].
841 ucPLL_DutyCycle
& 0xf) << 12;
842 tmds
->tmds_pll
[i
].value
|=
843 (tmds_info
->asMiscInfo
[i
].
844 ucPLL_VoltageSwing
& 0xf) << 16;
846 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
847 tmds
->tmds_pll
[i
].freq
,
848 tmds
->tmds_pll
[i
].value
);
850 if (maxfreq
== tmds
->tmds_pll
[i
].freq
) {
851 tmds
->tmds_pll
[i
].freq
= 0xffffffff;
860 static struct radeon_atom_ss
*radeon_atombios_get_ss_info(struct
865 struct drm_device
*dev
= encoder
->base
.dev
;
866 struct radeon_device
*rdev
= dev
->dev_private
;
867 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
868 int index
= GetIndexIntoMasterTable(DATA
, PPLL_SS_Info
);
869 uint16_t data_offset
;
870 struct _ATOM_SPREAD_SPECTRUM_INFO
*ss_info
;
872 struct radeon_atom_ss
*ss
= NULL
;
874 if (id
> ATOM_MAX_SS_ENTRY
)
877 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
878 &crev
, &data_offset
);
881 (struct _ATOM_SPREAD_SPECTRUM_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
885 kzalloc(sizeof(struct radeon_atom_ss
), GFP_KERNEL
);
890 ss
->percentage
= le16_to_cpu(ss_info
->asSS_Info
[id
].usSpreadSpectrumPercentage
);
891 ss
->type
= ss_info
->asSS_Info
[id
].ucSpreadSpectrumType
;
892 ss
->step
= ss_info
->asSS_Info
[id
].ucSS_Step
;
893 ss
->delay
= ss_info
->asSS_Info
[id
].ucSS_Delay
;
894 ss
->range
= ss_info
->asSS_Info
[id
].ucSS_Range
;
895 ss
->refdiv
= ss_info
->asSS_Info
[id
].ucRecommendedRef_Div
;
901 struct _ATOM_LVDS_INFO info
;
902 struct _ATOM_LVDS_INFO_V12 info_12
;
905 struct radeon_encoder_atom_dig
*radeon_atombios_get_lvds_info(struct
909 struct drm_device
*dev
= encoder
->base
.dev
;
910 struct radeon_device
*rdev
= dev
->dev_private
;
911 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
912 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
913 uint16_t data_offset
;
914 union lvds_info
*lvds_info
;
916 struct radeon_encoder_atom_dig
*lvds
= NULL
;
918 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
919 &crev
, &data_offset
);
922 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
926 kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
931 lvds
->native_mode
.clock
=
932 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
933 lvds
->native_mode
.hdisplay
=
934 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
935 lvds
->native_mode
.vdisplay
=
936 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
937 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
938 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
939 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
940 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
941 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
942 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
943 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
944 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
945 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
946 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
947 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
948 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
949 lvds
->panel_pwr_delay
=
950 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
951 lvds
->lvds_misc
= lvds_info
->info
.ucLVDS_Misc
;
952 /* set crtc values */
953 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
955 lvds
->ss
= radeon_atombios_get_ss_info(encoder
, lvds_info
->info
.ucSS_Id
);
957 encoder
->native_mode
= lvds
->native_mode
;
962 struct radeon_encoder_primary_dac
*
963 radeon_atombios_get_primary_dac_info(struct radeon_encoder
*encoder
)
965 struct drm_device
*dev
= encoder
->base
.dev
;
966 struct radeon_device
*rdev
= dev
->dev_private
;
967 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
968 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
969 uint16_t data_offset
;
970 struct _COMPASSIONATE_DATA
*dac_info
;
973 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
975 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
, &crev
, &data_offset
);
977 dac_info
= (struct _COMPASSIONATE_DATA
*)(mode_info
->atom_context
->bios
+ data_offset
);
980 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
), GFP_KERNEL
);
985 bg
= dac_info
->ucDAC1_BG_Adjustment
;
986 dac
= dac_info
->ucDAC1_DAC_Adjustment
;
987 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
993 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
994 struct drm_display_mode
*mode
)
996 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
997 ATOM_ANALOG_TV_INFO
*tv_info
;
998 ATOM_ANALOG_TV_INFO_V1_2
*tv_info_v1_2
;
999 ATOM_DTD_FORMAT
*dtd_timings
;
1000 int data_index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1002 u16 data_offset
, misc
;
1004 atom_parse_data_header(mode_info
->atom_context
, data_index
, NULL
, &frev
, &crev
, &data_offset
);
1008 tv_info
= (ATOM_ANALOG_TV_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1009 if (index
> MAX_SUPPORTED_TV_TIMING
)
1012 mode
->crtc_htotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Total
);
1013 mode
->crtc_hdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Disp
);
1014 mode
->crtc_hsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
);
1015 mode
->crtc_hsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
) +
1016 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncWidth
);
1018 mode
->crtc_vtotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Total
);
1019 mode
->crtc_vdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Disp
);
1020 mode
->crtc_vsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
);
1021 mode
->crtc_vsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
) +
1022 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncWidth
);
1025 misc
= le16_to_cpu(tv_info
->aModeTimings
[index
].susModeMiscInfo
.usAccess
);
1026 if (misc
& ATOM_VSYNC_POLARITY
)
1027 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1028 if (misc
& ATOM_HSYNC_POLARITY
)
1029 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1030 if (misc
& ATOM_COMPOSITESYNC
)
1031 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1032 if (misc
& ATOM_INTERLACE
)
1033 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1034 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1035 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1037 mode
->clock
= le16_to_cpu(tv_info
->aModeTimings
[index
].usPixelClock
) * 10;
1040 /* PAL timings appear to have wrong values for totals */
1041 mode
->crtc_htotal
-= 1;
1042 mode
->crtc_vtotal
-= 1;
1046 tv_info_v1_2
= (ATOM_ANALOG_TV_INFO_V1_2
*)(mode_info
->atom_context
->bios
+ data_offset
);
1047 if (index
> MAX_SUPPORTED_TV_TIMING_V1_2
)
1050 dtd_timings
= &tv_info_v1_2
->aModeTimings
[index
];
1051 mode
->crtc_htotal
= le16_to_cpu(dtd_timings
->usHActive
) +
1052 le16_to_cpu(dtd_timings
->usHBlanking_Time
);
1053 mode
->crtc_hdisplay
= le16_to_cpu(dtd_timings
->usHActive
);
1054 mode
->crtc_hsync_start
= le16_to_cpu(dtd_timings
->usHActive
) +
1055 le16_to_cpu(dtd_timings
->usHSyncOffset
);
1056 mode
->crtc_hsync_end
= mode
->crtc_hsync_start
+
1057 le16_to_cpu(dtd_timings
->usHSyncWidth
);
1059 mode
->crtc_vtotal
= le16_to_cpu(dtd_timings
->usVActive
) +
1060 le16_to_cpu(dtd_timings
->usVBlanking_Time
);
1061 mode
->crtc_vdisplay
= le16_to_cpu(dtd_timings
->usVActive
);
1062 mode
->crtc_vsync_start
= le16_to_cpu(dtd_timings
->usVActive
) +
1063 le16_to_cpu(dtd_timings
->usVSyncOffset
);
1064 mode
->crtc_vsync_end
= mode
->crtc_vsync_start
+
1065 le16_to_cpu(dtd_timings
->usVSyncWidth
);
1068 misc
= le16_to_cpu(dtd_timings
->susModeMiscInfo
.usAccess
);
1069 if (misc
& ATOM_VSYNC_POLARITY
)
1070 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1071 if (misc
& ATOM_HSYNC_POLARITY
)
1072 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1073 if (misc
& ATOM_COMPOSITESYNC
)
1074 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1075 if (misc
& ATOM_INTERLACE
)
1076 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1077 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1078 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1080 mode
->clock
= le16_to_cpu(dtd_timings
->usPixClk
) * 10;
1086 struct radeon_encoder_tv_dac
*
1087 radeon_atombios_get_tv_dac_info(struct radeon_encoder
*encoder
)
1089 struct drm_device
*dev
= encoder
->base
.dev
;
1090 struct radeon_device
*rdev
= dev
->dev_private
;
1091 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1092 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1093 uint16_t data_offset
;
1094 struct _COMPASSIONATE_DATA
*dac_info
;
1097 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1099 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
, &crev
, &data_offset
);
1101 dac_info
= (struct _COMPASSIONATE_DATA
*)(mode_info
->atom_context
->bios
+ data_offset
);
1104 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1109 bg
= dac_info
->ucDAC2_CRT2_BG_Adjustment
;
1110 dac
= dac_info
->ucDAC2_CRT2_DAC_Adjustment
;
1111 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1113 bg
= dac_info
->ucDAC2_PAL_BG_Adjustment
;
1114 dac
= dac_info
->ucDAC2_PAL_DAC_Adjustment
;
1115 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1117 bg
= dac_info
->ucDAC2_NTSC_BG_Adjustment
;
1118 dac
= dac_info
->ucDAC2_NTSC_DAC_Adjustment
;
1119 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1125 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
)
1127 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args
;
1128 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicClockGating
);
1130 args
.ucEnable
= enable
;
1132 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1135 void radeon_atom_static_pwrmgt_setup(struct radeon_device
*rdev
, int enable
)
1137 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args
;
1138 int index
= GetIndexIntoMasterTable(COMMAND
, EnableASIC_StaticPwrMgt
);
1140 args
.ucEnable
= enable
;
1142 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1145 uint32_t radeon_atom_get_engine_clock(struct radeon_device
*rdev
)
1147 GET_ENGINE_CLOCK_PS_ALLOCATION args
;
1148 int index
= GetIndexIntoMasterTable(COMMAND
, GetEngineClock
);
1150 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1151 return args
.ulReturnEngineClock
;
1154 uint32_t radeon_atom_get_memory_clock(struct radeon_device
*rdev
)
1156 GET_MEMORY_CLOCK_PS_ALLOCATION args
;
1157 int index
= GetIndexIntoMasterTable(COMMAND
, GetMemoryClock
);
1159 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1160 return args
.ulReturnMemoryClock
;
1163 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
,
1166 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
1167 int index
= GetIndexIntoMasterTable(COMMAND
, SetEngineClock
);
1169 args
.ulTargetEngineClock
= eng_clock
; /* 10 khz */
1171 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1174 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
,
1177 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
1178 int index
= GetIndexIntoMasterTable(COMMAND
, SetMemoryClock
);
1180 if (rdev
->flags
& RADEON_IS_IGP
)
1183 args
.ulTargetMemoryClock
= mem_clock
; /* 10 khz */
1185 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1188 void radeon_atom_initialize_bios_scratch_regs(struct drm_device
*dev
)
1190 struct radeon_device
*rdev
= dev
->dev_private
;
1191 uint32_t bios_2_scratch
, bios_6_scratch
;
1193 if (rdev
->family
>= CHIP_R600
) {
1194 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
1195 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1197 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
1198 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1201 /* let the bios control the backlight */
1202 bios_2_scratch
&= ~ATOM_S2_VRI_BRIGHT_ENABLE
;
1204 /* tell the bios not to handle mode switching */
1205 bios_6_scratch
|= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
| ATOM_S6_ACC_MODE
);
1207 if (rdev
->family
>= CHIP_R600
) {
1208 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
1209 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1211 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
1212 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1217 void radeon_save_bios_scratch_regs(struct radeon_device
*rdev
)
1219 uint32_t scratch_reg
;
1222 if (rdev
->family
>= CHIP_R600
)
1223 scratch_reg
= R600_BIOS_0_SCRATCH
;
1225 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
1227 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
1228 rdev
->bios_scratch
[i
] = RREG32(scratch_reg
+ (i
* 4));
1231 void radeon_restore_bios_scratch_regs(struct radeon_device
*rdev
)
1233 uint32_t scratch_reg
;
1236 if (rdev
->family
>= CHIP_R600
)
1237 scratch_reg
= R600_BIOS_0_SCRATCH
;
1239 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
1241 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
1242 WREG32(scratch_reg
+ (i
* 4), rdev
->bios_scratch
[i
]);
1245 void radeon_atom_output_lock(struct drm_encoder
*encoder
, bool lock
)
1247 struct drm_device
*dev
= encoder
->dev
;
1248 struct radeon_device
*rdev
= dev
->dev_private
;
1249 uint32_t bios_6_scratch
;
1251 if (rdev
->family
>= CHIP_R600
)
1252 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1254 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1257 bios_6_scratch
|= ATOM_S6_CRITICAL_STATE
;
1259 bios_6_scratch
&= ~ATOM_S6_CRITICAL_STATE
;
1261 if (rdev
->family
>= CHIP_R600
)
1262 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1264 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1267 /* at some point we may want to break this out into individual functions */
1269 radeon_atombios_connected_scratch_regs(struct drm_connector
*connector
,
1270 struct drm_encoder
*encoder
,
1273 struct drm_device
*dev
= connector
->dev
;
1274 struct radeon_device
*rdev
= dev
->dev_private
;
1275 struct radeon_connector
*radeon_connector
=
1276 to_radeon_connector(connector
);
1277 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1278 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
1280 if (rdev
->family
>= CHIP_R600
) {
1281 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
1282 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
1283 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1285 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
1286 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
1287 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1290 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
1291 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
1293 DRM_DEBUG("TV1 connected\n");
1294 bios_3_scratch
|= ATOM_S3_TV1_ACTIVE
;
1295 bios_6_scratch
|= ATOM_S6_ACC_REQ_TV1
;
1297 DRM_DEBUG("TV1 disconnected\n");
1298 bios_0_scratch
&= ~ATOM_S0_TV1_MASK
;
1299 bios_3_scratch
&= ~ATOM_S3_TV1_ACTIVE
;
1300 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_TV1
;
1303 if ((radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) &&
1304 (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
)) {
1306 DRM_DEBUG("CV connected\n");
1307 bios_3_scratch
|= ATOM_S3_CV_ACTIVE
;
1308 bios_6_scratch
|= ATOM_S6_ACC_REQ_CV
;
1310 DRM_DEBUG("CV disconnected\n");
1311 bios_0_scratch
&= ~ATOM_S0_CV_MASK
;
1312 bios_3_scratch
&= ~ATOM_S3_CV_ACTIVE
;
1313 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CV
;
1316 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
1317 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
1319 DRM_DEBUG("LCD1 connected\n");
1320 bios_0_scratch
|= ATOM_S0_LCD1
;
1321 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
1322 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
1324 DRM_DEBUG("LCD1 disconnected\n");
1325 bios_0_scratch
&= ~ATOM_S0_LCD1
;
1326 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
1327 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
1330 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
1331 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
1333 DRM_DEBUG("CRT1 connected\n");
1334 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
1335 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
1336 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
1338 DRM_DEBUG("CRT1 disconnected\n");
1339 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
1340 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
1341 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
1344 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
1345 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
1347 DRM_DEBUG("CRT2 connected\n");
1348 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
1349 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
1350 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
1352 DRM_DEBUG("CRT2 disconnected\n");
1353 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
1354 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
1355 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
1358 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
1359 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
1361 DRM_DEBUG("DFP1 connected\n");
1362 bios_0_scratch
|= ATOM_S0_DFP1
;
1363 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
1364 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
1366 DRM_DEBUG("DFP1 disconnected\n");
1367 bios_0_scratch
&= ~ATOM_S0_DFP1
;
1368 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
1369 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
1372 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
1373 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
1375 DRM_DEBUG("DFP2 connected\n");
1376 bios_0_scratch
|= ATOM_S0_DFP2
;
1377 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
1378 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
1380 DRM_DEBUG("DFP2 disconnected\n");
1381 bios_0_scratch
&= ~ATOM_S0_DFP2
;
1382 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
1383 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
1386 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
1387 (radeon_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
1389 DRM_DEBUG("DFP3 connected\n");
1390 bios_0_scratch
|= ATOM_S0_DFP3
;
1391 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
1392 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
1394 DRM_DEBUG("DFP3 disconnected\n");
1395 bios_0_scratch
&= ~ATOM_S0_DFP3
;
1396 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
1397 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
1400 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
1401 (radeon_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
1403 DRM_DEBUG("DFP4 connected\n");
1404 bios_0_scratch
|= ATOM_S0_DFP4
;
1405 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
1406 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
1408 DRM_DEBUG("DFP4 disconnected\n");
1409 bios_0_scratch
&= ~ATOM_S0_DFP4
;
1410 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
1411 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
1414 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
1415 (radeon_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
1417 DRM_DEBUG("DFP5 connected\n");
1418 bios_0_scratch
|= ATOM_S0_DFP5
;
1419 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
1420 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
1422 DRM_DEBUG("DFP5 disconnected\n");
1423 bios_0_scratch
&= ~ATOM_S0_DFP5
;
1424 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
1425 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
1429 if (rdev
->family
>= CHIP_R600
) {
1430 WREG32(R600_BIOS_0_SCRATCH
, bios_0_scratch
);
1431 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
1432 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1434 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
1435 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
1436 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1441 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
1443 struct drm_device
*dev
= encoder
->dev
;
1444 struct radeon_device
*rdev
= dev
->dev_private
;
1445 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1446 uint32_t bios_3_scratch
;
1448 if (rdev
->family
>= CHIP_R600
)
1449 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
1451 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
1453 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1454 bios_3_scratch
&= ~ATOM_S3_TV1_CRTC_ACTIVE
;
1455 bios_3_scratch
|= (crtc
<< 18);
1457 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1458 bios_3_scratch
&= ~ATOM_S3_CV_CRTC_ACTIVE
;
1459 bios_3_scratch
|= (crtc
<< 24);
1461 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1462 bios_3_scratch
&= ~ATOM_S3_CRT1_CRTC_ACTIVE
;
1463 bios_3_scratch
|= (crtc
<< 16);
1465 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1466 bios_3_scratch
&= ~ATOM_S3_CRT2_CRTC_ACTIVE
;
1467 bios_3_scratch
|= (crtc
<< 20);
1469 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1470 bios_3_scratch
&= ~ATOM_S3_LCD1_CRTC_ACTIVE
;
1471 bios_3_scratch
|= (crtc
<< 17);
1473 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
1474 bios_3_scratch
&= ~ATOM_S3_DFP1_CRTC_ACTIVE
;
1475 bios_3_scratch
|= (crtc
<< 19);
1477 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
1478 bios_3_scratch
&= ~ATOM_S3_DFP2_CRTC_ACTIVE
;
1479 bios_3_scratch
|= (crtc
<< 23);
1481 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
1482 bios_3_scratch
&= ~ATOM_S3_DFP3_CRTC_ACTIVE
;
1483 bios_3_scratch
|= (crtc
<< 25);
1486 if (rdev
->family
>= CHIP_R600
)
1487 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
1489 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
1493 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
1495 struct drm_device
*dev
= encoder
->dev
;
1496 struct radeon_device
*rdev
= dev
->dev_private
;
1497 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1498 uint32_t bios_2_scratch
;
1500 if (rdev
->family
>= CHIP_R600
)
1501 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
1503 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
1505 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1507 bios_2_scratch
&= ~ATOM_S2_TV1_DPMS_STATE
;
1509 bios_2_scratch
|= ATOM_S2_TV1_DPMS_STATE
;
1511 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1513 bios_2_scratch
&= ~ATOM_S2_CV_DPMS_STATE
;
1515 bios_2_scratch
|= ATOM_S2_CV_DPMS_STATE
;
1517 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1519 bios_2_scratch
&= ~ATOM_S2_CRT1_DPMS_STATE
;
1521 bios_2_scratch
|= ATOM_S2_CRT1_DPMS_STATE
;
1523 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1525 bios_2_scratch
&= ~ATOM_S2_CRT2_DPMS_STATE
;
1527 bios_2_scratch
|= ATOM_S2_CRT2_DPMS_STATE
;
1529 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1531 bios_2_scratch
&= ~ATOM_S2_LCD1_DPMS_STATE
;
1533 bios_2_scratch
|= ATOM_S2_LCD1_DPMS_STATE
;
1535 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
1537 bios_2_scratch
&= ~ATOM_S2_DFP1_DPMS_STATE
;
1539 bios_2_scratch
|= ATOM_S2_DFP1_DPMS_STATE
;
1541 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
1543 bios_2_scratch
&= ~ATOM_S2_DFP2_DPMS_STATE
;
1545 bios_2_scratch
|= ATOM_S2_DFP2_DPMS_STATE
;
1547 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
1549 bios_2_scratch
&= ~ATOM_S2_DFP3_DPMS_STATE
;
1551 bios_2_scratch
|= ATOM_S2_DFP3_DPMS_STATE
;
1553 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) {
1555 bios_2_scratch
&= ~ATOM_S2_DFP4_DPMS_STATE
;
1557 bios_2_scratch
|= ATOM_S2_DFP4_DPMS_STATE
;
1559 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) {
1561 bios_2_scratch
&= ~ATOM_S2_DFP5_DPMS_STATE
;
1563 bios_2_scratch
|= ATOM_S2_DFP5_DPMS_STATE
;
1566 if (rdev
->family
>= CHIP_R600
)
1567 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
1569 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);