2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/radeon_drm.h>
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_enum(struct drm_device
*dev
, uint32_t supported_device
,
37 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
39 radeon_add_atom_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
40 uint32_t supported_device
, u16 caps
);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device
*dev
,
45 uint32_t connector_id
,
46 uint32_t supported_device
,
48 struct radeon_i2c_bus_rec
*i2c_bus
,
49 uint32_t igp_lane_info
,
50 uint16_t connector_object_id
,
51 struct radeon_hpd
*hpd
,
52 struct radeon_router
*router
);
54 /* from radeon_legacy_encoder.c */
56 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
57 uint32_t supported_device
);
60 static int radeon_atom_get_max_vddc(struct radeon_device
*rdev
, u8 voltage_type
,
61 u16 voltage_id
, u16
*voltage
);
63 union atom_supported_devices
{
64 struct _ATOM_SUPPORTED_DEVICES_INFO info
;
65 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2
;
66 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1
;
69 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device
*rdev
,
70 ATOM_GPIO_I2C_ASSIGMENT
*gpio
,
73 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
74 if ((rdev
->family
== CHIP_R420
) ||
75 (rdev
->family
== CHIP_R423
) ||
76 (rdev
->family
== CHIP_RV410
)) {
77 if ((le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x0018) ||
78 (le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x0019) ||
79 (le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x001a)) {
80 gpio
->ucClkMaskShift
= 0x19;
81 gpio
->ucDataMaskShift
= 0x18;
85 /* some evergreen boards have bad data for this entry */
86 if (ASIC_IS_DCE4(rdev
)) {
88 (le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x1936) &&
89 (gpio
->sucI2cId
.ucAccess
== 0)) {
90 gpio
->sucI2cId
.ucAccess
= 0x97;
91 gpio
->ucDataMaskShift
= 8;
92 gpio
->ucDataEnShift
= 8;
93 gpio
->ucDataY_Shift
= 8;
94 gpio
->ucDataA_Shift
= 8;
98 /* some DCE3 boards have bad data for this entry */
99 if (ASIC_IS_DCE3(rdev
)) {
101 (le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x1fda) &&
102 (gpio
->sucI2cId
.ucAccess
== 0x94))
103 gpio
->sucI2cId
.ucAccess
= 0x14;
107 static struct radeon_i2c_bus_rec
radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT
*gpio
)
109 struct radeon_i2c_bus_rec i2c
;
111 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
113 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
) * 4;
114 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
) * 4;
115 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
) * 4;
116 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
) * 4;
117 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
) * 4;
118 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
) * 4;
119 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
) * 4;
120 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
) * 4;
121 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
122 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
123 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
124 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
125 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
126 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
127 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
128 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
130 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
131 i2c
.hw_capable
= true;
133 i2c
.hw_capable
= false;
135 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
140 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
142 if (i2c
.mask_clk_reg
)
150 static struct radeon_i2c_bus_rec
radeon_lookup_i2c_gpio(struct radeon_device
*rdev
,
153 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
154 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
155 struct radeon_i2c_bus_rec i2c
;
156 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
157 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
158 uint16_t data_offset
, size
;
161 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
164 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
165 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
167 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
168 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
170 for (i
= 0; i
< num_indices
; i
++) {
171 gpio
= &i2c_info
->asGPIO_Info
[i
];
173 radeon_lookup_i2c_gpio_quirks(rdev
, gpio
, i
);
175 if (gpio
->sucI2cId
.ucAccess
== id
) {
176 i2c
= radeon_get_bus_rec_for_i2c_gpio(gpio
);
185 void radeon_atombios_i2c_init(struct radeon_device
*rdev
)
187 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
188 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
189 struct radeon_i2c_bus_rec i2c
;
190 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
191 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
192 uint16_t data_offset
, size
;
196 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
197 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
199 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
200 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
202 for (i
= 0; i
< num_indices
; i
++) {
203 gpio
= &i2c_info
->asGPIO_Info
[i
];
205 radeon_lookup_i2c_gpio_quirks(rdev
, gpio
, i
);
207 i2c
= radeon_get_bus_rec_for_i2c_gpio(gpio
);
210 sprintf(stmp
, "0x%x", i2c
.i2c_id
);
211 rdev
->i2c_bus
[i
] = radeon_i2c_create(rdev
->ddev
, &i2c
, stmp
);
217 static struct radeon_gpio_rec
radeon_lookup_gpio(struct radeon_device
*rdev
,
220 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
221 struct radeon_gpio_rec gpio
;
222 int index
= GetIndexIntoMasterTable(DATA
, GPIO_Pin_LUT
);
223 struct _ATOM_GPIO_PIN_LUT
*gpio_info
;
224 ATOM_GPIO_PIN_ASSIGNMENT
*pin
;
225 u16 data_offset
, size
;
228 memset(&gpio
, 0, sizeof(struct radeon_gpio_rec
));
231 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
232 gpio_info
= (struct _ATOM_GPIO_PIN_LUT
*)(ctx
->bios
+ data_offset
);
234 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
235 sizeof(ATOM_GPIO_PIN_ASSIGNMENT
);
237 for (i
= 0; i
< num_indices
; i
++) {
238 pin
= &gpio_info
->asGPIO_Pin
[i
];
239 if (id
== pin
->ucGPIO_ID
) {
240 gpio
.id
= pin
->ucGPIO_ID
;
241 gpio
.reg
= le16_to_cpu(pin
->usGpioPin_AIndex
) * 4;
242 gpio
.mask
= (1 << pin
->ucGpioPinBitShift
);
252 static struct radeon_hpd
radeon_atom_get_hpd_info_from_gpio(struct radeon_device
*rdev
,
253 struct radeon_gpio_rec
*gpio
)
255 struct radeon_hpd hpd
;
258 memset(&hpd
, 0, sizeof(struct radeon_hpd
));
260 if (ASIC_IS_DCE6(rdev
))
261 reg
= SI_DC_GPIO_HPD_A
;
262 else if (ASIC_IS_DCE4(rdev
))
263 reg
= EVERGREEN_DC_GPIO_HPD_A
;
265 reg
= AVIVO_DC_GPIO_HPD_A
;
268 if (gpio
->reg
== reg
) {
271 hpd
.hpd
= RADEON_HPD_1
;
274 hpd
.hpd
= RADEON_HPD_2
;
277 hpd
.hpd
= RADEON_HPD_3
;
280 hpd
.hpd
= RADEON_HPD_4
;
283 hpd
.hpd
= RADEON_HPD_5
;
286 hpd
.hpd
= RADEON_HPD_6
;
289 hpd
.hpd
= RADEON_HPD_NONE
;
293 hpd
.hpd
= RADEON_HPD_NONE
;
297 static bool radeon_atom_apply_quirks(struct drm_device
*dev
,
298 uint32_t supported_device
,
300 struct radeon_i2c_bus_rec
*i2c_bus
,
302 struct radeon_hpd
*hpd
)
305 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
306 if ((dev
->pdev
->device
== 0x791e) &&
307 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
308 (dev
->pdev
->subsystem_device
== 0x826d)) {
309 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
310 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
311 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
314 /* Asrock RS600 board lists the DVI port as HDMI */
315 if ((dev
->pdev
->device
== 0x7941) &&
316 (dev
->pdev
->subsystem_vendor
== 0x1849) &&
317 (dev
->pdev
->subsystem_device
== 0x7941)) {
318 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
319 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
320 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
323 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
324 if ((dev
->pdev
->device
== 0x796e) &&
325 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
326 (dev
->pdev
->subsystem_device
== 0x7302)) {
327 if ((supported_device
== ATOM_DEVICE_DFP2_SUPPORT
) ||
328 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
332 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
333 if ((dev
->pdev
->device
== 0x7941) &&
334 (dev
->pdev
->subsystem_vendor
== 0x147b) &&
335 (dev
->pdev
->subsystem_device
== 0x2412)) {
336 if (*connector_type
== DRM_MODE_CONNECTOR_DVII
)
340 /* Falcon NW laptop lists vga ddc line for LVDS */
341 if ((dev
->pdev
->device
== 0x5653) &&
342 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
343 (dev
->pdev
->subsystem_device
== 0x0291)) {
344 if (*connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
345 i2c_bus
->valid
= false;
350 /* HIS X1300 is DVI+VGA, not DVI+DVI */
351 if ((dev
->pdev
->device
== 0x7146) &&
352 (dev
->pdev
->subsystem_vendor
== 0x17af) &&
353 (dev
->pdev
->subsystem_device
== 0x2058)) {
354 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
358 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
359 if ((dev
->pdev
->device
== 0x7142) &&
360 (dev
->pdev
->subsystem_vendor
== 0x1458) &&
361 (dev
->pdev
->subsystem_device
== 0x2134)) {
362 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
368 if ((dev
->pdev
->device
== 0x71C5) &&
369 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
370 (dev
->pdev
->subsystem_device
== 0x0080)) {
371 if ((supported_device
== ATOM_DEVICE_CRT1_SUPPORT
) ||
372 (supported_device
== ATOM_DEVICE_DFP2_SUPPORT
))
374 if (supported_device
== ATOM_DEVICE_CRT2_SUPPORT
)
378 /* mac rv630, rv730, others */
379 if ((supported_device
== ATOM_DEVICE_TV1_SUPPORT
) &&
380 (*connector_type
== DRM_MODE_CONNECTOR_DVII
)) {
381 *connector_type
= DRM_MODE_CONNECTOR_9PinDIN
;
382 *line_mux
= CONNECTOR_7PIN_DIN_ENUM_ID1
;
385 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
386 if ((dev
->pdev
->device
== 0x9598) &&
387 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
388 (dev
->pdev
->subsystem_device
== 0x01da)) {
389 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
390 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
394 /* ASUS HD 3600 board lists the DVI port as HDMI */
395 if ((dev
->pdev
->device
== 0x9598) &&
396 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
397 (dev
->pdev
->subsystem_device
== 0x01e4)) {
398 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
399 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
403 /* ASUS HD 3450 board lists the DVI port as HDMI */
404 if ((dev
->pdev
->device
== 0x95C5) &&
405 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
406 (dev
->pdev
->subsystem_device
== 0x01e2)) {
407 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
408 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
412 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
413 * HDMI + VGA reporting as HDMI
415 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
416 if (supported_device
& (ATOM_DEVICE_CRT_SUPPORT
)) {
417 *connector_type
= DRM_MODE_CONNECTOR_VGA
;
422 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
423 * on the laptop and a DVI port on the docking station and
424 * both share the same encoder, hpd pin, and ddc line.
425 * So while the bios table is technically correct,
426 * we drop the DVI port here since xrandr has no concept of
427 * encoders and will try and drive both connectors
428 * with different crtcs which isn't possible on the hardware
429 * side and leaves no crtcs for LVDS or VGA.
431 if (((dev
->pdev
->device
== 0x95c4) || (dev
->pdev
->device
== 0x9591)) &&
432 (dev
->pdev
->subsystem_vendor
== 0x1025) &&
433 (dev
->pdev
->subsystem_device
== 0x013c)) {
434 if ((*connector_type
== DRM_MODE_CONNECTOR_DVII
) &&
435 (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)) {
436 /* actually it's a DVI-D port not DVI-I */
437 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
442 /* XFX Pine Group device rv730 reports no VGA DDC lines
443 * even though they are wired up to record 0x93
445 if ((dev
->pdev
->device
== 0x9498) &&
446 (dev
->pdev
->subsystem_vendor
== 0x1682) &&
447 (dev
->pdev
->subsystem_device
== 0x2452) &&
448 (i2c_bus
->valid
== false) &&
449 !(supported_device
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))) {
450 struct radeon_device
*rdev
= dev
->dev_private
;
451 *i2c_bus
= radeon_lookup_i2c_gpio(rdev
, 0x93);
454 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
455 if (((dev
->pdev
->device
== 0x9802) || (dev
->pdev
->device
== 0x9806)) &&
456 (dev
->pdev
->subsystem_vendor
== 0x1734) &&
457 (dev
->pdev
->subsystem_device
== 0x11bd)) {
458 if (*connector_type
== DRM_MODE_CONNECTOR_VGA
) {
459 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
461 } else if (*connector_type
== DRM_MODE_CONNECTOR_DVID
) {
462 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
470 const int supported_devices_connector_convert
[] = {
471 DRM_MODE_CONNECTOR_Unknown
,
472 DRM_MODE_CONNECTOR_VGA
,
473 DRM_MODE_CONNECTOR_DVII
,
474 DRM_MODE_CONNECTOR_DVID
,
475 DRM_MODE_CONNECTOR_DVIA
,
476 DRM_MODE_CONNECTOR_SVIDEO
,
477 DRM_MODE_CONNECTOR_Composite
,
478 DRM_MODE_CONNECTOR_LVDS
,
479 DRM_MODE_CONNECTOR_Unknown
,
480 DRM_MODE_CONNECTOR_Unknown
,
481 DRM_MODE_CONNECTOR_HDMIA
,
482 DRM_MODE_CONNECTOR_HDMIB
,
483 DRM_MODE_CONNECTOR_Unknown
,
484 DRM_MODE_CONNECTOR_Unknown
,
485 DRM_MODE_CONNECTOR_9PinDIN
,
486 DRM_MODE_CONNECTOR_DisplayPort
489 const uint16_t supported_devices_connector_object_id_convert
[] = {
490 CONNECTOR_OBJECT_ID_NONE
,
491 CONNECTOR_OBJECT_ID_VGA
,
492 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
, /* not all boards support DL */
493 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
, /* not all boards support DL */
494 CONNECTOR_OBJECT_ID_VGA
, /* technically DVI-A */
495 CONNECTOR_OBJECT_ID_COMPOSITE
,
496 CONNECTOR_OBJECT_ID_SVIDEO
,
497 CONNECTOR_OBJECT_ID_LVDS
,
498 CONNECTOR_OBJECT_ID_9PIN_DIN
,
499 CONNECTOR_OBJECT_ID_9PIN_DIN
,
500 CONNECTOR_OBJECT_ID_DISPLAYPORT
,
501 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
,
502 CONNECTOR_OBJECT_ID_HDMI_TYPE_B
,
503 CONNECTOR_OBJECT_ID_SVIDEO
506 const int object_connector_convert
[] = {
507 DRM_MODE_CONNECTOR_Unknown
,
508 DRM_MODE_CONNECTOR_DVII
,
509 DRM_MODE_CONNECTOR_DVII
,
510 DRM_MODE_CONNECTOR_DVID
,
511 DRM_MODE_CONNECTOR_DVID
,
512 DRM_MODE_CONNECTOR_VGA
,
513 DRM_MODE_CONNECTOR_Composite
,
514 DRM_MODE_CONNECTOR_SVIDEO
,
515 DRM_MODE_CONNECTOR_Unknown
,
516 DRM_MODE_CONNECTOR_Unknown
,
517 DRM_MODE_CONNECTOR_9PinDIN
,
518 DRM_MODE_CONNECTOR_Unknown
,
519 DRM_MODE_CONNECTOR_HDMIA
,
520 DRM_MODE_CONNECTOR_HDMIB
,
521 DRM_MODE_CONNECTOR_LVDS
,
522 DRM_MODE_CONNECTOR_9PinDIN
,
523 DRM_MODE_CONNECTOR_Unknown
,
524 DRM_MODE_CONNECTOR_Unknown
,
525 DRM_MODE_CONNECTOR_Unknown
,
526 DRM_MODE_CONNECTOR_DisplayPort
,
527 DRM_MODE_CONNECTOR_eDP
,
528 DRM_MODE_CONNECTOR_Unknown
531 bool radeon_get_atom_connector_info_from_object_table(struct drm_device
*dev
)
533 struct radeon_device
*rdev
= dev
->dev_private
;
534 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
535 struct atom_context
*ctx
= mode_info
->atom_context
;
536 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
537 u16 size
, data_offset
;
539 ATOM_CONNECTOR_OBJECT_TABLE
*con_obj
;
540 ATOM_ENCODER_OBJECT_TABLE
*enc_obj
;
541 ATOM_OBJECT_TABLE
*router_obj
;
542 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
543 ATOM_OBJECT_HEADER
*obj_header
;
544 int i
, j
, k
, path_size
, device_support
;
546 u16 igp_lane_info
, conn_id
, connector_object_id
;
547 struct radeon_i2c_bus_rec ddc_bus
;
548 struct radeon_router router
;
549 struct radeon_gpio_rec gpio
;
550 struct radeon_hpd hpd
;
552 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
))
558 obj_header
= (ATOM_OBJECT_HEADER
*) (ctx
->bios
+ data_offset
);
559 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
560 (ctx
->bios
+ data_offset
+
561 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
562 con_obj
= (ATOM_CONNECTOR_OBJECT_TABLE
*)
563 (ctx
->bios
+ data_offset
+
564 le16_to_cpu(obj_header
->usConnectorObjectTableOffset
));
565 enc_obj
= (ATOM_ENCODER_OBJECT_TABLE
*)
566 (ctx
->bios
+ data_offset
+
567 le16_to_cpu(obj_header
->usEncoderObjectTableOffset
));
568 router_obj
= (ATOM_OBJECT_TABLE
*)
569 (ctx
->bios
+ data_offset
+
570 le16_to_cpu(obj_header
->usRouterObjectTableOffset
));
571 device_support
= le16_to_cpu(obj_header
->usDeviceSupport
);
574 for (i
= 0; i
< path_obj
->ucNumOfDispPath
; i
++) {
575 uint8_t *addr
= (uint8_t *) path_obj
->asDispPath
;
576 ATOM_DISPLAY_OBJECT_PATH
*path
;
578 path
= (ATOM_DISPLAY_OBJECT_PATH
*) addr
;
579 path_size
+= le16_to_cpu(path
->usSize
);
581 if (device_support
& le16_to_cpu(path
->usDeviceTag
)) {
582 uint8_t con_obj_id
, con_obj_num
, con_obj_type
;
585 (le16_to_cpu(path
->usConnObjectId
) & OBJECT_ID_MASK
)
588 (le16_to_cpu(path
->usConnObjectId
) & ENUM_ID_MASK
)
591 (le16_to_cpu(path
->usConnObjectId
) &
592 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
594 /* TODO CV support */
595 if (le16_to_cpu(path
->usDeviceTag
) ==
596 ATOM_DEVICE_CV_SUPPORT
)
600 if ((rdev
->flags
& RADEON_IS_IGP
) &&
602 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR
)) {
603 uint16_t igp_offset
= 0;
604 ATOM_INTEGRATED_SYSTEM_INFO_V2
*igp_obj
;
607 GetIndexIntoMasterTable(DATA
,
608 IntegratedSystemInfo
);
610 if (atom_parse_data_header(ctx
, index
, &size
, &frev
,
611 &crev
, &igp_offset
)) {
615 (ATOM_INTEGRATED_SYSTEM_INFO_V2
616 *) (ctx
->bios
+ igp_offset
);
619 uint32_t slot_config
, ct
;
621 if (con_obj_num
== 1)
630 ct
= (slot_config
>> 16) & 0xff;
632 object_connector_convert
634 connector_object_id
= ct
;
636 slot_config
& 0xffff;
644 object_connector_convert
[con_obj_id
];
645 connector_object_id
= con_obj_id
;
650 object_connector_convert
[con_obj_id
];
651 connector_object_id
= con_obj_id
;
654 if (connector_type
== DRM_MODE_CONNECTOR_Unknown
)
657 router
.ddc_valid
= false;
658 router
.cd_valid
= false;
659 for (j
= 0; j
< ((le16_to_cpu(path
->usSize
) - 8) / 2); j
++) {
660 uint8_t grph_obj_id
, grph_obj_num
, grph_obj_type
;
663 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
664 OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
666 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
667 ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
669 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
670 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
672 if (grph_obj_type
== GRAPH_OBJECT_TYPE_ENCODER
) {
673 for (k
= 0; k
< enc_obj
->ucNumberOfObjects
; k
++) {
674 u16 encoder_obj
= le16_to_cpu(enc_obj
->asObjects
[k
].usObjectID
);
675 if (le16_to_cpu(path
->usGraphicObjIds
[j
]) == encoder_obj
) {
676 ATOM_COMMON_RECORD_HEADER
*record
= (ATOM_COMMON_RECORD_HEADER
*)
677 (ctx
->bios
+ data_offset
+
678 le16_to_cpu(enc_obj
->asObjects
[k
].usRecordOffset
));
679 ATOM_ENCODER_CAP_RECORD
*cap_record
;
682 while (record
->ucRecordSize
> 0 &&
683 record
->ucRecordType
> 0 &&
684 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
685 switch (record
->ucRecordType
) {
686 case ATOM_ENCODER_CAP_RECORD_TYPE
:
687 cap_record
=(ATOM_ENCODER_CAP_RECORD
*)
689 caps
= le16_to_cpu(cap_record
->usEncoderCap
);
692 record
= (ATOM_COMMON_RECORD_HEADER
*)
693 ((char *)record
+ record
->ucRecordSize
);
695 radeon_add_atom_encoder(dev
,
703 } else if (grph_obj_type
== GRAPH_OBJECT_TYPE_ROUTER
) {
704 for (k
= 0; k
< router_obj
->ucNumberOfObjects
; k
++) {
705 u16 router_obj_id
= le16_to_cpu(router_obj
->asObjects
[k
].usObjectID
);
706 if (le16_to_cpu(path
->usGraphicObjIds
[j
]) == router_obj_id
) {
707 ATOM_COMMON_RECORD_HEADER
*record
= (ATOM_COMMON_RECORD_HEADER
*)
708 (ctx
->bios
+ data_offset
+
709 le16_to_cpu(router_obj
->asObjects
[k
].usRecordOffset
));
710 ATOM_I2C_RECORD
*i2c_record
;
711 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
712 ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*ddc_path
;
713 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
*cd_path
;
714 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*router_src_dst_table
=
715 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*)
716 (ctx
->bios
+ data_offset
+
717 le16_to_cpu(router_obj
->asObjects
[k
].usSrcDstTableOffset
));
720 router
.router_id
= router_obj_id
;
721 for (enum_id
= 0; enum_id
< router_src_dst_table
->ucNumberOfDst
;
723 if (le16_to_cpu(path
->usConnObjectId
) ==
724 le16_to_cpu(router_src_dst_table
->usDstObjectID
[enum_id
]))
728 while (record
->ucRecordSize
> 0 &&
729 record
->ucRecordType
> 0 &&
730 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
731 switch (record
->ucRecordType
) {
732 case ATOM_I2C_RECORD_TYPE
:
737 (ATOM_I2C_ID_CONFIG_ACCESS
*)
738 &i2c_record
->sucI2cId
;
740 radeon_lookup_i2c_gpio(rdev
,
743 router
.i2c_addr
= i2c_record
->ucI2CAddr
>> 1;
745 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE
:
746 ddc_path
= (ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*)
748 router
.ddc_valid
= true;
749 router
.ddc_mux_type
= ddc_path
->ucMuxType
;
750 router
.ddc_mux_control_pin
= ddc_path
->ucMuxControlPin
;
751 router
.ddc_mux_state
= ddc_path
->ucMuxState
[enum_id
];
753 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE
:
754 cd_path
= (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
*)
756 router
.cd_valid
= true;
757 router
.cd_mux_type
= cd_path
->ucMuxType
;
758 router
.cd_mux_control_pin
= cd_path
->ucMuxControlPin
;
759 router
.cd_mux_state
= cd_path
->ucMuxState
[enum_id
];
762 record
= (ATOM_COMMON_RECORD_HEADER
*)
763 ((char *)record
+ record
->ucRecordSize
);
770 /* look up gpio for ddc, hpd */
771 ddc_bus
.valid
= false;
772 hpd
.hpd
= RADEON_HPD_NONE
;
773 if ((le16_to_cpu(path
->usDeviceTag
) &
774 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) == 0) {
775 for (j
= 0; j
< con_obj
->ucNumberOfObjects
; j
++) {
776 if (le16_to_cpu(path
->usConnObjectId
) ==
777 le16_to_cpu(con_obj
->asObjects
[j
].
779 ATOM_COMMON_RECORD_HEADER
781 (ATOM_COMMON_RECORD_HEADER
783 (ctx
->bios
+ data_offset
+
784 le16_to_cpu(con_obj
->
787 ATOM_I2C_RECORD
*i2c_record
;
788 ATOM_HPD_INT_RECORD
*hpd_record
;
789 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
791 while (record
->ucRecordSize
> 0 &&
792 record
->ucRecordType
> 0 &&
793 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
794 switch (record
->ucRecordType
) {
795 case ATOM_I2C_RECORD_TYPE
:
800 (ATOM_I2C_ID_CONFIG_ACCESS
*)
801 &i2c_record
->sucI2cId
;
802 ddc_bus
= radeon_lookup_i2c_gpio(rdev
,
806 case ATOM_HPD_INT_RECORD_TYPE
:
808 (ATOM_HPD_INT_RECORD
*)
810 gpio
= radeon_lookup_gpio(rdev
,
811 hpd_record
->ucHPDIntGPIOID
);
812 hpd
= radeon_atom_get_hpd_info_from_gpio(rdev
, &gpio
);
813 hpd
.plugged_state
= hpd_record
->ucPlugged_PinState
;
817 (ATOM_COMMON_RECORD_HEADER
828 /* needed for aux chan transactions */
829 ddc_bus
.hpd
= hpd
.hpd
;
831 conn_id
= le16_to_cpu(path
->usConnObjectId
);
833 if (!radeon_atom_apply_quirks
834 (dev
, le16_to_cpu(path
->usDeviceTag
), &connector_type
,
835 &ddc_bus
, &conn_id
, &hpd
))
838 radeon_add_atom_connector(dev
,
842 connector_type
, &ddc_bus
,
851 radeon_link_encoder_connector(dev
);
856 static uint16_t atombios_get_connector_object_id(struct drm_device
*dev
,
860 struct radeon_device
*rdev
= dev
->dev_private
;
862 if (rdev
->flags
& RADEON_IS_IGP
) {
863 return supported_devices_connector_object_id_convert
865 } else if (((connector_type
== DRM_MODE_CONNECTOR_DVII
) ||
866 (connector_type
== DRM_MODE_CONNECTOR_DVID
)) &&
867 (devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
868 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
869 struct atom_context
*ctx
= mode_info
->atom_context
;
870 int index
= GetIndexIntoMasterTable(DATA
, XTMDS_Info
);
871 uint16_t size
, data_offset
;
873 ATOM_XTMDS_INFO
*xtmds
;
875 if (atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
)) {
876 xtmds
= (ATOM_XTMDS_INFO
*)(ctx
->bios
+ data_offset
);
878 if (xtmds
->ucSupportedLink
& ATOM_XTMDS_SUPPORTED_DUALLINK
) {
879 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
880 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
882 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
884 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
885 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
887 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
890 return supported_devices_connector_object_id_convert
893 return supported_devices_connector_object_id_convert
898 struct bios_connector
{
903 struct radeon_i2c_bus_rec ddc_bus
;
904 struct radeon_hpd hpd
;
907 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
911 struct radeon_device
*rdev
= dev
->dev_private
;
912 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
913 struct atom_context
*ctx
= mode_info
->atom_context
;
914 int index
= GetIndexIntoMasterTable(DATA
, SupportedDevicesInfo
);
915 uint16_t size
, data_offset
;
917 uint16_t device_support
;
919 union atom_supported_devices
*supported_devices
;
920 int i
, j
, max_device
;
921 struct bios_connector
*bios_connectors
;
922 size_t bc_size
= sizeof(*bios_connectors
) * ATOM_MAX_SUPPORTED_DEVICE
;
923 struct radeon_router router
;
925 router
.ddc_valid
= false;
926 router
.cd_valid
= false;
928 bios_connectors
= kzalloc(bc_size
, GFP_KERNEL
);
929 if (!bios_connectors
)
932 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
,
934 kfree(bios_connectors
);
939 (union atom_supported_devices
*)(ctx
->bios
+ data_offset
);
941 device_support
= le16_to_cpu(supported_devices
->info
.usDeviceSupport
);
944 max_device
= ATOM_MAX_SUPPORTED_DEVICE
;
946 max_device
= ATOM_MAX_SUPPORTED_DEVICE_INFO
;
948 for (i
= 0; i
< max_device
; i
++) {
949 ATOM_CONNECTOR_INFO_I2C ci
=
950 supported_devices
->info
.asConnInfo
[i
];
952 bios_connectors
[i
].valid
= false;
954 if (!(device_support
& (1 << i
))) {
958 if (i
== ATOM_DEVICE_CV_INDEX
) {
959 DRM_DEBUG_KMS("Skipping Component Video\n");
963 bios_connectors
[i
].connector_type
=
964 supported_devices_connector_convert
[ci
.sucConnectorInfo
.
968 if (bios_connectors
[i
].connector_type
==
969 DRM_MODE_CONNECTOR_Unknown
)
972 dac
= ci
.sucConnectorInfo
.sbfAccess
.bfAssociatedDAC
;
974 bios_connectors
[i
].line_mux
=
975 ci
.sucI2cId
.ucAccess
;
977 /* give tv unique connector ids */
978 if (i
== ATOM_DEVICE_TV1_INDEX
) {
979 bios_connectors
[i
].ddc_bus
.valid
= false;
980 bios_connectors
[i
].line_mux
= 50;
981 } else if (i
== ATOM_DEVICE_TV2_INDEX
) {
982 bios_connectors
[i
].ddc_bus
.valid
= false;
983 bios_connectors
[i
].line_mux
= 51;
984 } else if (i
== ATOM_DEVICE_CV_INDEX
) {
985 bios_connectors
[i
].ddc_bus
.valid
= false;
986 bios_connectors
[i
].line_mux
= 52;
988 bios_connectors
[i
].ddc_bus
=
989 radeon_lookup_i2c_gpio(rdev
,
990 bios_connectors
[i
].line_mux
);
992 if ((crev
> 1) && (frev
> 1)) {
993 u8 isb
= supported_devices
->info_2d1
.asIntSrcInfo
[i
].ucIntSrcBitmap
;
996 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
999 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
1002 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
1006 if (i
== ATOM_DEVICE_DFP1_INDEX
)
1007 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
1008 else if (i
== ATOM_DEVICE_DFP2_INDEX
)
1009 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
1011 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
1014 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1015 * shared with a DVI port, we'll pick up the DVI connector when we
1016 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1018 if (i
== ATOM_DEVICE_CRT1_INDEX
|| i
== ATOM_DEVICE_CRT2_INDEX
)
1019 bios_connectors
[i
].connector_type
=
1020 DRM_MODE_CONNECTOR_VGA
;
1022 if (!radeon_atom_apply_quirks
1023 (dev
, (1 << i
), &bios_connectors
[i
].connector_type
,
1024 &bios_connectors
[i
].ddc_bus
, &bios_connectors
[i
].line_mux
,
1025 &bios_connectors
[i
].hpd
))
1028 bios_connectors
[i
].valid
= true;
1029 bios_connectors
[i
].devices
= (1 << i
);
1031 if (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
)
1032 radeon_add_atom_encoder(dev
,
1033 radeon_get_encoder_enum(dev
,
1039 radeon_add_legacy_encoder(dev
,
1040 radeon_get_encoder_enum(dev
,
1046 /* combine shared connectors */
1047 for (i
= 0; i
< max_device
; i
++) {
1048 if (bios_connectors
[i
].valid
) {
1049 for (j
= 0; j
< max_device
; j
++) {
1050 if (bios_connectors
[j
].valid
&& (i
!= j
)) {
1051 if (bios_connectors
[i
].line_mux
==
1052 bios_connectors
[j
].line_mux
) {
1053 /* make sure not to combine LVDS */
1054 if (bios_connectors
[i
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1055 bios_connectors
[i
].line_mux
= 53;
1056 bios_connectors
[i
].ddc_bus
.valid
= false;
1059 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1060 bios_connectors
[j
].line_mux
= 53;
1061 bios_connectors
[j
].ddc_bus
.valid
= false;
1064 /* combine analog and digital for DVI-I */
1065 if (((bios_connectors
[i
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
1066 (bios_connectors
[j
].devices
& (ATOM_DEVICE_CRT_SUPPORT
))) ||
1067 ((bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
1068 (bios_connectors
[i
].devices
& (ATOM_DEVICE_CRT_SUPPORT
)))) {
1069 bios_connectors
[i
].devices
|=
1070 bios_connectors
[j
].devices
;
1071 bios_connectors
[i
].connector_type
=
1072 DRM_MODE_CONNECTOR_DVII
;
1073 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
))
1074 bios_connectors
[i
].hpd
=
1075 bios_connectors
[j
].hpd
;
1076 bios_connectors
[j
].valid
= false;
1084 /* add the connectors */
1085 for (i
= 0; i
< max_device
; i
++) {
1086 if (bios_connectors
[i
].valid
) {
1087 uint16_t connector_object_id
=
1088 atombios_get_connector_object_id(dev
,
1089 bios_connectors
[i
].connector_type
,
1090 bios_connectors
[i
].devices
);
1091 radeon_add_atom_connector(dev
,
1092 bios_connectors
[i
].line_mux
,
1093 bios_connectors
[i
].devices
,
1096 &bios_connectors
[i
].ddc_bus
,
1098 connector_object_id
,
1099 &bios_connectors
[i
].hpd
,
1104 radeon_link_encoder_connector(dev
);
1106 kfree(bios_connectors
);
1110 union firmware_info
{
1111 ATOM_FIRMWARE_INFO info
;
1112 ATOM_FIRMWARE_INFO_V1_2 info_12
;
1113 ATOM_FIRMWARE_INFO_V1_3 info_13
;
1114 ATOM_FIRMWARE_INFO_V1_4 info_14
;
1115 ATOM_FIRMWARE_INFO_V2_1 info_21
;
1116 ATOM_FIRMWARE_INFO_V2_2 info_22
;
1119 bool radeon_atom_get_clock_info(struct drm_device
*dev
)
1121 struct radeon_device
*rdev
= dev
->dev_private
;
1122 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1123 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
1124 union firmware_info
*firmware_info
;
1126 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
1127 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
1128 struct radeon_pll
*dcpll
= &rdev
->clock
.dcpll
;
1129 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
1130 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
1131 uint16_t data_offset
;
1133 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1134 &frev
, &crev
, &data_offset
)) {
1136 (union firmware_info
*)(mode_info
->atom_context
->bios
+
1139 p1pll
->reference_freq
=
1140 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1141 p1pll
->reference_div
= 0;
1144 p1pll
->pll_out_min
=
1145 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Output
);
1147 p1pll
->pll_out_min
=
1148 le32_to_cpu(firmware_info
->info_12
.ulMinPixelClockPLL_Output
);
1149 p1pll
->pll_out_max
=
1150 le32_to_cpu(firmware_info
->info
.ulMaxPixelClockPLL_Output
);
1153 p1pll
->lcd_pll_out_min
=
1154 le16_to_cpu(firmware_info
->info_14
.usLcdMinPixelClockPLL_Output
) * 100;
1155 if (p1pll
->lcd_pll_out_min
== 0)
1156 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1157 p1pll
->lcd_pll_out_max
=
1158 le16_to_cpu(firmware_info
->info_14
.usLcdMaxPixelClockPLL_Output
) * 100;
1159 if (p1pll
->lcd_pll_out_max
== 0)
1160 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1162 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1163 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1166 if (p1pll
->pll_out_min
== 0) {
1167 if (ASIC_IS_AVIVO(rdev
))
1168 p1pll
->pll_out_min
= 64800;
1170 p1pll
->pll_out_min
= 20000;
1174 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Input
);
1176 le16_to_cpu(firmware_info
->info
.usMaxPixelClockPLL_Input
);
1181 if (ASIC_IS_DCE4(rdev
))
1182 spll
->reference_freq
=
1183 le16_to_cpu(firmware_info
->info_21
.usCoreReferenceClock
);
1185 spll
->reference_freq
=
1186 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1187 spll
->reference_div
= 0;
1190 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Output
);
1192 le32_to_cpu(firmware_info
->info
.ulMaxEngineClockPLL_Output
);
1195 if (spll
->pll_out_min
== 0) {
1196 if (ASIC_IS_AVIVO(rdev
))
1197 spll
->pll_out_min
= 64800;
1199 spll
->pll_out_min
= 20000;
1203 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Input
);
1205 le16_to_cpu(firmware_info
->info
.usMaxEngineClockPLL_Input
);
1208 if (ASIC_IS_DCE4(rdev
))
1209 mpll
->reference_freq
=
1210 le16_to_cpu(firmware_info
->info_21
.usMemoryReferenceClock
);
1212 mpll
->reference_freq
=
1213 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1214 mpll
->reference_div
= 0;
1217 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Output
);
1219 le32_to_cpu(firmware_info
->info
.ulMaxMemoryClockPLL_Output
);
1222 if (mpll
->pll_out_min
== 0) {
1223 if (ASIC_IS_AVIVO(rdev
))
1224 mpll
->pll_out_min
= 64800;
1226 mpll
->pll_out_min
= 20000;
1230 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Input
);
1232 le16_to_cpu(firmware_info
->info
.usMaxMemoryClockPLL_Input
);
1234 rdev
->clock
.default_sclk
=
1235 le32_to_cpu(firmware_info
->info
.ulDefaultEngineClock
);
1236 rdev
->clock
.default_mclk
=
1237 le32_to_cpu(firmware_info
->info
.ulDefaultMemoryClock
);
1239 if (ASIC_IS_DCE4(rdev
)) {
1240 rdev
->clock
.default_dispclk
=
1241 le32_to_cpu(firmware_info
->info_21
.ulDefaultDispEngineClkFreq
);
1242 if (rdev
->clock
.default_dispclk
== 0) {
1243 if (ASIC_IS_DCE5(rdev
))
1244 rdev
->clock
.default_dispclk
= 54000; /* 540 Mhz */
1246 rdev
->clock
.default_dispclk
= 60000; /* 600 Mhz */
1248 rdev
->clock
.dp_extclk
=
1249 le16_to_cpu(firmware_info
->info_21
.usUniphyDPModeExtClkFreq
);
1253 rdev
->clock
.max_pixel_clock
= le16_to_cpu(firmware_info
->info
.usMaxPixelClock
);
1254 if (rdev
->clock
.max_pixel_clock
== 0)
1255 rdev
->clock
.max_pixel_clock
= 40000;
1257 /* not technically a clock, but... */
1258 rdev
->mode_info
.firmware_flags
=
1259 le16_to_cpu(firmware_info
->info
.usFirmwareCapability
.susAccess
);
1268 struct _ATOM_INTEGRATED_SYSTEM_INFO info
;
1269 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2
;
1270 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6
;
1271 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7
;
1272 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8
;
1275 bool radeon_atombios_sideport_present(struct radeon_device
*rdev
)
1277 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1278 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1279 union igp_info
*igp_info
;
1283 /* sideport is AMD only */
1284 if (rdev
->family
== CHIP_RS600
)
1287 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1288 &frev
, &crev
, &data_offset
)) {
1289 igp_info
= (union igp_info
*)(mode_info
->atom_context
->bios
+
1293 if (le32_to_cpu(igp_info
->info
.ulBootUpMemoryClock
))
1297 if (le32_to_cpu(igp_info
->info_2
.ulBootUpSidePortClock
))
1301 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
1308 bool radeon_atombios_get_tmds_info(struct radeon_encoder
*encoder
,
1309 struct radeon_encoder_int_tmds
*tmds
)
1311 struct drm_device
*dev
= encoder
->base
.dev
;
1312 struct radeon_device
*rdev
= dev
->dev_private
;
1313 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1314 int index
= GetIndexIntoMasterTable(DATA
, TMDS_Info
);
1315 uint16_t data_offset
;
1316 struct _ATOM_TMDS_INFO
*tmds_info
;
1321 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1322 &frev
, &crev
, &data_offset
)) {
1324 (struct _ATOM_TMDS_INFO
*)(mode_info
->atom_context
->bios
+
1327 maxfreq
= le16_to_cpu(tmds_info
->usMaxFrequency
);
1328 for (i
= 0; i
< 4; i
++) {
1329 tmds
->tmds_pll
[i
].freq
=
1330 le16_to_cpu(tmds_info
->asMiscInfo
[i
].usFrequency
);
1331 tmds
->tmds_pll
[i
].value
=
1332 tmds_info
->asMiscInfo
[i
].ucPLL_ChargePump
& 0x3f;
1333 tmds
->tmds_pll
[i
].value
|=
1334 (tmds_info
->asMiscInfo
[i
].
1335 ucPLL_VCO_Gain
& 0x3f) << 6;
1336 tmds
->tmds_pll
[i
].value
|=
1337 (tmds_info
->asMiscInfo
[i
].
1338 ucPLL_DutyCycle
& 0xf) << 12;
1339 tmds
->tmds_pll
[i
].value
|=
1340 (tmds_info
->asMiscInfo
[i
].
1341 ucPLL_VoltageSwing
& 0xf) << 16;
1343 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1344 tmds
->tmds_pll
[i
].freq
,
1345 tmds
->tmds_pll
[i
].value
);
1347 if (maxfreq
== tmds
->tmds_pll
[i
].freq
) {
1348 tmds
->tmds_pll
[i
].freq
= 0xffffffff;
1357 bool radeon_atombios_get_ppll_ss_info(struct radeon_device
*rdev
,
1358 struct radeon_atom_ss
*ss
,
1361 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1362 int index
= GetIndexIntoMasterTable(DATA
, PPLL_SS_Info
);
1363 uint16_t data_offset
, size
;
1364 struct _ATOM_SPREAD_SPECTRUM_INFO
*ss_info
;
1368 memset(ss
, 0, sizeof(struct radeon_atom_ss
));
1369 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1370 &frev
, &crev
, &data_offset
)) {
1372 (struct _ATOM_SPREAD_SPECTRUM_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1374 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1375 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT
);
1377 for (i
= 0; i
< num_indices
; i
++) {
1378 if (ss_info
->asSS_Info
[i
].ucSS_Id
== id
) {
1380 le16_to_cpu(ss_info
->asSS_Info
[i
].usSpreadSpectrumPercentage
);
1381 ss
->type
= ss_info
->asSS_Info
[i
].ucSpreadSpectrumType
;
1382 ss
->step
= ss_info
->asSS_Info
[i
].ucSS_Step
;
1383 ss
->delay
= ss_info
->asSS_Info
[i
].ucSS_Delay
;
1384 ss
->range
= ss_info
->asSS_Info
[i
].ucSS_Range
;
1385 ss
->refdiv
= ss_info
->asSS_Info
[i
].ucRecommendedRef_Div
;
1393 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device
*rdev
,
1394 struct radeon_atom_ss
*ss
,
1397 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1398 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1399 u16 data_offset
, size
;
1400 union igp_info
*igp_info
;
1402 u16 percentage
= 0, rate
= 0;
1404 /* get any igp specific overrides */
1405 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1406 &frev
, &crev
, &data_offset
)) {
1407 igp_info
= (union igp_info
*)
1408 (mode_info
->atom_context
->bios
+ data_offset
);
1412 case ASIC_INTERNAL_SS_ON_TMDS
:
1413 percentage
= le16_to_cpu(igp_info
->info_6
.usDVISSPercentage
);
1414 rate
= le16_to_cpu(igp_info
->info_6
.usDVISSpreadRateIn10Hz
);
1416 case ASIC_INTERNAL_SS_ON_HDMI
:
1417 percentage
= le16_to_cpu(igp_info
->info_6
.usHDMISSPercentage
);
1418 rate
= le16_to_cpu(igp_info
->info_6
.usHDMISSpreadRateIn10Hz
);
1420 case ASIC_INTERNAL_SS_ON_LVDS
:
1421 percentage
= le16_to_cpu(igp_info
->info_6
.usLvdsSSPercentage
);
1422 rate
= le16_to_cpu(igp_info
->info_6
.usLvdsSSpreadRateIn10Hz
);
1428 case ASIC_INTERNAL_SS_ON_TMDS
:
1429 percentage
= le16_to_cpu(igp_info
->info_7
.usDVISSPercentage
);
1430 rate
= le16_to_cpu(igp_info
->info_7
.usDVISSpreadRateIn10Hz
);
1432 case ASIC_INTERNAL_SS_ON_HDMI
:
1433 percentage
= le16_to_cpu(igp_info
->info_7
.usHDMISSPercentage
);
1434 rate
= le16_to_cpu(igp_info
->info_7
.usHDMISSpreadRateIn10Hz
);
1436 case ASIC_INTERNAL_SS_ON_LVDS
:
1437 percentage
= le16_to_cpu(igp_info
->info_7
.usLvdsSSPercentage
);
1438 rate
= le16_to_cpu(igp_info
->info_7
.usLvdsSSpreadRateIn10Hz
);
1444 case ASIC_INTERNAL_SS_ON_TMDS
:
1445 percentage
= le16_to_cpu(igp_info
->info_8
.usDVISSPercentage
);
1446 rate
= le16_to_cpu(igp_info
->info_8
.usDVISSpreadRateIn10Hz
);
1448 case ASIC_INTERNAL_SS_ON_HDMI
:
1449 percentage
= le16_to_cpu(igp_info
->info_8
.usHDMISSPercentage
);
1450 rate
= le16_to_cpu(igp_info
->info_8
.usHDMISSpreadRateIn10Hz
);
1452 case ASIC_INTERNAL_SS_ON_LVDS
:
1453 percentage
= le16_to_cpu(igp_info
->info_8
.usLvdsSSPercentage
);
1454 rate
= le16_to_cpu(igp_info
->info_8
.usLvdsSSpreadRateIn10Hz
);
1459 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
1463 ss
->percentage
= percentage
;
1469 union asic_ss_info
{
1470 struct _ATOM_ASIC_INTERNAL_SS_INFO info
;
1471 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2
;
1472 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3
;
1475 bool radeon_atombios_get_asic_ss_info(struct radeon_device
*rdev
,
1476 struct radeon_atom_ss
*ss
,
1479 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1480 int index
= GetIndexIntoMasterTable(DATA
, ASIC_InternalSS_Info
);
1481 uint16_t data_offset
, size
;
1482 union asic_ss_info
*ss_info
;
1486 memset(ss
, 0, sizeof(struct radeon_atom_ss
));
1487 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1488 &frev
, &crev
, &data_offset
)) {
1491 (union asic_ss_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1495 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1496 sizeof(ATOM_ASIC_SS_ASSIGNMENT
);
1498 for (i
= 0; i
< num_indices
; i
++) {
1499 if ((ss_info
->info
.asSpreadSpectrum
[i
].ucClockIndication
== id
) &&
1500 (clock
<= le32_to_cpu(ss_info
->info
.asSpreadSpectrum
[i
].ulTargetClockRange
))) {
1502 le16_to_cpu(ss_info
->info
.asSpreadSpectrum
[i
].usSpreadSpectrumPercentage
);
1503 ss
->type
= ss_info
->info
.asSpreadSpectrum
[i
].ucSpreadSpectrumMode
;
1504 ss
->rate
= le16_to_cpu(ss_info
->info
.asSpreadSpectrum
[i
].usSpreadRateInKhz
);
1510 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1511 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2
);
1512 for (i
= 0; i
< num_indices
; i
++) {
1513 if ((ss_info
->info_2
.asSpreadSpectrum
[i
].ucClockIndication
== id
) &&
1514 (clock
<= le32_to_cpu(ss_info
->info_2
.asSpreadSpectrum
[i
].ulTargetClockRange
))) {
1516 le16_to_cpu(ss_info
->info_2
.asSpreadSpectrum
[i
].usSpreadSpectrumPercentage
);
1517 ss
->type
= ss_info
->info_2
.asSpreadSpectrum
[i
].ucSpreadSpectrumMode
;
1518 ss
->rate
= le16_to_cpu(ss_info
->info_2
.asSpreadSpectrum
[i
].usSpreadRateIn10Hz
);
1524 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1525 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3
);
1526 for (i
= 0; i
< num_indices
; i
++) {
1527 if ((ss_info
->info_3
.asSpreadSpectrum
[i
].ucClockIndication
== id
) &&
1528 (clock
<= le32_to_cpu(ss_info
->info_3
.asSpreadSpectrum
[i
].ulTargetClockRange
))) {
1530 le16_to_cpu(ss_info
->info_3
.asSpreadSpectrum
[i
].usSpreadSpectrumPercentage
);
1531 ss
->type
= ss_info
->info_3
.asSpreadSpectrum
[i
].ucSpreadSpectrumMode
;
1532 ss
->rate
= le16_to_cpu(ss_info
->info_3
.asSpreadSpectrum
[i
].usSpreadRateIn10Hz
);
1533 if (rdev
->flags
& RADEON_IS_IGP
)
1534 radeon_atombios_get_igp_ss_overrides(rdev
, ss
, id
);
1540 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev
, crev
);
1549 struct _ATOM_LVDS_INFO info
;
1550 struct _ATOM_LVDS_INFO_V12 info_12
;
1553 struct radeon_encoder_atom_dig
*radeon_atombios_get_lvds_info(struct
1557 struct drm_device
*dev
= encoder
->base
.dev
;
1558 struct radeon_device
*rdev
= dev
->dev_private
;
1559 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1560 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
1561 uint16_t data_offset
, misc
;
1562 union lvds_info
*lvds_info
;
1564 struct radeon_encoder_atom_dig
*lvds
= NULL
;
1565 int encoder_enum
= (encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1567 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1568 &frev
, &crev
, &data_offset
)) {
1570 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1572 kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
1577 lvds
->native_mode
.clock
=
1578 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
1579 lvds
->native_mode
.hdisplay
=
1580 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
1581 lvds
->native_mode
.vdisplay
=
1582 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
1583 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
1584 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
1585 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
1586 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
1587 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
1588 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
1589 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
1590 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
1591 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
1592 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncOffset
);
1593 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
1594 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
1595 lvds
->panel_pwr_delay
=
1596 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
1597 lvds
->lcd_misc
= lvds_info
->info
.ucLVDS_Misc
;
1599 misc
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.susModeMiscInfo
.usAccess
);
1600 if (misc
& ATOM_VSYNC_POLARITY
)
1601 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
1602 if (misc
& ATOM_HSYNC_POLARITY
)
1603 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
1604 if (misc
& ATOM_COMPOSITESYNC
)
1605 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_CSYNC
;
1606 if (misc
& ATOM_INTERLACE
)
1607 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
1608 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1609 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_DBLSCAN
;
1611 lvds
->native_mode
.width_mm
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.usImageHSize
);
1612 lvds
->native_mode
.height_mm
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.usImageVSize
);
1614 /* set crtc values */
1615 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1617 lvds
->lcd_ss_id
= lvds_info
->info
.ucSS_Id
;
1619 encoder
->native_mode
= lvds
->native_mode
;
1621 if (encoder_enum
== 2)
1624 lvds
->linkb
= false;
1626 /* parse the lcd record table */
1627 if (le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
)) {
1628 ATOM_FAKE_EDID_PATCH_RECORD
*fake_edid_record
;
1629 ATOM_PANEL_RESOLUTION_PATCH_RECORD
*panel_res_record
;
1630 bool bad_record
= false;
1633 if ((frev
== 1) && (crev
< 2))
1635 record
= (u8
*)(mode_info
->atom_context
->bios
+
1636 le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
));
1639 record
= (u8
*)(mode_info
->atom_context
->bios
+
1641 le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
));
1642 while (*record
!= ATOM_RECORD_END_TYPE
) {
1644 case LCD_MODE_PATCH_RECORD_MODE_TYPE
:
1645 record
+= sizeof(ATOM_PATCH_RECORD_MODE
);
1647 case LCD_RTS_RECORD_TYPE
:
1648 record
+= sizeof(ATOM_LCD_RTS_RECORD
);
1650 case LCD_CAP_RECORD_TYPE
:
1651 record
+= sizeof(ATOM_LCD_MODE_CONTROL_CAP
);
1653 case LCD_FAKE_EDID_PATCH_RECORD_TYPE
:
1654 fake_edid_record
= (ATOM_FAKE_EDID_PATCH_RECORD
*)record
;
1655 if (fake_edid_record
->ucFakeEDIDLength
) {
1658 max((int)EDID_LENGTH
, (int)fake_edid_record
->ucFakeEDIDLength
);
1659 edid
= kmalloc(edid_size
, GFP_KERNEL
);
1661 memcpy((u8
*)edid
, (u8
*)&fake_edid_record
->ucFakeEDIDString
[0],
1662 fake_edid_record
->ucFakeEDIDLength
);
1664 if (drm_edid_is_valid(edid
)) {
1665 rdev
->mode_info
.bios_hardcoded_edid
= edid
;
1666 rdev
->mode_info
.bios_hardcoded_edid_size
= edid_size
;
1671 record
+= sizeof(ATOM_FAKE_EDID_PATCH_RECORD
);
1673 case LCD_PANEL_RESOLUTION_RECORD_TYPE
:
1674 panel_res_record
= (ATOM_PANEL_RESOLUTION_PATCH_RECORD
*)record
;
1675 lvds
->native_mode
.width_mm
= panel_res_record
->usHSize
;
1676 lvds
->native_mode
.height_mm
= panel_res_record
->usVSize
;
1677 record
+= sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD
);
1680 DRM_ERROR("Bad LCD record %d\n", *record
);
1692 struct radeon_encoder_primary_dac
*
1693 radeon_atombios_get_primary_dac_info(struct radeon_encoder
*encoder
)
1695 struct drm_device
*dev
= encoder
->base
.dev
;
1696 struct radeon_device
*rdev
= dev
->dev_private
;
1697 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1698 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1699 uint16_t data_offset
;
1700 struct _COMPASSIONATE_DATA
*dac_info
;
1703 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
1705 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1706 &frev
, &crev
, &data_offset
)) {
1707 dac_info
= (struct _COMPASSIONATE_DATA
*)
1708 (mode_info
->atom_context
->bios
+ data_offset
);
1710 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
), GFP_KERNEL
);
1715 bg
= dac_info
->ucDAC1_BG_Adjustment
;
1716 dac
= dac_info
->ucDAC1_DAC_Adjustment
;
1717 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
1723 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
1724 struct drm_display_mode
*mode
)
1726 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1727 ATOM_ANALOG_TV_INFO
*tv_info
;
1728 ATOM_ANALOG_TV_INFO_V1_2
*tv_info_v1_2
;
1729 ATOM_DTD_FORMAT
*dtd_timings
;
1730 int data_index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1732 u16 data_offset
, misc
;
1734 if (!atom_parse_data_header(mode_info
->atom_context
, data_index
, NULL
,
1735 &frev
, &crev
, &data_offset
))
1740 tv_info
= (ATOM_ANALOG_TV_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1741 if (index
>= MAX_SUPPORTED_TV_TIMING
)
1744 mode
->crtc_htotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Total
);
1745 mode
->crtc_hdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Disp
);
1746 mode
->crtc_hsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
);
1747 mode
->crtc_hsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
) +
1748 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncWidth
);
1750 mode
->crtc_vtotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Total
);
1751 mode
->crtc_vdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Disp
);
1752 mode
->crtc_vsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
);
1753 mode
->crtc_vsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
) +
1754 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncWidth
);
1757 misc
= le16_to_cpu(tv_info
->aModeTimings
[index
].susModeMiscInfo
.usAccess
);
1758 if (misc
& ATOM_VSYNC_POLARITY
)
1759 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1760 if (misc
& ATOM_HSYNC_POLARITY
)
1761 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1762 if (misc
& ATOM_COMPOSITESYNC
)
1763 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1764 if (misc
& ATOM_INTERLACE
)
1765 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1766 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1767 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1769 mode
->clock
= le16_to_cpu(tv_info
->aModeTimings
[index
].usPixelClock
) * 10;
1772 /* PAL timings appear to have wrong values for totals */
1773 mode
->crtc_htotal
-= 1;
1774 mode
->crtc_vtotal
-= 1;
1778 tv_info_v1_2
= (ATOM_ANALOG_TV_INFO_V1_2
*)(mode_info
->atom_context
->bios
+ data_offset
);
1779 if (index
>= MAX_SUPPORTED_TV_TIMING_V1_2
)
1782 dtd_timings
= &tv_info_v1_2
->aModeTimings
[index
];
1783 mode
->crtc_htotal
= le16_to_cpu(dtd_timings
->usHActive
) +
1784 le16_to_cpu(dtd_timings
->usHBlanking_Time
);
1785 mode
->crtc_hdisplay
= le16_to_cpu(dtd_timings
->usHActive
);
1786 mode
->crtc_hsync_start
= le16_to_cpu(dtd_timings
->usHActive
) +
1787 le16_to_cpu(dtd_timings
->usHSyncOffset
);
1788 mode
->crtc_hsync_end
= mode
->crtc_hsync_start
+
1789 le16_to_cpu(dtd_timings
->usHSyncWidth
);
1791 mode
->crtc_vtotal
= le16_to_cpu(dtd_timings
->usVActive
) +
1792 le16_to_cpu(dtd_timings
->usVBlanking_Time
);
1793 mode
->crtc_vdisplay
= le16_to_cpu(dtd_timings
->usVActive
);
1794 mode
->crtc_vsync_start
= le16_to_cpu(dtd_timings
->usVActive
) +
1795 le16_to_cpu(dtd_timings
->usVSyncOffset
);
1796 mode
->crtc_vsync_end
= mode
->crtc_vsync_start
+
1797 le16_to_cpu(dtd_timings
->usVSyncWidth
);
1800 misc
= le16_to_cpu(dtd_timings
->susModeMiscInfo
.usAccess
);
1801 if (misc
& ATOM_VSYNC_POLARITY
)
1802 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1803 if (misc
& ATOM_HSYNC_POLARITY
)
1804 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1805 if (misc
& ATOM_COMPOSITESYNC
)
1806 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1807 if (misc
& ATOM_INTERLACE
)
1808 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1809 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1810 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1812 mode
->clock
= le16_to_cpu(dtd_timings
->usPixClk
) * 10;
1819 radeon_atombios_get_tv_info(struct radeon_device
*rdev
)
1821 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1822 int index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1823 uint16_t data_offset
;
1825 struct _ATOM_ANALOG_TV_INFO
*tv_info
;
1826 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
1828 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1829 &frev
, &crev
, &data_offset
)) {
1831 tv_info
= (struct _ATOM_ANALOG_TV_INFO
*)
1832 (mode_info
->atom_context
->bios
+ data_offset
);
1834 switch (tv_info
->ucTV_BootUpDefaultStandard
) {
1836 tv_std
= TV_STD_NTSC
;
1837 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1840 tv_std
= TV_STD_NTSC_J
;
1841 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1844 tv_std
= TV_STD_PAL
;
1845 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1848 tv_std
= TV_STD_PAL_M
;
1849 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1852 tv_std
= TV_STD_PAL_N
;
1853 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1856 tv_std
= TV_STD_PAL_CN
;
1857 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1860 tv_std
= TV_STD_PAL_60
;
1861 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1864 tv_std
= TV_STD_SECAM
;
1865 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1868 tv_std
= TV_STD_NTSC
;
1869 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1876 struct radeon_encoder_tv_dac
*
1877 radeon_atombios_get_tv_dac_info(struct radeon_encoder
*encoder
)
1879 struct drm_device
*dev
= encoder
->base
.dev
;
1880 struct radeon_device
*rdev
= dev
->dev_private
;
1881 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1882 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1883 uint16_t data_offset
;
1884 struct _COMPASSIONATE_DATA
*dac_info
;
1887 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1889 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1890 &frev
, &crev
, &data_offset
)) {
1892 dac_info
= (struct _COMPASSIONATE_DATA
*)
1893 (mode_info
->atom_context
->bios
+ data_offset
);
1895 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1900 bg
= dac_info
->ucDAC2_CRT2_BG_Adjustment
;
1901 dac
= dac_info
->ucDAC2_CRT2_DAC_Adjustment
;
1902 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1904 bg
= dac_info
->ucDAC2_PAL_BG_Adjustment
;
1905 dac
= dac_info
->ucDAC2_PAL_DAC_Adjustment
;
1906 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1908 bg
= dac_info
->ucDAC2_NTSC_BG_Adjustment
;
1909 dac
= dac_info
->ucDAC2_NTSC_DAC_Adjustment
;
1910 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1912 tv_dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
1917 static const char *thermal_controller_names
[] = {
1928 static const char *pp_lib_thermal_controller_names
[] = {
1951 struct _ATOM_POWERPLAY_INFO info
;
1952 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
1953 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
1954 struct _ATOM_PPLIB_POWERPLAYTABLE pplib
;
1955 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2
;
1956 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3
;
1959 union pplib_clock_info
{
1960 struct _ATOM_PPLIB_R600_CLOCK_INFO r600
;
1961 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780
;
1962 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen
;
1963 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo
;
1964 struct _ATOM_PPLIB_SI_CLOCK_INFO si
;
1965 struct _ATOM_PPLIB_CI_CLOCK_INFO ci
;
1968 union pplib_power_state
{
1969 struct _ATOM_PPLIB_STATE v1
;
1970 struct _ATOM_PPLIB_STATE_V2 v2
;
1973 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device
*rdev
,
1975 u32 misc
, u32 misc2
)
1977 rdev
->pm
.power_state
[state_index
].misc
= misc
;
1978 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
1979 /* order matters! */
1980 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
1981 rdev
->pm
.power_state
[state_index
].type
=
1982 POWER_STATE_TYPE_POWERSAVE
;
1983 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
1984 rdev
->pm
.power_state
[state_index
].type
=
1985 POWER_STATE_TYPE_BATTERY
;
1986 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
1987 rdev
->pm
.power_state
[state_index
].type
=
1988 POWER_STATE_TYPE_BATTERY
;
1989 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
1990 rdev
->pm
.power_state
[state_index
].type
=
1991 POWER_STATE_TYPE_BALANCED
;
1992 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
) {
1993 rdev
->pm
.power_state
[state_index
].type
=
1994 POWER_STATE_TYPE_PERFORMANCE
;
1995 rdev
->pm
.power_state
[state_index
].flags
&=
1996 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1998 if (misc2
& ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE
)
1999 rdev
->pm
.power_state
[state_index
].type
=
2000 POWER_STATE_TYPE_BALANCED
;
2001 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
2002 rdev
->pm
.power_state
[state_index
].type
=
2003 POWER_STATE_TYPE_DEFAULT
;
2004 rdev
->pm
.default_power_state_index
= state_index
;
2005 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2006 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2007 } else if (state_index
== 0) {
2008 rdev
->pm
.power_state
[state_index
].clock_info
[0].flags
|=
2009 RADEON_PM_MODE_NO_DISPLAY
;
2013 static int radeon_atombios_parse_power_table_1_3(struct radeon_device
*rdev
)
2015 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2016 u32 misc
, misc2
= 0;
2017 int num_modes
= 0, i
;
2018 int state_index
= 0;
2019 struct radeon_i2c_bus_rec i2c_bus
;
2020 union power_info
*power_info
;
2021 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2025 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2026 &frev
, &crev
, &data_offset
))
2028 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
2030 /* add the i2c bus for thermal/fan chip */
2031 if ((power_info
->info
.ucOverdriveThermalController
> 0) &&
2032 (power_info
->info
.ucOverdriveThermalController
< ARRAY_SIZE(thermal_controller_names
))) {
2033 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2034 thermal_controller_names
[power_info
->info
.ucOverdriveThermalController
],
2035 power_info
->info
.ucOverdriveControllerAddress
>> 1);
2036 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, power_info
->info
.ucOverdriveI2cLine
);
2037 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
2038 if (rdev
->pm
.i2c_bus
) {
2039 struct i2c_board_info info
= { };
2040 const char *name
= thermal_controller_names
[power_info
->info
.
2041 ucOverdriveThermalController
];
2042 info
.addr
= power_info
->info
.ucOverdriveControllerAddress
>> 1;
2043 strlcpy(info
.type
, name
, sizeof(info
.type
));
2044 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
2047 num_modes
= power_info
->info
.ucNumOfPowerModeEntries
;
2048 if (num_modes
> ATOM_MAX_NUMBEROF_POWER_BLOCK
)
2049 num_modes
= ATOM_MAX_NUMBEROF_POWER_BLOCK
;
2052 rdev
->pm
.power_state
= kzalloc(sizeof(struct radeon_power_state
) * num_modes
, GFP_KERNEL
);
2053 if (!rdev
->pm
.power_state
)
2055 /* last mode is usually default, array is low to high */
2056 for (i
= 0; i
< num_modes
; i
++) {
2057 rdev
->pm
.power_state
[state_index
].clock_info
=
2058 kzalloc(sizeof(struct radeon_pm_clock_info
) * 1, GFP_KERNEL
);
2059 if (!rdev
->pm
.power_state
[state_index
].clock_info
)
2061 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2062 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2065 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2066 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usMemoryClock
);
2067 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2068 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usEngineClock
);
2069 /* skip invalid modes */
2070 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2071 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2073 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2074 power_info
->info
.asPowerPlayInfo
[i
].ucNumPciELanes
;
2075 misc
= le32_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].ulMiscInfo
);
2076 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
2077 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
2078 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2080 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
2081 radeon_lookup_gpio(rdev
,
2082 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
2083 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
2084 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2087 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2089 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
2090 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2092 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
2093 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
2095 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2096 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, 0);
2100 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2101 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMemoryClock
);
2102 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2103 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulEngineClock
);
2104 /* skip invalid modes */
2105 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2106 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2108 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2109 power_info
->info_2
.asPowerPlayInfo
[i
].ucNumPciELanes
;
2110 misc
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo
);
2111 misc2
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo2
);
2112 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
2113 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
2114 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2116 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
2117 radeon_lookup_gpio(rdev
,
2118 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
2119 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
2120 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2123 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2125 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
2126 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2128 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
2129 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
2131 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2132 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, misc2
);
2136 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2137 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMemoryClock
);
2138 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2139 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulEngineClock
);
2140 /* skip invalid modes */
2141 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2142 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2144 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2145 power_info
->info_3
.asPowerPlayInfo
[i
].ucNumPciELanes
;
2146 misc
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo
);
2147 misc2
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo2
);
2148 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
2149 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
2150 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2152 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
2153 radeon_lookup_gpio(rdev
,
2154 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
2155 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
2156 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2159 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2161 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
2162 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2164 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
2165 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
2166 if (misc2
& ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN
) {
2167 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_enabled
=
2169 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_id
=
2170 power_info
->info_3
.asPowerPlayInfo
[i
].ucVDDCI_VoltageDropIndex
;
2173 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2174 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, misc2
);
2179 /* last mode is usually default */
2180 if (rdev
->pm
.default_power_state_index
== -1) {
2181 rdev
->pm
.power_state
[state_index
- 1].type
=
2182 POWER_STATE_TYPE_DEFAULT
;
2183 rdev
->pm
.default_power_state_index
= state_index
- 1;
2184 rdev
->pm
.power_state
[state_index
- 1].default_clock_mode
=
2185 &rdev
->pm
.power_state
[state_index
- 1].clock_info
[0];
2186 rdev
->pm
.power_state
[state_index
].flags
&=
2187 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2188 rdev
->pm
.power_state
[state_index
].misc
= 0;
2189 rdev
->pm
.power_state
[state_index
].misc2
= 0;
2194 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device
*rdev
,
2195 ATOM_PPLIB_THERMALCONTROLLER
*controller
)
2197 struct radeon_i2c_bus_rec i2c_bus
;
2199 /* add the i2c bus for thermal/fan chip */
2200 if (controller
->ucType
> 0) {
2201 if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV6xx
) {
2202 DRM_INFO("Internal thermal controller %s fan control\n",
2203 (controller
->ucFanParameters
&
2204 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2205 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV6XX
;
2206 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV770
) {
2207 DRM_INFO("Internal thermal controller %s fan control\n",
2208 (controller
->ucFanParameters
&
2209 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2210 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV770
;
2211 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_EVERGREEN
) {
2212 DRM_INFO("Internal thermal controller %s fan control\n",
2213 (controller
->ucFanParameters
&
2214 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2215 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_EVERGREEN
;
2216 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_SUMO
) {
2217 DRM_INFO("Internal thermal controller %s fan control\n",
2218 (controller
->ucFanParameters
&
2219 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2220 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_SUMO
;
2221 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_NISLANDS
) {
2222 DRM_INFO("Internal thermal controller %s fan control\n",
2223 (controller
->ucFanParameters
&
2224 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2225 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NI
;
2226 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_SISLANDS
) {
2227 DRM_INFO("Internal thermal controller %s fan control\n",
2228 (controller
->ucFanParameters
&
2229 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2230 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_SI
;
2231 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_CISLANDS
) {
2232 DRM_INFO("Internal thermal controller %s fan control\n",
2233 (controller
->ucFanParameters
&
2234 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2235 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_CI
;
2236 } else if ((controller
->ucType
==
2237 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO
) ||
2238 (controller
->ucType
==
2239 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL
) ||
2240 (controller
->ucType
==
2241 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL
)) {
2242 DRM_INFO("Special thermal controller config\n");
2243 } else if (controller
->ucType
< ARRAY_SIZE(pp_lib_thermal_controller_names
)) {
2244 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2245 pp_lib_thermal_controller_names
[controller
->ucType
],
2246 controller
->ucI2cAddress
>> 1,
2247 (controller
->ucFanParameters
&
2248 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2249 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, controller
->ucI2cLine
);
2250 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
2251 if (rdev
->pm
.i2c_bus
) {
2252 struct i2c_board_info info
= { };
2253 const char *name
= pp_lib_thermal_controller_names
[controller
->ucType
];
2254 info
.addr
= controller
->ucI2cAddress
>> 1;
2255 strlcpy(info
.type
, name
, sizeof(info
.type
));
2256 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
2259 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2261 controller
->ucI2cAddress
>> 1,
2262 (controller
->ucFanParameters
&
2263 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2268 static void radeon_atombios_get_default_voltages(struct radeon_device
*rdev
,
2269 u16
*vddc
, u16
*vddci
)
2271 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2272 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
2275 union firmware_info
*firmware_info
;
2280 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2281 &frev
, &crev
, &data_offset
)) {
2283 (union firmware_info
*)(mode_info
->atom_context
->bios
+
2285 *vddc
= le16_to_cpu(firmware_info
->info_14
.usBootUpVDDCVoltage
);
2286 if ((frev
== 2) && (crev
>= 2))
2287 *vddci
= le16_to_cpu(firmware_info
->info_22
.usBootUpVDDCIVoltage
);
2291 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device
*rdev
,
2292 int state_index
, int mode_index
,
2293 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
)
2296 u32 misc
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
2297 u32 misc2
= le16_to_cpu(non_clock_info
->usClassification
);
2300 radeon_atombios_get_default_voltages(rdev
, &vddc
, &vddci
);
2302 rdev
->pm
.power_state
[state_index
].misc
= misc
;
2303 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
2304 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2305 ((misc
& ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
) >>
2306 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
) + 1;
2307 switch (misc2
& ATOM_PPLIB_CLASSIFICATION_UI_MASK
) {
2308 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
:
2309 rdev
->pm
.power_state
[state_index
].type
=
2310 POWER_STATE_TYPE_BATTERY
;
2312 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
:
2313 rdev
->pm
.power_state
[state_index
].type
=
2314 POWER_STATE_TYPE_BALANCED
;
2316 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
:
2317 rdev
->pm
.power_state
[state_index
].type
=
2318 POWER_STATE_TYPE_PERFORMANCE
;
2320 case ATOM_PPLIB_CLASSIFICATION_UI_NONE
:
2321 if (misc2
& ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
2322 rdev
->pm
.power_state
[state_index
].type
=
2323 POWER_STATE_TYPE_PERFORMANCE
;
2326 rdev
->pm
.power_state
[state_index
].flags
= 0;
2327 if (misc
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
)
2328 rdev
->pm
.power_state
[state_index
].flags
|=
2329 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2330 if (misc2
& ATOM_PPLIB_CLASSIFICATION_BOOT
) {
2331 rdev
->pm
.power_state
[state_index
].type
=
2332 POWER_STATE_TYPE_DEFAULT
;
2333 rdev
->pm
.default_power_state_index
= state_index
;
2334 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2335 &rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
- 1];
2336 if ((rdev
->family
>= CHIP_BARTS
) && !(rdev
->flags
& RADEON_IS_IGP
)) {
2337 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2338 rdev
->pm
.default_sclk
= rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
;
2339 rdev
->pm
.default_mclk
= rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
;
2340 rdev
->pm
.default_vddc
= rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.voltage
;
2341 rdev
->pm
.default_vddci
= rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci
;
2343 /* patch the table values with the default slck/mclk from firmware info */
2344 for (j
= 0; j
< mode_index
; j
++) {
2345 rdev
->pm
.power_state
[state_index
].clock_info
[j
].mclk
=
2346 rdev
->clock
.default_mclk
;
2347 rdev
->pm
.power_state
[state_index
].clock_info
[j
].sclk
=
2348 rdev
->clock
.default_sclk
;
2350 rdev
->pm
.power_state
[state_index
].clock_info
[j
].voltage
.voltage
=
2357 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device
*rdev
,
2358 int state_index
, int mode_index
,
2359 union pplib_clock_info
*clock_info
)
2364 if (rdev
->flags
& RADEON_IS_IGP
) {
2365 if (rdev
->family
>= CHIP_PALM
) {
2366 sclk
= le16_to_cpu(clock_info
->sumo
.usEngineClockLow
);
2367 sclk
|= clock_info
->sumo
.ucEngineClockHigh
<< 16;
2368 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2370 sclk
= le16_to_cpu(clock_info
->rs780
.usLowEngineClockLow
);
2371 sclk
|= clock_info
->rs780
.ucLowEngineClockHigh
<< 16;
2372 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2374 } else if (rdev
->family
>= CHIP_BONAIRE
) {
2375 sclk
= le16_to_cpu(clock_info
->ci
.usEngineClockLow
);
2376 sclk
|= clock_info
->ci
.ucEngineClockHigh
<< 16;
2377 mclk
= le16_to_cpu(clock_info
->ci
.usMemoryClockLow
);
2378 mclk
|= clock_info
->ci
.ucMemoryClockHigh
<< 16;
2379 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2380 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2381 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2383 } else if (rdev
->family
>= CHIP_TAHITI
) {
2384 sclk
= le16_to_cpu(clock_info
->si
.usEngineClockLow
);
2385 sclk
|= clock_info
->si
.ucEngineClockHigh
<< 16;
2386 mclk
= le16_to_cpu(clock_info
->si
.usMemoryClockLow
);
2387 mclk
|= clock_info
->si
.ucMemoryClockHigh
<< 16;
2388 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2389 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2390 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2392 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2393 le16_to_cpu(clock_info
->si
.usVDDC
);
2394 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.vddci
=
2395 le16_to_cpu(clock_info
->si
.usVDDCI
);
2396 } else if (rdev
->family
>= CHIP_CEDAR
) {
2397 sclk
= le16_to_cpu(clock_info
->evergreen
.usEngineClockLow
);
2398 sclk
|= clock_info
->evergreen
.ucEngineClockHigh
<< 16;
2399 mclk
= le16_to_cpu(clock_info
->evergreen
.usMemoryClockLow
);
2400 mclk
|= clock_info
->evergreen
.ucMemoryClockHigh
<< 16;
2401 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2402 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2403 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2405 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2406 le16_to_cpu(clock_info
->evergreen
.usVDDC
);
2407 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.vddci
=
2408 le16_to_cpu(clock_info
->evergreen
.usVDDCI
);
2410 sclk
= le16_to_cpu(clock_info
->r600
.usEngineClockLow
);
2411 sclk
|= clock_info
->r600
.ucEngineClockHigh
<< 16;
2412 mclk
= le16_to_cpu(clock_info
->r600
.usMemoryClockLow
);
2413 mclk
|= clock_info
->r600
.ucMemoryClockHigh
<< 16;
2414 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2415 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2416 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2418 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2419 le16_to_cpu(clock_info
->r600
.usVDDC
);
2422 /* patch up vddc if necessary */
2423 switch (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
) {
2424 case ATOM_VIRTUAL_VOLTAGE_ID0
:
2425 case ATOM_VIRTUAL_VOLTAGE_ID1
:
2426 case ATOM_VIRTUAL_VOLTAGE_ID2
:
2427 case ATOM_VIRTUAL_VOLTAGE_ID3
:
2428 if (radeon_atom_get_max_vddc(rdev
, VOLTAGE_TYPE_VDDC
,
2429 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
,
2431 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
= vddc
;
2437 if (rdev
->flags
& RADEON_IS_IGP
) {
2438 /* skip invalid modes */
2439 if (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0)
2442 /* skip invalid modes */
2443 if ((rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
== 0) ||
2444 (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0))
2450 static int radeon_atombios_parse_power_table_4_5(struct radeon_device
*rdev
)
2452 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2453 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
2454 union pplib_power_state
*power_state
;
2456 int state_index
= 0, mode_index
= 0;
2457 union pplib_clock_info
*clock_info
;
2459 union power_info
*power_info
;
2460 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2464 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2465 &frev
, &crev
, &data_offset
))
2467 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
2469 radeon_atombios_add_pplib_thermal_controller(rdev
, &power_info
->pplib
.sThermalController
);
2470 if (power_info
->pplib
.ucNumStates
== 0)
2472 rdev
->pm
.power_state
= kzalloc(sizeof(struct radeon_power_state
) *
2473 power_info
->pplib
.ucNumStates
, GFP_KERNEL
);
2474 if (!rdev
->pm
.power_state
)
2476 /* first mode is usually default, followed by low to high */
2477 for (i
= 0; i
< power_info
->pplib
.ucNumStates
; i
++) {
2479 power_state
= (union pplib_power_state
*)
2480 (mode_info
->atom_context
->bios
+ data_offset
+
2481 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
) +
2482 i
* power_info
->pplib
.ucStateEntrySize
);
2483 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2484 (mode_info
->atom_context
->bios
+ data_offset
+
2485 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
) +
2486 (power_state
->v1
.ucNonClockStateIndex
*
2487 power_info
->pplib
.ucNonClockSize
));
2488 rdev
->pm
.power_state
[i
].clock_info
= kzalloc(sizeof(struct radeon_pm_clock_info
) *
2489 ((power_info
->pplib
.ucStateEntrySize
- 1) ?
2490 (power_info
->pplib
.ucStateEntrySize
- 1) : 1),
2492 if (!rdev
->pm
.power_state
[i
].clock_info
)
2494 if (power_info
->pplib
.ucStateEntrySize
- 1) {
2495 for (j
= 0; j
< (power_info
->pplib
.ucStateEntrySize
- 1); j
++) {
2496 clock_info
= (union pplib_clock_info
*)
2497 (mode_info
->atom_context
->bios
+ data_offset
+
2498 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
) +
2499 (power_state
->v1
.ucClockStateIndices
[j
] *
2500 power_info
->pplib
.ucClockInfoSize
));
2501 valid
= radeon_atombios_parse_pplib_clock_info(rdev
,
2502 state_index
, mode_index
,
2508 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2509 rdev
->clock
.default_mclk
;
2510 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2511 rdev
->clock
.default_sclk
;
2514 rdev
->pm
.power_state
[state_index
].num_clock_modes
= mode_index
;
2516 radeon_atombios_parse_pplib_non_clock_info(rdev
, state_index
, mode_index
,
2521 /* if multiple clock modes, mark the lowest as no display */
2522 for (i
= 0; i
< state_index
; i
++) {
2523 if (rdev
->pm
.power_state
[i
].num_clock_modes
> 1)
2524 rdev
->pm
.power_state
[i
].clock_info
[0].flags
|=
2525 RADEON_PM_MODE_NO_DISPLAY
;
2527 /* first mode is usually default */
2528 if (rdev
->pm
.default_power_state_index
== -1) {
2529 rdev
->pm
.power_state
[0].type
=
2530 POWER_STATE_TYPE_DEFAULT
;
2531 rdev
->pm
.default_power_state_index
= 0;
2532 rdev
->pm
.power_state
[0].default_clock_mode
=
2533 &rdev
->pm
.power_state
[0].clock_info
[0];
2538 static int radeon_atombios_parse_power_table_6(struct radeon_device
*rdev
)
2540 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2541 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
2542 union pplib_power_state
*power_state
;
2543 int i
, j
, non_clock_array_index
, clock_array_index
;
2544 int state_index
= 0, mode_index
= 0;
2545 union pplib_clock_info
*clock_info
;
2546 struct _StateArray
*state_array
;
2547 struct _ClockInfoArray
*clock_info_array
;
2548 struct _NonClockInfoArray
*non_clock_info_array
;
2550 union power_info
*power_info
;
2551 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2554 u8
*power_state_offset
;
2556 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2557 &frev
, &crev
, &data_offset
))
2559 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
2561 radeon_atombios_add_pplib_thermal_controller(rdev
, &power_info
->pplib
.sThermalController
);
2562 state_array
= (struct _StateArray
*)
2563 (mode_info
->atom_context
->bios
+ data_offset
+
2564 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
));
2565 clock_info_array
= (struct _ClockInfoArray
*)
2566 (mode_info
->atom_context
->bios
+ data_offset
+
2567 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
));
2568 non_clock_info_array
= (struct _NonClockInfoArray
*)
2569 (mode_info
->atom_context
->bios
+ data_offset
+
2570 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
));
2571 if (state_array
->ucNumEntries
== 0)
2573 rdev
->pm
.power_state
= kzalloc(sizeof(struct radeon_power_state
) *
2574 state_array
->ucNumEntries
, GFP_KERNEL
);
2575 if (!rdev
->pm
.power_state
)
2577 power_state_offset
= (u8
*)state_array
->states
;
2578 for (i
= 0; i
< state_array
->ucNumEntries
; i
++) {
2580 power_state
= (union pplib_power_state
*)power_state_offset
;
2581 non_clock_array_index
= power_state
->v2
.nonClockInfoIndex
;
2582 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2583 &non_clock_info_array
->nonClockInfo
[non_clock_array_index
];
2584 rdev
->pm
.power_state
[i
].clock_info
= kzalloc(sizeof(struct radeon_pm_clock_info
) *
2585 (power_state
->v2
.ucNumDPMLevels
?
2586 power_state
->v2
.ucNumDPMLevels
: 1),
2588 if (!rdev
->pm
.power_state
[i
].clock_info
)
2590 if (power_state
->v2
.ucNumDPMLevels
) {
2591 for (j
= 0; j
< power_state
->v2
.ucNumDPMLevels
; j
++) {
2592 clock_array_index
= power_state
->v2
.clockInfoIndex
[j
];
2593 clock_info
= (union pplib_clock_info
*)
2594 &clock_info_array
->clockInfo
[clock_array_index
* clock_info_array
->ucEntrySize
];
2595 valid
= radeon_atombios_parse_pplib_clock_info(rdev
,
2596 state_index
, mode_index
,
2602 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2603 rdev
->clock
.default_mclk
;
2604 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2605 rdev
->clock
.default_sclk
;
2608 rdev
->pm
.power_state
[state_index
].num_clock_modes
= mode_index
;
2610 radeon_atombios_parse_pplib_non_clock_info(rdev
, state_index
, mode_index
,
2614 power_state_offset
+= 2 + power_state
->v2
.ucNumDPMLevels
;
2616 /* if multiple clock modes, mark the lowest as no display */
2617 for (i
= 0; i
< state_index
; i
++) {
2618 if (rdev
->pm
.power_state
[i
].num_clock_modes
> 1)
2619 rdev
->pm
.power_state
[i
].clock_info
[0].flags
|=
2620 RADEON_PM_MODE_NO_DISPLAY
;
2622 /* first mode is usually default */
2623 if (rdev
->pm
.default_power_state_index
== -1) {
2624 rdev
->pm
.power_state
[0].type
=
2625 POWER_STATE_TYPE_DEFAULT
;
2626 rdev
->pm
.default_power_state_index
= 0;
2627 rdev
->pm
.power_state
[0].default_clock_mode
=
2628 &rdev
->pm
.power_state
[0].clock_info
[0];
2633 void radeon_atombios_get_power_modes(struct radeon_device
*rdev
)
2635 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2636 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2639 int state_index
= 0;
2641 rdev
->pm
.default_power_state_index
= -1;
2643 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2644 &frev
, &crev
, &data_offset
)) {
2649 state_index
= radeon_atombios_parse_power_table_1_3(rdev
);
2653 state_index
= radeon_atombios_parse_power_table_4_5(rdev
);
2656 state_index
= radeon_atombios_parse_power_table_6(rdev
);
2663 if (state_index
== 0) {
2664 rdev
->pm
.power_state
= kzalloc(sizeof(struct radeon_power_state
), GFP_KERNEL
);
2665 if (rdev
->pm
.power_state
) {
2666 rdev
->pm
.power_state
[0].clock_info
=
2667 kzalloc(sizeof(struct radeon_pm_clock_info
) * 1, GFP_KERNEL
);
2668 if (rdev
->pm
.power_state
[0].clock_info
) {
2669 /* add the default mode */
2670 rdev
->pm
.power_state
[state_index
].type
=
2671 POWER_STATE_TYPE_DEFAULT
;
2672 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2673 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= rdev
->clock
.default_mclk
;
2674 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= rdev
->clock
.default_sclk
;
2675 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2676 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2677 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2678 rdev
->pm
.power_state
[state_index
].pcie_lanes
= 16;
2679 rdev
->pm
.default_power_state_index
= state_index
;
2680 rdev
->pm
.power_state
[state_index
].flags
= 0;
2686 rdev
->pm
.num_power_states
= state_index
;
2688 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
2689 rdev
->pm
.current_clock_mode_index
= 0;
2690 if (rdev
->pm
.default_power_state_index
>= 0)
2691 rdev
->pm
.current_vddc
=
2692 rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
2694 rdev
->pm
.current_vddc
= 0;
2697 union get_clock_dividers
{
2698 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1
;
2699 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2
;
2700 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3
;
2701 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4
;
2702 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5
;
2705 int radeon_atom_get_clock_dividers(struct radeon_device
*rdev
,
2709 struct atom_clock_dividers
*dividers
)
2711 union get_clock_dividers args
;
2712 int index
= GetIndexIntoMasterTable(COMMAND
, ComputeMemoryEnginePLL
);
2715 memset(&args
, 0, sizeof(args
));
2716 memset(dividers
, 0, sizeof(struct atom_clock_dividers
));
2718 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2724 args
.v1
.ucAction
= clock_type
;
2725 args
.v1
.ulClock
= cpu_to_le32(clock
); /* 10 khz */
2727 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2729 dividers
->post_div
= args
.v1
.ucPostDiv
;
2730 dividers
->fb_div
= args
.v1
.ucFbDiv
;
2731 dividers
->enable_post_div
= true;
2736 /* r6xx, r7xx, evergreen, ni, si */
2737 if (rdev
->family
<= CHIP_RV770
) {
2738 args
.v2
.ucAction
= clock_type
;
2739 args
.v2
.ulClock
= cpu_to_le32(clock
); /* 10 khz */
2741 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2743 dividers
->post_div
= args
.v2
.ucPostDiv
;
2744 dividers
->fb_div
= le16_to_cpu(args
.v2
.usFbDiv
);
2745 dividers
->ref_div
= args
.v2
.ucAction
;
2746 if (rdev
->family
== CHIP_RV770
) {
2747 dividers
->enable_post_div
= (le32_to_cpu(args
.v2
.ulClock
) & (1 << 24)) ?
2749 dividers
->vco_mode
= (le32_to_cpu(args
.v2
.ulClock
) & (1 << 25)) ? 1 : 0;
2751 dividers
->enable_post_div
= (dividers
->fb_div
& 1) ? true : false;
2753 if (clock_type
== COMPUTE_ENGINE_PLL_PARAM
) {
2754 args
.v3
.ulClockParams
= cpu_to_le32((clock_type
<< 24) | clock
);
2756 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2758 dividers
->post_div
= args
.v3
.ucPostDiv
;
2759 dividers
->enable_post_div
= (args
.v3
.ucCntlFlag
&
2760 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN
) ? true : false;
2761 dividers
->enable_dithen
= (args
.v3
.ucCntlFlag
&
2762 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE
) ? false : true;
2763 dividers
->fb_div
= le16_to_cpu(args
.v3
.ulFbDiv
.usFbDiv
);
2764 dividers
->frac_fb_div
= le16_to_cpu(args
.v3
.ulFbDiv
.usFbDivFrac
);
2765 dividers
->ref_div
= args
.v3
.ucRefDiv
;
2766 dividers
->vco_mode
= (args
.v3
.ucCntlFlag
&
2767 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE
) ? 1 : 0;
2769 /* for SI we use ComputeMemoryClockParam for memory plls */
2770 if (rdev
->family
>= CHIP_TAHITI
)
2772 args
.v5
.ulClockParams
= cpu_to_le32((clock_type
<< 24) | clock
);
2774 args
.v5
.ucInputFlag
= ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN
;
2776 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2778 dividers
->post_div
= args
.v5
.ucPostDiv
;
2779 dividers
->enable_post_div
= (args
.v5
.ucCntlFlag
&
2780 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN
) ? true : false;
2781 dividers
->enable_dithen
= (args
.v5
.ucCntlFlag
&
2782 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE
) ? false : true;
2783 dividers
->whole_fb_div
= le16_to_cpu(args
.v5
.ulFbDiv
.usFbDiv
);
2784 dividers
->frac_fb_div
= le16_to_cpu(args
.v5
.ulFbDiv
.usFbDivFrac
);
2785 dividers
->ref_div
= args
.v5
.ucRefDiv
;
2786 dividers
->vco_mode
= (args
.v5
.ucCntlFlag
&
2787 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE
) ? 1 : 0;
2793 args
.v4
.ulClock
= cpu_to_le32(clock
); /* 10 khz */
2795 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2797 dividers
->post_div
= args
.v4
.ucPostDiv
;
2798 dividers
->real_clock
= le32_to_cpu(args
.v4
.ulClock
);
2806 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
)
2808 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args
;
2809 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicClockGating
);
2811 args
.ucEnable
= enable
;
2813 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2816 uint32_t radeon_atom_get_engine_clock(struct radeon_device
*rdev
)
2818 GET_ENGINE_CLOCK_PS_ALLOCATION args
;
2819 int index
= GetIndexIntoMasterTable(COMMAND
, GetEngineClock
);
2821 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2822 return le32_to_cpu(args
.ulReturnEngineClock
);
2825 uint32_t radeon_atom_get_memory_clock(struct radeon_device
*rdev
)
2827 GET_MEMORY_CLOCK_PS_ALLOCATION args
;
2828 int index
= GetIndexIntoMasterTable(COMMAND
, GetMemoryClock
);
2830 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2831 return le32_to_cpu(args
.ulReturnMemoryClock
);
2834 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
,
2837 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
2838 int index
= GetIndexIntoMasterTable(COMMAND
, SetEngineClock
);
2840 args
.ulTargetEngineClock
= cpu_to_le32(eng_clock
); /* 10 khz */
2842 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2845 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
,
2848 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
2849 int index
= GetIndexIntoMasterTable(COMMAND
, SetMemoryClock
);
2851 if (rdev
->flags
& RADEON_IS_IGP
)
2854 args
.ulTargetMemoryClock
= cpu_to_le32(mem_clock
); /* 10 khz */
2856 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2860 struct _SET_VOLTAGE_PS_ALLOCATION alloc
;
2861 struct _SET_VOLTAGE_PARAMETERS v1
;
2862 struct _SET_VOLTAGE_PARAMETERS_V2 v2
;
2863 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3
;
2866 void radeon_atom_set_voltage(struct radeon_device
*rdev
, u16 voltage_level
, u8 voltage_type
)
2868 union set_voltage args
;
2869 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
2870 u8 frev
, crev
, volt_index
= voltage_level
;
2872 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2875 /* 0xff01 is a flag rather then an actual voltage */
2876 if (voltage_level
== 0xff01)
2881 args
.v1
.ucVoltageType
= voltage_type
;
2882 args
.v1
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_ALL_SOURCE
;
2883 args
.v1
.ucVoltageIndex
= volt_index
;
2886 args
.v2
.ucVoltageType
= voltage_type
;
2887 args
.v2
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE
;
2888 args
.v2
.usVoltageLevel
= cpu_to_le16(voltage_level
);
2891 args
.v3
.ucVoltageType
= voltage_type
;
2892 args
.v3
.ucVoltageMode
= ATOM_SET_VOLTAGE
;
2893 args
.v3
.usVoltageLevel
= cpu_to_le16(voltage_level
);
2896 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
2900 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2903 static int radeon_atom_get_max_vddc(struct radeon_device
*rdev
, u8 voltage_type
,
2904 u16 voltage_id
, u16
*voltage
)
2906 union set_voltage args
;
2907 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
2910 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2917 args
.v2
.ucVoltageType
= SET_VOLTAGE_GET_MAX_VOLTAGE
;
2918 args
.v2
.ucVoltageMode
= 0;
2919 args
.v2
.usVoltageLevel
= 0;
2921 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2923 *voltage
= le16_to_cpu(args
.v2
.usVoltageLevel
);
2926 args
.v3
.ucVoltageType
= voltage_type
;
2927 args
.v3
.ucVoltageMode
= ATOM_GET_VOLTAGE_LEVEL
;
2928 args
.v3
.usVoltageLevel
= cpu_to_le16(voltage_id
);
2930 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2932 *voltage
= le16_to_cpu(args
.v3
.usVoltageLevel
);
2935 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
2942 void radeon_atom_initialize_bios_scratch_regs(struct drm_device
*dev
)
2944 struct radeon_device
*rdev
= dev
->dev_private
;
2945 uint32_t bios_2_scratch
, bios_6_scratch
;
2947 if (rdev
->family
>= CHIP_R600
) {
2948 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
2949 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
2951 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
2952 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2955 /* let the bios control the backlight */
2956 bios_2_scratch
&= ~ATOM_S2_VRI_BRIGHT_ENABLE
;
2958 /* tell the bios not to handle mode switching */
2959 bios_6_scratch
|= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
;
2961 if (rdev
->family
>= CHIP_R600
) {
2962 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
2963 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2965 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
2966 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2971 void radeon_save_bios_scratch_regs(struct radeon_device
*rdev
)
2973 uint32_t scratch_reg
;
2976 if (rdev
->family
>= CHIP_R600
)
2977 scratch_reg
= R600_BIOS_0_SCRATCH
;
2979 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
2981 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
2982 rdev
->bios_scratch
[i
] = RREG32(scratch_reg
+ (i
* 4));
2985 void radeon_restore_bios_scratch_regs(struct radeon_device
*rdev
)
2987 uint32_t scratch_reg
;
2990 if (rdev
->family
>= CHIP_R600
)
2991 scratch_reg
= R600_BIOS_0_SCRATCH
;
2993 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
2995 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
2996 WREG32(scratch_reg
+ (i
* 4), rdev
->bios_scratch
[i
]);
2999 void radeon_atom_output_lock(struct drm_encoder
*encoder
, bool lock
)
3001 struct drm_device
*dev
= encoder
->dev
;
3002 struct radeon_device
*rdev
= dev
->dev_private
;
3003 uint32_t bios_6_scratch
;
3005 if (rdev
->family
>= CHIP_R600
)
3006 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
3008 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3011 bios_6_scratch
|= ATOM_S6_CRITICAL_STATE
;
3012 bios_6_scratch
&= ~ATOM_S6_ACC_MODE
;
3014 bios_6_scratch
&= ~ATOM_S6_CRITICAL_STATE
;
3015 bios_6_scratch
|= ATOM_S6_ACC_MODE
;
3018 if (rdev
->family
>= CHIP_R600
)
3019 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
3021 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
3024 /* at some point we may want to break this out into individual functions */
3026 radeon_atombios_connected_scratch_regs(struct drm_connector
*connector
,
3027 struct drm_encoder
*encoder
,
3030 struct drm_device
*dev
= connector
->dev
;
3031 struct radeon_device
*rdev
= dev
->dev_private
;
3032 struct radeon_connector
*radeon_connector
=
3033 to_radeon_connector(connector
);
3034 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3035 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
3037 if (rdev
->family
>= CHIP_R600
) {
3038 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
3039 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
3040 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
3042 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
3043 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
3044 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3047 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
3048 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
3050 DRM_DEBUG_KMS("TV1 connected\n");
3051 bios_3_scratch
|= ATOM_S3_TV1_ACTIVE
;
3052 bios_6_scratch
|= ATOM_S6_ACC_REQ_TV1
;
3054 DRM_DEBUG_KMS("TV1 disconnected\n");
3055 bios_0_scratch
&= ~ATOM_S0_TV1_MASK
;
3056 bios_3_scratch
&= ~ATOM_S3_TV1_ACTIVE
;
3057 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_TV1
;
3060 if ((radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) &&
3061 (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
)) {
3063 DRM_DEBUG_KMS("CV connected\n");
3064 bios_3_scratch
|= ATOM_S3_CV_ACTIVE
;
3065 bios_6_scratch
|= ATOM_S6_ACC_REQ_CV
;
3067 DRM_DEBUG_KMS("CV disconnected\n");
3068 bios_0_scratch
&= ~ATOM_S0_CV_MASK
;
3069 bios_3_scratch
&= ~ATOM_S3_CV_ACTIVE
;
3070 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CV
;
3073 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
3074 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
3076 DRM_DEBUG_KMS("LCD1 connected\n");
3077 bios_0_scratch
|= ATOM_S0_LCD1
;
3078 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
3079 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
3081 DRM_DEBUG_KMS("LCD1 disconnected\n");
3082 bios_0_scratch
&= ~ATOM_S0_LCD1
;
3083 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
3084 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
3087 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
3088 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
3090 DRM_DEBUG_KMS("CRT1 connected\n");
3091 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
3092 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
3093 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
3095 DRM_DEBUG_KMS("CRT1 disconnected\n");
3096 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
3097 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
3098 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
3101 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
3102 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
3104 DRM_DEBUG_KMS("CRT2 connected\n");
3105 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
3106 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
3107 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
3109 DRM_DEBUG_KMS("CRT2 disconnected\n");
3110 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
3111 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
3112 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
3115 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
3116 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
3118 DRM_DEBUG_KMS("DFP1 connected\n");
3119 bios_0_scratch
|= ATOM_S0_DFP1
;
3120 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
3121 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
3123 DRM_DEBUG_KMS("DFP1 disconnected\n");
3124 bios_0_scratch
&= ~ATOM_S0_DFP1
;
3125 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
3126 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
3129 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
3130 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
3132 DRM_DEBUG_KMS("DFP2 connected\n");
3133 bios_0_scratch
|= ATOM_S0_DFP2
;
3134 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
3135 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
3137 DRM_DEBUG_KMS("DFP2 disconnected\n");
3138 bios_0_scratch
&= ~ATOM_S0_DFP2
;
3139 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
3140 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
3143 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
3144 (radeon_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
3146 DRM_DEBUG_KMS("DFP3 connected\n");
3147 bios_0_scratch
|= ATOM_S0_DFP3
;
3148 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
3149 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
3151 DRM_DEBUG_KMS("DFP3 disconnected\n");
3152 bios_0_scratch
&= ~ATOM_S0_DFP3
;
3153 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
3154 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
3157 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
3158 (radeon_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
3160 DRM_DEBUG_KMS("DFP4 connected\n");
3161 bios_0_scratch
|= ATOM_S0_DFP4
;
3162 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
3163 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
3165 DRM_DEBUG_KMS("DFP4 disconnected\n");
3166 bios_0_scratch
&= ~ATOM_S0_DFP4
;
3167 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
3168 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
3171 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
3172 (radeon_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
3174 DRM_DEBUG_KMS("DFP5 connected\n");
3175 bios_0_scratch
|= ATOM_S0_DFP5
;
3176 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
3177 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
3179 DRM_DEBUG_KMS("DFP5 disconnected\n");
3180 bios_0_scratch
&= ~ATOM_S0_DFP5
;
3181 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
3182 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
3185 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP6_SUPPORT
) &&
3186 (radeon_connector
->devices
& ATOM_DEVICE_DFP6_SUPPORT
)) {
3188 DRM_DEBUG_KMS("DFP6 connected\n");
3189 bios_0_scratch
|= ATOM_S0_DFP6
;
3190 bios_3_scratch
|= ATOM_S3_DFP6_ACTIVE
;
3191 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP6
;
3193 DRM_DEBUG_KMS("DFP6 disconnected\n");
3194 bios_0_scratch
&= ~ATOM_S0_DFP6
;
3195 bios_3_scratch
&= ~ATOM_S3_DFP6_ACTIVE
;
3196 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP6
;
3200 if (rdev
->family
>= CHIP_R600
) {
3201 WREG32(R600_BIOS_0_SCRATCH
, bios_0_scratch
);
3202 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
3203 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
3205 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
3206 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
3207 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
3212 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
3214 struct drm_device
*dev
= encoder
->dev
;
3215 struct radeon_device
*rdev
= dev
->dev_private
;
3216 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3217 uint32_t bios_3_scratch
;
3219 if (ASIC_IS_DCE4(rdev
))
3222 if (rdev
->family
>= CHIP_R600
)
3223 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
3225 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
3227 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
3228 bios_3_scratch
&= ~ATOM_S3_TV1_CRTC_ACTIVE
;
3229 bios_3_scratch
|= (crtc
<< 18);
3231 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
3232 bios_3_scratch
&= ~ATOM_S3_CV_CRTC_ACTIVE
;
3233 bios_3_scratch
|= (crtc
<< 24);
3235 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
3236 bios_3_scratch
&= ~ATOM_S3_CRT1_CRTC_ACTIVE
;
3237 bios_3_scratch
|= (crtc
<< 16);
3239 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
3240 bios_3_scratch
&= ~ATOM_S3_CRT2_CRTC_ACTIVE
;
3241 bios_3_scratch
|= (crtc
<< 20);
3243 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
3244 bios_3_scratch
&= ~ATOM_S3_LCD1_CRTC_ACTIVE
;
3245 bios_3_scratch
|= (crtc
<< 17);
3247 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
3248 bios_3_scratch
&= ~ATOM_S3_DFP1_CRTC_ACTIVE
;
3249 bios_3_scratch
|= (crtc
<< 19);
3251 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
3252 bios_3_scratch
&= ~ATOM_S3_DFP2_CRTC_ACTIVE
;
3253 bios_3_scratch
|= (crtc
<< 23);
3255 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
3256 bios_3_scratch
&= ~ATOM_S3_DFP3_CRTC_ACTIVE
;
3257 bios_3_scratch
|= (crtc
<< 25);
3260 if (rdev
->family
>= CHIP_R600
)
3261 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
3263 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
3267 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
3269 struct drm_device
*dev
= encoder
->dev
;
3270 struct radeon_device
*rdev
= dev
->dev_private
;
3271 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3272 uint32_t bios_2_scratch
;
3274 if (ASIC_IS_DCE4(rdev
))
3277 if (rdev
->family
>= CHIP_R600
)
3278 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
3280 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
3282 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
3284 bios_2_scratch
&= ~ATOM_S2_TV1_DPMS_STATE
;
3286 bios_2_scratch
|= ATOM_S2_TV1_DPMS_STATE
;
3288 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
3290 bios_2_scratch
&= ~ATOM_S2_CV_DPMS_STATE
;
3292 bios_2_scratch
|= ATOM_S2_CV_DPMS_STATE
;
3294 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
3296 bios_2_scratch
&= ~ATOM_S2_CRT1_DPMS_STATE
;
3298 bios_2_scratch
|= ATOM_S2_CRT1_DPMS_STATE
;
3300 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
3302 bios_2_scratch
&= ~ATOM_S2_CRT2_DPMS_STATE
;
3304 bios_2_scratch
|= ATOM_S2_CRT2_DPMS_STATE
;
3306 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
3308 bios_2_scratch
&= ~ATOM_S2_LCD1_DPMS_STATE
;
3310 bios_2_scratch
|= ATOM_S2_LCD1_DPMS_STATE
;
3312 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
3314 bios_2_scratch
&= ~ATOM_S2_DFP1_DPMS_STATE
;
3316 bios_2_scratch
|= ATOM_S2_DFP1_DPMS_STATE
;
3318 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
3320 bios_2_scratch
&= ~ATOM_S2_DFP2_DPMS_STATE
;
3322 bios_2_scratch
|= ATOM_S2_DFP2_DPMS_STATE
;
3324 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
3326 bios_2_scratch
&= ~ATOM_S2_DFP3_DPMS_STATE
;
3328 bios_2_scratch
|= ATOM_S2_DFP3_DPMS_STATE
;
3330 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) {
3332 bios_2_scratch
&= ~ATOM_S2_DFP4_DPMS_STATE
;
3334 bios_2_scratch
|= ATOM_S2_DFP4_DPMS_STATE
;
3336 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) {
3338 bios_2_scratch
&= ~ATOM_S2_DFP5_DPMS_STATE
;
3340 bios_2_scratch
|= ATOM_S2_DFP5_DPMS_STATE
;
3343 if (rdev
->family
>= CHIP_R600
)
3344 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
3346 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);