projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/radeon/kms: expose thermal/fan i2c buses
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_atombios.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
52
53 /* from radeon_legacy_encoder.c */
54 extern void
55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
57
58 union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
62 };
63
64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
65 uint8_t id)
66 {
67 struct atom_context *ctx = rdev->mode_info.atom_context;
68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
72 uint16_t data_offset;
73 int i;
74
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
76 i2c.valid = false;
77
78 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
79
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
82
83 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
84 gpio = &i2c_info->asGPIO_Info[i];
85
86 if (gpio->sucI2cId.ucAccess == id) {
87 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
88 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
89 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
90 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
91 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
92 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
93 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
94 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
95 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
96 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
97 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
98 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
99 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
100 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
101 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
102 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
103
104 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
105 i2c.hw_capable = true;
106 else
107 i2c.hw_capable = false;
108
109 if (gpio->sucI2cId.ucAccess == 0xa0)
110 i2c.mm_i2c = true;
111 else
112 i2c.mm_i2c = false;
113
114 i2c.i2c_id = gpio->sucI2cId.ucAccess;
115
116 i2c.valid = true;
117 break;
118 }
119 }
120
121 return i2c;
122 }
123
124 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
125 u8 id)
126 {
127 struct atom_context *ctx = rdev->mode_info.atom_context;
128 struct radeon_gpio_rec gpio;
129 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
130 struct _ATOM_GPIO_PIN_LUT *gpio_info;
131 ATOM_GPIO_PIN_ASSIGNMENT *pin;
132 u16 data_offset, size;
133 int i, num_indices;
134
135 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
136 gpio.valid = false;
137
138 atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
139
140 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
141
142 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
143
144 for (i = 0; i < num_indices; i++) {
145 pin = &gpio_info->asGPIO_Pin[i];
146 if (id == pin->ucGPIO_ID) {
147 gpio.id = pin->ucGPIO_ID;
148 gpio.reg = pin->usGpioPin_AIndex * 4;
149 gpio.mask = (1 << pin->ucGpioPinBitShift);
150 gpio.valid = true;
151 break;
152 }
153 }
154
155 return gpio;
156 }
157
158 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
159 struct radeon_gpio_rec *gpio)
160 {
161 struct radeon_hpd hpd;
162 u32 reg;
163
164 if (ASIC_IS_DCE4(rdev))
165 reg = EVERGREEN_DC_GPIO_HPD_A;
166 else
167 reg = AVIVO_DC_GPIO_HPD_A;
168
169 hpd.gpio = *gpio;
170 if (gpio->reg == reg) {
171 switch(gpio->mask) {
172 case (1 << 0):
173 hpd.hpd = RADEON_HPD_1;
174 break;
175 case (1 << 8):
176 hpd.hpd = RADEON_HPD_2;
177 break;
178 case (1 << 16):
179 hpd.hpd = RADEON_HPD_3;
180 break;
181 case (1 << 24):
182 hpd.hpd = RADEON_HPD_4;
183 break;
184 case (1 << 26):
185 hpd.hpd = RADEON_HPD_5;
186 break;
187 case (1 << 28):
188 hpd.hpd = RADEON_HPD_6;
189 break;
190 default:
191 hpd.hpd = RADEON_HPD_NONE;
192 break;
193 }
194 } else
195 hpd.hpd = RADEON_HPD_NONE;
196 return hpd;
197 }
198
199 static bool radeon_atom_apply_quirks(struct drm_device *dev,
200 uint32_t supported_device,
201 int *connector_type,
202 struct radeon_i2c_bus_rec *i2c_bus,
203 uint16_t *line_mux,
204 struct radeon_hpd *hpd)
205 {
206
207 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
208 if ((dev->pdev->device == 0x791e) &&
209 (dev->pdev->subsystem_vendor == 0x1043) &&
210 (dev->pdev->subsystem_device == 0x826d)) {
211 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
212 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
213 *connector_type = DRM_MODE_CONNECTOR_DVID;
214 }
215
216 /* Asrock RS600 board lists the DVI port as HDMI */
217 if ((dev->pdev->device == 0x7941) &&
218 (dev->pdev->subsystem_vendor == 0x1849) &&
219 (dev->pdev->subsystem_device == 0x7941)) {
220 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
221 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
222 *connector_type = DRM_MODE_CONNECTOR_DVID;
223 }
224
225 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
226 if ((dev->pdev->device == 0x7941) &&
227 (dev->pdev->subsystem_vendor == 0x147b) &&
228 (dev->pdev->subsystem_device == 0x2412)) {
229 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
230 return false;
231 }
232
233 /* Falcon NW laptop lists vga ddc line for LVDS */
234 if ((dev->pdev->device == 0x5653) &&
235 (dev->pdev->subsystem_vendor == 0x1462) &&
236 (dev->pdev->subsystem_device == 0x0291)) {
237 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
238 i2c_bus->valid = false;
239 *line_mux = 53;
240 }
241 }
242
243 /* HIS X1300 is DVI+VGA, not DVI+DVI */
244 if ((dev->pdev->device == 0x7146) &&
245 (dev->pdev->subsystem_vendor == 0x17af) &&
246 (dev->pdev->subsystem_device == 0x2058)) {
247 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
248 return false;
249 }
250
251 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
252 if ((dev->pdev->device == 0x7142) &&
253 (dev->pdev->subsystem_vendor == 0x1458) &&
254 (dev->pdev->subsystem_device == 0x2134)) {
255 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
256 return false;
257 }
258
259
260 /* Funky macbooks */
261 if ((dev->pdev->device == 0x71C5) &&
262 (dev->pdev->subsystem_vendor == 0x106b) &&
263 (dev->pdev->subsystem_device == 0x0080)) {
264 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
265 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
266 return false;
267 }
268
269 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
270 if ((dev->pdev->device == 0x9598) &&
271 (dev->pdev->subsystem_vendor == 0x1043) &&
272 (dev->pdev->subsystem_device == 0x01da)) {
273 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
274 *connector_type = DRM_MODE_CONNECTOR_DVII;
275 }
276 }
277
278 /* ASUS HD 3450 board lists the DVI port as HDMI */
279 if ((dev->pdev->device == 0x95C5) &&
280 (dev->pdev->subsystem_vendor == 0x1043) &&
281 (dev->pdev->subsystem_device == 0x01e2)) {
282 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
283 *connector_type = DRM_MODE_CONNECTOR_DVII;
284 }
285 }
286
287 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
288 * HDMI + VGA reporting as HDMI
289 */
290 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
291 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
292 *connector_type = DRM_MODE_CONNECTOR_VGA;
293 *line_mux = 0;
294 }
295 }
296
297 /* Acer laptop reports DVI-D as DVI-I */
298 if ((dev->pdev->device == 0x95c4) &&
299 (dev->pdev->subsystem_vendor == 0x1025) &&
300 (dev->pdev->subsystem_device == 0x013c)) {
301 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
302 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
303 *connector_type = DRM_MODE_CONNECTOR_DVID;
304 }
305
306 /* XFX Pine Group device rv730 reports no VGA DDC lines
307 * even though they are wired up to record 0x93
308 */
309 if ((dev->pdev->device == 0x9498) &&
310 (dev->pdev->subsystem_vendor == 0x1682) &&
311 (dev->pdev->subsystem_device == 0x2452)) {
312 struct radeon_device *rdev = dev->dev_private;
313 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
314 }
315 return true;
316 }
317
318 const int supported_devices_connector_convert[] = {
319 DRM_MODE_CONNECTOR_Unknown,
320 DRM_MODE_CONNECTOR_VGA,
321 DRM_MODE_CONNECTOR_DVII,
322 DRM_MODE_CONNECTOR_DVID,
323 DRM_MODE_CONNECTOR_DVIA,
324 DRM_MODE_CONNECTOR_SVIDEO,
325 DRM_MODE_CONNECTOR_Composite,
326 DRM_MODE_CONNECTOR_LVDS,
327 DRM_MODE_CONNECTOR_Unknown,
328 DRM_MODE_CONNECTOR_Unknown,
329 DRM_MODE_CONNECTOR_HDMIA,
330 DRM_MODE_CONNECTOR_HDMIB,
331 DRM_MODE_CONNECTOR_Unknown,
332 DRM_MODE_CONNECTOR_Unknown,
333 DRM_MODE_CONNECTOR_9PinDIN,
334 DRM_MODE_CONNECTOR_DisplayPort
335 };
336
337 const uint16_t supported_devices_connector_object_id_convert[] = {
338 CONNECTOR_OBJECT_ID_NONE,
339 CONNECTOR_OBJECT_ID_VGA,
340 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
341 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
342 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
343 CONNECTOR_OBJECT_ID_COMPOSITE,
344 CONNECTOR_OBJECT_ID_SVIDEO,
345 CONNECTOR_OBJECT_ID_LVDS,
346 CONNECTOR_OBJECT_ID_9PIN_DIN,
347 CONNECTOR_OBJECT_ID_9PIN_DIN,
348 CONNECTOR_OBJECT_ID_DISPLAYPORT,
349 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
350 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
351 CONNECTOR_OBJECT_ID_SVIDEO
352 };
353
354 const int object_connector_convert[] = {
355 DRM_MODE_CONNECTOR_Unknown,
356 DRM_MODE_CONNECTOR_DVII,
357 DRM_MODE_CONNECTOR_DVII,
358 DRM_MODE_CONNECTOR_DVID,
359 DRM_MODE_CONNECTOR_DVID,
360 DRM_MODE_CONNECTOR_VGA,
361 DRM_MODE_CONNECTOR_Composite,
362 DRM_MODE_CONNECTOR_SVIDEO,
363 DRM_MODE_CONNECTOR_Unknown,
364 DRM_MODE_CONNECTOR_Unknown,
365 DRM_MODE_CONNECTOR_9PinDIN,
366 DRM_MODE_CONNECTOR_Unknown,
367 DRM_MODE_CONNECTOR_HDMIA,
368 DRM_MODE_CONNECTOR_HDMIB,
369 DRM_MODE_CONNECTOR_LVDS,
370 DRM_MODE_CONNECTOR_9PinDIN,
371 DRM_MODE_CONNECTOR_Unknown,
372 DRM_MODE_CONNECTOR_Unknown,
373 DRM_MODE_CONNECTOR_Unknown,
374 DRM_MODE_CONNECTOR_DisplayPort,
375 DRM_MODE_CONNECTOR_eDP,
376 DRM_MODE_CONNECTOR_Unknown
377 };
378
379 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
380 {
381 struct radeon_device *rdev = dev->dev_private;
382 struct radeon_mode_info *mode_info = &rdev->mode_info;
383 struct atom_context *ctx = mode_info->atom_context;
384 int index = GetIndexIntoMasterTable(DATA, Object_Header);
385 u16 size, data_offset;
386 u8 frev, crev;
387 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
388 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
389 ATOM_OBJECT_HEADER *obj_header;
390 int i, j, path_size, device_support;
391 int connector_type;
392 u16 igp_lane_info, conn_id, connector_object_id;
393 bool linkb;
394 struct radeon_i2c_bus_rec ddc_bus;
395 struct radeon_gpio_rec gpio;
396 struct radeon_hpd hpd;
397
398 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
399
400 if (data_offset == 0)
401 return false;
402
403 if (crev < 2)
404 return false;
405
406 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
407 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
408 (ctx->bios + data_offset +
409 le16_to_cpu(obj_header->usDisplayPathTableOffset));
410 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
411 (ctx->bios + data_offset +
412 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
413 device_support = le16_to_cpu(obj_header->usDeviceSupport);
414
415 path_size = 0;
416 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
417 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
418 ATOM_DISPLAY_OBJECT_PATH *path;
419 addr += path_size;
420 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
421 path_size += le16_to_cpu(path->usSize);
422 linkb = false;
423 if (device_support & le16_to_cpu(path->usDeviceTag)) {
424 uint8_t con_obj_id, con_obj_num, con_obj_type;
425
426 con_obj_id =
427 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
428 >> OBJECT_ID_SHIFT;
429 con_obj_num =
430 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
431 >> ENUM_ID_SHIFT;
432 con_obj_type =
433 (le16_to_cpu(path->usConnObjectId) &
434 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
435
436 /* TODO CV support */
437 if (le16_to_cpu(path->usDeviceTag) ==
438 ATOM_DEVICE_CV_SUPPORT)
439 continue;
440
441 /* IGP chips */
442 if ((rdev->flags & RADEON_IS_IGP) &&
443 (con_obj_id ==
444 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
445 uint16_t igp_offset = 0;
446 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
447
448 index =
449 GetIndexIntoMasterTable(DATA,
450 IntegratedSystemInfo);
451
452 atom_parse_data_header(ctx, index, &size, &frev,
453 &crev, &igp_offset);
454
455 if (crev >= 2) {
456 igp_obj =
457 (ATOM_INTEGRATED_SYSTEM_INFO_V2
458 *) (ctx->bios + igp_offset);
459
460 if (igp_obj) {
461 uint32_t slot_config, ct;
462
463 if (con_obj_num == 1)
464 slot_config =
465 igp_obj->
466 ulDDISlot1Config;
467 else
468 slot_config =
469 igp_obj->
470 ulDDISlot2Config;
471
472 ct = (slot_config >> 16) & 0xff;
473 connector_type =
474 object_connector_convert
475 [ct];
476 connector_object_id = ct;
477 igp_lane_info =
478 slot_config & 0xffff;
479 } else
480 continue;
481 } else
482 continue;
483 } else {
484 igp_lane_info = 0;
485 connector_type =
486 object_connector_convert[con_obj_id];
487 connector_object_id = con_obj_id;
488 }
489
490 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
491 continue;
492
493 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
494 j++) {
495 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
496
497 enc_obj_id =
498 (le16_to_cpu(path->usGraphicObjIds[j]) &
499 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
500 enc_obj_num =
501 (le16_to_cpu(path->usGraphicObjIds[j]) &
502 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
503 enc_obj_type =
504 (le16_to_cpu(path->usGraphicObjIds[j]) &
505 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
506
507 /* FIXME: add support for router objects */
508 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
509 if (enc_obj_num == 2)
510 linkb = true;
511 else
512 linkb = false;
513
514 radeon_add_atom_encoder(dev,
515 enc_obj_id,
516 le16_to_cpu
517 (path->
518 usDeviceTag));
519
520 }
521 }
522
523 /* look up gpio for ddc, hpd */
524 if ((le16_to_cpu(path->usDeviceTag) &
525 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
526 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
527 if (le16_to_cpu(path->usConnObjectId) ==
528 le16_to_cpu(con_obj->asObjects[j].
529 usObjectID)) {
530 ATOM_COMMON_RECORD_HEADER
531 *record =
532 (ATOM_COMMON_RECORD_HEADER
533 *)
534 (ctx->bios + data_offset +
535 le16_to_cpu(con_obj->
536 asObjects[j].
537 usRecordOffset));
538 ATOM_I2C_RECORD *i2c_record;
539 ATOM_HPD_INT_RECORD *hpd_record;
540 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
541 hpd.hpd = RADEON_HPD_NONE;
542
543 while (record->ucRecordType > 0
544 && record->
545 ucRecordType <=
546 ATOM_MAX_OBJECT_RECORD_NUMBER) {
547 switch (record->ucRecordType) {
548 case ATOM_I2C_RECORD_TYPE:
549 i2c_record =
550 (ATOM_I2C_RECORD *)
551 record;
552 i2c_config =
553 (ATOM_I2C_ID_CONFIG_ACCESS *)
554 &i2c_record->sucI2cId;
555 ddc_bus = radeon_lookup_i2c_gpio(rdev,
556 i2c_config->
557 ucAccess);
558 break;
559 case ATOM_HPD_INT_RECORD_TYPE:
560 hpd_record =
561 (ATOM_HPD_INT_RECORD *)
562 record;
563 gpio = radeon_lookup_gpio(rdev,
564 hpd_record->ucHPDIntGPIOID);
565 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
566 hpd.plugged_state = hpd_record->ucPlugged_PinState;
567 break;
568 }
569 record =
570 (ATOM_COMMON_RECORD_HEADER
571 *) ((char *)record
572 +
573 record->
574 ucRecordSize);
575 }
576 break;
577 }
578 }
579 } else {
580 hpd.hpd = RADEON_HPD_NONE;
581 ddc_bus.valid = false;
582 }
583
584 /* needed for aux chan transactions */
585 ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
586
587 conn_id = le16_to_cpu(path->usConnObjectId);
588
589 if (!radeon_atom_apply_quirks
590 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
591 &ddc_bus, &conn_id, &hpd))
592 continue;
593
594 radeon_add_atom_connector(dev,
595 conn_id,
596 le16_to_cpu(path->
597 usDeviceTag),
598 connector_type, &ddc_bus,
599 linkb, igp_lane_info,
600 connector_object_id,
601 &hpd);
602
603 }
604 }
605
606 radeon_link_encoder_connector(dev);
607
608 return true;
609 }
610
611 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
612 int connector_type,
613 uint16_t devices)
614 {
615 struct radeon_device *rdev = dev->dev_private;
616
617 if (rdev->flags & RADEON_IS_IGP) {
618 return supported_devices_connector_object_id_convert
619 [connector_type];
620 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
621 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
622 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
623 struct radeon_mode_info *mode_info = &rdev->mode_info;
624 struct atom_context *ctx = mode_info->atom_context;
625 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
626 uint16_t size, data_offset;
627 uint8_t frev, crev;
628 ATOM_XTMDS_INFO *xtmds;
629
630 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
631 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
632
633 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
634 if (connector_type == DRM_MODE_CONNECTOR_DVII)
635 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
636 else
637 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
638 } else {
639 if (connector_type == DRM_MODE_CONNECTOR_DVII)
640 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
641 else
642 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
643 }
644 } else {
645 return supported_devices_connector_object_id_convert
646 [connector_type];
647 }
648 }
649
650 struct bios_connector {
651 bool valid;
652 uint16_t line_mux;
653 uint16_t devices;
654 int connector_type;
655 struct radeon_i2c_bus_rec ddc_bus;
656 struct radeon_hpd hpd;
657 };
658
659 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
660 drm_device
661 *dev)
662 {
663 struct radeon_device *rdev = dev->dev_private;
664 struct radeon_mode_info *mode_info = &rdev->mode_info;
665 struct atom_context *ctx = mode_info->atom_context;
666 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
667 uint16_t size, data_offset;
668 uint8_t frev, crev;
669 uint16_t device_support;
670 uint8_t dac;
671 union atom_supported_devices *supported_devices;
672 int i, j, max_device;
673 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
674
675 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
676
677 supported_devices =
678 (union atom_supported_devices *)(ctx->bios + data_offset);
679
680 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
681
682 if (frev > 1)
683 max_device = ATOM_MAX_SUPPORTED_DEVICE;
684 else
685 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
686
687 for (i = 0; i < max_device; i++) {
688 ATOM_CONNECTOR_INFO_I2C ci =
689 supported_devices->info.asConnInfo[i];
690
691 bios_connectors[i].valid = false;
692
693 if (!(device_support & (1 << i))) {
694 continue;
695 }
696
697 if (i == ATOM_DEVICE_CV_INDEX) {
698 DRM_DEBUG("Skipping Component Video\n");
699 continue;
700 }
701
702 bios_connectors[i].connector_type =
703 supported_devices_connector_convert[ci.sucConnectorInfo.
704 sbfAccess.
705 bfConnectorType];
706
707 if (bios_connectors[i].connector_type ==
708 DRM_MODE_CONNECTOR_Unknown)
709 continue;
710
711 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
712
713 bios_connectors[i].line_mux =
714 ci.sucI2cId.ucAccess;
715
716 /* give tv unique connector ids */
717 if (i == ATOM_DEVICE_TV1_INDEX) {
718 bios_connectors[i].ddc_bus.valid = false;
719 bios_connectors[i].line_mux = 50;
720 } else if (i == ATOM_DEVICE_TV2_INDEX) {
721 bios_connectors[i].ddc_bus.valid = false;
722 bios_connectors[i].line_mux = 51;
723 } else if (i == ATOM_DEVICE_CV_INDEX) {
724 bios_connectors[i].ddc_bus.valid = false;
725 bios_connectors[i].line_mux = 52;
726 } else
727 bios_connectors[i].ddc_bus =
728 radeon_lookup_i2c_gpio(rdev,
729 bios_connectors[i].line_mux);
730
731 if ((crev > 1) && (frev > 1)) {
732 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
733 switch (isb) {
734 case 0x4:
735 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
736 break;
737 case 0xa:
738 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
739 break;
740 default:
741 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
742 break;
743 }
744 } else {
745 if (i == ATOM_DEVICE_DFP1_INDEX)
746 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
747 else if (i == ATOM_DEVICE_DFP2_INDEX)
748 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
749 else
750 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
751 }
752
753 /* Always set the connector type to VGA for CRT1/CRT2. if they are
754 * shared with a DVI port, we'll pick up the DVI connector when we
755 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
756 */
757 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
758 bios_connectors[i].connector_type =
759 DRM_MODE_CONNECTOR_VGA;
760
761 if (!radeon_atom_apply_quirks
762 (dev, (1 << i), &bios_connectors[i].connector_type,
763 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
764 &bios_connectors[i].hpd))
765 continue;
766
767 bios_connectors[i].valid = true;
768 bios_connectors[i].devices = (1 << i);
769
770 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
771 radeon_add_atom_encoder(dev,
772 radeon_get_encoder_id(dev,
773 (1 << i),
774 dac),
775 (1 << i));
776 else
777 radeon_add_legacy_encoder(dev,
778 radeon_get_encoder_id(dev,
779 (1 << i),
780 dac),
781 (1 << i));
782 }
783
784 /* combine shared connectors */
785 for (i = 0; i < max_device; i++) {
786 if (bios_connectors[i].valid) {
787 for (j = 0; j < max_device; j++) {
788 if (bios_connectors[j].valid && (i != j)) {
789 if (bios_connectors[i].line_mux ==
790 bios_connectors[j].line_mux) {
791 /* make sure not to combine LVDS */
792 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
793 bios_connectors[i].line_mux = 53;
794 bios_connectors[i].ddc_bus.valid = false;
795 continue;
796 }
797 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
798 bios_connectors[j].line_mux = 53;
799 bios_connectors[j].ddc_bus.valid = false;
800 continue;
801 }
802 /* combine analog and digital for DVI-I */
803 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
804 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
805 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
806 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
807 bios_connectors[i].devices |=
808 bios_connectors[j].devices;
809 bios_connectors[i].connector_type =
810 DRM_MODE_CONNECTOR_DVII;
811 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
812 bios_connectors[i].hpd =
813 bios_connectors[j].hpd;
814 bios_connectors[j].valid = false;
815 }
816 }
817 }
818 }
819 }
820 }
821
822 /* add the connectors */
823 for (i = 0; i < max_device; i++) {
824 if (bios_connectors[i].valid) {
825 uint16_t connector_object_id =
826 atombios_get_connector_object_id(dev,
827 bios_connectors[i].connector_type,
828 bios_connectors[i].devices);
829 radeon_add_atom_connector(dev,
830 bios_connectors[i].line_mux,
831 bios_connectors[i].devices,
832 bios_connectors[i].
833 connector_type,
834 &bios_connectors[i].ddc_bus,
835 false, 0,
836 connector_object_id,
837 &bios_connectors[i].hpd);
838 }
839 }
840
841 radeon_link_encoder_connector(dev);
842
843 return true;
844 }
845
846 union firmware_info {
847 ATOM_FIRMWARE_INFO info;
848 ATOM_FIRMWARE_INFO_V1_2 info_12;
849 ATOM_FIRMWARE_INFO_V1_3 info_13;
850 ATOM_FIRMWARE_INFO_V1_4 info_14;
851 ATOM_FIRMWARE_INFO_V2_1 info_21;
852 };
853
854 bool radeon_atom_get_clock_info(struct drm_device *dev)
855 {
856 struct radeon_device *rdev = dev->dev_private;
857 struct radeon_mode_info *mode_info = &rdev->mode_info;
858 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
859 union firmware_info *firmware_info;
860 uint8_t frev, crev;
861 struct radeon_pll *p1pll = &rdev->clock.p1pll;
862 struct radeon_pll *p2pll = &rdev->clock.p2pll;
863 struct radeon_pll *dcpll = &rdev->clock.dcpll;
864 struct radeon_pll *spll = &rdev->clock.spll;
865 struct radeon_pll *mpll = &rdev->clock.mpll;
866 uint16_t data_offset;
867
868 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
869 &crev, &data_offset);
870
871 firmware_info =
872 (union firmware_info *)(mode_info->atom_context->bios +
873 data_offset);
874
875 if (firmware_info) {
876 /* pixel clocks */
877 p1pll->reference_freq =
878 le16_to_cpu(firmware_info->info.usReferenceClock);
879 p1pll->reference_div = 0;
880
881 if (crev < 2)
882 p1pll->pll_out_min =
883 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
884 else
885 p1pll->pll_out_min =
886 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
887 p1pll->pll_out_max =
888 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
889
890 if (crev >= 4) {
891 p1pll->lcd_pll_out_min =
892 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
893 if (p1pll->lcd_pll_out_min == 0)
894 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
895 p1pll->lcd_pll_out_max =
896 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
897 if (p1pll->lcd_pll_out_max == 0)
898 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
899 } else {
900 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
901 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
902 }
903
904 if (p1pll->pll_out_min == 0) {
905 if (ASIC_IS_AVIVO(rdev))
906 p1pll->pll_out_min = 64800;
907 else
908 p1pll->pll_out_min = 20000;
909 } else if (p1pll->pll_out_min > 64800) {
910 /* Limiting the pll output range is a good thing generally as
911 * it limits the number of possible pll combinations for a given
912 * frequency presumably to the ones that work best on each card.
913 * However, certain duallink DVI monitors seem to like
914 * pll combinations that would be limited by this at least on
915 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
916 * family.
917 */
918 if (!radeon_new_pll)
919 p1pll->pll_out_min = 64800;
920 }
921
922 p1pll->pll_in_min =
923 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
924 p1pll->pll_in_max =
925 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
926
927 *p2pll = *p1pll;
928
929 /* system clock */
930 spll->reference_freq =
931 le16_to_cpu(firmware_info->info.usReferenceClock);
932 spll->reference_div = 0;
933
934 spll->pll_out_min =
935 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
936 spll->pll_out_max =
937 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
938
939 /* ??? */
940 if (spll->pll_out_min == 0) {
941 if (ASIC_IS_AVIVO(rdev))
942 spll->pll_out_min = 64800;
943 else
944 spll->pll_out_min = 20000;
945 }
946
947 spll->pll_in_min =
948 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
949 spll->pll_in_max =
950 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
951
952 /* memory clock */
953 mpll->reference_freq =
954 le16_to_cpu(firmware_info->info.usReferenceClock);
955 mpll->reference_div = 0;
956
957 mpll->pll_out_min =
958 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
959 mpll->pll_out_max =
960 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
961
962 /* ??? */
963 if (mpll->pll_out_min == 0) {
964 if (ASIC_IS_AVIVO(rdev))
965 mpll->pll_out_min = 64800;
966 else
967 mpll->pll_out_min = 20000;
968 }
969
970 mpll->pll_in_min =
971 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
972 mpll->pll_in_max =
973 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
974
975 rdev->clock.default_sclk =
976 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
977 rdev->clock.default_mclk =
978 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
979
980 if (ASIC_IS_DCE4(rdev)) {
981 rdev->clock.default_dispclk =
982 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
983 if (rdev->clock.default_dispclk == 0)
984 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
985 rdev->clock.dp_extclk =
986 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
987 }
988 *dcpll = *p1pll;
989
990 return true;
991 }
992
993 return false;
994 }
995
996 union igp_info {
997 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
998 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
999 };
1000
1001 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1002 {
1003 struct radeon_mode_info *mode_info = &rdev->mode_info;
1004 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1005 union igp_info *igp_info;
1006 u8 frev, crev;
1007 u16 data_offset;
1008
1009 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1010 &crev, &data_offset);
1011
1012 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1013 data_offset);
1014
1015 if (igp_info) {
1016 switch (crev) {
1017 case 1:
1018 if (igp_info->info.ucMemoryType & 0xf0)
1019 return true;
1020 break;
1021 case 2:
1022 if (igp_info->info_2.ucMemoryType & 0x0f)
1023 return true;
1024 break;
1025 default:
1026 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1027 break;
1028 }
1029 }
1030 return false;
1031 }
1032
1033 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1034 struct radeon_encoder_int_tmds *tmds)
1035 {
1036 struct drm_device *dev = encoder->base.dev;
1037 struct radeon_device *rdev = dev->dev_private;
1038 struct radeon_mode_info *mode_info = &rdev->mode_info;
1039 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1040 uint16_t data_offset;
1041 struct _ATOM_TMDS_INFO *tmds_info;
1042 uint8_t frev, crev;
1043 uint16_t maxfreq;
1044 int i;
1045
1046 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1047 &crev, &data_offset);
1048
1049 tmds_info =
1050 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1051 data_offset);
1052
1053 if (tmds_info) {
1054 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1055 for (i = 0; i < 4; i++) {
1056 tmds->tmds_pll[i].freq =
1057 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1058 tmds->tmds_pll[i].value =
1059 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1060 tmds->tmds_pll[i].value |=
1061 (tmds_info->asMiscInfo[i].
1062 ucPLL_VCO_Gain & 0x3f) << 6;
1063 tmds->tmds_pll[i].value |=
1064 (tmds_info->asMiscInfo[i].
1065 ucPLL_DutyCycle & 0xf) << 12;
1066 tmds->tmds_pll[i].value |=
1067 (tmds_info->asMiscInfo[i].
1068 ucPLL_VoltageSwing & 0xf) << 16;
1069
1070 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1071 tmds->tmds_pll[i].freq,
1072 tmds->tmds_pll[i].value);
1073
1074 if (maxfreq == tmds->tmds_pll[i].freq) {
1075 tmds->tmds_pll[i].freq = 0xffffffff;
1076 break;
1077 }
1078 }
1079 return true;
1080 }
1081 return false;
1082 }
1083
1084 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1085 radeon_encoder
1086 *encoder,
1087 int id)
1088 {
1089 struct drm_device *dev = encoder->base.dev;
1090 struct radeon_device *rdev = dev->dev_private;
1091 struct radeon_mode_info *mode_info = &rdev->mode_info;
1092 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1093 uint16_t data_offset;
1094 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1095 uint8_t frev, crev;
1096 struct radeon_atom_ss *ss = NULL;
1097 int i;
1098
1099 if (id > ATOM_MAX_SS_ENTRY)
1100 return NULL;
1101
1102 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1103 &crev, &data_offset);
1104
1105 ss_info =
1106 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1107
1108 if (ss_info) {
1109 ss =
1110 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1111
1112 if (!ss)
1113 return NULL;
1114
1115 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1116 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1117 ss->percentage =
1118 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1119 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1120 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1121 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1122 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1123 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1124 break;
1125 }
1126 }
1127 }
1128 return ss;
1129 }
1130
1131 static void radeon_atom_apply_lvds_quirks(struct drm_device *dev,
1132 struct radeon_encoder_atom_dig *lvds)
1133 {
1134
1135 /* Toshiba A300-1BU laptop panel doesn't like new pll divider algo */
1136 if ((dev->pdev->device == 0x95c4) &&
1137 (dev->pdev->subsystem_vendor == 0x1179) &&
1138 (dev->pdev->subsystem_device == 0xff50)) {
1139 if ((lvds->native_mode.hdisplay == 1280) &&
1140 (lvds->native_mode.vdisplay == 800))
1141 lvds->pll_algo = PLL_ALGO_LEGACY;
1142 }
1143
1144 /* Dell Studio 15 laptop panel doesn't like new pll divider algo */
1145 if ((dev->pdev->device == 0x95c4) &&
1146 (dev->pdev->subsystem_vendor == 0x1028) &&
1147 (dev->pdev->subsystem_device == 0x029f)) {
1148 if ((lvds->native_mode.hdisplay == 1280) &&
1149 (lvds->native_mode.vdisplay == 800))
1150 lvds->pll_algo = PLL_ALGO_LEGACY;
1151 }
1152
1153 }
1154
1155 union lvds_info {
1156 struct _ATOM_LVDS_INFO info;
1157 struct _ATOM_LVDS_INFO_V12 info_12;
1158 };
1159
1160 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1161 radeon_encoder
1162 *encoder)
1163 {
1164 struct drm_device *dev = encoder->base.dev;
1165 struct radeon_device *rdev = dev->dev_private;
1166 struct radeon_mode_info *mode_info = &rdev->mode_info;
1167 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1168 uint16_t data_offset, misc;
1169 union lvds_info *lvds_info;
1170 uint8_t frev, crev;
1171 struct radeon_encoder_atom_dig *lvds = NULL;
1172
1173 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1174 &crev, &data_offset);
1175
1176 lvds_info =
1177 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1178
1179 if (lvds_info) {
1180 lvds =
1181 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1182
1183 if (!lvds)
1184 return NULL;
1185
1186 lvds->native_mode.clock =
1187 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1188 lvds->native_mode.hdisplay =
1189 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1190 lvds->native_mode.vdisplay =
1191 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1192 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1193 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1194 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1195 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1196 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1197 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1198 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1199 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1200 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1201 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1202 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1203 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1204 lvds->panel_pwr_delay =
1205 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1206 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1207
1208 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1209 if (misc & ATOM_VSYNC_POLARITY)
1210 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1211 if (misc & ATOM_HSYNC_POLARITY)
1212 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1213 if (misc & ATOM_COMPOSITESYNC)
1214 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1215 if (misc & ATOM_INTERLACE)
1216 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1217 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1218 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1219
1220 /* set crtc values */
1221 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1222
1223 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1224
1225 if (ASIC_IS_AVIVO(rdev)) {
1226 if (radeon_new_pll == 0)
1227 lvds->pll_algo = PLL_ALGO_LEGACY;
1228 else
1229 lvds->pll_algo = PLL_ALGO_NEW;
1230 } else {
1231 if (radeon_new_pll == 1)
1232 lvds->pll_algo = PLL_ALGO_NEW;
1233 else
1234 lvds->pll_algo = PLL_ALGO_LEGACY;
1235 }
1236
1237 /* LVDS quirks */
1238 radeon_atom_apply_lvds_quirks(dev, lvds);
1239
1240 encoder->native_mode = lvds->native_mode;
1241 }
1242 return lvds;
1243 }
1244
1245 struct radeon_encoder_primary_dac *
1246 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1247 {
1248 struct drm_device *dev = encoder->base.dev;
1249 struct radeon_device *rdev = dev->dev_private;
1250 struct radeon_mode_info *mode_info = &rdev->mode_info;
1251 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1252 uint16_t data_offset;
1253 struct _COMPASSIONATE_DATA *dac_info;
1254 uint8_t frev, crev;
1255 uint8_t bg, dac;
1256 struct radeon_encoder_primary_dac *p_dac = NULL;
1257
1258 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1259
1260 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1261
1262 if (dac_info) {
1263 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1264
1265 if (!p_dac)
1266 return NULL;
1267
1268 bg = dac_info->ucDAC1_BG_Adjustment;
1269 dac = dac_info->ucDAC1_DAC_Adjustment;
1270 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1271
1272 }
1273 return p_dac;
1274 }
1275
1276 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1277 struct drm_display_mode *mode)
1278 {
1279 struct radeon_mode_info *mode_info = &rdev->mode_info;
1280 ATOM_ANALOG_TV_INFO *tv_info;
1281 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1282 ATOM_DTD_FORMAT *dtd_timings;
1283 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1284 u8 frev, crev;
1285 u16 data_offset, misc;
1286
1287 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1288
1289 switch (crev) {
1290 case 1:
1291 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1292 if (index > MAX_SUPPORTED_TV_TIMING)
1293 return false;
1294
1295 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1296 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1297 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1298 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1299 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1300
1301 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1302 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1303 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1304 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1305 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1306
1307 mode->flags = 0;
1308 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1309 if (misc & ATOM_VSYNC_POLARITY)
1310 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1311 if (misc & ATOM_HSYNC_POLARITY)
1312 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1313 if (misc & ATOM_COMPOSITESYNC)
1314 mode->flags |= DRM_MODE_FLAG_CSYNC;
1315 if (misc & ATOM_INTERLACE)
1316 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1317 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1318 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1319
1320 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1321
1322 if (index == 1) {
1323 /* PAL timings appear to have wrong values for totals */
1324 mode->crtc_htotal -= 1;
1325 mode->crtc_vtotal -= 1;
1326 }
1327 break;
1328 case 2:
1329 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1330 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1331 return false;
1332
1333 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1334 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1335 le16_to_cpu(dtd_timings->usHBlanking_Time);
1336 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1337 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1338 le16_to_cpu(dtd_timings->usHSyncOffset);
1339 mode->crtc_hsync_end = mode->crtc_hsync_start +
1340 le16_to_cpu(dtd_timings->usHSyncWidth);
1341
1342 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1343 le16_to_cpu(dtd_timings->usVBlanking_Time);
1344 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1345 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1346 le16_to_cpu(dtd_timings->usVSyncOffset);
1347 mode->crtc_vsync_end = mode->crtc_vsync_start +
1348 le16_to_cpu(dtd_timings->usVSyncWidth);
1349
1350 mode->flags = 0;
1351 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1352 if (misc & ATOM_VSYNC_POLARITY)
1353 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1354 if (misc & ATOM_HSYNC_POLARITY)
1355 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1356 if (misc & ATOM_COMPOSITESYNC)
1357 mode->flags |= DRM_MODE_FLAG_CSYNC;
1358 if (misc & ATOM_INTERLACE)
1359 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1360 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1361 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1362
1363 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1364 break;
1365 }
1366 return true;
1367 }
1368
1369 enum radeon_tv_std
1370 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1371 {
1372 struct radeon_mode_info *mode_info = &rdev->mode_info;
1373 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1374 uint16_t data_offset;
1375 uint8_t frev, crev;
1376 struct _ATOM_ANALOG_TV_INFO *tv_info;
1377 enum radeon_tv_std tv_std = TV_STD_NTSC;
1378
1379 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1380
1381 tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1382
1383 switch (tv_info->ucTV_BootUpDefaultStandard) {
1384 case ATOM_TV_NTSC:
1385 tv_std = TV_STD_NTSC;
1386 DRM_INFO("Default TV standard: NTSC\n");
1387 break;
1388 case ATOM_TV_NTSCJ:
1389 tv_std = TV_STD_NTSC_J;
1390 DRM_INFO("Default TV standard: NTSC-J\n");
1391 break;
1392 case ATOM_TV_PAL:
1393 tv_std = TV_STD_PAL;
1394 DRM_INFO("Default TV standard: PAL\n");
1395 break;
1396 case ATOM_TV_PALM:
1397 tv_std = TV_STD_PAL_M;
1398 DRM_INFO("Default TV standard: PAL-M\n");
1399 break;
1400 case ATOM_TV_PALN:
1401 tv_std = TV_STD_PAL_N;
1402 DRM_INFO("Default TV standard: PAL-N\n");
1403 break;
1404 case ATOM_TV_PALCN:
1405 tv_std = TV_STD_PAL_CN;
1406 DRM_INFO("Default TV standard: PAL-CN\n");
1407 break;
1408 case ATOM_TV_PAL60:
1409 tv_std = TV_STD_PAL_60;
1410 DRM_INFO("Default TV standard: PAL-60\n");
1411 break;
1412 case ATOM_TV_SECAM:
1413 tv_std = TV_STD_SECAM;
1414 DRM_INFO("Default TV standard: SECAM\n");
1415 break;
1416 default:
1417 tv_std = TV_STD_NTSC;
1418 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1419 break;
1420 }
1421 return tv_std;
1422 }
1423
1424 struct radeon_encoder_tv_dac *
1425 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1426 {
1427 struct drm_device *dev = encoder->base.dev;
1428 struct radeon_device *rdev = dev->dev_private;
1429 struct radeon_mode_info *mode_info = &rdev->mode_info;
1430 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1431 uint16_t data_offset;
1432 struct _COMPASSIONATE_DATA *dac_info;
1433 uint8_t frev, crev;
1434 uint8_t bg, dac;
1435 struct radeon_encoder_tv_dac *tv_dac = NULL;
1436
1437 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1438
1439 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1440
1441 if (dac_info) {
1442 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1443
1444 if (!tv_dac)
1445 return NULL;
1446
1447 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1448 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1449 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1450
1451 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1452 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1453 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1454
1455 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1456 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1457 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1458
1459 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1460 }
1461 return tv_dac;
1462 }
1463
1464 static const char *thermal_controller_names[] = {
1465 "NONE",
1466 "LM63",
1467 "ADM1032",
1468 "ADM1030",
1469 "MUA6649",
1470 "LM64",
1471 "F75375",
1472 "ASC7512",
1473 };
1474
1475 static const char *pp_lib_thermal_controller_names[] = {
1476 "NONE",
1477 "LM63",
1478 "ADM1032",
1479 "ADM1030",
1480 "MUA6649",
1481 "LM64",
1482 "F75375",
1483 "RV6xx",
1484 "RV770",
1485 "ADT7473",
1486 };
1487
1488 union power_info {
1489 struct _ATOM_POWERPLAY_INFO info;
1490 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1491 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1492 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1493 };
1494
1495 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1496 {
1497 struct radeon_mode_info *mode_info = &rdev->mode_info;
1498 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1499 u16 data_offset;
1500 u8 frev, crev;
1501 u32 misc, misc2 = 0, sclk, mclk;
1502 union power_info *power_info;
1503 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1504 struct _ATOM_PPLIB_STATE *power_state;
1505 int num_modes = 0, i, j;
1506 int state_index = 0, mode_index = 0;
1507 struct radeon_i2c_bus_rec i2c_bus;
1508
1509 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1510
1511 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1512
1513 rdev->pm.default_power_state = NULL;
1514
1515 if (power_info) {
1516 if (frev < 4) {
1517 /* add the i2c bus for thermal/fan chip */
1518 if (power_info->info.ucOverdriveThermalController > 0) {
1519 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1520 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1521 power_info->info.ucOverdriveControllerAddress >> 1);
1522 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1523 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1524 }
1525 num_modes = power_info->info.ucNumOfPowerModeEntries;
1526 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1527 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1528 for (i = 0; i < num_modes; i++) {
1529 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1530 switch (frev) {
1531 case 1:
1532 rdev->pm.power_state[state_index].num_clock_modes = 1;
1533 rdev->pm.power_state[state_index].clock_info[0].mclk =
1534 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1535 rdev->pm.power_state[state_index].clock_info[0].sclk =
1536 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1537 /* skip invalid modes */
1538 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1539 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1540 continue;
1541 /* skip overclock modes for now */
1542 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1543 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1544 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1545 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1546 continue;
1547 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1548 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1549 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1550 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1551 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1552 VOLTAGE_GPIO;
1553 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1554 radeon_lookup_gpio(rdev,
1555 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1556 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1557 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1558 true;
1559 else
1560 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1561 false;
1562 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1563 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1564 VOLTAGE_VDDC;
1565 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1566 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1567 }
1568 /* order matters! */
1569 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1570 rdev->pm.power_state[state_index].type =
1571 POWER_STATE_TYPE_POWERSAVE;
1572 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1573 rdev->pm.power_state[state_index].type =
1574 POWER_STATE_TYPE_BATTERY;
1575 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1576 rdev->pm.power_state[state_index].type =
1577 POWER_STATE_TYPE_BATTERY;
1578 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1579 rdev->pm.power_state[state_index].type =
1580 POWER_STATE_TYPE_BALANCED;
1581 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1582 rdev->pm.power_state[state_index].type =
1583 POWER_STATE_TYPE_PERFORMANCE;
1584 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1585 rdev->pm.power_state[state_index].type =
1586 POWER_STATE_TYPE_DEFAULT;
1587 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1588 rdev->pm.power_state[state_index].default_clock_mode =
1589 &rdev->pm.power_state[state_index].clock_info[0];
1590 }
1591 state_index++;
1592 break;
1593 case 2:
1594 rdev->pm.power_state[state_index].num_clock_modes = 1;
1595 rdev->pm.power_state[state_index].clock_info[0].mclk =
1596 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1597 rdev->pm.power_state[state_index].clock_info[0].sclk =
1598 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1599 /* skip invalid modes */
1600 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1601 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1602 continue;
1603 /* skip overclock modes for now */
1604 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1605 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1606 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1607 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1608 continue;
1609 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1610 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1611 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1612 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1613 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1614 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1615 VOLTAGE_GPIO;
1616 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1617 radeon_lookup_gpio(rdev,
1618 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1619 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1620 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1621 true;
1622 else
1623 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1624 false;
1625 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1626 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1627 VOLTAGE_VDDC;
1628 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1629 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1630 }
1631 /* order matters! */
1632 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1633 rdev->pm.power_state[state_index].type =
1634 POWER_STATE_TYPE_POWERSAVE;
1635 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1636 rdev->pm.power_state[state_index].type =
1637 POWER_STATE_TYPE_BATTERY;
1638 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1639 rdev->pm.power_state[state_index].type =
1640 POWER_STATE_TYPE_BATTERY;
1641 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1642 rdev->pm.power_state[state_index].type =
1643 POWER_STATE_TYPE_BALANCED;
1644 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1645 rdev->pm.power_state[state_index].type =
1646 POWER_STATE_TYPE_PERFORMANCE;
1647 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1648 rdev->pm.power_state[state_index].type =
1649 POWER_STATE_TYPE_BALANCED;
1650 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1651 rdev->pm.power_state[state_index].type =
1652 POWER_STATE_TYPE_DEFAULT;
1653 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1654 rdev->pm.power_state[state_index].default_clock_mode =
1655 &rdev->pm.power_state[state_index].clock_info[0];
1656 }
1657 state_index++;
1658 break;
1659 case 3:
1660 rdev->pm.power_state[state_index].num_clock_modes = 1;
1661 rdev->pm.power_state[state_index].clock_info[0].mclk =
1662 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1663 rdev->pm.power_state[state_index].clock_info[0].sclk =
1664 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1665 /* skip invalid modes */
1666 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1667 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1668 continue;
1669 /* skip overclock modes for now */
1670 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1671 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1672 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1673 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1674 continue;
1675 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1676 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1677 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1678 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1679 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1680 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1681 VOLTAGE_GPIO;
1682 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1683 radeon_lookup_gpio(rdev,
1684 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1685 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1686 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1687 true;
1688 else
1689 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1690 false;
1691 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1692 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1693 VOLTAGE_VDDC;
1694 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1695 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1696 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1697 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1698 true;
1699 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1700 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1701 }
1702 }
1703 /* order matters! */
1704 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1705 rdev->pm.power_state[state_index].type =
1706 POWER_STATE_TYPE_POWERSAVE;
1707 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1708 rdev->pm.power_state[state_index].type =
1709 POWER_STATE_TYPE_BATTERY;
1710 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1711 rdev->pm.power_state[state_index].type =
1712 POWER_STATE_TYPE_BATTERY;
1713 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1714 rdev->pm.power_state[state_index].type =
1715 POWER_STATE_TYPE_BALANCED;
1716 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1717 rdev->pm.power_state[state_index].type =
1718 POWER_STATE_TYPE_PERFORMANCE;
1719 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1720 rdev->pm.power_state[state_index].type =
1721 POWER_STATE_TYPE_BALANCED;
1722 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1723 rdev->pm.power_state[state_index].type =
1724 POWER_STATE_TYPE_DEFAULT;
1725 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1726 rdev->pm.power_state[state_index].default_clock_mode =
1727 &rdev->pm.power_state[state_index].clock_info[0];
1728 }
1729 state_index++;
1730 break;
1731 }
1732 }
1733 } else if (frev == 4) {
1734 /* add the i2c bus for thermal/fan chip */
1735 /* no support for internal controller yet */
1736 if (power_info->info_4.sThermalController.ucType > 0) {
1737 if ((power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) &&
1738 (power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV770)) {
1739 DRM_INFO("Internal thermal controller %s fan control\n",
1740 (power_info->info_4.sThermalController.ucFanParameters &
1741 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1742 } else {
1743 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1744 pp_lib_thermal_controller_names[power_info->info_4.sThermalController.ucType],
1745 power_info->info_4.sThermalController.ucI2cAddress >> 1,
1746 (power_info->info_4.sThermalController.ucFanParameters &
1747 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1748 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info_4.sThermalController.ucI2cLine);
1749 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1750 }
1751 }
1752 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1753 mode_index = 0;
1754 power_state = (struct _ATOM_PPLIB_STATE *)
1755 (mode_info->atom_context->bios +
1756 data_offset +
1757 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1758 i * power_info->info_4.ucStateEntrySize);
1759 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1760 (mode_info->atom_context->bios +
1761 data_offset +
1762 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1763 (power_state->ucNonClockStateIndex *
1764 power_info->info_4.ucNonClockSize));
1765 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1766 if (rdev->flags & RADEON_IS_IGP) {
1767 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1768 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1769 (mode_info->atom_context->bios +
1770 data_offset +
1771 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1772 (power_state->ucClockStateIndices[j] *
1773 power_info->info_4.ucClockInfoSize));
1774 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1775 sclk |= clock_info->ucLowEngineClockHigh << 16;
1776 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1777 /* skip invalid modes */
1778 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1779 continue;
1780 /* skip overclock modes for now */
1781 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1782 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
1783 continue;
1784 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1785 VOLTAGE_SW;
1786 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1787 clock_info->usVDDC;
1788 mode_index++;
1789 } else {
1790 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1791 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1792 (mode_info->atom_context->bios +
1793 data_offset +
1794 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1795 (power_state->ucClockStateIndices[j] *
1796 power_info->info_4.ucClockInfoSize));
1797 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1798 sclk |= clock_info->ucEngineClockHigh << 16;
1799 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1800 mclk |= clock_info->ucMemoryClockHigh << 16;
1801 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1802 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1803 /* skip invalid modes */
1804 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1805 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1806 continue;
1807 /* skip overclock modes for now */
1808 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1809 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1810 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1811 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1812 continue;
1813 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1814 VOLTAGE_SW;
1815 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1816 clock_info->usVDDC;
1817 mode_index++;
1818 }
1819 }
1820 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1821 if (mode_index) {
1822 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1823 misc2 = le16_to_cpu(non_clock_info->usClassification);
1824 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1825 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1826 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1827 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1828 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1829 rdev->pm.power_state[state_index].type =
1830 POWER_STATE_TYPE_BATTERY;
1831 break;
1832 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1833 rdev->pm.power_state[state_index].type =
1834 POWER_STATE_TYPE_BALANCED;
1835 break;
1836 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1837 rdev->pm.power_state[state_index].type =
1838 POWER_STATE_TYPE_PERFORMANCE;
1839 break;
1840 }
1841 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1842 rdev->pm.power_state[state_index].type =
1843 POWER_STATE_TYPE_DEFAULT;
1844 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1845 rdev->pm.power_state[state_index].default_clock_mode =
1846 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1847 }
1848 state_index++;
1849 }
1850 }
1851 }
1852 } else {
1853 /* XXX figure out some good default low power mode for cards w/out power tables */
1854 }
1855
1856 if (rdev->pm.default_power_state == NULL) {
1857 /* add the default mode */
1858 rdev->pm.power_state[state_index].type =
1859 POWER_STATE_TYPE_DEFAULT;
1860 rdev->pm.power_state[state_index].num_clock_modes = 1;
1861 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1862 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1863 rdev->pm.power_state[state_index].default_clock_mode =
1864 &rdev->pm.power_state[state_index].clock_info[0];
1865 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1866 if (rdev->asic->get_pcie_lanes)
1867 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1868 else
1869 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1870 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1871 state_index++;
1872 }
1873 rdev->pm.num_power_states = state_index;
1874
1875 rdev->pm.current_power_state = rdev->pm.default_power_state;
1876 rdev->pm.current_clock_mode =
1877 rdev->pm.default_power_state->default_clock_mode;
1878 }
1879
1880 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1881 {
1882 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1883 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1884
1885 args.ucEnable = enable;
1886
1887 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1888 }
1889
1890 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1891 {
1892 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1893 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1894
1895 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1896 return args.ulReturnEngineClock;
1897 }
1898
1899 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1900 {
1901 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1902 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1903
1904 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1905 return args.ulReturnMemoryClock;
1906 }
1907
1908 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1909 uint32_t eng_clock)
1910 {
1911 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1912 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1913
1914 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1915
1916 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1917 }
1918
1919 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1920 uint32_t mem_clock)
1921 {
1922 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1923 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1924
1925 if (rdev->flags & RADEON_IS_IGP)
1926 return;
1927
1928 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1929
1930 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1931 }
1932
1933 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1934 {
1935 struct radeon_device *rdev = dev->dev_private;
1936 uint32_t bios_2_scratch, bios_6_scratch;
1937
1938 if (rdev->family >= CHIP_R600) {
1939 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1940 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1941 } else {
1942 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1943 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1944 }
1945
1946 /* let the bios control the backlight */
1947 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1948
1949 /* tell the bios not to handle mode switching */
1950 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1951
1952 if (rdev->family >= CHIP_R600) {
1953 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1954 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1955 } else {
1956 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1957 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1958 }
1959
1960 }
1961
1962 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1963 {
1964 uint32_t scratch_reg;
1965 int i;
1966
1967 if (rdev->family >= CHIP_R600)
1968 scratch_reg = R600_BIOS_0_SCRATCH;
1969 else
1970 scratch_reg = RADEON_BIOS_0_SCRATCH;
1971
1972 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1973 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1974 }
1975
1976 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1977 {
1978 uint32_t scratch_reg;
1979 int i;
1980
1981 if (rdev->family >= CHIP_R600)
1982 scratch_reg = R600_BIOS_0_SCRATCH;
1983 else
1984 scratch_reg = RADEON_BIOS_0_SCRATCH;
1985
1986 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1987 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1988 }
1989
1990 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1991 {
1992 struct drm_device *dev = encoder->dev;
1993 struct radeon_device *rdev = dev->dev_private;
1994 uint32_t bios_6_scratch;
1995
1996 if (rdev->family >= CHIP_R600)
1997 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1998 else
1999 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2000
2001 if (lock)
2002 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2003 else
2004 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2005
2006 if (rdev->family >= CHIP_R600)
2007 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2008 else
2009 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2010 }
2011
2012 /* at some point we may want to break this out into individual functions */
2013 void
2014 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2015 struct drm_encoder *encoder,
2016 bool connected)
2017 {
2018 struct drm_device *dev = connector->dev;
2019 struct radeon_device *rdev = dev->dev_private;
2020 struct radeon_connector *radeon_connector =
2021 to_radeon_connector(connector);
2022 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2023 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2024
2025 if (rdev->family >= CHIP_R600) {
2026 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2027 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2028 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2029 } else {
2030 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2031 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2032 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2033 }
2034
2035 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2036 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2037 if (connected) {
2038 DRM_DEBUG("TV1 connected\n");
2039 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2040 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2041 } else {
2042 DRM_DEBUG("TV1 disconnected\n");
2043 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2044 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2045 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2046 }
2047 }
2048 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2049 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2050 if (connected) {
2051 DRM_DEBUG("CV connected\n");
2052 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2053 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2054 } else {
2055 DRM_DEBUG("CV disconnected\n");
2056 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2057 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2058 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2059 }
2060 }
2061 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2062 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2063 if (connected) {
2064 DRM_DEBUG("LCD1 connected\n");
2065 bios_0_scratch |= ATOM_S0_LCD1;
2066 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2067 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2068 } else {
2069 DRM_DEBUG("LCD1 disconnected\n");
2070 bios_0_scratch &= ~ATOM_S0_LCD1;
2071 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2072 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2073 }
2074 }
2075 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2076 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2077 if (connected) {
2078 DRM_DEBUG("CRT1 connected\n");
2079 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2080 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2081 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2082 } else {
2083 DRM_DEBUG("CRT1 disconnected\n");
2084 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2085 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2086 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2087 }
2088 }
2089 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2090 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2091 if (connected) {
2092 DRM_DEBUG("CRT2 connected\n");
2093 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2094 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2095 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2096 } else {
2097 DRM_DEBUG("CRT2 disconnected\n");
2098 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2099 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2100 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2101 }
2102 }
2103 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2104 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2105 if (connected) {
2106 DRM_DEBUG("DFP1 connected\n");
2107 bios_0_scratch |= ATOM_S0_DFP1;
2108 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2109 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2110 } else {
2111 DRM_DEBUG("DFP1 disconnected\n");
2112 bios_0_scratch &= ~ATOM_S0_DFP1;
2113 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2114 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2115 }
2116 }
2117 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2118 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2119 if (connected) {
2120 DRM_DEBUG("DFP2 connected\n");
2121 bios_0_scratch |= ATOM_S0_DFP2;
2122 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2123 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2124 } else {
2125 DRM_DEBUG("DFP2 disconnected\n");
2126 bios_0_scratch &= ~ATOM_S0_DFP2;
2127 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2128 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2129 }
2130 }
2131 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2132 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2133 if (connected) {
2134 DRM_DEBUG("DFP3 connected\n");
2135 bios_0_scratch |= ATOM_S0_DFP3;
2136 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2137 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2138 } else {
2139 DRM_DEBUG("DFP3 disconnected\n");
2140 bios_0_scratch &= ~ATOM_S0_DFP3;
2141 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2142 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2143 }
2144 }
2145 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2146 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2147 if (connected) {
2148 DRM_DEBUG("DFP4 connected\n");
2149 bios_0_scratch |= ATOM_S0_DFP4;
2150 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2151 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2152 } else {
2153 DRM_DEBUG("DFP4 disconnected\n");
2154 bios_0_scratch &= ~ATOM_S0_DFP4;
2155 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2156 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2157 }
2158 }
2159 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2160 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2161 if (connected) {
2162 DRM_DEBUG("DFP5 connected\n");
2163 bios_0_scratch |= ATOM_S0_DFP5;
2164 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2165 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2166 } else {
2167 DRM_DEBUG("DFP5 disconnected\n");
2168 bios_0_scratch &= ~ATOM_S0_DFP5;
2169 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2170 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2171 }
2172 }
2173
2174 if (rdev->family >= CHIP_R600) {
2175 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2176 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2177 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2178 } else {
2179 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2180 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2181 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2182 }
2183 }
2184
2185 void
2186 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2187 {
2188 struct drm_device *dev = encoder->dev;
2189 struct radeon_device *rdev = dev->dev_private;
2190 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2191 uint32_t bios_3_scratch;
2192
2193 if (rdev->family >= CHIP_R600)
2194 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2195 else
2196 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2197
2198 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2199 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2200 bios_3_scratch |= (crtc << 18);
2201 }
2202 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2203 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2204 bios_3_scratch |= (crtc << 24);
2205 }
2206 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2207 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2208 bios_3_scratch |= (crtc << 16);
2209 }
2210 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2211 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2212 bios_3_scratch |= (crtc << 20);
2213 }
2214 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2215 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2216 bios_3_scratch |= (crtc << 17);
2217 }
2218 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2219 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2220 bios_3_scratch |= (crtc << 19);
2221 }
2222 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2223 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2224 bios_3_scratch |= (crtc << 23);
2225 }
2226 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2227 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2228 bios_3_scratch |= (crtc << 25);
2229 }
2230
2231 if (rdev->family >= CHIP_R600)
2232 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2233 else
2234 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2235 }
2236
2237 void
2238 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2239 {
2240 struct drm_device *dev = encoder->dev;
2241 struct radeon_device *rdev = dev->dev_private;
2242 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2243 uint32_t bios_2_scratch;
2244
2245 if (rdev->family >= CHIP_R600)
2246 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2247 else
2248 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2249
2250 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2251 if (on)
2252 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2253 else
2254 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2255 }
2256 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2257 if (on)
2258 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2259 else
2260 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2261 }
2262 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2263 if (on)
2264 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2265 else
2266 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2267 }
2268 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2269 if (on)
2270 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2271 else
2272 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2273 }
2274 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2275 if (on)
2276 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2277 else
2278 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2279 }
2280 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2281 if (on)
2282 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2283 else
2284 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2285 }
2286 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2287 if (on)
2288 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2289 else
2290 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2291 }
2292 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2293 if (on)
2294 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2295 else
2296 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2297 }
2298 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2299 if (on)
2300 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2301 else
2302 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2303 }
2304 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2305 if (on)
2306 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2307 else
2308 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2309 }
2310
2311 if (rdev->family >= CHIP_R600)
2312 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2313 else
2314 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2315 }
Linux kernel - Deliverables
This page took 0.117374 seconds and 5 git commands to generate.