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drm/radeon/kms: parse the extended LCD info block
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_atombios.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
53
54 /* from radeon_legacy_encoder.c */
55 extern void
56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
58
59 union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63 };
64
65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
67 {
68 struct atom_context *ctx = rdev->mode_info.atom_context;
69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
73 uint16_t data_offset, size;
74 int i, num_indices;
75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
86 gpio = &i2c_info->asGPIO_Info[i];
87
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
91 (gpio->usClkMaskRegisterIndex == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
101 if (gpio->sucI2cId.ucAccess == id) {
102 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
103 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
104 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
105 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
106 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
107 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
108 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
109 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
110 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
111 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
112 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
113 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
114 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
115 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
116 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
117 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
118
119 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
120 i2c.hw_capable = true;
121 else
122 i2c.hw_capable = false;
123
124 if (gpio->sucI2cId.ucAccess == 0xa0)
125 i2c.mm_i2c = true;
126 else
127 i2c.mm_i2c = false;
128
129 i2c.i2c_id = gpio->sucI2cId.ucAccess;
130
131 if (i2c.mask_clk_reg)
132 i2c.valid = true;
133 break;
134 }
135 }
136 }
137
138 return i2c;
139 }
140
141 void radeon_atombios_i2c_init(struct radeon_device *rdev)
142 {
143 struct atom_context *ctx = rdev->mode_info.atom_context;
144 ATOM_GPIO_I2C_ASSIGMENT *gpio;
145 struct radeon_i2c_bus_rec i2c;
146 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
147 struct _ATOM_GPIO_I2C_INFO *i2c_info;
148 uint16_t data_offset, size;
149 int i, num_indices;
150 char stmp[32];
151
152 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
153
154 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
155 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
156
157 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
158 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
159
160 for (i = 0; i < num_indices; i++) {
161 gpio = &i2c_info->asGPIO_Info[i];
162 i2c.valid = false;
163
164 /* some evergreen boards have bad data for this entry */
165 if (ASIC_IS_DCE4(rdev)) {
166 if ((i == 7) &&
167 (gpio->usClkMaskRegisterIndex == 0x1936) &&
168 (gpio->sucI2cId.ucAccess == 0)) {
169 gpio->sucI2cId.ucAccess = 0x97;
170 gpio->ucDataMaskShift = 8;
171 gpio->ucDataEnShift = 8;
172 gpio->ucDataY_Shift = 8;
173 gpio->ucDataA_Shift = 8;
174 }
175 }
176
177 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
178 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
179 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
180 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
181 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
182 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
183 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
184 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
185 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
186 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
187 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
188 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
189 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
190 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
191 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
192 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
193
194 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
195 i2c.hw_capable = true;
196 else
197 i2c.hw_capable = false;
198
199 if (gpio->sucI2cId.ucAccess == 0xa0)
200 i2c.mm_i2c = true;
201 else
202 i2c.mm_i2c = false;
203
204 i2c.i2c_id = gpio->sucI2cId.ucAccess;
205
206 if (i2c.mask_clk_reg) {
207 i2c.valid = true;
208 sprintf(stmp, "0x%x", i2c.i2c_id);
209 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
210 }
211 }
212 }
213 }
214
215 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
216 u8 id)
217 {
218 struct atom_context *ctx = rdev->mode_info.atom_context;
219 struct radeon_gpio_rec gpio;
220 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
221 struct _ATOM_GPIO_PIN_LUT *gpio_info;
222 ATOM_GPIO_PIN_ASSIGNMENT *pin;
223 u16 data_offset, size;
224 int i, num_indices;
225
226 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
227 gpio.valid = false;
228
229 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
230 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
231
232 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
233 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
234
235 for (i = 0; i < num_indices; i++) {
236 pin = &gpio_info->asGPIO_Pin[i];
237 if (id == pin->ucGPIO_ID) {
238 gpio.id = pin->ucGPIO_ID;
239 gpio.reg = pin->usGpioPin_AIndex * 4;
240 gpio.mask = (1 << pin->ucGpioPinBitShift);
241 gpio.valid = true;
242 break;
243 }
244 }
245 }
246
247 return gpio;
248 }
249
250 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
251 struct radeon_gpio_rec *gpio)
252 {
253 struct radeon_hpd hpd;
254 u32 reg;
255
256 memset(&hpd, 0, sizeof(struct radeon_hpd));
257
258 if (ASIC_IS_DCE4(rdev))
259 reg = EVERGREEN_DC_GPIO_HPD_A;
260 else
261 reg = AVIVO_DC_GPIO_HPD_A;
262
263 hpd.gpio = *gpio;
264 if (gpio->reg == reg) {
265 switch(gpio->mask) {
266 case (1 << 0):
267 hpd.hpd = RADEON_HPD_1;
268 break;
269 case (1 << 8):
270 hpd.hpd = RADEON_HPD_2;
271 break;
272 case (1 << 16):
273 hpd.hpd = RADEON_HPD_3;
274 break;
275 case (1 << 24):
276 hpd.hpd = RADEON_HPD_4;
277 break;
278 case (1 << 26):
279 hpd.hpd = RADEON_HPD_5;
280 break;
281 case (1 << 28):
282 hpd.hpd = RADEON_HPD_6;
283 break;
284 default:
285 hpd.hpd = RADEON_HPD_NONE;
286 break;
287 }
288 } else
289 hpd.hpd = RADEON_HPD_NONE;
290 return hpd;
291 }
292
293 static bool radeon_atom_apply_quirks(struct drm_device *dev,
294 uint32_t supported_device,
295 int *connector_type,
296 struct radeon_i2c_bus_rec *i2c_bus,
297 uint16_t *line_mux,
298 struct radeon_hpd *hpd)
299 {
300 struct radeon_device *rdev = dev->dev_private;
301
302 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
303 if ((dev->pdev->device == 0x791e) &&
304 (dev->pdev->subsystem_vendor == 0x1043) &&
305 (dev->pdev->subsystem_device == 0x826d)) {
306 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
307 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
308 *connector_type = DRM_MODE_CONNECTOR_DVID;
309 }
310
311 /* Asrock RS600 board lists the DVI port as HDMI */
312 if ((dev->pdev->device == 0x7941) &&
313 (dev->pdev->subsystem_vendor == 0x1849) &&
314 (dev->pdev->subsystem_device == 0x7941)) {
315 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
316 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
317 *connector_type = DRM_MODE_CONNECTOR_DVID;
318 }
319
320 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
321 if ((dev->pdev->device == 0x796e) &&
322 (dev->pdev->subsystem_vendor == 0x1462) &&
323 (dev->pdev->subsystem_device == 0x7302)) {
324 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
325 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
326 return false;
327 }
328
329 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
330 if ((dev->pdev->device == 0x7941) &&
331 (dev->pdev->subsystem_vendor == 0x147b) &&
332 (dev->pdev->subsystem_device == 0x2412)) {
333 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
334 return false;
335 }
336
337 /* Falcon NW laptop lists vga ddc line for LVDS */
338 if ((dev->pdev->device == 0x5653) &&
339 (dev->pdev->subsystem_vendor == 0x1462) &&
340 (dev->pdev->subsystem_device == 0x0291)) {
341 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
342 i2c_bus->valid = false;
343 *line_mux = 53;
344 }
345 }
346
347 /* HIS X1300 is DVI+VGA, not DVI+DVI */
348 if ((dev->pdev->device == 0x7146) &&
349 (dev->pdev->subsystem_vendor == 0x17af) &&
350 (dev->pdev->subsystem_device == 0x2058)) {
351 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
352 return false;
353 }
354
355 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
356 if ((dev->pdev->device == 0x7142) &&
357 (dev->pdev->subsystem_vendor == 0x1458) &&
358 (dev->pdev->subsystem_device == 0x2134)) {
359 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
360 return false;
361 }
362
363
364 /* Funky macbooks */
365 if ((dev->pdev->device == 0x71C5) &&
366 (dev->pdev->subsystem_vendor == 0x106b) &&
367 (dev->pdev->subsystem_device == 0x0080)) {
368 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
369 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
370 return false;
371 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
372 *line_mux = 0x90;
373 }
374
375 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
376 if ((dev->pdev->device == 0x9598) &&
377 (dev->pdev->subsystem_vendor == 0x1043) &&
378 (dev->pdev->subsystem_device == 0x01da)) {
379 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
380 *connector_type = DRM_MODE_CONNECTOR_DVII;
381 }
382 }
383
384 /* ASUS HD 3600 board lists the DVI port as HDMI */
385 if ((dev->pdev->device == 0x9598) &&
386 (dev->pdev->subsystem_vendor == 0x1043) &&
387 (dev->pdev->subsystem_device == 0x01e4)) {
388 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
389 *connector_type = DRM_MODE_CONNECTOR_DVII;
390 }
391 }
392
393 /* ASUS HD 3450 board lists the DVI port as HDMI */
394 if ((dev->pdev->device == 0x95C5) &&
395 (dev->pdev->subsystem_vendor == 0x1043) &&
396 (dev->pdev->subsystem_device == 0x01e2)) {
397 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
398 *connector_type = DRM_MODE_CONNECTOR_DVII;
399 }
400 }
401
402 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
403 * HDMI + VGA reporting as HDMI
404 */
405 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
406 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
407 *connector_type = DRM_MODE_CONNECTOR_VGA;
408 *line_mux = 0;
409 }
410 }
411
412 /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
413 if ((dev->pdev->device == 0x95c4) &&
414 (dev->pdev->subsystem_vendor == 0x1025) &&
415 (dev->pdev->subsystem_device == 0x013c)) {
416 struct radeon_gpio_rec gpio;
417
418 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
419 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
420 gpio = radeon_lookup_gpio(rdev, 6);
421 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
422 *connector_type = DRM_MODE_CONNECTOR_DVID;
423 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
424 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
425 gpio = radeon_lookup_gpio(rdev, 7);
426 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
427 }
428 }
429
430 /* XFX Pine Group device rv730 reports no VGA DDC lines
431 * even though they are wired up to record 0x93
432 */
433 if ((dev->pdev->device == 0x9498) &&
434 (dev->pdev->subsystem_vendor == 0x1682) &&
435 (dev->pdev->subsystem_device == 0x2452)) {
436 struct radeon_device *rdev = dev->dev_private;
437 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
438 }
439 return true;
440 }
441
442 const int supported_devices_connector_convert[] = {
443 DRM_MODE_CONNECTOR_Unknown,
444 DRM_MODE_CONNECTOR_VGA,
445 DRM_MODE_CONNECTOR_DVII,
446 DRM_MODE_CONNECTOR_DVID,
447 DRM_MODE_CONNECTOR_DVIA,
448 DRM_MODE_CONNECTOR_SVIDEO,
449 DRM_MODE_CONNECTOR_Composite,
450 DRM_MODE_CONNECTOR_LVDS,
451 DRM_MODE_CONNECTOR_Unknown,
452 DRM_MODE_CONNECTOR_Unknown,
453 DRM_MODE_CONNECTOR_HDMIA,
454 DRM_MODE_CONNECTOR_HDMIB,
455 DRM_MODE_CONNECTOR_Unknown,
456 DRM_MODE_CONNECTOR_Unknown,
457 DRM_MODE_CONNECTOR_9PinDIN,
458 DRM_MODE_CONNECTOR_DisplayPort
459 };
460
461 const uint16_t supported_devices_connector_object_id_convert[] = {
462 CONNECTOR_OBJECT_ID_NONE,
463 CONNECTOR_OBJECT_ID_VGA,
464 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
465 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
466 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
467 CONNECTOR_OBJECT_ID_COMPOSITE,
468 CONNECTOR_OBJECT_ID_SVIDEO,
469 CONNECTOR_OBJECT_ID_LVDS,
470 CONNECTOR_OBJECT_ID_9PIN_DIN,
471 CONNECTOR_OBJECT_ID_9PIN_DIN,
472 CONNECTOR_OBJECT_ID_DISPLAYPORT,
473 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
474 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
475 CONNECTOR_OBJECT_ID_SVIDEO
476 };
477
478 const int object_connector_convert[] = {
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_DVII,
481 DRM_MODE_CONNECTOR_DVII,
482 DRM_MODE_CONNECTOR_DVID,
483 DRM_MODE_CONNECTOR_DVID,
484 DRM_MODE_CONNECTOR_VGA,
485 DRM_MODE_CONNECTOR_Composite,
486 DRM_MODE_CONNECTOR_SVIDEO,
487 DRM_MODE_CONNECTOR_Unknown,
488 DRM_MODE_CONNECTOR_Unknown,
489 DRM_MODE_CONNECTOR_9PinDIN,
490 DRM_MODE_CONNECTOR_Unknown,
491 DRM_MODE_CONNECTOR_HDMIA,
492 DRM_MODE_CONNECTOR_HDMIB,
493 DRM_MODE_CONNECTOR_LVDS,
494 DRM_MODE_CONNECTOR_9PinDIN,
495 DRM_MODE_CONNECTOR_Unknown,
496 DRM_MODE_CONNECTOR_Unknown,
497 DRM_MODE_CONNECTOR_Unknown,
498 DRM_MODE_CONNECTOR_DisplayPort,
499 DRM_MODE_CONNECTOR_eDP,
500 DRM_MODE_CONNECTOR_Unknown
501 };
502
503 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
504 {
505 struct radeon_device *rdev = dev->dev_private;
506 struct radeon_mode_info *mode_info = &rdev->mode_info;
507 struct atom_context *ctx = mode_info->atom_context;
508 int index = GetIndexIntoMasterTable(DATA, Object_Header);
509 u16 size, data_offset;
510 u8 frev, crev;
511 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
512 ATOM_OBJECT_TABLE *router_obj;
513 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
514 ATOM_OBJECT_HEADER *obj_header;
515 int i, j, k, path_size, device_support;
516 int connector_type;
517 u16 igp_lane_info, conn_id, connector_object_id;
518 struct radeon_i2c_bus_rec ddc_bus;
519 struct radeon_router router;
520 struct radeon_gpio_rec gpio;
521 struct radeon_hpd hpd;
522
523 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
524 return false;
525
526 if (crev < 2)
527 return false;
528
529 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
530 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
531 (ctx->bios + data_offset +
532 le16_to_cpu(obj_header->usDisplayPathTableOffset));
533 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
534 (ctx->bios + data_offset +
535 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
536 router_obj = (ATOM_OBJECT_TABLE *)
537 (ctx->bios + data_offset +
538 le16_to_cpu(obj_header->usRouterObjectTableOffset));
539 device_support = le16_to_cpu(obj_header->usDeviceSupport);
540
541 path_size = 0;
542 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
543 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
544 ATOM_DISPLAY_OBJECT_PATH *path;
545 addr += path_size;
546 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
547 path_size += le16_to_cpu(path->usSize);
548
549 if (device_support & le16_to_cpu(path->usDeviceTag)) {
550 uint8_t con_obj_id, con_obj_num, con_obj_type;
551
552 con_obj_id =
553 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
554 >> OBJECT_ID_SHIFT;
555 con_obj_num =
556 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
557 >> ENUM_ID_SHIFT;
558 con_obj_type =
559 (le16_to_cpu(path->usConnObjectId) &
560 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
561
562 /* TODO CV support */
563 if (le16_to_cpu(path->usDeviceTag) ==
564 ATOM_DEVICE_CV_SUPPORT)
565 continue;
566
567 /* IGP chips */
568 if ((rdev->flags & RADEON_IS_IGP) &&
569 (con_obj_id ==
570 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
571 uint16_t igp_offset = 0;
572 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
573
574 index =
575 GetIndexIntoMasterTable(DATA,
576 IntegratedSystemInfo);
577
578 if (atom_parse_data_header(ctx, index, &size, &frev,
579 &crev, &igp_offset)) {
580
581 if (crev >= 2) {
582 igp_obj =
583 (ATOM_INTEGRATED_SYSTEM_INFO_V2
584 *) (ctx->bios + igp_offset);
585
586 if (igp_obj) {
587 uint32_t slot_config, ct;
588
589 if (con_obj_num == 1)
590 slot_config =
591 igp_obj->
592 ulDDISlot1Config;
593 else
594 slot_config =
595 igp_obj->
596 ulDDISlot2Config;
597
598 ct = (slot_config >> 16) & 0xff;
599 connector_type =
600 object_connector_convert
601 [ct];
602 connector_object_id = ct;
603 igp_lane_info =
604 slot_config & 0xffff;
605 } else
606 continue;
607 } else
608 continue;
609 } else {
610 igp_lane_info = 0;
611 connector_type =
612 object_connector_convert[con_obj_id];
613 connector_object_id = con_obj_id;
614 }
615 } else {
616 igp_lane_info = 0;
617 connector_type =
618 object_connector_convert[con_obj_id];
619 connector_object_id = con_obj_id;
620 }
621
622 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
623 continue;
624
625 router.ddc_valid = false;
626 router.cd_valid = false;
627 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
628 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
629
630 grph_obj_id =
631 (le16_to_cpu(path->usGraphicObjIds[j]) &
632 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
633 grph_obj_num =
634 (le16_to_cpu(path->usGraphicObjIds[j]) &
635 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
636 grph_obj_type =
637 (le16_to_cpu(path->usGraphicObjIds[j]) &
638 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
639
640 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
641 u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
642
643 radeon_add_atom_encoder(dev,
644 encoder_obj,
645 le16_to_cpu
646 (path->
647 usDeviceTag));
648
649 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
650 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
651 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
652 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
653 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
654 (ctx->bios + data_offset +
655 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
656 ATOM_I2C_RECORD *i2c_record;
657 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
658 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
659 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
660 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
661 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
662 (ctx->bios + data_offset +
663 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
664 int enum_id;
665
666 router.router_id = router_obj_id;
667 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
668 enum_id++) {
669 if (le16_to_cpu(path->usConnObjectId) ==
670 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
671 break;
672 }
673
674 while (record->ucRecordType > 0 &&
675 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
676 switch (record->ucRecordType) {
677 case ATOM_I2C_RECORD_TYPE:
678 i2c_record =
679 (ATOM_I2C_RECORD *)
680 record;
681 i2c_config =
682 (ATOM_I2C_ID_CONFIG_ACCESS *)
683 &i2c_record->sucI2cId;
684 router.i2c_info =
685 radeon_lookup_i2c_gpio(rdev,
686 i2c_config->
687 ucAccess);
688 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
689 break;
690 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
691 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
692 record;
693 router.ddc_valid = true;
694 router.ddc_mux_type = ddc_path->ucMuxType;
695 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
696 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
697 break;
698 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
699 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
700 record;
701 router.cd_valid = true;
702 router.cd_mux_type = cd_path->ucMuxType;
703 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
704 router.cd_mux_state = cd_path->ucMuxState[enum_id];
705 break;
706 }
707 record = (ATOM_COMMON_RECORD_HEADER *)
708 ((char *)record + record->ucRecordSize);
709 }
710 }
711 }
712 }
713 }
714
715 /* look up gpio for ddc, hpd */
716 ddc_bus.valid = false;
717 hpd.hpd = RADEON_HPD_NONE;
718 if ((le16_to_cpu(path->usDeviceTag) &
719 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
720 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
721 if (le16_to_cpu(path->usConnObjectId) ==
722 le16_to_cpu(con_obj->asObjects[j].
723 usObjectID)) {
724 ATOM_COMMON_RECORD_HEADER
725 *record =
726 (ATOM_COMMON_RECORD_HEADER
727 *)
728 (ctx->bios + data_offset +
729 le16_to_cpu(con_obj->
730 asObjects[j].
731 usRecordOffset));
732 ATOM_I2C_RECORD *i2c_record;
733 ATOM_HPD_INT_RECORD *hpd_record;
734 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
735
736 while (record->ucRecordType > 0
737 && record->
738 ucRecordType <=
739 ATOM_MAX_OBJECT_RECORD_NUMBER) {
740 switch (record->ucRecordType) {
741 case ATOM_I2C_RECORD_TYPE:
742 i2c_record =
743 (ATOM_I2C_RECORD *)
744 record;
745 i2c_config =
746 (ATOM_I2C_ID_CONFIG_ACCESS *)
747 &i2c_record->sucI2cId;
748 ddc_bus = radeon_lookup_i2c_gpio(rdev,
749 i2c_config->
750 ucAccess);
751 break;
752 case ATOM_HPD_INT_RECORD_TYPE:
753 hpd_record =
754 (ATOM_HPD_INT_RECORD *)
755 record;
756 gpio = radeon_lookup_gpio(rdev,
757 hpd_record->ucHPDIntGPIOID);
758 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
759 hpd.plugged_state = hpd_record->ucPlugged_PinState;
760 break;
761 }
762 record =
763 (ATOM_COMMON_RECORD_HEADER
764 *) ((char *)record
765 +
766 record->
767 ucRecordSize);
768 }
769 break;
770 }
771 }
772 }
773
774 /* needed for aux chan transactions */
775 ddc_bus.hpd = hpd.hpd;
776
777 conn_id = le16_to_cpu(path->usConnObjectId);
778
779 if (!radeon_atom_apply_quirks
780 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
781 &ddc_bus, &conn_id, &hpd))
782 continue;
783
784 radeon_add_atom_connector(dev,
785 conn_id,
786 le16_to_cpu(path->
787 usDeviceTag),
788 connector_type, &ddc_bus,
789 igp_lane_info,
790 connector_object_id,
791 &hpd,
792 &router);
793
794 }
795 }
796
797 radeon_link_encoder_connector(dev);
798
799 return true;
800 }
801
802 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
803 int connector_type,
804 uint16_t devices)
805 {
806 struct radeon_device *rdev = dev->dev_private;
807
808 if (rdev->flags & RADEON_IS_IGP) {
809 return supported_devices_connector_object_id_convert
810 [connector_type];
811 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
812 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
813 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
814 struct radeon_mode_info *mode_info = &rdev->mode_info;
815 struct atom_context *ctx = mode_info->atom_context;
816 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
817 uint16_t size, data_offset;
818 uint8_t frev, crev;
819 ATOM_XTMDS_INFO *xtmds;
820
821 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
822 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
823
824 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
825 if (connector_type == DRM_MODE_CONNECTOR_DVII)
826 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
827 else
828 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
829 } else {
830 if (connector_type == DRM_MODE_CONNECTOR_DVII)
831 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
832 else
833 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
834 }
835 } else
836 return supported_devices_connector_object_id_convert
837 [connector_type];
838 } else {
839 return supported_devices_connector_object_id_convert
840 [connector_type];
841 }
842 }
843
844 struct bios_connector {
845 bool valid;
846 uint16_t line_mux;
847 uint16_t devices;
848 int connector_type;
849 struct radeon_i2c_bus_rec ddc_bus;
850 struct radeon_hpd hpd;
851 };
852
853 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
854 drm_device
855 *dev)
856 {
857 struct radeon_device *rdev = dev->dev_private;
858 struct radeon_mode_info *mode_info = &rdev->mode_info;
859 struct atom_context *ctx = mode_info->atom_context;
860 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
861 uint16_t size, data_offset;
862 uint8_t frev, crev;
863 uint16_t device_support;
864 uint8_t dac;
865 union atom_supported_devices *supported_devices;
866 int i, j, max_device;
867 struct bios_connector *bios_connectors;
868 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
869 struct radeon_router router;
870
871 router.ddc_valid = false;
872 router.cd_valid = false;
873
874 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
875 if (!bios_connectors)
876 return false;
877
878 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
879 &data_offset)) {
880 kfree(bios_connectors);
881 return false;
882 }
883
884 supported_devices =
885 (union atom_supported_devices *)(ctx->bios + data_offset);
886
887 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
888
889 if (frev > 1)
890 max_device = ATOM_MAX_SUPPORTED_DEVICE;
891 else
892 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
893
894 for (i = 0; i < max_device; i++) {
895 ATOM_CONNECTOR_INFO_I2C ci =
896 supported_devices->info.asConnInfo[i];
897
898 bios_connectors[i].valid = false;
899
900 if (!(device_support & (1 << i))) {
901 continue;
902 }
903
904 if (i == ATOM_DEVICE_CV_INDEX) {
905 DRM_DEBUG_KMS("Skipping Component Video\n");
906 continue;
907 }
908
909 bios_connectors[i].connector_type =
910 supported_devices_connector_convert[ci.sucConnectorInfo.
911 sbfAccess.
912 bfConnectorType];
913
914 if (bios_connectors[i].connector_type ==
915 DRM_MODE_CONNECTOR_Unknown)
916 continue;
917
918 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
919
920 bios_connectors[i].line_mux =
921 ci.sucI2cId.ucAccess;
922
923 /* give tv unique connector ids */
924 if (i == ATOM_DEVICE_TV1_INDEX) {
925 bios_connectors[i].ddc_bus.valid = false;
926 bios_connectors[i].line_mux = 50;
927 } else if (i == ATOM_DEVICE_TV2_INDEX) {
928 bios_connectors[i].ddc_bus.valid = false;
929 bios_connectors[i].line_mux = 51;
930 } else if (i == ATOM_DEVICE_CV_INDEX) {
931 bios_connectors[i].ddc_bus.valid = false;
932 bios_connectors[i].line_mux = 52;
933 } else
934 bios_connectors[i].ddc_bus =
935 radeon_lookup_i2c_gpio(rdev,
936 bios_connectors[i].line_mux);
937
938 if ((crev > 1) && (frev > 1)) {
939 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
940 switch (isb) {
941 case 0x4:
942 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
943 break;
944 case 0xa:
945 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
946 break;
947 default:
948 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
949 break;
950 }
951 } else {
952 if (i == ATOM_DEVICE_DFP1_INDEX)
953 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
954 else if (i == ATOM_DEVICE_DFP2_INDEX)
955 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
956 else
957 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
958 }
959
960 /* Always set the connector type to VGA for CRT1/CRT2. if they are
961 * shared with a DVI port, we'll pick up the DVI connector when we
962 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
963 */
964 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
965 bios_connectors[i].connector_type =
966 DRM_MODE_CONNECTOR_VGA;
967
968 if (!radeon_atom_apply_quirks
969 (dev, (1 << i), &bios_connectors[i].connector_type,
970 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
971 &bios_connectors[i].hpd))
972 continue;
973
974 bios_connectors[i].valid = true;
975 bios_connectors[i].devices = (1 << i);
976
977 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
978 radeon_add_atom_encoder(dev,
979 radeon_get_encoder_enum(dev,
980 (1 << i),
981 dac),
982 (1 << i));
983 else
984 radeon_add_legacy_encoder(dev,
985 radeon_get_encoder_enum(dev,
986 (1 << i),
987 dac),
988 (1 << i));
989 }
990
991 /* combine shared connectors */
992 for (i = 0; i < max_device; i++) {
993 if (bios_connectors[i].valid) {
994 for (j = 0; j < max_device; j++) {
995 if (bios_connectors[j].valid && (i != j)) {
996 if (bios_connectors[i].line_mux ==
997 bios_connectors[j].line_mux) {
998 /* make sure not to combine LVDS */
999 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1000 bios_connectors[i].line_mux = 53;
1001 bios_connectors[i].ddc_bus.valid = false;
1002 continue;
1003 }
1004 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1005 bios_connectors[j].line_mux = 53;
1006 bios_connectors[j].ddc_bus.valid = false;
1007 continue;
1008 }
1009 /* combine analog and digital for DVI-I */
1010 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1011 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1012 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1013 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1014 bios_connectors[i].devices |=
1015 bios_connectors[j].devices;
1016 bios_connectors[i].connector_type =
1017 DRM_MODE_CONNECTOR_DVII;
1018 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1019 bios_connectors[i].hpd =
1020 bios_connectors[j].hpd;
1021 bios_connectors[j].valid = false;
1022 }
1023 }
1024 }
1025 }
1026 }
1027 }
1028
1029 /* add the connectors */
1030 for (i = 0; i < max_device; i++) {
1031 if (bios_connectors[i].valid) {
1032 uint16_t connector_object_id =
1033 atombios_get_connector_object_id(dev,
1034 bios_connectors[i].connector_type,
1035 bios_connectors[i].devices);
1036 radeon_add_atom_connector(dev,
1037 bios_connectors[i].line_mux,
1038 bios_connectors[i].devices,
1039 bios_connectors[i].
1040 connector_type,
1041 &bios_connectors[i].ddc_bus,
1042 0,
1043 connector_object_id,
1044 &bios_connectors[i].hpd,
1045 &router);
1046 }
1047 }
1048
1049 radeon_link_encoder_connector(dev);
1050
1051 kfree(bios_connectors);
1052 return true;
1053 }
1054
1055 union firmware_info {
1056 ATOM_FIRMWARE_INFO info;
1057 ATOM_FIRMWARE_INFO_V1_2 info_12;
1058 ATOM_FIRMWARE_INFO_V1_3 info_13;
1059 ATOM_FIRMWARE_INFO_V1_4 info_14;
1060 ATOM_FIRMWARE_INFO_V2_1 info_21;
1061 };
1062
1063 bool radeon_atom_get_clock_info(struct drm_device *dev)
1064 {
1065 struct radeon_device *rdev = dev->dev_private;
1066 struct radeon_mode_info *mode_info = &rdev->mode_info;
1067 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1068 union firmware_info *firmware_info;
1069 uint8_t frev, crev;
1070 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1071 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1072 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1073 struct radeon_pll *spll = &rdev->clock.spll;
1074 struct radeon_pll *mpll = &rdev->clock.mpll;
1075 uint16_t data_offset;
1076
1077 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1078 &frev, &crev, &data_offset)) {
1079 firmware_info =
1080 (union firmware_info *)(mode_info->atom_context->bios +
1081 data_offset);
1082 /* pixel clocks */
1083 p1pll->reference_freq =
1084 le16_to_cpu(firmware_info->info.usReferenceClock);
1085 p1pll->reference_div = 0;
1086
1087 if (crev < 2)
1088 p1pll->pll_out_min =
1089 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1090 else
1091 p1pll->pll_out_min =
1092 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1093 p1pll->pll_out_max =
1094 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1095
1096 if (crev >= 4) {
1097 p1pll->lcd_pll_out_min =
1098 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1099 if (p1pll->lcd_pll_out_min == 0)
1100 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1101 p1pll->lcd_pll_out_max =
1102 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1103 if (p1pll->lcd_pll_out_max == 0)
1104 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1105 } else {
1106 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1107 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1108 }
1109
1110 if (p1pll->pll_out_min == 0) {
1111 if (ASIC_IS_AVIVO(rdev))
1112 p1pll->pll_out_min = 64800;
1113 else
1114 p1pll->pll_out_min = 20000;
1115 } else if (p1pll->pll_out_min > 64800) {
1116 /* Limiting the pll output range is a good thing generally as
1117 * it limits the number of possible pll combinations for a given
1118 * frequency presumably to the ones that work best on each card.
1119 * However, certain duallink DVI monitors seem to like
1120 * pll combinations that would be limited by this at least on
1121 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1122 * family.
1123 */
1124 p1pll->pll_out_min = 64800;
1125 }
1126
1127 p1pll->pll_in_min =
1128 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1129 p1pll->pll_in_max =
1130 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1131
1132 *p2pll = *p1pll;
1133
1134 /* system clock */
1135 spll->reference_freq =
1136 le16_to_cpu(firmware_info->info.usReferenceClock);
1137 spll->reference_div = 0;
1138
1139 spll->pll_out_min =
1140 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1141 spll->pll_out_max =
1142 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1143
1144 /* ??? */
1145 if (spll->pll_out_min == 0) {
1146 if (ASIC_IS_AVIVO(rdev))
1147 spll->pll_out_min = 64800;
1148 else
1149 spll->pll_out_min = 20000;
1150 }
1151
1152 spll->pll_in_min =
1153 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1154 spll->pll_in_max =
1155 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1156
1157 /* memory clock */
1158 mpll->reference_freq =
1159 le16_to_cpu(firmware_info->info.usReferenceClock);
1160 mpll->reference_div = 0;
1161
1162 mpll->pll_out_min =
1163 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1164 mpll->pll_out_max =
1165 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1166
1167 /* ??? */
1168 if (mpll->pll_out_min == 0) {
1169 if (ASIC_IS_AVIVO(rdev))
1170 mpll->pll_out_min = 64800;
1171 else
1172 mpll->pll_out_min = 20000;
1173 }
1174
1175 mpll->pll_in_min =
1176 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1177 mpll->pll_in_max =
1178 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1179
1180 rdev->clock.default_sclk =
1181 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1182 rdev->clock.default_mclk =
1183 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1184
1185 if (ASIC_IS_DCE4(rdev)) {
1186 rdev->clock.default_dispclk =
1187 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1188 if (rdev->clock.default_dispclk == 0)
1189 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1190 rdev->clock.dp_extclk =
1191 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1192 }
1193 *dcpll = *p1pll;
1194
1195 return true;
1196 }
1197
1198 return false;
1199 }
1200
1201 union igp_info {
1202 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1203 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1204 };
1205
1206 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1207 {
1208 struct radeon_mode_info *mode_info = &rdev->mode_info;
1209 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1210 union igp_info *igp_info;
1211 u8 frev, crev;
1212 u16 data_offset;
1213
1214 /* sideport is AMD only */
1215 if (rdev->family == CHIP_RS600)
1216 return false;
1217
1218 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1219 &frev, &crev, &data_offset)) {
1220 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1221 data_offset);
1222 switch (crev) {
1223 case 1:
1224 if (igp_info->info.ulBootUpMemoryClock)
1225 return true;
1226 break;
1227 case 2:
1228 if (igp_info->info_2.ulBootUpSidePortClock)
1229 return true;
1230 break;
1231 default:
1232 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1233 break;
1234 }
1235 }
1236 return false;
1237 }
1238
1239 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1240 struct radeon_encoder_int_tmds *tmds)
1241 {
1242 struct drm_device *dev = encoder->base.dev;
1243 struct radeon_device *rdev = dev->dev_private;
1244 struct radeon_mode_info *mode_info = &rdev->mode_info;
1245 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1246 uint16_t data_offset;
1247 struct _ATOM_TMDS_INFO *tmds_info;
1248 uint8_t frev, crev;
1249 uint16_t maxfreq;
1250 int i;
1251
1252 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1253 &frev, &crev, &data_offset)) {
1254 tmds_info =
1255 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1256 data_offset);
1257
1258 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1259 for (i = 0; i < 4; i++) {
1260 tmds->tmds_pll[i].freq =
1261 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1262 tmds->tmds_pll[i].value =
1263 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1264 tmds->tmds_pll[i].value |=
1265 (tmds_info->asMiscInfo[i].
1266 ucPLL_VCO_Gain & 0x3f) << 6;
1267 tmds->tmds_pll[i].value |=
1268 (tmds_info->asMiscInfo[i].
1269 ucPLL_DutyCycle & 0xf) << 12;
1270 tmds->tmds_pll[i].value |=
1271 (tmds_info->asMiscInfo[i].
1272 ucPLL_VoltageSwing & 0xf) << 16;
1273
1274 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1275 tmds->tmds_pll[i].freq,
1276 tmds->tmds_pll[i].value);
1277
1278 if (maxfreq == tmds->tmds_pll[i].freq) {
1279 tmds->tmds_pll[i].freq = 0xffffffff;
1280 break;
1281 }
1282 }
1283 return true;
1284 }
1285 return false;
1286 }
1287
1288 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1289 struct radeon_atom_ss *ss,
1290 int id)
1291 {
1292 struct radeon_mode_info *mode_info = &rdev->mode_info;
1293 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1294 uint16_t data_offset, size;
1295 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1296 uint8_t frev, crev;
1297 int i, num_indices;
1298
1299 memset(ss, 0, sizeof(struct radeon_atom_ss));
1300 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1301 &frev, &crev, &data_offset)) {
1302 ss_info =
1303 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1304
1305 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1306 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1307
1308 for (i = 0; i < num_indices; i++) {
1309 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1310 ss->percentage =
1311 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1312 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1313 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1314 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1315 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1316 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1317 return true;
1318 }
1319 }
1320 }
1321 return false;
1322 }
1323
1324 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1325 struct radeon_atom_ss *ss,
1326 int id)
1327 {
1328 struct radeon_mode_info *mode_info = &rdev->mode_info;
1329 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1330 u16 data_offset, size;
1331 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1332 u8 frev, crev;
1333 u16 percentage = 0, rate = 0;
1334
1335 /* get any igp specific overrides */
1336 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1337 &frev, &crev, &data_offset)) {
1338 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1339 (mode_info->atom_context->bios + data_offset);
1340 switch (id) {
1341 case ASIC_INTERNAL_SS_ON_TMDS:
1342 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1343 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1344 break;
1345 case ASIC_INTERNAL_SS_ON_HDMI:
1346 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1347 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1348 break;
1349 case ASIC_INTERNAL_SS_ON_LVDS:
1350 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1351 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1352 break;
1353 }
1354 if (percentage)
1355 ss->percentage = percentage;
1356 if (rate)
1357 ss->rate = rate;
1358 }
1359 }
1360
1361 union asic_ss_info {
1362 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1363 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1364 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1365 };
1366
1367 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1368 struct radeon_atom_ss *ss,
1369 int id, u32 clock)
1370 {
1371 struct radeon_mode_info *mode_info = &rdev->mode_info;
1372 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1373 uint16_t data_offset, size;
1374 union asic_ss_info *ss_info;
1375 uint8_t frev, crev;
1376 int i, num_indices;
1377
1378 memset(ss, 0, sizeof(struct radeon_atom_ss));
1379 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1380 &frev, &crev, &data_offset)) {
1381
1382 ss_info =
1383 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1384
1385 switch (frev) {
1386 case 1:
1387 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1388 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1389
1390 for (i = 0; i < num_indices; i++) {
1391 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1392 (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) {
1393 ss->percentage =
1394 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1395 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1396 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1397 return true;
1398 }
1399 }
1400 break;
1401 case 2:
1402 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1403 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1404 for (i = 0; i < num_indices; i++) {
1405 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1406 (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) {
1407 ss->percentage =
1408 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1409 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1410 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1411 return true;
1412 }
1413 }
1414 break;
1415 case 3:
1416 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1417 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1418 for (i = 0; i < num_indices; i++) {
1419 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1420 (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) {
1421 ss->percentage =
1422 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1423 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1424 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1425 if (rdev->flags & RADEON_IS_IGP)
1426 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1427 return true;
1428 }
1429 }
1430 break;
1431 default:
1432 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1433 break;
1434 }
1435
1436 }
1437 return false;
1438 }
1439
1440 union lvds_info {
1441 struct _ATOM_LVDS_INFO info;
1442 struct _ATOM_LVDS_INFO_V12 info_12;
1443 };
1444
1445 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1446 radeon_encoder
1447 *encoder)
1448 {
1449 struct drm_device *dev = encoder->base.dev;
1450 struct radeon_device *rdev = dev->dev_private;
1451 struct radeon_mode_info *mode_info = &rdev->mode_info;
1452 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1453 uint16_t data_offset, misc;
1454 union lvds_info *lvds_info;
1455 uint8_t frev, crev;
1456 struct radeon_encoder_atom_dig *lvds = NULL;
1457 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1458
1459 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1460 &frev, &crev, &data_offset)) {
1461 lvds_info =
1462 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1463 lvds =
1464 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1465
1466 if (!lvds)
1467 return NULL;
1468
1469 lvds->native_mode.clock =
1470 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1471 lvds->native_mode.hdisplay =
1472 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1473 lvds->native_mode.vdisplay =
1474 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1475 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1476 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1477 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1478 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1479 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1480 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1481 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1482 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1483 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1484 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1485 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1486 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1487 lvds->panel_pwr_delay =
1488 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1489 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1490
1491 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1492 if (misc & ATOM_VSYNC_POLARITY)
1493 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1494 if (misc & ATOM_HSYNC_POLARITY)
1495 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1496 if (misc & ATOM_COMPOSITESYNC)
1497 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1498 if (misc & ATOM_INTERLACE)
1499 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1500 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1501 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1502
1503 lvds->native_mode.width_mm = lvds_info->info.sLCDTiming.usImageHSize;
1504 lvds->native_mode.height_mm = lvds_info->info.sLCDTiming.usImageVSize;
1505
1506 /* set crtc values */
1507 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1508
1509 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1510
1511 encoder->native_mode = lvds->native_mode;
1512
1513 if (encoder_enum == 2)
1514 lvds->linkb = true;
1515 else
1516 lvds->linkb = false;
1517
1518 /* parse the lcd record table */
1519 if (lvds_info->info.usModePatchTableOffset) {
1520 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1521 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1522 bool bad_record = false;
1523 u8 *record = (u8 *)(mode_info->atom_context->bios +
1524 data_offset +
1525 lvds_info->info.usModePatchTableOffset);
1526 while (*record != ATOM_RECORD_END_TYPE) {
1527 switch (*record) {
1528 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1529 record += sizeof(ATOM_PATCH_RECORD_MODE);
1530 break;
1531 case LCD_RTS_RECORD_TYPE:
1532 record += sizeof(ATOM_LCD_RTS_RECORD);
1533 break;
1534 case LCD_CAP_RECORD_TYPE:
1535 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1536 break;
1537 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1538 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1539 if (fake_edid_record->ucFakeEDIDLength) {
1540 struct edid *edid;
1541 int edid_size =
1542 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1543 edid = kmalloc(edid_size, GFP_KERNEL);
1544 if (edid) {
1545 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1546 fake_edid_record->ucFakeEDIDLength);
1547
1548 if (drm_edid_is_valid(edid))
1549 rdev->mode_info.bios_hardcoded_edid = edid;
1550 else
1551 kfree(edid);
1552 }
1553 }
1554 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1555 break;
1556 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1557 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1558 lvds->native_mode.width_mm = panel_res_record->usHSize;
1559 lvds->native_mode.height_mm = panel_res_record->usVSize;
1560 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1561 break;
1562 default:
1563 DRM_ERROR("Bad LCD record %d\n", *record);
1564 bad_record = true;
1565 break;
1566 }
1567 if (bad_record)
1568 break;
1569 }
1570 }
1571 }
1572 return lvds;
1573 }
1574
1575 struct radeon_encoder_primary_dac *
1576 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1577 {
1578 struct drm_device *dev = encoder->base.dev;
1579 struct radeon_device *rdev = dev->dev_private;
1580 struct radeon_mode_info *mode_info = &rdev->mode_info;
1581 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1582 uint16_t data_offset;
1583 struct _COMPASSIONATE_DATA *dac_info;
1584 uint8_t frev, crev;
1585 uint8_t bg, dac;
1586 struct radeon_encoder_primary_dac *p_dac = NULL;
1587
1588 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1589 &frev, &crev, &data_offset)) {
1590 dac_info = (struct _COMPASSIONATE_DATA *)
1591 (mode_info->atom_context->bios + data_offset);
1592
1593 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1594
1595 if (!p_dac)
1596 return NULL;
1597
1598 bg = dac_info->ucDAC1_BG_Adjustment;
1599 dac = dac_info->ucDAC1_DAC_Adjustment;
1600 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1601
1602 }
1603 return p_dac;
1604 }
1605
1606 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1607 struct drm_display_mode *mode)
1608 {
1609 struct radeon_mode_info *mode_info = &rdev->mode_info;
1610 ATOM_ANALOG_TV_INFO *tv_info;
1611 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1612 ATOM_DTD_FORMAT *dtd_timings;
1613 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1614 u8 frev, crev;
1615 u16 data_offset, misc;
1616
1617 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1618 &frev, &crev, &data_offset))
1619 return false;
1620
1621 switch (crev) {
1622 case 1:
1623 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1624 if (index >= MAX_SUPPORTED_TV_TIMING)
1625 return false;
1626
1627 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1628 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1629 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1630 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1631 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1632
1633 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1634 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1635 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1636 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1637 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1638
1639 mode->flags = 0;
1640 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1641 if (misc & ATOM_VSYNC_POLARITY)
1642 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1643 if (misc & ATOM_HSYNC_POLARITY)
1644 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1645 if (misc & ATOM_COMPOSITESYNC)
1646 mode->flags |= DRM_MODE_FLAG_CSYNC;
1647 if (misc & ATOM_INTERLACE)
1648 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1649 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1650 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1651
1652 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1653
1654 if (index == 1) {
1655 /* PAL timings appear to have wrong values for totals */
1656 mode->crtc_htotal -= 1;
1657 mode->crtc_vtotal -= 1;
1658 }
1659 break;
1660 case 2:
1661 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1662 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1663 return false;
1664
1665 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1666 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1667 le16_to_cpu(dtd_timings->usHBlanking_Time);
1668 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1669 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1670 le16_to_cpu(dtd_timings->usHSyncOffset);
1671 mode->crtc_hsync_end = mode->crtc_hsync_start +
1672 le16_to_cpu(dtd_timings->usHSyncWidth);
1673
1674 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1675 le16_to_cpu(dtd_timings->usVBlanking_Time);
1676 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1677 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1678 le16_to_cpu(dtd_timings->usVSyncOffset);
1679 mode->crtc_vsync_end = mode->crtc_vsync_start +
1680 le16_to_cpu(dtd_timings->usVSyncWidth);
1681
1682 mode->flags = 0;
1683 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1684 if (misc & ATOM_VSYNC_POLARITY)
1685 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1686 if (misc & ATOM_HSYNC_POLARITY)
1687 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1688 if (misc & ATOM_COMPOSITESYNC)
1689 mode->flags |= DRM_MODE_FLAG_CSYNC;
1690 if (misc & ATOM_INTERLACE)
1691 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1692 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1693 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1694
1695 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1696 break;
1697 }
1698 return true;
1699 }
1700
1701 enum radeon_tv_std
1702 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1703 {
1704 struct radeon_mode_info *mode_info = &rdev->mode_info;
1705 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1706 uint16_t data_offset;
1707 uint8_t frev, crev;
1708 struct _ATOM_ANALOG_TV_INFO *tv_info;
1709 enum radeon_tv_std tv_std = TV_STD_NTSC;
1710
1711 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1712 &frev, &crev, &data_offset)) {
1713
1714 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1715 (mode_info->atom_context->bios + data_offset);
1716
1717 switch (tv_info->ucTV_BootUpDefaultStandard) {
1718 case ATOM_TV_NTSC:
1719 tv_std = TV_STD_NTSC;
1720 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1721 break;
1722 case ATOM_TV_NTSCJ:
1723 tv_std = TV_STD_NTSC_J;
1724 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1725 break;
1726 case ATOM_TV_PAL:
1727 tv_std = TV_STD_PAL;
1728 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1729 break;
1730 case ATOM_TV_PALM:
1731 tv_std = TV_STD_PAL_M;
1732 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1733 break;
1734 case ATOM_TV_PALN:
1735 tv_std = TV_STD_PAL_N;
1736 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1737 break;
1738 case ATOM_TV_PALCN:
1739 tv_std = TV_STD_PAL_CN;
1740 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1741 break;
1742 case ATOM_TV_PAL60:
1743 tv_std = TV_STD_PAL_60;
1744 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1745 break;
1746 case ATOM_TV_SECAM:
1747 tv_std = TV_STD_SECAM;
1748 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1749 break;
1750 default:
1751 tv_std = TV_STD_NTSC;
1752 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1753 break;
1754 }
1755 }
1756 return tv_std;
1757 }
1758
1759 struct radeon_encoder_tv_dac *
1760 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1761 {
1762 struct drm_device *dev = encoder->base.dev;
1763 struct radeon_device *rdev = dev->dev_private;
1764 struct radeon_mode_info *mode_info = &rdev->mode_info;
1765 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1766 uint16_t data_offset;
1767 struct _COMPASSIONATE_DATA *dac_info;
1768 uint8_t frev, crev;
1769 uint8_t bg, dac;
1770 struct radeon_encoder_tv_dac *tv_dac = NULL;
1771
1772 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1773 &frev, &crev, &data_offset)) {
1774
1775 dac_info = (struct _COMPASSIONATE_DATA *)
1776 (mode_info->atom_context->bios + data_offset);
1777
1778 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1779
1780 if (!tv_dac)
1781 return NULL;
1782
1783 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1784 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1785 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1786
1787 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1788 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1789 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1790
1791 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1792 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1793 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1794
1795 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1796 }
1797 return tv_dac;
1798 }
1799
1800 static const char *thermal_controller_names[] = {
1801 "NONE",
1802 "lm63",
1803 "adm1032",
1804 "adm1030",
1805 "max6649",
1806 "lm64",
1807 "f75375",
1808 "asc7xxx",
1809 };
1810
1811 static const char *pp_lib_thermal_controller_names[] = {
1812 "NONE",
1813 "lm63",
1814 "adm1032",
1815 "adm1030",
1816 "max6649",
1817 "lm64",
1818 "f75375",
1819 "RV6xx",
1820 "RV770",
1821 "adt7473",
1822 "NONE",
1823 "External GPIO",
1824 "Evergreen",
1825 "emc2103",
1826 "Sumo",
1827 };
1828
1829 union power_info {
1830 struct _ATOM_POWERPLAY_INFO info;
1831 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1832 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1833 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1834 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1835 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1836 };
1837
1838 union pplib_clock_info {
1839 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1840 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1841 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1842 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1843 };
1844
1845 union pplib_power_state {
1846 struct _ATOM_PPLIB_STATE v1;
1847 struct _ATOM_PPLIB_STATE_V2 v2;
1848 };
1849
1850 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1851 int state_index,
1852 u32 misc, u32 misc2)
1853 {
1854 rdev->pm.power_state[state_index].misc = misc;
1855 rdev->pm.power_state[state_index].misc2 = misc2;
1856 /* order matters! */
1857 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1858 rdev->pm.power_state[state_index].type =
1859 POWER_STATE_TYPE_POWERSAVE;
1860 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1861 rdev->pm.power_state[state_index].type =
1862 POWER_STATE_TYPE_BATTERY;
1863 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1864 rdev->pm.power_state[state_index].type =
1865 POWER_STATE_TYPE_BATTERY;
1866 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1867 rdev->pm.power_state[state_index].type =
1868 POWER_STATE_TYPE_BALANCED;
1869 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1870 rdev->pm.power_state[state_index].type =
1871 POWER_STATE_TYPE_PERFORMANCE;
1872 rdev->pm.power_state[state_index].flags &=
1873 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1874 }
1875 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1876 rdev->pm.power_state[state_index].type =
1877 POWER_STATE_TYPE_BALANCED;
1878 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1879 rdev->pm.power_state[state_index].type =
1880 POWER_STATE_TYPE_DEFAULT;
1881 rdev->pm.default_power_state_index = state_index;
1882 rdev->pm.power_state[state_index].default_clock_mode =
1883 &rdev->pm.power_state[state_index].clock_info[0];
1884 } else if (state_index == 0) {
1885 rdev->pm.power_state[state_index].clock_info[0].flags |=
1886 RADEON_PM_MODE_NO_DISPLAY;
1887 }
1888 }
1889
1890 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1891 {
1892 struct radeon_mode_info *mode_info = &rdev->mode_info;
1893 u32 misc, misc2 = 0;
1894 int num_modes = 0, i;
1895 int state_index = 0;
1896 struct radeon_i2c_bus_rec i2c_bus;
1897 union power_info *power_info;
1898 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1899 u16 data_offset;
1900 u8 frev, crev;
1901
1902 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1903 &frev, &crev, &data_offset))
1904 return state_index;
1905 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1906
1907 /* add the i2c bus for thermal/fan chip */
1908 if (power_info->info.ucOverdriveThermalController > 0) {
1909 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1910 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1911 power_info->info.ucOverdriveControllerAddress >> 1);
1912 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1913 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1914 if (rdev->pm.i2c_bus) {
1915 struct i2c_board_info info = { };
1916 const char *name = thermal_controller_names[power_info->info.
1917 ucOverdriveThermalController];
1918 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1919 strlcpy(info.type, name, sizeof(info.type));
1920 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1921 }
1922 }
1923 num_modes = power_info->info.ucNumOfPowerModeEntries;
1924 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1925 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1926 /* last mode is usually default, array is low to high */
1927 for (i = 0; i < num_modes; i++) {
1928 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1929 switch (frev) {
1930 case 1:
1931 rdev->pm.power_state[state_index].num_clock_modes = 1;
1932 rdev->pm.power_state[state_index].clock_info[0].mclk =
1933 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1934 rdev->pm.power_state[state_index].clock_info[0].sclk =
1935 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1936 /* skip invalid modes */
1937 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1938 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1939 continue;
1940 rdev->pm.power_state[state_index].pcie_lanes =
1941 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1942 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1943 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1944 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1945 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1946 VOLTAGE_GPIO;
1947 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1948 radeon_lookup_gpio(rdev,
1949 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1950 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1951 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1952 true;
1953 else
1954 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1955 false;
1956 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1957 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1958 VOLTAGE_VDDC;
1959 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1960 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1961 }
1962 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1963 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
1964 state_index++;
1965 break;
1966 case 2:
1967 rdev->pm.power_state[state_index].num_clock_modes = 1;
1968 rdev->pm.power_state[state_index].clock_info[0].mclk =
1969 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1970 rdev->pm.power_state[state_index].clock_info[0].sclk =
1971 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1972 /* skip invalid modes */
1973 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1974 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1975 continue;
1976 rdev->pm.power_state[state_index].pcie_lanes =
1977 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1978 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1979 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1980 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1981 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1982 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1983 VOLTAGE_GPIO;
1984 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1985 radeon_lookup_gpio(rdev,
1986 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1987 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1988 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1989 true;
1990 else
1991 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1992 false;
1993 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1994 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1995 VOLTAGE_VDDC;
1996 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1997 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1998 }
1999 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2000 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2001 state_index++;
2002 break;
2003 case 3:
2004 rdev->pm.power_state[state_index].num_clock_modes = 1;
2005 rdev->pm.power_state[state_index].clock_info[0].mclk =
2006 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2007 rdev->pm.power_state[state_index].clock_info[0].sclk =
2008 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2009 /* skip invalid modes */
2010 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2011 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2012 continue;
2013 rdev->pm.power_state[state_index].pcie_lanes =
2014 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2015 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2016 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2017 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2018 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2019 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2020 VOLTAGE_GPIO;
2021 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2022 radeon_lookup_gpio(rdev,
2023 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2024 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2025 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2026 true;
2027 else
2028 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2029 false;
2030 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2031 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2032 VOLTAGE_VDDC;
2033 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2034 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2035 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2036 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2037 true;
2038 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2039 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2040 }
2041 }
2042 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2043 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2044 state_index++;
2045 break;
2046 }
2047 }
2048 /* last mode is usually default */
2049 if (rdev->pm.default_power_state_index == -1) {
2050 rdev->pm.power_state[state_index - 1].type =
2051 POWER_STATE_TYPE_DEFAULT;
2052 rdev->pm.default_power_state_index = state_index - 1;
2053 rdev->pm.power_state[state_index - 1].default_clock_mode =
2054 &rdev->pm.power_state[state_index - 1].clock_info[0];
2055 rdev->pm.power_state[state_index].flags &=
2056 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2057 rdev->pm.power_state[state_index].misc = 0;
2058 rdev->pm.power_state[state_index].misc2 = 0;
2059 }
2060 return state_index;
2061 }
2062
2063 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2064 ATOM_PPLIB_THERMALCONTROLLER *controller)
2065 {
2066 struct radeon_i2c_bus_rec i2c_bus;
2067
2068 /* add the i2c bus for thermal/fan chip */
2069 if (controller->ucType > 0) {
2070 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2071 DRM_INFO("Internal thermal controller %s fan control\n",
2072 (controller->ucFanParameters &
2073 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2074 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2075 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2076 DRM_INFO("Internal thermal controller %s fan control\n",
2077 (controller->ucFanParameters &
2078 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2079 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2080 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2081 DRM_INFO("Internal thermal controller %s fan control\n",
2082 (controller->ucFanParameters &
2083 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2084 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2085 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2086 DRM_INFO("Internal thermal controller %s fan control\n",
2087 (controller->ucFanParameters &
2088 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2089 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2090 } else if ((controller->ucType ==
2091 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2092 (controller->ucType ==
2093 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2094 (controller->ucType ==
2095 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2096 DRM_INFO("Special thermal controller config\n");
2097 } else {
2098 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2099 pp_lib_thermal_controller_names[controller->ucType],
2100 controller->ucI2cAddress >> 1,
2101 (controller->ucFanParameters &
2102 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2103 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2104 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2105 if (rdev->pm.i2c_bus) {
2106 struct i2c_board_info info = { };
2107 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2108 info.addr = controller->ucI2cAddress >> 1;
2109 strlcpy(info.type, name, sizeof(info.type));
2110 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2111 }
2112 }
2113 }
2114 }
2115
2116 static u16 radeon_atombios_get_default_vddc(struct radeon_device *rdev)
2117 {
2118 struct radeon_mode_info *mode_info = &rdev->mode_info;
2119 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2120 u8 frev, crev;
2121 u16 data_offset;
2122 union firmware_info *firmware_info;
2123 u16 vddc = 0;
2124
2125 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2126 &frev, &crev, &data_offset)) {
2127 firmware_info =
2128 (union firmware_info *)(mode_info->atom_context->bios +
2129 data_offset);
2130 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
2131 }
2132
2133 return vddc;
2134 }
2135
2136 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2137 int state_index, int mode_index,
2138 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2139 {
2140 int j;
2141 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2142 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2143 u16 vddc = radeon_atombios_get_default_vddc(rdev);
2144
2145 rdev->pm.power_state[state_index].misc = misc;
2146 rdev->pm.power_state[state_index].misc2 = misc2;
2147 rdev->pm.power_state[state_index].pcie_lanes =
2148 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2149 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2150 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2151 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2152 rdev->pm.power_state[state_index].type =
2153 POWER_STATE_TYPE_BATTERY;
2154 break;
2155 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2156 rdev->pm.power_state[state_index].type =
2157 POWER_STATE_TYPE_BALANCED;
2158 break;
2159 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2160 rdev->pm.power_state[state_index].type =
2161 POWER_STATE_TYPE_PERFORMANCE;
2162 break;
2163 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2164 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2165 rdev->pm.power_state[state_index].type =
2166 POWER_STATE_TYPE_PERFORMANCE;
2167 break;
2168 }
2169 rdev->pm.power_state[state_index].flags = 0;
2170 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2171 rdev->pm.power_state[state_index].flags |=
2172 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2173 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2174 rdev->pm.power_state[state_index].type =
2175 POWER_STATE_TYPE_DEFAULT;
2176 rdev->pm.default_power_state_index = state_index;
2177 rdev->pm.power_state[state_index].default_clock_mode =
2178 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2179 /* patch the table values with the default slck/mclk from firmware info */
2180 for (j = 0; j < mode_index; j++) {
2181 rdev->pm.power_state[state_index].clock_info[j].mclk =
2182 rdev->clock.default_mclk;
2183 rdev->pm.power_state[state_index].clock_info[j].sclk =
2184 rdev->clock.default_sclk;
2185 if (vddc)
2186 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2187 vddc;
2188 }
2189 }
2190 }
2191
2192 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2193 int state_index, int mode_index,
2194 union pplib_clock_info *clock_info)
2195 {
2196 u32 sclk, mclk;
2197
2198 if (rdev->flags & RADEON_IS_IGP) {
2199 if (rdev->family >= CHIP_PALM) {
2200 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2201 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2202 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2203 } else {
2204 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2205 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2206 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2207 }
2208 } else if (ASIC_IS_DCE4(rdev)) {
2209 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2210 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2211 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2212 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2213 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2214 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2215 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2216 VOLTAGE_SW;
2217 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2218 clock_info->evergreen.usVDDC;
2219 } else {
2220 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2221 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2222 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2223 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2224 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2225 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2226 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2227 VOLTAGE_SW;
2228 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2229 clock_info->r600.usVDDC;
2230 }
2231
2232 if (rdev->flags & RADEON_IS_IGP) {
2233 /* skip invalid modes */
2234 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2235 return false;
2236 } else {
2237 /* skip invalid modes */
2238 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2239 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2240 return false;
2241 }
2242 return true;
2243 }
2244
2245 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2246 {
2247 struct radeon_mode_info *mode_info = &rdev->mode_info;
2248 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2249 union pplib_power_state *power_state;
2250 int i, j;
2251 int state_index = 0, mode_index = 0;
2252 union pplib_clock_info *clock_info;
2253 bool valid;
2254 union power_info *power_info;
2255 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2256 u16 data_offset;
2257 u8 frev, crev;
2258
2259 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2260 &frev, &crev, &data_offset))
2261 return state_index;
2262 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2263
2264 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2265 /* first mode is usually default, followed by low to high */
2266 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2267 mode_index = 0;
2268 power_state = (union pplib_power_state *)
2269 (mode_info->atom_context->bios + data_offset +
2270 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2271 i * power_info->pplib.ucStateEntrySize);
2272 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2273 (mode_info->atom_context->bios + data_offset +
2274 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2275 (power_state->v1.ucNonClockStateIndex *
2276 power_info->pplib.ucNonClockSize));
2277 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2278 clock_info = (union pplib_clock_info *)
2279 (mode_info->atom_context->bios + data_offset +
2280 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2281 (power_state->v1.ucClockStateIndices[j] *
2282 power_info->pplib.ucClockInfoSize));
2283 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2284 state_index, mode_index,
2285 clock_info);
2286 if (valid)
2287 mode_index++;
2288 }
2289 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2290 if (mode_index) {
2291 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2292 non_clock_info);
2293 state_index++;
2294 }
2295 }
2296 /* if multiple clock modes, mark the lowest as no display */
2297 for (i = 0; i < state_index; i++) {
2298 if (rdev->pm.power_state[i].num_clock_modes > 1)
2299 rdev->pm.power_state[i].clock_info[0].flags |=
2300 RADEON_PM_MODE_NO_DISPLAY;
2301 }
2302 /* first mode is usually default */
2303 if (rdev->pm.default_power_state_index == -1) {
2304 rdev->pm.power_state[0].type =
2305 POWER_STATE_TYPE_DEFAULT;
2306 rdev->pm.default_power_state_index = 0;
2307 rdev->pm.power_state[0].default_clock_mode =
2308 &rdev->pm.power_state[0].clock_info[0];
2309 }
2310 return state_index;
2311 }
2312
2313 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2314 {
2315 struct radeon_mode_info *mode_info = &rdev->mode_info;
2316 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2317 union pplib_power_state *power_state;
2318 int i, j, non_clock_array_index, clock_array_index;
2319 int state_index = 0, mode_index = 0;
2320 union pplib_clock_info *clock_info;
2321 struct StateArray *state_array;
2322 struct ClockInfoArray *clock_info_array;
2323 struct NonClockInfoArray *non_clock_info_array;
2324 bool valid;
2325 union power_info *power_info;
2326 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2327 u16 data_offset;
2328 u8 frev, crev;
2329
2330 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2331 &frev, &crev, &data_offset))
2332 return state_index;
2333 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2334
2335 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2336 state_array = (struct StateArray *)
2337 (mode_info->atom_context->bios + data_offset +
2338 power_info->pplib.usStateArrayOffset);
2339 clock_info_array = (struct ClockInfoArray *)
2340 (mode_info->atom_context->bios + data_offset +
2341 power_info->pplib.usClockInfoArrayOffset);
2342 non_clock_info_array = (struct NonClockInfoArray *)
2343 (mode_info->atom_context->bios + data_offset +
2344 power_info->pplib.usNonClockInfoArrayOffset);
2345 for (i = 0; i < state_array->ucNumEntries; i++) {
2346 mode_index = 0;
2347 power_state = (union pplib_power_state *)&state_array->states[i];
2348 /* XXX this might be an inagua bug... */
2349 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2350 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2351 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2352 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2353 clock_array_index = power_state->v2.clockInfoIndex[j];
2354 /* XXX this might be an inagua bug... */
2355 if (clock_array_index >= clock_info_array->ucNumEntries)
2356 continue;
2357 clock_info = (union pplib_clock_info *)
2358 &clock_info_array->clockInfo[clock_array_index];
2359 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2360 state_index, mode_index,
2361 clock_info);
2362 if (valid)
2363 mode_index++;
2364 }
2365 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2366 if (mode_index) {
2367 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2368 non_clock_info);
2369 state_index++;
2370 }
2371 }
2372 /* if multiple clock modes, mark the lowest as no display */
2373 for (i = 0; i < state_index; i++) {
2374 if (rdev->pm.power_state[i].num_clock_modes > 1)
2375 rdev->pm.power_state[i].clock_info[0].flags |=
2376 RADEON_PM_MODE_NO_DISPLAY;
2377 }
2378 /* first mode is usually default */
2379 if (rdev->pm.default_power_state_index == -1) {
2380 rdev->pm.power_state[0].type =
2381 POWER_STATE_TYPE_DEFAULT;
2382 rdev->pm.default_power_state_index = 0;
2383 rdev->pm.power_state[0].default_clock_mode =
2384 &rdev->pm.power_state[0].clock_info[0];
2385 }
2386 return state_index;
2387 }
2388
2389 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2390 {
2391 struct radeon_mode_info *mode_info = &rdev->mode_info;
2392 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2393 u16 data_offset;
2394 u8 frev, crev;
2395 int state_index = 0;
2396
2397 rdev->pm.default_power_state_index = -1;
2398
2399 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2400 &frev, &crev, &data_offset)) {
2401 switch (frev) {
2402 case 1:
2403 case 2:
2404 case 3:
2405 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2406 break;
2407 case 4:
2408 case 5:
2409 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2410 break;
2411 case 6:
2412 state_index = radeon_atombios_parse_power_table_6(rdev);
2413 break;
2414 default:
2415 break;
2416 }
2417 } else {
2418 /* add the default mode */
2419 rdev->pm.power_state[state_index].type =
2420 POWER_STATE_TYPE_DEFAULT;
2421 rdev->pm.power_state[state_index].num_clock_modes = 1;
2422 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2423 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2424 rdev->pm.power_state[state_index].default_clock_mode =
2425 &rdev->pm.power_state[state_index].clock_info[0];
2426 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2427 rdev->pm.power_state[state_index].pcie_lanes = 16;
2428 rdev->pm.default_power_state_index = state_index;
2429 rdev->pm.power_state[state_index].flags = 0;
2430 state_index++;
2431 }
2432
2433 rdev->pm.num_power_states = state_index;
2434
2435 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2436 rdev->pm.current_clock_mode_index = 0;
2437 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2438 }
2439
2440 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2441 {
2442 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2443 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2444
2445 args.ucEnable = enable;
2446
2447 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2448 }
2449
2450 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2451 {
2452 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2453 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2454
2455 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2456 return args.ulReturnEngineClock;
2457 }
2458
2459 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2460 {
2461 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2462 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2463
2464 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2465 return args.ulReturnMemoryClock;
2466 }
2467
2468 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2469 uint32_t eng_clock)
2470 {
2471 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2472 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2473
2474 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2475
2476 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2477 }
2478
2479 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2480 uint32_t mem_clock)
2481 {
2482 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2483 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2484
2485 if (rdev->flags & RADEON_IS_IGP)
2486 return;
2487
2488 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2489
2490 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2491 }
2492
2493 union set_voltage {
2494 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2495 struct _SET_VOLTAGE_PARAMETERS v1;
2496 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2497 };
2498
2499 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2500 {
2501 union set_voltage args;
2502 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2503 u8 frev, crev, volt_index = level;
2504
2505 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2506 return;
2507
2508 switch (crev) {
2509 case 1:
2510 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2511 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2512 args.v1.ucVoltageIndex = volt_index;
2513 break;
2514 case 2:
2515 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2516 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2517 args.v2.usVoltageLevel = cpu_to_le16(level);
2518 break;
2519 default:
2520 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2521 return;
2522 }
2523
2524 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2525 }
2526
2527
2528
2529 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2530 {
2531 struct radeon_device *rdev = dev->dev_private;
2532 uint32_t bios_2_scratch, bios_6_scratch;
2533
2534 if (rdev->family >= CHIP_R600) {
2535 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2536 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2537 } else {
2538 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2539 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2540 }
2541
2542 /* let the bios control the backlight */
2543 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2544
2545 /* tell the bios not to handle mode switching */
2546 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2547
2548 if (rdev->family >= CHIP_R600) {
2549 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2550 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2551 } else {
2552 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2553 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2554 }
2555
2556 }
2557
2558 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2559 {
2560 uint32_t scratch_reg;
2561 int i;
2562
2563 if (rdev->family >= CHIP_R600)
2564 scratch_reg = R600_BIOS_0_SCRATCH;
2565 else
2566 scratch_reg = RADEON_BIOS_0_SCRATCH;
2567
2568 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2569 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2570 }
2571
2572 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2573 {
2574 uint32_t scratch_reg;
2575 int i;
2576
2577 if (rdev->family >= CHIP_R600)
2578 scratch_reg = R600_BIOS_0_SCRATCH;
2579 else
2580 scratch_reg = RADEON_BIOS_0_SCRATCH;
2581
2582 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2583 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2584 }
2585
2586 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2587 {
2588 struct drm_device *dev = encoder->dev;
2589 struct radeon_device *rdev = dev->dev_private;
2590 uint32_t bios_6_scratch;
2591
2592 if (rdev->family >= CHIP_R600)
2593 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2594 else
2595 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2596
2597 if (lock)
2598 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2599 else
2600 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2601
2602 if (rdev->family >= CHIP_R600)
2603 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2604 else
2605 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2606 }
2607
2608 /* at some point we may want to break this out into individual functions */
2609 void
2610 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2611 struct drm_encoder *encoder,
2612 bool connected)
2613 {
2614 struct drm_device *dev = connector->dev;
2615 struct radeon_device *rdev = dev->dev_private;
2616 struct radeon_connector *radeon_connector =
2617 to_radeon_connector(connector);
2618 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2619 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2620
2621 if (rdev->family >= CHIP_R600) {
2622 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2623 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2624 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2625 } else {
2626 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2627 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2628 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2629 }
2630
2631 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2632 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2633 if (connected) {
2634 DRM_DEBUG_KMS("TV1 connected\n");
2635 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2636 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2637 } else {
2638 DRM_DEBUG_KMS("TV1 disconnected\n");
2639 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2640 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2641 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2642 }
2643 }
2644 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2645 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2646 if (connected) {
2647 DRM_DEBUG_KMS("CV connected\n");
2648 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2649 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2650 } else {
2651 DRM_DEBUG_KMS("CV disconnected\n");
2652 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2653 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2654 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2655 }
2656 }
2657 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2658 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2659 if (connected) {
2660 DRM_DEBUG_KMS("LCD1 connected\n");
2661 bios_0_scratch |= ATOM_S0_LCD1;
2662 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2663 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2664 } else {
2665 DRM_DEBUG_KMS("LCD1 disconnected\n");
2666 bios_0_scratch &= ~ATOM_S0_LCD1;
2667 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2668 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2669 }
2670 }
2671 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2672 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2673 if (connected) {
2674 DRM_DEBUG_KMS("CRT1 connected\n");
2675 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2676 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2677 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2678 } else {
2679 DRM_DEBUG_KMS("CRT1 disconnected\n");
2680 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2681 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2682 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2683 }
2684 }
2685 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2686 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2687 if (connected) {
2688 DRM_DEBUG_KMS("CRT2 connected\n");
2689 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2690 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2691 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2692 } else {
2693 DRM_DEBUG_KMS("CRT2 disconnected\n");
2694 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2695 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2696 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2697 }
2698 }
2699 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2700 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2701 if (connected) {
2702 DRM_DEBUG_KMS("DFP1 connected\n");
2703 bios_0_scratch |= ATOM_S0_DFP1;
2704 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2705 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2706 } else {
2707 DRM_DEBUG_KMS("DFP1 disconnected\n");
2708 bios_0_scratch &= ~ATOM_S0_DFP1;
2709 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2710 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2711 }
2712 }
2713 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2714 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2715 if (connected) {
2716 DRM_DEBUG_KMS("DFP2 connected\n");
2717 bios_0_scratch |= ATOM_S0_DFP2;
2718 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2719 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2720 } else {
2721 DRM_DEBUG_KMS("DFP2 disconnected\n");
2722 bios_0_scratch &= ~ATOM_S0_DFP2;
2723 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2724 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2725 }
2726 }
2727 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2728 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2729 if (connected) {
2730 DRM_DEBUG_KMS("DFP3 connected\n");
2731 bios_0_scratch |= ATOM_S0_DFP3;
2732 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2733 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2734 } else {
2735 DRM_DEBUG_KMS("DFP3 disconnected\n");
2736 bios_0_scratch &= ~ATOM_S0_DFP3;
2737 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2738 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2739 }
2740 }
2741 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2742 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2743 if (connected) {
2744 DRM_DEBUG_KMS("DFP4 connected\n");
2745 bios_0_scratch |= ATOM_S0_DFP4;
2746 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2747 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2748 } else {
2749 DRM_DEBUG_KMS("DFP4 disconnected\n");
2750 bios_0_scratch &= ~ATOM_S0_DFP4;
2751 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2752 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2753 }
2754 }
2755 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2756 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2757 if (connected) {
2758 DRM_DEBUG_KMS("DFP5 connected\n");
2759 bios_0_scratch |= ATOM_S0_DFP5;
2760 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2761 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2762 } else {
2763 DRM_DEBUG_KMS("DFP5 disconnected\n");
2764 bios_0_scratch &= ~ATOM_S0_DFP5;
2765 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2766 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2767 }
2768 }
2769
2770 if (rdev->family >= CHIP_R600) {
2771 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2772 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2773 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2774 } else {
2775 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2776 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2777 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2778 }
2779 }
2780
2781 void
2782 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2783 {
2784 struct drm_device *dev = encoder->dev;
2785 struct radeon_device *rdev = dev->dev_private;
2786 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2787 uint32_t bios_3_scratch;
2788
2789 if (rdev->family >= CHIP_R600)
2790 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2791 else
2792 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2793
2794 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2795 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2796 bios_3_scratch |= (crtc << 18);
2797 }
2798 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2799 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2800 bios_3_scratch |= (crtc << 24);
2801 }
2802 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2803 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2804 bios_3_scratch |= (crtc << 16);
2805 }
2806 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2807 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2808 bios_3_scratch |= (crtc << 20);
2809 }
2810 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2811 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2812 bios_3_scratch |= (crtc << 17);
2813 }
2814 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2815 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2816 bios_3_scratch |= (crtc << 19);
2817 }
2818 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2819 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2820 bios_3_scratch |= (crtc << 23);
2821 }
2822 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2823 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2824 bios_3_scratch |= (crtc << 25);
2825 }
2826
2827 if (rdev->family >= CHIP_R600)
2828 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2829 else
2830 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2831 }
2832
2833 void
2834 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2835 {
2836 struct drm_device *dev = encoder->dev;
2837 struct radeon_device *rdev = dev->dev_private;
2838 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2839 uint32_t bios_2_scratch;
2840
2841 if (rdev->family >= CHIP_R600)
2842 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2843 else
2844 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2845
2846 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2847 if (on)
2848 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2849 else
2850 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2851 }
2852 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2853 if (on)
2854 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2855 else
2856 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2857 }
2858 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2859 if (on)
2860 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2861 else
2862 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2863 }
2864 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2865 if (on)
2866 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2867 else
2868 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2869 }
2870 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2871 if (on)
2872 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2873 else
2874 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2875 }
2876 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2877 if (on)
2878 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2879 else
2880 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2881 }
2882 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2883 if (on)
2884 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2885 else
2886 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2887 }
2888 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2889 if (on)
2890 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2891 else
2892 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2893 }
2894 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2895 if (on)
2896 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2897 else
2898 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2899 }
2900 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2901 if (on)
2902 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2903 else
2904 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2905 }
2906
2907 if (rdev->family >= CHIP_R600)
2908 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2909 else
2910 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2911 }
Linux kernel - Deliverables
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