2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_enum(struct drm_device
*dev
, uint32_t supported_device
,
37 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
39 radeon_add_atom_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
40 uint32_t supported_device
);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device
*dev
,
45 uint32_t connector_id
,
46 uint32_t supported_device
,
48 struct radeon_i2c_bus_rec
*i2c_bus
,
49 uint32_t igp_lane_info
,
50 uint16_t connector_object_id
,
51 struct radeon_hpd
*hpd
,
52 struct radeon_router
*router
);
54 /* from radeon_legacy_encoder.c */
56 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
57 uint32_t supported_device
);
59 union atom_supported_devices
{
60 struct _ATOM_SUPPORTED_DEVICES_INFO info
;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2
;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1
;
65 static inline struct radeon_i2c_bus_rec
radeon_lookup_i2c_gpio(struct radeon_device
*rdev
,
68 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
69 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
70 struct radeon_i2c_bus_rec i2c
;
71 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
72 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
73 uint16_t data_offset
, size
;
76 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
79 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
80 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
82 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
85 for (i
= 0; i
< num_indices
; i
++) {
86 gpio
= &i2c_info
->asGPIO_Info
[i
];
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev
)) {
91 (gpio
->usClkMaskRegisterIndex
== 0x1936) &&
92 (gpio
->sucI2cId
.ucAccess
== 0)) {
93 gpio
->sucI2cId
.ucAccess
= 0x97;
94 gpio
->ucDataMaskShift
= 8;
95 gpio
->ucDataEnShift
= 8;
96 gpio
->ucDataY_Shift
= 8;
97 gpio
->ucDataA_Shift
= 8;
101 if (gpio
->sucI2cId
.ucAccess
== id
) {
102 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
) * 4;
103 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
) * 4;
104 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
) * 4;
105 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
) * 4;
106 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
) * 4;
107 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
) * 4;
108 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
) * 4;
109 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
) * 4;
110 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
111 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
112 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
113 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
114 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
115 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
116 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
117 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
119 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
120 i2c
.hw_capable
= true;
122 i2c
.hw_capable
= false;
124 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
129 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
131 if (i2c
.mask_clk_reg
)
141 void radeon_atombios_i2c_init(struct radeon_device
*rdev
)
143 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
144 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
145 struct radeon_i2c_bus_rec i2c
;
146 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
147 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
148 uint16_t data_offset
, size
;
152 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
154 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
155 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
157 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
158 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
160 for (i
= 0; i
< num_indices
; i
++) {
161 gpio
= &i2c_info
->asGPIO_Info
[i
];
164 /* some evergreen boards have bad data for this entry */
165 if (ASIC_IS_DCE4(rdev
)) {
167 (gpio
->usClkMaskRegisterIndex
== 0x1936) &&
168 (gpio
->sucI2cId
.ucAccess
== 0)) {
169 gpio
->sucI2cId
.ucAccess
= 0x97;
170 gpio
->ucDataMaskShift
= 8;
171 gpio
->ucDataEnShift
= 8;
172 gpio
->ucDataY_Shift
= 8;
173 gpio
->ucDataA_Shift
= 8;
177 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
) * 4;
178 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
) * 4;
179 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
) * 4;
180 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
) * 4;
181 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
) * 4;
182 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
) * 4;
183 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
) * 4;
184 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
) * 4;
185 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
186 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
187 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
188 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
189 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
190 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
191 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
192 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
194 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
195 i2c
.hw_capable
= true;
197 i2c
.hw_capable
= false;
199 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
204 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
206 if (i2c
.mask_clk_reg
) {
208 sprintf(stmp
, "0x%x", i2c
.i2c_id
);
209 rdev
->i2c_bus
[i
] = radeon_i2c_create(rdev
->ddev
, &i2c
, stmp
);
215 static inline struct radeon_gpio_rec
radeon_lookup_gpio(struct radeon_device
*rdev
,
218 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
219 struct radeon_gpio_rec gpio
;
220 int index
= GetIndexIntoMasterTable(DATA
, GPIO_Pin_LUT
);
221 struct _ATOM_GPIO_PIN_LUT
*gpio_info
;
222 ATOM_GPIO_PIN_ASSIGNMENT
*pin
;
223 u16 data_offset
, size
;
226 memset(&gpio
, 0, sizeof(struct radeon_gpio_rec
));
229 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
230 gpio_info
= (struct _ATOM_GPIO_PIN_LUT
*)(ctx
->bios
+ data_offset
);
232 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
233 sizeof(ATOM_GPIO_PIN_ASSIGNMENT
);
235 for (i
= 0; i
< num_indices
; i
++) {
236 pin
= &gpio_info
->asGPIO_Pin
[i
];
237 if (id
== pin
->ucGPIO_ID
) {
238 gpio
.id
= pin
->ucGPIO_ID
;
239 gpio
.reg
= pin
->usGpioPin_AIndex
* 4;
240 gpio
.mask
= (1 << pin
->ucGpioPinBitShift
);
250 static struct radeon_hpd
radeon_atom_get_hpd_info_from_gpio(struct radeon_device
*rdev
,
251 struct radeon_gpio_rec
*gpio
)
253 struct radeon_hpd hpd
;
256 memset(&hpd
, 0, sizeof(struct radeon_hpd
));
258 if (ASIC_IS_DCE4(rdev
))
259 reg
= EVERGREEN_DC_GPIO_HPD_A
;
261 reg
= AVIVO_DC_GPIO_HPD_A
;
264 if (gpio
->reg
== reg
) {
267 hpd
.hpd
= RADEON_HPD_1
;
270 hpd
.hpd
= RADEON_HPD_2
;
273 hpd
.hpd
= RADEON_HPD_3
;
276 hpd
.hpd
= RADEON_HPD_4
;
279 hpd
.hpd
= RADEON_HPD_5
;
282 hpd
.hpd
= RADEON_HPD_6
;
285 hpd
.hpd
= RADEON_HPD_NONE
;
289 hpd
.hpd
= RADEON_HPD_NONE
;
293 static bool radeon_atom_apply_quirks(struct drm_device
*dev
,
294 uint32_t supported_device
,
296 struct radeon_i2c_bus_rec
*i2c_bus
,
298 struct radeon_hpd
*hpd
)
300 struct radeon_device
*rdev
= dev
->dev_private
;
302 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
303 if ((dev
->pdev
->device
== 0x791e) &&
304 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
305 (dev
->pdev
->subsystem_device
== 0x826d)) {
306 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
307 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
308 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
311 /* Asrock RS600 board lists the DVI port as HDMI */
312 if ((dev
->pdev
->device
== 0x7941) &&
313 (dev
->pdev
->subsystem_vendor
== 0x1849) &&
314 (dev
->pdev
->subsystem_device
== 0x7941)) {
315 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
316 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
317 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
320 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
321 if ((dev
->pdev
->device
== 0x7941) &&
322 (dev
->pdev
->subsystem_vendor
== 0x147b) &&
323 (dev
->pdev
->subsystem_device
== 0x2412)) {
324 if (*connector_type
== DRM_MODE_CONNECTOR_DVII
)
328 /* Falcon NW laptop lists vga ddc line for LVDS */
329 if ((dev
->pdev
->device
== 0x5653) &&
330 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
331 (dev
->pdev
->subsystem_device
== 0x0291)) {
332 if (*connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
333 i2c_bus
->valid
= false;
338 /* HIS X1300 is DVI+VGA, not DVI+DVI */
339 if ((dev
->pdev
->device
== 0x7146) &&
340 (dev
->pdev
->subsystem_vendor
== 0x17af) &&
341 (dev
->pdev
->subsystem_device
== 0x2058)) {
342 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
346 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
347 if ((dev
->pdev
->device
== 0x7142) &&
348 (dev
->pdev
->subsystem_vendor
== 0x1458) &&
349 (dev
->pdev
->subsystem_device
== 0x2134)) {
350 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
356 if ((dev
->pdev
->device
== 0x71C5) &&
357 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
358 (dev
->pdev
->subsystem_device
== 0x0080)) {
359 if ((supported_device
== ATOM_DEVICE_CRT1_SUPPORT
) ||
360 (supported_device
== ATOM_DEVICE_DFP2_SUPPORT
))
362 if (supported_device
== ATOM_DEVICE_CRT2_SUPPORT
)
366 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
367 if ((dev
->pdev
->device
== 0x9598) &&
368 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
369 (dev
->pdev
->subsystem_device
== 0x01da)) {
370 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
371 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
375 /* ASUS HD 3600 board lists the DVI port as HDMI */
376 if ((dev
->pdev
->device
== 0x9598) &&
377 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
378 (dev
->pdev
->subsystem_device
== 0x01e4)) {
379 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
380 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
384 /* ASUS HD 3450 board lists the DVI port as HDMI */
385 if ((dev
->pdev
->device
== 0x95C5) &&
386 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
387 (dev
->pdev
->subsystem_device
== 0x01e2)) {
388 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
389 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
393 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
394 * HDMI + VGA reporting as HDMI
396 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
397 if (supported_device
& (ATOM_DEVICE_CRT_SUPPORT
)) {
398 *connector_type
= DRM_MODE_CONNECTOR_VGA
;
403 /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
404 if ((dev
->pdev
->device
== 0x95c4) &&
405 (dev
->pdev
->subsystem_vendor
== 0x1025) &&
406 (dev
->pdev
->subsystem_device
== 0x013c)) {
407 struct radeon_gpio_rec gpio
;
409 if ((*connector_type
== DRM_MODE_CONNECTOR_DVII
) &&
410 (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)) {
411 gpio
= radeon_lookup_gpio(rdev
, 6);
412 *hpd
= radeon_atom_get_hpd_info_from_gpio(rdev
, &gpio
);
413 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
414 } else if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
415 (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)) {
416 gpio
= radeon_lookup_gpio(rdev
, 7);
417 *hpd
= radeon_atom_get_hpd_info_from_gpio(rdev
, &gpio
);
421 /* XFX Pine Group device rv730 reports no VGA DDC lines
422 * even though they are wired up to record 0x93
424 if ((dev
->pdev
->device
== 0x9498) &&
425 (dev
->pdev
->subsystem_vendor
== 0x1682) &&
426 (dev
->pdev
->subsystem_device
== 0x2452)) {
427 struct radeon_device
*rdev
= dev
->dev_private
;
428 *i2c_bus
= radeon_lookup_i2c_gpio(rdev
, 0x93);
433 const int supported_devices_connector_convert
[] = {
434 DRM_MODE_CONNECTOR_Unknown
,
435 DRM_MODE_CONNECTOR_VGA
,
436 DRM_MODE_CONNECTOR_DVII
,
437 DRM_MODE_CONNECTOR_DVID
,
438 DRM_MODE_CONNECTOR_DVIA
,
439 DRM_MODE_CONNECTOR_SVIDEO
,
440 DRM_MODE_CONNECTOR_Composite
,
441 DRM_MODE_CONNECTOR_LVDS
,
442 DRM_MODE_CONNECTOR_Unknown
,
443 DRM_MODE_CONNECTOR_Unknown
,
444 DRM_MODE_CONNECTOR_HDMIA
,
445 DRM_MODE_CONNECTOR_HDMIB
,
446 DRM_MODE_CONNECTOR_Unknown
,
447 DRM_MODE_CONNECTOR_Unknown
,
448 DRM_MODE_CONNECTOR_9PinDIN
,
449 DRM_MODE_CONNECTOR_DisplayPort
452 const uint16_t supported_devices_connector_object_id_convert
[] = {
453 CONNECTOR_OBJECT_ID_NONE
,
454 CONNECTOR_OBJECT_ID_VGA
,
455 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
, /* not all boards support DL */
456 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
, /* not all boards support DL */
457 CONNECTOR_OBJECT_ID_VGA
, /* technically DVI-A */
458 CONNECTOR_OBJECT_ID_COMPOSITE
,
459 CONNECTOR_OBJECT_ID_SVIDEO
,
460 CONNECTOR_OBJECT_ID_LVDS
,
461 CONNECTOR_OBJECT_ID_9PIN_DIN
,
462 CONNECTOR_OBJECT_ID_9PIN_DIN
,
463 CONNECTOR_OBJECT_ID_DISPLAYPORT
,
464 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
,
465 CONNECTOR_OBJECT_ID_HDMI_TYPE_B
,
466 CONNECTOR_OBJECT_ID_SVIDEO
469 const int object_connector_convert
[] = {
470 DRM_MODE_CONNECTOR_Unknown
,
471 DRM_MODE_CONNECTOR_DVII
,
472 DRM_MODE_CONNECTOR_DVII
,
473 DRM_MODE_CONNECTOR_DVID
,
474 DRM_MODE_CONNECTOR_DVID
,
475 DRM_MODE_CONNECTOR_VGA
,
476 DRM_MODE_CONNECTOR_Composite
,
477 DRM_MODE_CONNECTOR_SVIDEO
,
478 DRM_MODE_CONNECTOR_Unknown
,
479 DRM_MODE_CONNECTOR_Unknown
,
480 DRM_MODE_CONNECTOR_9PinDIN
,
481 DRM_MODE_CONNECTOR_Unknown
,
482 DRM_MODE_CONNECTOR_HDMIA
,
483 DRM_MODE_CONNECTOR_HDMIB
,
484 DRM_MODE_CONNECTOR_LVDS
,
485 DRM_MODE_CONNECTOR_9PinDIN
,
486 DRM_MODE_CONNECTOR_Unknown
,
487 DRM_MODE_CONNECTOR_Unknown
,
488 DRM_MODE_CONNECTOR_Unknown
,
489 DRM_MODE_CONNECTOR_DisplayPort
,
490 DRM_MODE_CONNECTOR_eDP
,
491 DRM_MODE_CONNECTOR_Unknown
494 bool radeon_get_atom_connector_info_from_object_table(struct drm_device
*dev
)
496 struct radeon_device
*rdev
= dev
->dev_private
;
497 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
498 struct atom_context
*ctx
= mode_info
->atom_context
;
499 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
500 u16 size
, data_offset
;
502 ATOM_CONNECTOR_OBJECT_TABLE
*con_obj
;
503 ATOM_OBJECT_TABLE
*router_obj
;
504 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
505 ATOM_OBJECT_HEADER
*obj_header
;
506 int i
, j
, k
, path_size
, device_support
;
508 u16 igp_lane_info
, conn_id
, connector_object_id
;
509 struct radeon_i2c_bus_rec ddc_bus
;
510 struct radeon_router router
;
511 struct radeon_gpio_rec gpio
;
512 struct radeon_hpd hpd
;
514 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
))
520 router
.valid
= false;
522 obj_header
= (ATOM_OBJECT_HEADER
*) (ctx
->bios
+ data_offset
);
523 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
524 (ctx
->bios
+ data_offset
+
525 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
526 con_obj
= (ATOM_CONNECTOR_OBJECT_TABLE
*)
527 (ctx
->bios
+ data_offset
+
528 le16_to_cpu(obj_header
->usConnectorObjectTableOffset
));
529 router_obj
= (ATOM_OBJECT_TABLE
*)
530 (ctx
->bios
+ data_offset
+
531 le16_to_cpu(obj_header
->usRouterObjectTableOffset
));
532 device_support
= le16_to_cpu(obj_header
->usDeviceSupport
);
535 for (i
= 0; i
< path_obj
->ucNumOfDispPath
; i
++) {
536 uint8_t *addr
= (uint8_t *) path_obj
->asDispPath
;
537 ATOM_DISPLAY_OBJECT_PATH
*path
;
539 path
= (ATOM_DISPLAY_OBJECT_PATH
*) addr
;
540 path_size
+= le16_to_cpu(path
->usSize
);
542 if (device_support
& le16_to_cpu(path
->usDeviceTag
)) {
543 uint8_t con_obj_id
, con_obj_num
, con_obj_type
;
546 (le16_to_cpu(path
->usConnObjectId
) & OBJECT_ID_MASK
)
549 (le16_to_cpu(path
->usConnObjectId
) & ENUM_ID_MASK
)
552 (le16_to_cpu(path
->usConnObjectId
) &
553 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
555 /* TODO CV support */
556 if (le16_to_cpu(path
->usDeviceTag
) ==
557 ATOM_DEVICE_CV_SUPPORT
)
561 if ((rdev
->flags
& RADEON_IS_IGP
) &&
563 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR
)) {
564 uint16_t igp_offset
= 0;
565 ATOM_INTEGRATED_SYSTEM_INFO_V2
*igp_obj
;
568 GetIndexIntoMasterTable(DATA
,
569 IntegratedSystemInfo
);
571 if (atom_parse_data_header(ctx
, index
, &size
, &frev
,
572 &crev
, &igp_offset
)) {
576 (ATOM_INTEGRATED_SYSTEM_INFO_V2
577 *) (ctx
->bios
+ igp_offset
);
580 uint32_t slot_config
, ct
;
582 if (con_obj_num
== 1)
591 ct
= (slot_config
>> 16) & 0xff;
593 object_connector_convert
595 connector_object_id
= ct
;
597 slot_config
& 0xffff;
605 object_connector_convert
[con_obj_id
];
606 connector_object_id
= con_obj_id
;
611 object_connector_convert
[con_obj_id
];
612 connector_object_id
= con_obj_id
;
615 if (connector_type
== DRM_MODE_CONNECTOR_Unknown
)
618 for (j
= 0; j
< ((le16_to_cpu(path
->usSize
) - 8) / 2); j
++) {
619 uint8_t grph_obj_id
, grph_obj_num
, grph_obj_type
;
622 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
623 OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
625 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
626 ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
628 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
629 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
631 if (grph_obj_type
== GRAPH_OBJECT_TYPE_ENCODER
) {
632 u16 encoder_obj
= le16_to_cpu(path
->usGraphicObjIds
[j
]);
634 radeon_add_atom_encoder(dev
,
640 } else if (grph_obj_type
== GRAPH_OBJECT_TYPE_ROUTER
) {
641 router
.valid
= false;
642 for (k
= 0; k
< router_obj
->ucNumberOfObjects
; k
++) {
643 u16 router_obj_id
= le16_to_cpu(router_obj
->asObjects
[j
].usObjectID
);
644 if (le16_to_cpu(path
->usGraphicObjIds
[j
]) == router_obj_id
) {
645 ATOM_COMMON_RECORD_HEADER
*record
= (ATOM_COMMON_RECORD_HEADER
*)
646 (ctx
->bios
+ data_offset
+
647 le16_to_cpu(router_obj
->asObjects
[k
].usRecordOffset
));
648 ATOM_I2C_RECORD
*i2c_record
;
649 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
650 ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*ddc_path
;
651 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*router_src_dst_table
=
652 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*)
653 (ctx
->bios
+ data_offset
+
654 le16_to_cpu(router_obj
->asObjects
[k
].usSrcDstTableOffset
));
657 router
.router_id
= router_obj_id
;
658 for (enum_id
= 0; enum_id
< router_src_dst_table
->ucNumberOfDst
;
660 if (le16_to_cpu(path
->usConnObjectId
) ==
661 le16_to_cpu(router_src_dst_table
->usDstObjectID
[enum_id
]))
665 while (record
->ucRecordType
> 0 &&
666 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
667 switch (record
->ucRecordType
) {
668 case ATOM_I2C_RECORD_TYPE
:
673 (ATOM_I2C_ID_CONFIG_ACCESS
*)
674 &i2c_record
->sucI2cId
;
676 radeon_lookup_i2c_gpio(rdev
,
679 router
.i2c_addr
= i2c_record
->ucI2CAddr
>> 1;
681 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE
:
682 ddc_path
= (ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*)
685 router
.mux_type
= ddc_path
->ucMuxType
;
686 router
.mux_control_pin
= ddc_path
->ucMuxControlPin
;
687 router
.mux_state
= ddc_path
->ucMuxState
[enum_id
];
690 record
= (ATOM_COMMON_RECORD_HEADER
*)
691 ((char *)record
+ record
->ucRecordSize
);
698 /* look up gpio for ddc, hpd */
699 ddc_bus
.valid
= false;
700 hpd
.hpd
= RADEON_HPD_NONE
;
701 if ((le16_to_cpu(path
->usDeviceTag
) &
702 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) == 0) {
703 for (j
= 0; j
< con_obj
->ucNumberOfObjects
; j
++) {
704 if (le16_to_cpu(path
->usConnObjectId
) ==
705 le16_to_cpu(con_obj
->asObjects
[j
].
707 ATOM_COMMON_RECORD_HEADER
709 (ATOM_COMMON_RECORD_HEADER
711 (ctx
->bios
+ data_offset
+
712 le16_to_cpu(con_obj
->
715 ATOM_I2C_RECORD
*i2c_record
;
716 ATOM_HPD_INT_RECORD
*hpd_record
;
717 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
719 while (record
->ucRecordType
> 0
722 ATOM_MAX_OBJECT_RECORD_NUMBER
) {
723 switch (record
->ucRecordType
) {
724 case ATOM_I2C_RECORD_TYPE
:
729 (ATOM_I2C_ID_CONFIG_ACCESS
*)
730 &i2c_record
->sucI2cId
;
731 ddc_bus
= radeon_lookup_i2c_gpio(rdev
,
735 case ATOM_HPD_INT_RECORD_TYPE
:
737 (ATOM_HPD_INT_RECORD
*)
739 gpio
= radeon_lookup_gpio(rdev
,
740 hpd_record
->ucHPDIntGPIOID
);
741 hpd
= radeon_atom_get_hpd_info_from_gpio(rdev
, &gpio
);
742 hpd
.plugged_state
= hpd_record
->ucPlugged_PinState
;
746 (ATOM_COMMON_RECORD_HEADER
757 /* needed for aux chan transactions */
758 ddc_bus
.hpd
= hpd
.hpd
;
760 conn_id
= le16_to_cpu(path
->usConnObjectId
);
762 if (!radeon_atom_apply_quirks
763 (dev
, le16_to_cpu(path
->usDeviceTag
), &connector_type
,
764 &ddc_bus
, &conn_id
, &hpd
))
767 radeon_add_atom_connector(dev
,
771 connector_type
, &ddc_bus
,
780 radeon_link_encoder_connector(dev
);
785 static uint16_t atombios_get_connector_object_id(struct drm_device
*dev
,
789 struct radeon_device
*rdev
= dev
->dev_private
;
791 if (rdev
->flags
& RADEON_IS_IGP
) {
792 return supported_devices_connector_object_id_convert
794 } else if (((connector_type
== DRM_MODE_CONNECTOR_DVII
) ||
795 (connector_type
== DRM_MODE_CONNECTOR_DVID
)) &&
796 (devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
797 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
798 struct atom_context
*ctx
= mode_info
->atom_context
;
799 int index
= GetIndexIntoMasterTable(DATA
, XTMDS_Info
);
800 uint16_t size
, data_offset
;
802 ATOM_XTMDS_INFO
*xtmds
;
804 if (atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
)) {
805 xtmds
= (ATOM_XTMDS_INFO
*)(ctx
->bios
+ data_offset
);
807 if (xtmds
->ucSupportedLink
& ATOM_XTMDS_SUPPORTED_DUALLINK
) {
808 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
809 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
811 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
813 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
814 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
816 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
819 return supported_devices_connector_object_id_convert
822 return supported_devices_connector_object_id_convert
827 struct bios_connector
{
832 struct radeon_i2c_bus_rec ddc_bus
;
833 struct radeon_hpd hpd
;
836 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
840 struct radeon_device
*rdev
= dev
->dev_private
;
841 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
842 struct atom_context
*ctx
= mode_info
->atom_context
;
843 int index
= GetIndexIntoMasterTable(DATA
, SupportedDevicesInfo
);
844 uint16_t size
, data_offset
;
846 uint16_t device_support
;
848 union atom_supported_devices
*supported_devices
;
849 int i
, j
, max_device
;
850 struct bios_connector
*bios_connectors
;
851 size_t bc_size
= sizeof(*bios_connectors
) * ATOM_MAX_SUPPORTED_DEVICE
;
852 struct radeon_router router
;
854 router
.valid
= false;
856 bios_connectors
= kzalloc(bc_size
, GFP_KERNEL
);
857 if (!bios_connectors
)
860 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
,
862 kfree(bios_connectors
);
867 (union atom_supported_devices
*)(ctx
->bios
+ data_offset
);
869 device_support
= le16_to_cpu(supported_devices
->info
.usDeviceSupport
);
872 max_device
= ATOM_MAX_SUPPORTED_DEVICE
;
874 max_device
= ATOM_MAX_SUPPORTED_DEVICE_INFO
;
876 for (i
= 0; i
< max_device
; i
++) {
877 ATOM_CONNECTOR_INFO_I2C ci
=
878 supported_devices
->info
.asConnInfo
[i
];
880 bios_connectors
[i
].valid
= false;
882 if (!(device_support
& (1 << i
))) {
886 if (i
== ATOM_DEVICE_CV_INDEX
) {
887 DRM_DEBUG_KMS("Skipping Component Video\n");
891 bios_connectors
[i
].connector_type
=
892 supported_devices_connector_convert
[ci
.sucConnectorInfo
.
896 if (bios_connectors
[i
].connector_type
==
897 DRM_MODE_CONNECTOR_Unknown
)
900 dac
= ci
.sucConnectorInfo
.sbfAccess
.bfAssociatedDAC
;
902 bios_connectors
[i
].line_mux
=
903 ci
.sucI2cId
.ucAccess
;
905 /* give tv unique connector ids */
906 if (i
== ATOM_DEVICE_TV1_INDEX
) {
907 bios_connectors
[i
].ddc_bus
.valid
= false;
908 bios_connectors
[i
].line_mux
= 50;
909 } else if (i
== ATOM_DEVICE_TV2_INDEX
) {
910 bios_connectors
[i
].ddc_bus
.valid
= false;
911 bios_connectors
[i
].line_mux
= 51;
912 } else if (i
== ATOM_DEVICE_CV_INDEX
) {
913 bios_connectors
[i
].ddc_bus
.valid
= false;
914 bios_connectors
[i
].line_mux
= 52;
916 bios_connectors
[i
].ddc_bus
=
917 radeon_lookup_i2c_gpio(rdev
,
918 bios_connectors
[i
].line_mux
);
920 if ((crev
> 1) && (frev
> 1)) {
921 u8 isb
= supported_devices
->info_2d1
.asIntSrcInfo
[i
].ucIntSrcBitmap
;
924 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
927 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
930 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
934 if (i
== ATOM_DEVICE_DFP1_INDEX
)
935 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
936 else if (i
== ATOM_DEVICE_DFP2_INDEX
)
937 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
939 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
942 /* Always set the connector type to VGA for CRT1/CRT2. if they are
943 * shared with a DVI port, we'll pick up the DVI connector when we
944 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
946 if (i
== ATOM_DEVICE_CRT1_INDEX
|| i
== ATOM_DEVICE_CRT2_INDEX
)
947 bios_connectors
[i
].connector_type
=
948 DRM_MODE_CONNECTOR_VGA
;
950 if (!radeon_atom_apply_quirks
951 (dev
, (1 << i
), &bios_connectors
[i
].connector_type
,
952 &bios_connectors
[i
].ddc_bus
, &bios_connectors
[i
].line_mux
,
953 &bios_connectors
[i
].hpd
))
956 bios_connectors
[i
].valid
= true;
957 bios_connectors
[i
].devices
= (1 << i
);
959 if (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
)
960 radeon_add_atom_encoder(dev
,
961 radeon_get_encoder_enum(dev
,
966 radeon_add_legacy_encoder(dev
,
967 radeon_get_encoder_enum(dev
,
973 /* combine shared connectors */
974 for (i
= 0; i
< max_device
; i
++) {
975 if (bios_connectors
[i
].valid
) {
976 for (j
= 0; j
< max_device
; j
++) {
977 if (bios_connectors
[j
].valid
&& (i
!= j
)) {
978 if (bios_connectors
[i
].line_mux
==
979 bios_connectors
[j
].line_mux
) {
980 /* make sure not to combine LVDS */
981 if (bios_connectors
[i
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
982 bios_connectors
[i
].line_mux
= 53;
983 bios_connectors
[i
].ddc_bus
.valid
= false;
986 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
987 bios_connectors
[j
].line_mux
= 53;
988 bios_connectors
[j
].ddc_bus
.valid
= false;
991 /* combine analog and digital for DVI-I */
992 if (((bios_connectors
[i
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
993 (bios_connectors
[j
].devices
& (ATOM_DEVICE_CRT_SUPPORT
))) ||
994 ((bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
995 (bios_connectors
[i
].devices
& (ATOM_DEVICE_CRT_SUPPORT
)))) {
996 bios_connectors
[i
].devices
|=
997 bios_connectors
[j
].devices
;
998 bios_connectors
[i
].connector_type
=
999 DRM_MODE_CONNECTOR_DVII
;
1000 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
))
1001 bios_connectors
[i
].hpd
=
1002 bios_connectors
[j
].hpd
;
1003 bios_connectors
[j
].valid
= false;
1011 /* add the connectors */
1012 for (i
= 0; i
< max_device
; i
++) {
1013 if (bios_connectors
[i
].valid
) {
1014 uint16_t connector_object_id
=
1015 atombios_get_connector_object_id(dev
,
1016 bios_connectors
[i
].connector_type
,
1017 bios_connectors
[i
].devices
);
1018 radeon_add_atom_connector(dev
,
1019 bios_connectors
[i
].line_mux
,
1020 bios_connectors
[i
].devices
,
1023 &bios_connectors
[i
].ddc_bus
,
1025 connector_object_id
,
1026 &bios_connectors
[i
].hpd
,
1031 radeon_link_encoder_connector(dev
);
1033 kfree(bios_connectors
);
1037 union firmware_info
{
1038 ATOM_FIRMWARE_INFO info
;
1039 ATOM_FIRMWARE_INFO_V1_2 info_12
;
1040 ATOM_FIRMWARE_INFO_V1_3 info_13
;
1041 ATOM_FIRMWARE_INFO_V1_4 info_14
;
1042 ATOM_FIRMWARE_INFO_V2_1 info_21
;
1045 bool radeon_atom_get_clock_info(struct drm_device
*dev
)
1047 struct radeon_device
*rdev
= dev
->dev_private
;
1048 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1049 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
1050 union firmware_info
*firmware_info
;
1052 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
1053 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
1054 struct radeon_pll
*dcpll
= &rdev
->clock
.dcpll
;
1055 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
1056 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
1057 uint16_t data_offset
;
1059 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1060 &frev
, &crev
, &data_offset
)) {
1062 (union firmware_info
*)(mode_info
->atom_context
->bios
+
1065 p1pll
->reference_freq
=
1066 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1067 p1pll
->reference_div
= 0;
1070 p1pll
->pll_out_min
=
1071 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Output
);
1073 p1pll
->pll_out_min
=
1074 le32_to_cpu(firmware_info
->info_12
.ulMinPixelClockPLL_Output
);
1075 p1pll
->pll_out_max
=
1076 le32_to_cpu(firmware_info
->info
.ulMaxPixelClockPLL_Output
);
1079 p1pll
->lcd_pll_out_min
=
1080 le16_to_cpu(firmware_info
->info_14
.usLcdMinPixelClockPLL_Output
) * 100;
1081 if (p1pll
->lcd_pll_out_min
== 0)
1082 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1083 p1pll
->lcd_pll_out_max
=
1084 le16_to_cpu(firmware_info
->info_14
.usLcdMaxPixelClockPLL_Output
) * 100;
1085 if (p1pll
->lcd_pll_out_max
== 0)
1086 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1088 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1089 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1092 if (p1pll
->pll_out_min
== 0) {
1093 if (ASIC_IS_AVIVO(rdev
))
1094 p1pll
->pll_out_min
= 64800;
1096 p1pll
->pll_out_min
= 20000;
1097 } else if (p1pll
->pll_out_min
> 64800) {
1098 /* Limiting the pll output range is a good thing generally as
1099 * it limits the number of possible pll combinations for a given
1100 * frequency presumably to the ones that work best on each card.
1101 * However, certain duallink DVI monitors seem to like
1102 * pll combinations that would be limited by this at least on
1103 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1106 if (!radeon_new_pll
)
1107 p1pll
->pll_out_min
= 64800;
1111 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Input
);
1113 le16_to_cpu(firmware_info
->info
.usMaxPixelClockPLL_Input
);
1118 spll
->reference_freq
=
1119 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1120 spll
->reference_div
= 0;
1123 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Output
);
1125 le32_to_cpu(firmware_info
->info
.ulMaxEngineClockPLL_Output
);
1128 if (spll
->pll_out_min
== 0) {
1129 if (ASIC_IS_AVIVO(rdev
))
1130 spll
->pll_out_min
= 64800;
1132 spll
->pll_out_min
= 20000;
1136 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Input
);
1138 le16_to_cpu(firmware_info
->info
.usMaxEngineClockPLL_Input
);
1141 mpll
->reference_freq
=
1142 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1143 mpll
->reference_div
= 0;
1146 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Output
);
1148 le32_to_cpu(firmware_info
->info
.ulMaxMemoryClockPLL_Output
);
1151 if (mpll
->pll_out_min
== 0) {
1152 if (ASIC_IS_AVIVO(rdev
))
1153 mpll
->pll_out_min
= 64800;
1155 mpll
->pll_out_min
= 20000;
1159 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Input
);
1161 le16_to_cpu(firmware_info
->info
.usMaxMemoryClockPLL_Input
);
1163 rdev
->clock
.default_sclk
=
1164 le32_to_cpu(firmware_info
->info
.ulDefaultEngineClock
);
1165 rdev
->clock
.default_mclk
=
1166 le32_to_cpu(firmware_info
->info
.ulDefaultMemoryClock
);
1168 if (ASIC_IS_DCE4(rdev
)) {
1169 rdev
->clock
.default_dispclk
=
1170 le32_to_cpu(firmware_info
->info_21
.ulDefaultDispEngineClkFreq
);
1171 if (rdev
->clock
.default_dispclk
== 0)
1172 rdev
->clock
.default_dispclk
= 60000; /* 600 Mhz */
1173 rdev
->clock
.dp_extclk
=
1174 le16_to_cpu(firmware_info
->info_21
.usUniphyDPModeExtClkFreq
);
1185 struct _ATOM_INTEGRATED_SYSTEM_INFO info
;
1186 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2
;
1189 bool radeon_atombios_sideport_present(struct radeon_device
*rdev
)
1191 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1192 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1193 union igp_info
*igp_info
;
1197 /* sideport is AMD only */
1198 if (rdev
->family
== CHIP_RS600
)
1201 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1202 &frev
, &crev
, &data_offset
)) {
1203 igp_info
= (union igp_info
*)(mode_info
->atom_context
->bios
+
1207 if (igp_info
->info
.ulBootUpMemoryClock
)
1211 if (igp_info
->info_2
.ulBootUpSidePortClock
)
1215 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
1222 bool radeon_atombios_get_tmds_info(struct radeon_encoder
*encoder
,
1223 struct radeon_encoder_int_tmds
*tmds
)
1225 struct drm_device
*dev
= encoder
->base
.dev
;
1226 struct radeon_device
*rdev
= dev
->dev_private
;
1227 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1228 int index
= GetIndexIntoMasterTable(DATA
, TMDS_Info
);
1229 uint16_t data_offset
;
1230 struct _ATOM_TMDS_INFO
*tmds_info
;
1235 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1236 &frev
, &crev
, &data_offset
)) {
1238 (struct _ATOM_TMDS_INFO
*)(mode_info
->atom_context
->bios
+
1241 maxfreq
= le16_to_cpu(tmds_info
->usMaxFrequency
);
1242 for (i
= 0; i
< 4; i
++) {
1243 tmds
->tmds_pll
[i
].freq
=
1244 le16_to_cpu(tmds_info
->asMiscInfo
[i
].usFrequency
);
1245 tmds
->tmds_pll
[i
].value
=
1246 tmds_info
->asMiscInfo
[i
].ucPLL_ChargePump
& 0x3f;
1247 tmds
->tmds_pll
[i
].value
|=
1248 (tmds_info
->asMiscInfo
[i
].
1249 ucPLL_VCO_Gain
& 0x3f) << 6;
1250 tmds
->tmds_pll
[i
].value
|=
1251 (tmds_info
->asMiscInfo
[i
].
1252 ucPLL_DutyCycle
& 0xf) << 12;
1253 tmds
->tmds_pll
[i
].value
|=
1254 (tmds_info
->asMiscInfo
[i
].
1255 ucPLL_VoltageSwing
& 0xf) << 16;
1257 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1258 tmds
->tmds_pll
[i
].freq
,
1259 tmds
->tmds_pll
[i
].value
);
1261 if (maxfreq
== tmds
->tmds_pll
[i
].freq
) {
1262 tmds
->tmds_pll
[i
].freq
= 0xffffffff;
1271 static struct radeon_atom_ss
*radeon_atombios_get_ss_info(struct
1276 struct drm_device
*dev
= encoder
->base
.dev
;
1277 struct radeon_device
*rdev
= dev
->dev_private
;
1278 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1279 int index
= GetIndexIntoMasterTable(DATA
, PPLL_SS_Info
);
1280 uint16_t data_offset
;
1281 struct _ATOM_SPREAD_SPECTRUM_INFO
*ss_info
;
1283 struct radeon_atom_ss
*ss
= NULL
;
1286 if (id
> ATOM_MAX_SS_ENTRY
)
1289 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1290 &frev
, &crev
, &data_offset
)) {
1292 (struct _ATOM_SPREAD_SPECTRUM_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1295 kzalloc(sizeof(struct radeon_atom_ss
), GFP_KERNEL
);
1300 for (i
= 0; i
< ATOM_MAX_SS_ENTRY
; i
++) {
1301 if (ss_info
->asSS_Info
[i
].ucSS_Id
== id
) {
1303 le16_to_cpu(ss_info
->asSS_Info
[i
].usSpreadSpectrumPercentage
);
1304 ss
->type
= ss_info
->asSS_Info
[i
].ucSpreadSpectrumType
;
1305 ss
->step
= ss_info
->asSS_Info
[i
].ucSS_Step
;
1306 ss
->delay
= ss_info
->asSS_Info
[i
].ucSS_Delay
;
1307 ss
->range
= ss_info
->asSS_Info
[i
].ucSS_Range
;
1308 ss
->refdiv
= ss_info
->asSS_Info
[i
].ucRecommendedRef_Div
;
1317 struct _ATOM_LVDS_INFO info
;
1318 struct _ATOM_LVDS_INFO_V12 info_12
;
1321 struct radeon_encoder_atom_dig
*radeon_atombios_get_lvds_info(struct
1325 struct drm_device
*dev
= encoder
->base
.dev
;
1326 struct radeon_device
*rdev
= dev
->dev_private
;
1327 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1328 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
1329 uint16_t data_offset
, misc
;
1330 union lvds_info
*lvds_info
;
1332 struct radeon_encoder_atom_dig
*lvds
= NULL
;
1333 int encoder_enum
= (encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1335 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1336 &frev
, &crev
, &data_offset
)) {
1338 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1340 kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
1345 lvds
->native_mode
.clock
=
1346 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
1347 lvds
->native_mode
.hdisplay
=
1348 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
1349 lvds
->native_mode
.vdisplay
=
1350 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
1351 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
1352 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
1353 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
1354 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
1355 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
1356 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
1357 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
1358 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
1359 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
1360 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncOffset
);
1361 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
1362 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
1363 lvds
->panel_pwr_delay
=
1364 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
1365 lvds
->lvds_misc
= lvds_info
->info
.ucLVDS_Misc
;
1367 misc
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.susModeMiscInfo
.usAccess
);
1368 if (misc
& ATOM_VSYNC_POLARITY
)
1369 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
1370 if (misc
& ATOM_HSYNC_POLARITY
)
1371 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
1372 if (misc
& ATOM_COMPOSITESYNC
)
1373 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_CSYNC
;
1374 if (misc
& ATOM_INTERLACE
)
1375 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
1376 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1377 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_DBLSCAN
;
1379 /* set crtc values */
1380 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1382 lvds
->ss
= radeon_atombios_get_ss_info(encoder
, lvds_info
->info
.ucSS_Id
);
1384 if (ASIC_IS_AVIVO(rdev
)) {
1385 if (radeon_new_pll
== 0)
1386 lvds
->pll_algo
= PLL_ALGO_LEGACY
;
1388 lvds
->pll_algo
= PLL_ALGO_NEW
;
1390 if (radeon_new_pll
== 1)
1391 lvds
->pll_algo
= PLL_ALGO_NEW
;
1393 lvds
->pll_algo
= PLL_ALGO_LEGACY
;
1396 encoder
->native_mode
= lvds
->native_mode
;
1398 if (encoder_enum
== 2)
1401 lvds
->linkb
= false;
1407 struct radeon_encoder_primary_dac
*
1408 radeon_atombios_get_primary_dac_info(struct radeon_encoder
*encoder
)
1410 struct drm_device
*dev
= encoder
->base
.dev
;
1411 struct radeon_device
*rdev
= dev
->dev_private
;
1412 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1413 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1414 uint16_t data_offset
;
1415 struct _COMPASSIONATE_DATA
*dac_info
;
1418 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
1420 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1421 &frev
, &crev
, &data_offset
)) {
1422 dac_info
= (struct _COMPASSIONATE_DATA
*)
1423 (mode_info
->atom_context
->bios
+ data_offset
);
1425 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
), GFP_KERNEL
);
1430 bg
= dac_info
->ucDAC1_BG_Adjustment
;
1431 dac
= dac_info
->ucDAC1_DAC_Adjustment
;
1432 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
1438 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
1439 struct drm_display_mode
*mode
)
1441 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1442 ATOM_ANALOG_TV_INFO
*tv_info
;
1443 ATOM_ANALOG_TV_INFO_V1_2
*tv_info_v1_2
;
1444 ATOM_DTD_FORMAT
*dtd_timings
;
1445 int data_index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1447 u16 data_offset
, misc
;
1449 if (!atom_parse_data_header(mode_info
->atom_context
, data_index
, NULL
,
1450 &frev
, &crev
, &data_offset
))
1455 tv_info
= (ATOM_ANALOG_TV_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1456 if (index
>= MAX_SUPPORTED_TV_TIMING
)
1459 mode
->crtc_htotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Total
);
1460 mode
->crtc_hdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Disp
);
1461 mode
->crtc_hsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
);
1462 mode
->crtc_hsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
) +
1463 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncWidth
);
1465 mode
->crtc_vtotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Total
);
1466 mode
->crtc_vdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Disp
);
1467 mode
->crtc_vsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
);
1468 mode
->crtc_vsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
) +
1469 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncWidth
);
1472 misc
= le16_to_cpu(tv_info
->aModeTimings
[index
].susModeMiscInfo
.usAccess
);
1473 if (misc
& ATOM_VSYNC_POLARITY
)
1474 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1475 if (misc
& ATOM_HSYNC_POLARITY
)
1476 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1477 if (misc
& ATOM_COMPOSITESYNC
)
1478 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1479 if (misc
& ATOM_INTERLACE
)
1480 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1481 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1482 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1484 mode
->clock
= le16_to_cpu(tv_info
->aModeTimings
[index
].usPixelClock
) * 10;
1487 /* PAL timings appear to have wrong values for totals */
1488 mode
->crtc_htotal
-= 1;
1489 mode
->crtc_vtotal
-= 1;
1493 tv_info_v1_2
= (ATOM_ANALOG_TV_INFO_V1_2
*)(mode_info
->atom_context
->bios
+ data_offset
);
1494 if (index
>= MAX_SUPPORTED_TV_TIMING_V1_2
)
1497 dtd_timings
= &tv_info_v1_2
->aModeTimings
[index
];
1498 mode
->crtc_htotal
= le16_to_cpu(dtd_timings
->usHActive
) +
1499 le16_to_cpu(dtd_timings
->usHBlanking_Time
);
1500 mode
->crtc_hdisplay
= le16_to_cpu(dtd_timings
->usHActive
);
1501 mode
->crtc_hsync_start
= le16_to_cpu(dtd_timings
->usHActive
) +
1502 le16_to_cpu(dtd_timings
->usHSyncOffset
);
1503 mode
->crtc_hsync_end
= mode
->crtc_hsync_start
+
1504 le16_to_cpu(dtd_timings
->usHSyncWidth
);
1506 mode
->crtc_vtotal
= le16_to_cpu(dtd_timings
->usVActive
) +
1507 le16_to_cpu(dtd_timings
->usVBlanking_Time
);
1508 mode
->crtc_vdisplay
= le16_to_cpu(dtd_timings
->usVActive
);
1509 mode
->crtc_vsync_start
= le16_to_cpu(dtd_timings
->usVActive
) +
1510 le16_to_cpu(dtd_timings
->usVSyncOffset
);
1511 mode
->crtc_vsync_end
= mode
->crtc_vsync_start
+
1512 le16_to_cpu(dtd_timings
->usVSyncWidth
);
1515 misc
= le16_to_cpu(dtd_timings
->susModeMiscInfo
.usAccess
);
1516 if (misc
& ATOM_VSYNC_POLARITY
)
1517 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1518 if (misc
& ATOM_HSYNC_POLARITY
)
1519 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1520 if (misc
& ATOM_COMPOSITESYNC
)
1521 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1522 if (misc
& ATOM_INTERLACE
)
1523 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1524 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1525 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1527 mode
->clock
= le16_to_cpu(dtd_timings
->usPixClk
) * 10;
1534 radeon_atombios_get_tv_info(struct radeon_device
*rdev
)
1536 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1537 int index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1538 uint16_t data_offset
;
1540 struct _ATOM_ANALOG_TV_INFO
*tv_info
;
1541 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
1543 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1544 &frev
, &crev
, &data_offset
)) {
1546 tv_info
= (struct _ATOM_ANALOG_TV_INFO
*)
1547 (mode_info
->atom_context
->bios
+ data_offset
);
1549 switch (tv_info
->ucTV_BootUpDefaultStandard
) {
1551 tv_std
= TV_STD_NTSC
;
1552 DRM_INFO("Default TV standard: NTSC\n");
1555 tv_std
= TV_STD_NTSC_J
;
1556 DRM_INFO("Default TV standard: NTSC-J\n");
1559 tv_std
= TV_STD_PAL
;
1560 DRM_INFO("Default TV standard: PAL\n");
1563 tv_std
= TV_STD_PAL_M
;
1564 DRM_INFO("Default TV standard: PAL-M\n");
1567 tv_std
= TV_STD_PAL_N
;
1568 DRM_INFO("Default TV standard: PAL-N\n");
1571 tv_std
= TV_STD_PAL_CN
;
1572 DRM_INFO("Default TV standard: PAL-CN\n");
1575 tv_std
= TV_STD_PAL_60
;
1576 DRM_INFO("Default TV standard: PAL-60\n");
1579 tv_std
= TV_STD_SECAM
;
1580 DRM_INFO("Default TV standard: SECAM\n");
1583 tv_std
= TV_STD_NTSC
;
1584 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1591 struct radeon_encoder_tv_dac
*
1592 radeon_atombios_get_tv_dac_info(struct radeon_encoder
*encoder
)
1594 struct drm_device
*dev
= encoder
->base
.dev
;
1595 struct radeon_device
*rdev
= dev
->dev_private
;
1596 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1597 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1598 uint16_t data_offset
;
1599 struct _COMPASSIONATE_DATA
*dac_info
;
1602 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1604 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1605 &frev
, &crev
, &data_offset
)) {
1607 dac_info
= (struct _COMPASSIONATE_DATA
*)
1608 (mode_info
->atom_context
->bios
+ data_offset
);
1610 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1615 bg
= dac_info
->ucDAC2_CRT2_BG_Adjustment
;
1616 dac
= dac_info
->ucDAC2_CRT2_DAC_Adjustment
;
1617 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1619 bg
= dac_info
->ucDAC2_PAL_BG_Adjustment
;
1620 dac
= dac_info
->ucDAC2_PAL_DAC_Adjustment
;
1621 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1623 bg
= dac_info
->ucDAC2_NTSC_BG_Adjustment
;
1624 dac
= dac_info
->ucDAC2_NTSC_DAC_Adjustment
;
1625 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1627 tv_dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
1632 static const char *thermal_controller_names
[] = {
1643 static const char *pp_lib_thermal_controller_names
[] = {
1656 "adt7473 with internal",
1661 struct _ATOM_POWERPLAY_INFO info
;
1662 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
1663 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
1664 struct _ATOM_PPLIB_POWERPLAYTABLE info_4
;
1667 void radeon_atombios_get_power_modes(struct radeon_device
*rdev
)
1669 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1670 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
1673 u32 misc
, misc2
= 0, sclk
, mclk
;
1674 union power_info
*power_info
;
1675 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
1676 struct _ATOM_PPLIB_STATE
*power_state
;
1677 int num_modes
= 0, i
, j
;
1678 int state_index
= 0, mode_index
= 0;
1679 struct radeon_i2c_bus_rec i2c_bus
;
1681 rdev
->pm
.default_power_state_index
= -1;
1683 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1684 &frev
, &crev
, &data_offset
)) {
1685 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1687 /* add the i2c bus for thermal/fan chip */
1688 if (power_info
->info
.ucOverdriveThermalController
> 0) {
1689 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1690 thermal_controller_names
[power_info
->info
.ucOverdriveThermalController
],
1691 power_info
->info
.ucOverdriveControllerAddress
>> 1);
1692 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, power_info
->info
.ucOverdriveI2cLine
);
1693 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
1694 if (rdev
->pm
.i2c_bus
) {
1695 struct i2c_board_info info
= { };
1696 const char *name
= thermal_controller_names
[power_info
->info
.
1697 ucOverdriveThermalController
];
1698 info
.addr
= power_info
->info
.ucOverdriveControllerAddress
>> 1;
1699 strlcpy(info
.type
, name
, sizeof(info
.type
));
1700 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
1703 num_modes
= power_info
->info
.ucNumOfPowerModeEntries
;
1704 if (num_modes
> ATOM_MAX_NUMBEROF_POWER_BLOCK
)
1705 num_modes
= ATOM_MAX_NUMBEROF_POWER_BLOCK
;
1706 /* last mode is usually default, array is low to high */
1707 for (i
= 0; i
< num_modes
; i
++) {
1708 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
1711 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1712 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
1713 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usMemoryClock
);
1714 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
1715 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usEngineClock
);
1716 /* skip invalid modes */
1717 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
1718 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
1720 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
1721 power_info
->info
.asPowerPlayInfo
[i
].ucNumPciELanes
;
1722 misc
= le32_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].ulMiscInfo
);
1723 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
1724 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
1725 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1727 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
1728 radeon_lookup_gpio(rdev
,
1729 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
1730 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
1731 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1734 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1736 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
1737 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1739 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
1740 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
1742 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1743 rdev
->pm
.power_state
[state_index
].misc
= misc
;
1744 /* order matters! */
1745 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
1746 rdev
->pm
.power_state
[state_index
].type
=
1747 POWER_STATE_TYPE_POWERSAVE
;
1748 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
1749 rdev
->pm
.power_state
[state_index
].type
=
1750 POWER_STATE_TYPE_BATTERY
;
1751 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
1752 rdev
->pm
.power_state
[state_index
].type
=
1753 POWER_STATE_TYPE_BATTERY
;
1754 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
1755 rdev
->pm
.power_state
[state_index
].type
=
1756 POWER_STATE_TYPE_BALANCED
;
1757 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
) {
1758 rdev
->pm
.power_state
[state_index
].type
=
1759 POWER_STATE_TYPE_PERFORMANCE
;
1760 rdev
->pm
.power_state
[state_index
].flags
&=
1761 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1763 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
1764 rdev
->pm
.power_state
[state_index
].type
=
1765 POWER_STATE_TYPE_DEFAULT
;
1766 rdev
->pm
.default_power_state_index
= state_index
;
1767 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
1768 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1769 rdev
->pm
.power_state
[state_index
].flags
&=
1770 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1771 } else if (state_index
== 0) {
1772 rdev
->pm
.power_state
[state_index
].clock_info
[0].flags
|=
1773 RADEON_PM_MODE_NO_DISPLAY
;
1778 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1779 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
1780 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMemoryClock
);
1781 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
1782 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulEngineClock
);
1783 /* skip invalid modes */
1784 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
1785 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
1787 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
1788 power_info
->info_2
.asPowerPlayInfo
[i
].ucNumPciELanes
;
1789 misc
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo
);
1790 misc2
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo2
);
1791 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
1792 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
1793 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1795 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
1796 radeon_lookup_gpio(rdev
,
1797 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
1798 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
1799 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1802 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1804 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
1805 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1807 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
1808 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
1810 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1811 rdev
->pm
.power_state
[state_index
].misc
= misc
;
1812 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
1813 /* order matters! */
1814 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
1815 rdev
->pm
.power_state
[state_index
].type
=
1816 POWER_STATE_TYPE_POWERSAVE
;
1817 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
1818 rdev
->pm
.power_state
[state_index
].type
=
1819 POWER_STATE_TYPE_BATTERY
;
1820 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
1821 rdev
->pm
.power_state
[state_index
].type
=
1822 POWER_STATE_TYPE_BATTERY
;
1823 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
1824 rdev
->pm
.power_state
[state_index
].type
=
1825 POWER_STATE_TYPE_BALANCED
;
1826 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
) {
1827 rdev
->pm
.power_state
[state_index
].type
=
1828 POWER_STATE_TYPE_PERFORMANCE
;
1829 rdev
->pm
.power_state
[state_index
].flags
&=
1830 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1832 if (misc2
& ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE
)
1833 rdev
->pm
.power_state
[state_index
].type
=
1834 POWER_STATE_TYPE_BALANCED
;
1835 if (misc2
& ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT
)
1836 rdev
->pm
.power_state
[state_index
].flags
&=
1837 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1838 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
1839 rdev
->pm
.power_state
[state_index
].type
=
1840 POWER_STATE_TYPE_DEFAULT
;
1841 rdev
->pm
.default_power_state_index
= state_index
;
1842 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
1843 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1844 rdev
->pm
.power_state
[state_index
].flags
&=
1845 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1846 } else if (state_index
== 0) {
1847 rdev
->pm
.power_state
[state_index
].clock_info
[0].flags
|=
1848 RADEON_PM_MODE_NO_DISPLAY
;
1853 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1854 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
1855 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMemoryClock
);
1856 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
1857 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulEngineClock
);
1858 /* skip invalid modes */
1859 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
1860 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
1862 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
1863 power_info
->info_3
.asPowerPlayInfo
[i
].ucNumPciELanes
;
1864 misc
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo
);
1865 misc2
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo2
);
1866 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
1867 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
1868 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1870 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
1871 radeon_lookup_gpio(rdev
,
1872 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
1873 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
1874 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1877 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1879 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
1880 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1882 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
1883 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
1884 if (misc2
& ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN
) {
1885 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_enabled
=
1887 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_id
=
1888 power_info
->info_3
.asPowerPlayInfo
[i
].ucVDDCI_VoltageDropIndex
;
1891 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1892 rdev
->pm
.power_state
[state_index
].misc
= misc
;
1893 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
1894 /* order matters! */
1895 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
1896 rdev
->pm
.power_state
[state_index
].type
=
1897 POWER_STATE_TYPE_POWERSAVE
;
1898 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
1899 rdev
->pm
.power_state
[state_index
].type
=
1900 POWER_STATE_TYPE_BATTERY
;
1901 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
1902 rdev
->pm
.power_state
[state_index
].type
=
1903 POWER_STATE_TYPE_BATTERY
;
1904 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
1905 rdev
->pm
.power_state
[state_index
].type
=
1906 POWER_STATE_TYPE_BALANCED
;
1907 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
) {
1908 rdev
->pm
.power_state
[state_index
].type
=
1909 POWER_STATE_TYPE_PERFORMANCE
;
1910 rdev
->pm
.power_state
[state_index
].flags
&=
1911 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1913 if (misc2
& ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE
)
1914 rdev
->pm
.power_state
[state_index
].type
=
1915 POWER_STATE_TYPE_BALANCED
;
1916 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
1917 rdev
->pm
.power_state
[state_index
].type
=
1918 POWER_STATE_TYPE_DEFAULT
;
1919 rdev
->pm
.default_power_state_index
= state_index
;
1920 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
1921 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1922 } else if (state_index
== 0) {
1923 rdev
->pm
.power_state
[state_index
].clock_info
[0].flags
|=
1924 RADEON_PM_MODE_NO_DISPLAY
;
1930 /* last mode is usually default */
1931 if (rdev
->pm
.default_power_state_index
== -1) {
1932 rdev
->pm
.power_state
[state_index
- 1].type
=
1933 POWER_STATE_TYPE_DEFAULT
;
1934 rdev
->pm
.default_power_state_index
= state_index
- 1;
1935 rdev
->pm
.power_state
[state_index
- 1].default_clock_mode
=
1936 &rdev
->pm
.power_state
[state_index
- 1].clock_info
[0];
1937 rdev
->pm
.power_state
[state_index
].flags
&=
1938 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1939 rdev
->pm
.power_state
[state_index
].misc
= 0;
1940 rdev
->pm
.power_state
[state_index
].misc2
= 0;
1943 int fw_index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
1944 uint8_t fw_frev
, fw_crev
;
1945 uint16_t fw_data_offset
, vddc
= 0;
1946 union firmware_info
*firmware_info
;
1947 ATOM_PPLIB_THERMALCONTROLLER
*controller
= &power_info
->info_4
.sThermalController
;
1949 if (atom_parse_data_header(mode_info
->atom_context
, fw_index
, NULL
,
1950 &fw_frev
, &fw_crev
, &fw_data_offset
)) {
1952 (union firmware_info
*)(mode_info
->atom_context
->bios
+
1954 vddc
= firmware_info
->info_14
.usBootUpVDDCVoltage
;
1957 /* add the i2c bus for thermal/fan chip */
1958 if (controller
->ucType
> 0) {
1959 if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV6xx
) {
1960 DRM_INFO("Internal thermal controller %s fan control\n",
1961 (controller
->ucFanParameters
&
1962 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
1963 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV6XX
;
1964 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV770
) {
1965 DRM_INFO("Internal thermal controller %s fan control\n",
1966 (controller
->ucFanParameters
&
1967 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
1968 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV770
;
1969 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_EVERGREEN
) {
1970 DRM_INFO("Internal thermal controller %s fan control\n",
1971 (controller
->ucFanParameters
&
1972 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
1973 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_EVERGREEN
;
1974 } else if ((controller
->ucType
==
1975 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO
) ||
1976 (controller
->ucType
==
1977 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL
)) {
1978 DRM_INFO("Special thermal controller config\n");
1980 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1981 pp_lib_thermal_controller_names
[controller
->ucType
],
1982 controller
->ucI2cAddress
>> 1,
1983 (controller
->ucFanParameters
&
1984 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
1985 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, controller
->ucI2cLine
);
1986 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
1987 if (rdev
->pm
.i2c_bus
) {
1988 struct i2c_board_info info
= { };
1989 const char *name
= pp_lib_thermal_controller_names
[controller
->ucType
];
1990 info
.addr
= controller
->ucI2cAddress
>> 1;
1991 strlcpy(info
.type
, name
, sizeof(info
.type
));
1992 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
1997 /* first mode is usually default, followed by low to high */
1998 for (i
= 0; i
< power_info
->info_4
.ucNumStates
; i
++) {
2000 power_state
= (struct _ATOM_PPLIB_STATE
*)
2001 (mode_info
->atom_context
->bios
+
2003 le16_to_cpu(power_info
->info_4
.usStateArrayOffset
) +
2004 i
* power_info
->info_4
.ucStateEntrySize
);
2005 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2006 (mode_info
->atom_context
->bios
+
2008 le16_to_cpu(power_info
->info_4
.usNonClockInfoArrayOffset
) +
2009 (power_state
->ucNonClockStateIndex
*
2010 power_info
->info_4
.ucNonClockSize
));
2011 for (j
= 0; j
< (power_info
->info_4
.ucStateEntrySize
- 1); j
++) {
2012 if (rdev
->flags
& RADEON_IS_IGP
) {
2013 struct _ATOM_PPLIB_RS780_CLOCK_INFO
*clock_info
=
2014 (struct _ATOM_PPLIB_RS780_CLOCK_INFO
*)
2015 (mode_info
->atom_context
->bios
+
2017 le16_to_cpu(power_info
->info_4
.usClockInfoArrayOffset
) +
2018 (power_state
->ucClockStateIndices
[j
] *
2019 power_info
->info_4
.ucClockInfoSize
));
2020 sclk
= le16_to_cpu(clock_info
->usLowEngineClockLow
);
2021 sclk
|= clock_info
->ucLowEngineClockHigh
<< 16;
2022 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2023 /* skip invalid modes */
2024 if (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0)
2026 /* voltage works differently on IGPs */
2028 } else if (ASIC_IS_DCE4(rdev
)) {
2029 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
*clock_info
=
2030 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
*)
2031 (mode_info
->atom_context
->bios
+
2033 le16_to_cpu(power_info
->info_4
.usClockInfoArrayOffset
) +
2034 (power_state
->ucClockStateIndices
[j
] *
2035 power_info
->info_4
.ucClockInfoSize
));
2036 sclk
= le16_to_cpu(clock_info
->usEngineClockLow
);
2037 sclk
|= clock_info
->ucEngineClockHigh
<< 16;
2038 mclk
= le16_to_cpu(clock_info
->usMemoryClockLow
);
2039 mclk
|= clock_info
->ucMemoryClockHigh
<< 16;
2040 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2041 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2042 /* skip invalid modes */
2043 if ((rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
== 0) ||
2044 (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0))
2046 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2048 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2053 struct _ATOM_PPLIB_R600_CLOCK_INFO
*clock_info
=
2054 (struct _ATOM_PPLIB_R600_CLOCK_INFO
*)
2055 (mode_info
->atom_context
->bios
+
2057 le16_to_cpu(power_info
->info_4
.usClockInfoArrayOffset
) +
2058 (power_state
->ucClockStateIndices
[j
] *
2059 power_info
->info_4
.ucClockInfoSize
));
2060 sclk
= le16_to_cpu(clock_info
->usEngineClockLow
);
2061 sclk
|= clock_info
->ucEngineClockHigh
<< 16;
2062 mclk
= le16_to_cpu(clock_info
->usMemoryClockLow
);
2063 mclk
|= clock_info
->ucMemoryClockHigh
<< 16;
2064 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2065 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2066 /* skip invalid modes */
2067 if ((rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
== 0) ||
2068 (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0))
2070 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2072 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2077 rdev
->pm
.power_state
[state_index
].num_clock_modes
= mode_index
;
2079 misc
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
2080 misc2
= le16_to_cpu(non_clock_info
->usClassification
);
2081 rdev
->pm
.power_state
[state_index
].misc
= misc
;
2082 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
2083 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2084 ((misc
& ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
) >>
2085 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
) + 1;
2086 switch (misc2
& ATOM_PPLIB_CLASSIFICATION_UI_MASK
) {
2087 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
:
2088 rdev
->pm
.power_state
[state_index
].type
=
2089 POWER_STATE_TYPE_BATTERY
;
2091 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
:
2092 rdev
->pm
.power_state
[state_index
].type
=
2093 POWER_STATE_TYPE_BALANCED
;
2095 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
:
2096 rdev
->pm
.power_state
[state_index
].type
=
2097 POWER_STATE_TYPE_PERFORMANCE
;
2099 case ATOM_PPLIB_CLASSIFICATION_UI_NONE
:
2100 if (misc2
& ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
2101 rdev
->pm
.power_state
[state_index
].type
=
2102 POWER_STATE_TYPE_PERFORMANCE
;
2105 rdev
->pm
.power_state
[state_index
].flags
= 0;
2106 if (misc
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
)
2107 rdev
->pm
.power_state
[state_index
].flags
|=
2108 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2109 if (misc2
& ATOM_PPLIB_CLASSIFICATION_BOOT
) {
2110 rdev
->pm
.power_state
[state_index
].type
=
2111 POWER_STATE_TYPE_DEFAULT
;
2112 rdev
->pm
.default_power_state_index
= state_index
;
2113 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2114 &rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
- 1];
2115 /* patch the table values with the default slck/mclk from firmware info */
2116 for (j
= 0; j
< mode_index
; j
++) {
2117 rdev
->pm
.power_state
[state_index
].clock_info
[j
].mclk
=
2118 rdev
->clock
.default_mclk
;
2119 rdev
->pm
.power_state
[state_index
].clock_info
[j
].sclk
=
2120 rdev
->clock
.default_sclk
;
2122 rdev
->pm
.power_state
[state_index
].clock_info
[j
].voltage
.voltage
=
2129 /* if multiple clock modes, mark the lowest as no display */
2130 for (i
= 0; i
< state_index
; i
++) {
2131 if (rdev
->pm
.power_state
[i
].num_clock_modes
> 1)
2132 rdev
->pm
.power_state
[i
].clock_info
[0].flags
|=
2133 RADEON_PM_MODE_NO_DISPLAY
;
2135 /* first mode is usually default */
2136 if (rdev
->pm
.default_power_state_index
== -1) {
2137 rdev
->pm
.power_state
[0].type
=
2138 POWER_STATE_TYPE_DEFAULT
;
2139 rdev
->pm
.default_power_state_index
= 0;
2140 rdev
->pm
.power_state
[0].default_clock_mode
=
2141 &rdev
->pm
.power_state
[0].clock_info
[0];
2145 /* add the default mode */
2146 rdev
->pm
.power_state
[state_index
].type
=
2147 POWER_STATE_TYPE_DEFAULT
;
2148 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2149 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= rdev
->clock
.default_mclk
;
2150 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= rdev
->clock
.default_sclk
;
2151 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2152 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2153 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2154 rdev
->pm
.power_state
[state_index
].pcie_lanes
= 16;
2155 rdev
->pm
.default_power_state_index
= state_index
;
2156 rdev
->pm
.power_state
[state_index
].flags
= 0;
2160 rdev
->pm
.num_power_states
= state_index
;
2162 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
2163 rdev
->pm
.current_clock_mode_index
= 0;
2164 rdev
->pm
.current_vddc
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
2167 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
)
2169 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args
;
2170 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicClockGating
);
2172 args
.ucEnable
= enable
;
2174 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2177 uint32_t radeon_atom_get_engine_clock(struct radeon_device
*rdev
)
2179 GET_ENGINE_CLOCK_PS_ALLOCATION args
;
2180 int index
= GetIndexIntoMasterTable(COMMAND
, GetEngineClock
);
2182 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2183 return args
.ulReturnEngineClock
;
2186 uint32_t radeon_atom_get_memory_clock(struct radeon_device
*rdev
)
2188 GET_MEMORY_CLOCK_PS_ALLOCATION args
;
2189 int index
= GetIndexIntoMasterTable(COMMAND
, GetMemoryClock
);
2191 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2192 return args
.ulReturnMemoryClock
;
2195 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
,
2198 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
2199 int index
= GetIndexIntoMasterTable(COMMAND
, SetEngineClock
);
2201 args
.ulTargetEngineClock
= eng_clock
; /* 10 khz */
2203 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2206 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
,
2209 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
2210 int index
= GetIndexIntoMasterTable(COMMAND
, SetMemoryClock
);
2212 if (rdev
->flags
& RADEON_IS_IGP
)
2215 args
.ulTargetMemoryClock
= mem_clock
; /* 10 khz */
2217 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2221 struct _SET_VOLTAGE_PS_ALLOCATION alloc
;
2222 struct _SET_VOLTAGE_PARAMETERS v1
;
2223 struct _SET_VOLTAGE_PARAMETERS_V2 v2
;
2226 void radeon_atom_set_voltage(struct radeon_device
*rdev
, u16 level
)
2228 union set_voltage args
;
2229 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
2230 u8 frev
, crev
, volt_index
= level
;
2232 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2237 args
.v1
.ucVoltageType
= SET_VOLTAGE_TYPE_ASIC_VDDC
;
2238 args
.v1
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_ALL_SOURCE
;
2239 args
.v1
.ucVoltageIndex
= volt_index
;
2242 args
.v2
.ucVoltageType
= SET_VOLTAGE_TYPE_ASIC_VDDC
;
2243 args
.v2
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE
;
2244 args
.v2
.usVoltageLevel
= cpu_to_le16(level
);
2247 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
2251 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2256 void radeon_atom_initialize_bios_scratch_regs(struct drm_device
*dev
)
2258 struct radeon_device
*rdev
= dev
->dev_private
;
2259 uint32_t bios_2_scratch
, bios_6_scratch
;
2261 if (rdev
->family
>= CHIP_R600
) {
2262 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
2263 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
2265 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
2266 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2269 /* let the bios control the backlight */
2270 bios_2_scratch
&= ~ATOM_S2_VRI_BRIGHT_ENABLE
;
2272 /* tell the bios not to handle mode switching */
2273 bios_6_scratch
|= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
| ATOM_S6_ACC_MODE
);
2275 if (rdev
->family
>= CHIP_R600
) {
2276 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
2277 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2279 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
2280 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2285 void radeon_save_bios_scratch_regs(struct radeon_device
*rdev
)
2287 uint32_t scratch_reg
;
2290 if (rdev
->family
>= CHIP_R600
)
2291 scratch_reg
= R600_BIOS_0_SCRATCH
;
2293 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
2295 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
2296 rdev
->bios_scratch
[i
] = RREG32(scratch_reg
+ (i
* 4));
2299 void radeon_restore_bios_scratch_regs(struct radeon_device
*rdev
)
2301 uint32_t scratch_reg
;
2304 if (rdev
->family
>= CHIP_R600
)
2305 scratch_reg
= R600_BIOS_0_SCRATCH
;
2307 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
2309 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
2310 WREG32(scratch_reg
+ (i
* 4), rdev
->bios_scratch
[i
]);
2313 void radeon_atom_output_lock(struct drm_encoder
*encoder
, bool lock
)
2315 struct drm_device
*dev
= encoder
->dev
;
2316 struct radeon_device
*rdev
= dev
->dev_private
;
2317 uint32_t bios_6_scratch
;
2319 if (rdev
->family
>= CHIP_R600
)
2320 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
2322 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2325 bios_6_scratch
|= ATOM_S6_CRITICAL_STATE
;
2327 bios_6_scratch
&= ~ATOM_S6_CRITICAL_STATE
;
2329 if (rdev
->family
>= CHIP_R600
)
2330 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2332 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2335 /* at some point we may want to break this out into individual functions */
2337 radeon_atombios_connected_scratch_regs(struct drm_connector
*connector
,
2338 struct drm_encoder
*encoder
,
2341 struct drm_device
*dev
= connector
->dev
;
2342 struct radeon_device
*rdev
= dev
->dev_private
;
2343 struct radeon_connector
*radeon_connector
=
2344 to_radeon_connector(connector
);
2345 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2346 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
2348 if (rdev
->family
>= CHIP_R600
) {
2349 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2350 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
2351 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
2353 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
2354 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
2355 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2358 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
2359 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
2361 DRM_DEBUG_KMS("TV1 connected\n");
2362 bios_3_scratch
|= ATOM_S3_TV1_ACTIVE
;
2363 bios_6_scratch
|= ATOM_S6_ACC_REQ_TV1
;
2365 DRM_DEBUG_KMS("TV1 disconnected\n");
2366 bios_0_scratch
&= ~ATOM_S0_TV1_MASK
;
2367 bios_3_scratch
&= ~ATOM_S3_TV1_ACTIVE
;
2368 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_TV1
;
2371 if ((radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) &&
2372 (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
)) {
2374 DRM_DEBUG_KMS("CV connected\n");
2375 bios_3_scratch
|= ATOM_S3_CV_ACTIVE
;
2376 bios_6_scratch
|= ATOM_S6_ACC_REQ_CV
;
2378 DRM_DEBUG_KMS("CV disconnected\n");
2379 bios_0_scratch
&= ~ATOM_S0_CV_MASK
;
2380 bios_3_scratch
&= ~ATOM_S3_CV_ACTIVE
;
2381 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CV
;
2384 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
2385 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
2387 DRM_DEBUG_KMS("LCD1 connected\n");
2388 bios_0_scratch
|= ATOM_S0_LCD1
;
2389 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
2390 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
2392 DRM_DEBUG_KMS("LCD1 disconnected\n");
2393 bios_0_scratch
&= ~ATOM_S0_LCD1
;
2394 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
2395 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
2398 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
2399 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
2401 DRM_DEBUG_KMS("CRT1 connected\n");
2402 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
2403 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
2404 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
2406 DRM_DEBUG_KMS("CRT1 disconnected\n");
2407 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
2408 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
2409 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
2412 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
2413 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
2415 DRM_DEBUG_KMS("CRT2 connected\n");
2416 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
2417 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
2418 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
2420 DRM_DEBUG_KMS("CRT2 disconnected\n");
2421 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
2422 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
2423 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
2426 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
2427 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
2429 DRM_DEBUG_KMS("DFP1 connected\n");
2430 bios_0_scratch
|= ATOM_S0_DFP1
;
2431 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
2432 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
2434 DRM_DEBUG_KMS("DFP1 disconnected\n");
2435 bios_0_scratch
&= ~ATOM_S0_DFP1
;
2436 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
2437 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
2440 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
2441 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
2443 DRM_DEBUG_KMS("DFP2 connected\n");
2444 bios_0_scratch
|= ATOM_S0_DFP2
;
2445 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
2446 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
2448 DRM_DEBUG_KMS("DFP2 disconnected\n");
2449 bios_0_scratch
&= ~ATOM_S0_DFP2
;
2450 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
2451 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
2454 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
2455 (radeon_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
2457 DRM_DEBUG_KMS("DFP3 connected\n");
2458 bios_0_scratch
|= ATOM_S0_DFP3
;
2459 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
2460 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
2462 DRM_DEBUG_KMS("DFP3 disconnected\n");
2463 bios_0_scratch
&= ~ATOM_S0_DFP3
;
2464 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
2465 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
2468 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
2469 (radeon_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
2471 DRM_DEBUG_KMS("DFP4 connected\n");
2472 bios_0_scratch
|= ATOM_S0_DFP4
;
2473 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
2474 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
2476 DRM_DEBUG_KMS("DFP4 disconnected\n");
2477 bios_0_scratch
&= ~ATOM_S0_DFP4
;
2478 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
2479 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
2482 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
2483 (radeon_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
2485 DRM_DEBUG_KMS("DFP5 connected\n");
2486 bios_0_scratch
|= ATOM_S0_DFP5
;
2487 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
2488 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
2490 DRM_DEBUG_KMS("DFP5 disconnected\n");
2491 bios_0_scratch
&= ~ATOM_S0_DFP5
;
2492 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
2493 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
2497 if (rdev
->family
>= CHIP_R600
) {
2498 WREG32(R600_BIOS_0_SCRATCH
, bios_0_scratch
);
2499 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
2500 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2502 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
2503 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
2504 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2509 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
2511 struct drm_device
*dev
= encoder
->dev
;
2512 struct radeon_device
*rdev
= dev
->dev_private
;
2513 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2514 uint32_t bios_3_scratch
;
2516 if (rdev
->family
>= CHIP_R600
)
2517 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
2519 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
2521 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2522 bios_3_scratch
&= ~ATOM_S3_TV1_CRTC_ACTIVE
;
2523 bios_3_scratch
|= (crtc
<< 18);
2525 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2526 bios_3_scratch
&= ~ATOM_S3_CV_CRTC_ACTIVE
;
2527 bios_3_scratch
|= (crtc
<< 24);
2529 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2530 bios_3_scratch
&= ~ATOM_S3_CRT1_CRTC_ACTIVE
;
2531 bios_3_scratch
|= (crtc
<< 16);
2533 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2534 bios_3_scratch
&= ~ATOM_S3_CRT2_CRTC_ACTIVE
;
2535 bios_3_scratch
|= (crtc
<< 20);
2537 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
2538 bios_3_scratch
&= ~ATOM_S3_LCD1_CRTC_ACTIVE
;
2539 bios_3_scratch
|= (crtc
<< 17);
2541 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
2542 bios_3_scratch
&= ~ATOM_S3_DFP1_CRTC_ACTIVE
;
2543 bios_3_scratch
|= (crtc
<< 19);
2545 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
2546 bios_3_scratch
&= ~ATOM_S3_DFP2_CRTC_ACTIVE
;
2547 bios_3_scratch
|= (crtc
<< 23);
2549 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
2550 bios_3_scratch
&= ~ATOM_S3_DFP3_CRTC_ACTIVE
;
2551 bios_3_scratch
|= (crtc
<< 25);
2554 if (rdev
->family
>= CHIP_R600
)
2555 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
2557 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
2561 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
2563 struct drm_device
*dev
= encoder
->dev
;
2564 struct radeon_device
*rdev
= dev
->dev_private
;
2565 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2566 uint32_t bios_2_scratch
;
2568 if (rdev
->family
>= CHIP_R600
)
2569 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
2571 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
2573 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2575 bios_2_scratch
&= ~ATOM_S2_TV1_DPMS_STATE
;
2577 bios_2_scratch
|= ATOM_S2_TV1_DPMS_STATE
;
2579 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2581 bios_2_scratch
&= ~ATOM_S2_CV_DPMS_STATE
;
2583 bios_2_scratch
|= ATOM_S2_CV_DPMS_STATE
;
2585 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2587 bios_2_scratch
&= ~ATOM_S2_CRT1_DPMS_STATE
;
2589 bios_2_scratch
|= ATOM_S2_CRT1_DPMS_STATE
;
2591 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2593 bios_2_scratch
&= ~ATOM_S2_CRT2_DPMS_STATE
;
2595 bios_2_scratch
|= ATOM_S2_CRT2_DPMS_STATE
;
2597 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
2599 bios_2_scratch
&= ~ATOM_S2_LCD1_DPMS_STATE
;
2601 bios_2_scratch
|= ATOM_S2_LCD1_DPMS_STATE
;
2603 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
2605 bios_2_scratch
&= ~ATOM_S2_DFP1_DPMS_STATE
;
2607 bios_2_scratch
|= ATOM_S2_DFP1_DPMS_STATE
;
2609 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
2611 bios_2_scratch
&= ~ATOM_S2_DFP2_DPMS_STATE
;
2613 bios_2_scratch
|= ATOM_S2_DFP2_DPMS_STATE
;
2615 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
2617 bios_2_scratch
&= ~ATOM_S2_DFP3_DPMS_STATE
;
2619 bios_2_scratch
|= ATOM_S2_DFP3_DPMS_STATE
;
2621 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) {
2623 bios_2_scratch
&= ~ATOM_S2_DFP4_DPMS_STATE
;
2625 bios_2_scratch
|= ATOM_S2_DFP4_DPMS_STATE
;
2627 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) {
2629 bios_2_scratch
&= ~ATOM_S2_DFP5_DPMS_STATE
;
2631 bios_2_scratch
|= ATOM_S2_DFP5_DPMS_STATE
;
2634 if (rdev
->family
>= CHIP_R600
)
2635 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
2637 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);