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Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_atombios.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device, u16 caps);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
53
54 /* from radeon_legacy_encoder.c */
55 extern void
56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
58
59 union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63 };
64
65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
67 {
68 struct atom_context *ctx = rdev->mode_info.atom_context;
69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
73 uint16_t data_offset, size;
74 int i, num_indices;
75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
86 gpio = &i2c_info->asGPIO_Info[i];
87
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
91 (gpio->usClkMaskRegisterIndex == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
101 /* some DCE3 boards have bad data for this entry */
102 if (ASIC_IS_DCE3(rdev)) {
103 if ((i == 4) &&
104 (gpio->usClkMaskRegisterIndex == 0x1fda) &&
105 (gpio->sucI2cId.ucAccess == 0x94))
106 gpio->sucI2cId.ucAccess = 0x14;
107 }
108
109 if (gpio->sucI2cId.ucAccess == id) {
110 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
111 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
112 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
113 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
114 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
115 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
116 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
117 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
118 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
119 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
120 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
121 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
122 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
123 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
124 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
125 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
126
127 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
128 i2c.hw_capable = true;
129 else
130 i2c.hw_capable = false;
131
132 if (gpio->sucI2cId.ucAccess == 0xa0)
133 i2c.mm_i2c = true;
134 else
135 i2c.mm_i2c = false;
136
137 i2c.i2c_id = gpio->sucI2cId.ucAccess;
138
139 if (i2c.mask_clk_reg)
140 i2c.valid = true;
141 break;
142 }
143 }
144 }
145
146 return i2c;
147 }
148
149 void radeon_atombios_i2c_init(struct radeon_device *rdev)
150 {
151 struct atom_context *ctx = rdev->mode_info.atom_context;
152 ATOM_GPIO_I2C_ASSIGMENT *gpio;
153 struct radeon_i2c_bus_rec i2c;
154 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
155 struct _ATOM_GPIO_I2C_INFO *i2c_info;
156 uint16_t data_offset, size;
157 int i, num_indices;
158 char stmp[32];
159
160 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
161
162 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
163 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
164
165 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
166 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
167
168 for (i = 0; i < num_indices; i++) {
169 gpio = &i2c_info->asGPIO_Info[i];
170 i2c.valid = false;
171
172 /* some evergreen boards have bad data for this entry */
173 if (ASIC_IS_DCE4(rdev)) {
174 if ((i == 7) &&
175 (gpio->usClkMaskRegisterIndex == 0x1936) &&
176 (gpio->sucI2cId.ucAccess == 0)) {
177 gpio->sucI2cId.ucAccess = 0x97;
178 gpio->ucDataMaskShift = 8;
179 gpio->ucDataEnShift = 8;
180 gpio->ucDataY_Shift = 8;
181 gpio->ucDataA_Shift = 8;
182 }
183 }
184
185 /* some DCE3 boards have bad data for this entry */
186 if (ASIC_IS_DCE3(rdev)) {
187 if ((i == 4) &&
188 (gpio->usClkMaskRegisterIndex == 0x1fda) &&
189 (gpio->sucI2cId.ucAccess == 0x94))
190 gpio->sucI2cId.ucAccess = 0x14;
191 }
192
193 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
194 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
195 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
196 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
197 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
198 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
199 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
200 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
201 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
202 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
203 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
204 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
205 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
206 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
207 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
208 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
209
210 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
211 i2c.hw_capable = true;
212 else
213 i2c.hw_capable = false;
214
215 if (gpio->sucI2cId.ucAccess == 0xa0)
216 i2c.mm_i2c = true;
217 else
218 i2c.mm_i2c = false;
219
220 i2c.i2c_id = gpio->sucI2cId.ucAccess;
221
222 if (i2c.mask_clk_reg) {
223 i2c.valid = true;
224 sprintf(stmp, "0x%x", i2c.i2c_id);
225 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
226 }
227 }
228 }
229 }
230
231 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
232 u8 id)
233 {
234 struct atom_context *ctx = rdev->mode_info.atom_context;
235 struct radeon_gpio_rec gpio;
236 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
237 struct _ATOM_GPIO_PIN_LUT *gpio_info;
238 ATOM_GPIO_PIN_ASSIGNMENT *pin;
239 u16 data_offset, size;
240 int i, num_indices;
241
242 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
243 gpio.valid = false;
244
245 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
246 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
247
248 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
249 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
250
251 for (i = 0; i < num_indices; i++) {
252 pin = &gpio_info->asGPIO_Pin[i];
253 if (id == pin->ucGPIO_ID) {
254 gpio.id = pin->ucGPIO_ID;
255 gpio.reg = pin->usGpioPin_AIndex * 4;
256 gpio.mask = (1 << pin->ucGpioPinBitShift);
257 gpio.valid = true;
258 break;
259 }
260 }
261 }
262
263 return gpio;
264 }
265
266 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
267 struct radeon_gpio_rec *gpio)
268 {
269 struct radeon_hpd hpd;
270 u32 reg;
271
272 memset(&hpd, 0, sizeof(struct radeon_hpd));
273
274 if (ASIC_IS_DCE4(rdev))
275 reg = EVERGREEN_DC_GPIO_HPD_A;
276 else
277 reg = AVIVO_DC_GPIO_HPD_A;
278
279 hpd.gpio = *gpio;
280 if (gpio->reg == reg) {
281 switch(gpio->mask) {
282 case (1 << 0):
283 hpd.hpd = RADEON_HPD_1;
284 break;
285 case (1 << 8):
286 hpd.hpd = RADEON_HPD_2;
287 break;
288 case (1 << 16):
289 hpd.hpd = RADEON_HPD_3;
290 break;
291 case (1 << 24):
292 hpd.hpd = RADEON_HPD_4;
293 break;
294 case (1 << 26):
295 hpd.hpd = RADEON_HPD_5;
296 break;
297 case (1 << 28):
298 hpd.hpd = RADEON_HPD_6;
299 break;
300 default:
301 hpd.hpd = RADEON_HPD_NONE;
302 break;
303 }
304 } else
305 hpd.hpd = RADEON_HPD_NONE;
306 return hpd;
307 }
308
309 static bool radeon_atom_apply_quirks(struct drm_device *dev,
310 uint32_t supported_device,
311 int *connector_type,
312 struct radeon_i2c_bus_rec *i2c_bus,
313 uint16_t *line_mux,
314 struct radeon_hpd *hpd)
315 {
316
317 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
318 if ((dev->pdev->device == 0x791e) &&
319 (dev->pdev->subsystem_vendor == 0x1043) &&
320 (dev->pdev->subsystem_device == 0x826d)) {
321 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
322 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
323 *connector_type = DRM_MODE_CONNECTOR_DVID;
324 }
325
326 /* Asrock RS600 board lists the DVI port as HDMI */
327 if ((dev->pdev->device == 0x7941) &&
328 (dev->pdev->subsystem_vendor == 0x1849) &&
329 (dev->pdev->subsystem_device == 0x7941)) {
330 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
331 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
332 *connector_type = DRM_MODE_CONNECTOR_DVID;
333 }
334
335 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
336 if ((dev->pdev->device == 0x796e) &&
337 (dev->pdev->subsystem_vendor == 0x1462) &&
338 (dev->pdev->subsystem_device == 0x7302)) {
339 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
340 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
341 return false;
342 }
343
344 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
345 if ((dev->pdev->device == 0x7941) &&
346 (dev->pdev->subsystem_vendor == 0x147b) &&
347 (dev->pdev->subsystem_device == 0x2412)) {
348 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
349 return false;
350 }
351
352 /* Falcon NW laptop lists vga ddc line for LVDS */
353 if ((dev->pdev->device == 0x5653) &&
354 (dev->pdev->subsystem_vendor == 0x1462) &&
355 (dev->pdev->subsystem_device == 0x0291)) {
356 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
357 i2c_bus->valid = false;
358 *line_mux = 53;
359 }
360 }
361
362 /* HIS X1300 is DVI+VGA, not DVI+DVI */
363 if ((dev->pdev->device == 0x7146) &&
364 (dev->pdev->subsystem_vendor == 0x17af) &&
365 (dev->pdev->subsystem_device == 0x2058)) {
366 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
367 return false;
368 }
369
370 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
371 if ((dev->pdev->device == 0x7142) &&
372 (dev->pdev->subsystem_vendor == 0x1458) &&
373 (dev->pdev->subsystem_device == 0x2134)) {
374 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
375 return false;
376 }
377
378
379 /* Funky macbooks */
380 if ((dev->pdev->device == 0x71C5) &&
381 (dev->pdev->subsystem_vendor == 0x106b) &&
382 (dev->pdev->subsystem_device == 0x0080)) {
383 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
384 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
385 return false;
386 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
387 *line_mux = 0x90;
388 }
389
390 /* mac rv630 */
391 if ((dev->pdev->device == 0x9588) &&
392 (dev->pdev->subsystem_vendor == 0x106b) &&
393 (dev->pdev->subsystem_device == 0x00a6)) {
394 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
395 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
396 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
397 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
398 }
399 }
400
401 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
402 if ((dev->pdev->device == 0x9598) &&
403 (dev->pdev->subsystem_vendor == 0x1043) &&
404 (dev->pdev->subsystem_device == 0x01da)) {
405 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
406 *connector_type = DRM_MODE_CONNECTOR_DVII;
407 }
408 }
409
410 /* ASUS HD 3600 board lists the DVI port as HDMI */
411 if ((dev->pdev->device == 0x9598) &&
412 (dev->pdev->subsystem_vendor == 0x1043) &&
413 (dev->pdev->subsystem_device == 0x01e4)) {
414 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
415 *connector_type = DRM_MODE_CONNECTOR_DVII;
416 }
417 }
418
419 /* ASUS HD 3450 board lists the DVI port as HDMI */
420 if ((dev->pdev->device == 0x95C5) &&
421 (dev->pdev->subsystem_vendor == 0x1043) &&
422 (dev->pdev->subsystem_device == 0x01e2)) {
423 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
424 *connector_type = DRM_MODE_CONNECTOR_DVII;
425 }
426 }
427
428 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
429 * HDMI + VGA reporting as HDMI
430 */
431 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
432 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
433 *connector_type = DRM_MODE_CONNECTOR_VGA;
434 *line_mux = 0;
435 }
436 }
437
438 /* Acer laptop (Acer TravelMate 5730G) has an HDMI port
439 * on the laptop and a DVI port on the docking station and
440 * both share the same encoder, hpd pin, and ddc line.
441 * So while the bios table is technically correct,
442 * we drop the DVI port here since xrandr has no concept of
443 * encoders and will try and drive both connectors
444 * with different crtcs which isn't possible on the hardware
445 * side and leaves no crtcs for LVDS or VGA.
446 */
447 if ((dev->pdev->device == 0x95c4) &&
448 (dev->pdev->subsystem_vendor == 0x1025) &&
449 (dev->pdev->subsystem_device == 0x013c)) {
450 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
451 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
452 /* actually it's a DVI-D port not DVI-I */
453 *connector_type = DRM_MODE_CONNECTOR_DVID;
454 return false;
455 }
456 }
457
458 /* XFX Pine Group device rv730 reports no VGA DDC lines
459 * even though they are wired up to record 0x93
460 */
461 if ((dev->pdev->device == 0x9498) &&
462 (dev->pdev->subsystem_vendor == 0x1682) &&
463 (dev->pdev->subsystem_device == 0x2452)) {
464 struct radeon_device *rdev = dev->dev_private;
465 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
466 }
467 return true;
468 }
469
470 const int supported_devices_connector_convert[] = {
471 DRM_MODE_CONNECTOR_Unknown,
472 DRM_MODE_CONNECTOR_VGA,
473 DRM_MODE_CONNECTOR_DVII,
474 DRM_MODE_CONNECTOR_DVID,
475 DRM_MODE_CONNECTOR_DVIA,
476 DRM_MODE_CONNECTOR_SVIDEO,
477 DRM_MODE_CONNECTOR_Composite,
478 DRM_MODE_CONNECTOR_LVDS,
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_Unknown,
481 DRM_MODE_CONNECTOR_HDMIA,
482 DRM_MODE_CONNECTOR_HDMIB,
483 DRM_MODE_CONNECTOR_Unknown,
484 DRM_MODE_CONNECTOR_Unknown,
485 DRM_MODE_CONNECTOR_9PinDIN,
486 DRM_MODE_CONNECTOR_DisplayPort
487 };
488
489 const uint16_t supported_devices_connector_object_id_convert[] = {
490 CONNECTOR_OBJECT_ID_NONE,
491 CONNECTOR_OBJECT_ID_VGA,
492 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
493 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
494 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
495 CONNECTOR_OBJECT_ID_COMPOSITE,
496 CONNECTOR_OBJECT_ID_SVIDEO,
497 CONNECTOR_OBJECT_ID_LVDS,
498 CONNECTOR_OBJECT_ID_9PIN_DIN,
499 CONNECTOR_OBJECT_ID_9PIN_DIN,
500 CONNECTOR_OBJECT_ID_DISPLAYPORT,
501 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
502 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
503 CONNECTOR_OBJECT_ID_SVIDEO
504 };
505
506 const int object_connector_convert[] = {
507 DRM_MODE_CONNECTOR_Unknown,
508 DRM_MODE_CONNECTOR_DVII,
509 DRM_MODE_CONNECTOR_DVII,
510 DRM_MODE_CONNECTOR_DVID,
511 DRM_MODE_CONNECTOR_DVID,
512 DRM_MODE_CONNECTOR_VGA,
513 DRM_MODE_CONNECTOR_Composite,
514 DRM_MODE_CONNECTOR_SVIDEO,
515 DRM_MODE_CONNECTOR_Unknown,
516 DRM_MODE_CONNECTOR_Unknown,
517 DRM_MODE_CONNECTOR_9PinDIN,
518 DRM_MODE_CONNECTOR_Unknown,
519 DRM_MODE_CONNECTOR_HDMIA,
520 DRM_MODE_CONNECTOR_HDMIB,
521 DRM_MODE_CONNECTOR_LVDS,
522 DRM_MODE_CONNECTOR_9PinDIN,
523 DRM_MODE_CONNECTOR_Unknown,
524 DRM_MODE_CONNECTOR_Unknown,
525 DRM_MODE_CONNECTOR_Unknown,
526 DRM_MODE_CONNECTOR_DisplayPort,
527 DRM_MODE_CONNECTOR_eDP,
528 DRM_MODE_CONNECTOR_Unknown
529 };
530
531 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
532 {
533 struct radeon_device *rdev = dev->dev_private;
534 struct radeon_mode_info *mode_info = &rdev->mode_info;
535 struct atom_context *ctx = mode_info->atom_context;
536 int index = GetIndexIntoMasterTable(DATA, Object_Header);
537 u16 size, data_offset;
538 u8 frev, crev;
539 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
540 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
541 ATOM_OBJECT_TABLE *router_obj;
542 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
543 ATOM_OBJECT_HEADER *obj_header;
544 int i, j, k, path_size, device_support;
545 int connector_type;
546 u16 igp_lane_info, conn_id, connector_object_id;
547 struct radeon_i2c_bus_rec ddc_bus;
548 struct radeon_router router;
549 struct radeon_gpio_rec gpio;
550 struct radeon_hpd hpd;
551
552 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
553 return false;
554
555 if (crev < 2)
556 return false;
557
558 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
559 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
560 (ctx->bios + data_offset +
561 le16_to_cpu(obj_header->usDisplayPathTableOffset));
562 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
563 (ctx->bios + data_offset +
564 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
565 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
566 (ctx->bios + data_offset +
567 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
568 router_obj = (ATOM_OBJECT_TABLE *)
569 (ctx->bios + data_offset +
570 le16_to_cpu(obj_header->usRouterObjectTableOffset));
571 device_support = le16_to_cpu(obj_header->usDeviceSupport);
572
573 path_size = 0;
574 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
575 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
576 ATOM_DISPLAY_OBJECT_PATH *path;
577 addr += path_size;
578 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
579 path_size += le16_to_cpu(path->usSize);
580
581 if (device_support & le16_to_cpu(path->usDeviceTag)) {
582 uint8_t con_obj_id, con_obj_num, con_obj_type;
583
584 con_obj_id =
585 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
586 >> OBJECT_ID_SHIFT;
587 con_obj_num =
588 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
589 >> ENUM_ID_SHIFT;
590 con_obj_type =
591 (le16_to_cpu(path->usConnObjectId) &
592 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
593
594 /* TODO CV support */
595 if (le16_to_cpu(path->usDeviceTag) ==
596 ATOM_DEVICE_CV_SUPPORT)
597 continue;
598
599 /* IGP chips */
600 if ((rdev->flags & RADEON_IS_IGP) &&
601 (con_obj_id ==
602 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
603 uint16_t igp_offset = 0;
604 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
605
606 index =
607 GetIndexIntoMasterTable(DATA,
608 IntegratedSystemInfo);
609
610 if (atom_parse_data_header(ctx, index, &size, &frev,
611 &crev, &igp_offset)) {
612
613 if (crev >= 2) {
614 igp_obj =
615 (ATOM_INTEGRATED_SYSTEM_INFO_V2
616 *) (ctx->bios + igp_offset);
617
618 if (igp_obj) {
619 uint32_t slot_config, ct;
620
621 if (con_obj_num == 1)
622 slot_config =
623 igp_obj->
624 ulDDISlot1Config;
625 else
626 slot_config =
627 igp_obj->
628 ulDDISlot2Config;
629
630 ct = (slot_config >> 16) & 0xff;
631 connector_type =
632 object_connector_convert
633 [ct];
634 connector_object_id = ct;
635 igp_lane_info =
636 slot_config & 0xffff;
637 } else
638 continue;
639 } else
640 continue;
641 } else {
642 igp_lane_info = 0;
643 connector_type =
644 object_connector_convert[con_obj_id];
645 connector_object_id = con_obj_id;
646 }
647 } else {
648 igp_lane_info = 0;
649 connector_type =
650 object_connector_convert[con_obj_id];
651 connector_object_id = con_obj_id;
652 }
653
654 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
655 continue;
656
657 router.ddc_valid = false;
658 router.cd_valid = false;
659 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
660 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
661
662 grph_obj_id =
663 (le16_to_cpu(path->usGraphicObjIds[j]) &
664 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
665 grph_obj_num =
666 (le16_to_cpu(path->usGraphicObjIds[j]) &
667 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
668 grph_obj_type =
669 (le16_to_cpu(path->usGraphicObjIds[j]) &
670 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
671
672 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
673 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
674 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
675 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
676 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
677 (ctx->bios + data_offset +
678 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
679 ATOM_ENCODER_CAP_RECORD *cap_record;
680 u16 caps = 0;
681
682 while (record->ucRecordType > 0 &&
683 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
684 switch (record->ucRecordType) {
685 case ATOM_ENCODER_CAP_RECORD_TYPE:
686 cap_record =(ATOM_ENCODER_CAP_RECORD *)
687 record;
688 caps = le16_to_cpu(cap_record->usEncoderCap);
689 break;
690 }
691 record = (ATOM_COMMON_RECORD_HEADER *)
692 ((char *)record + record->ucRecordSize);
693 }
694 radeon_add_atom_encoder(dev,
695 encoder_obj,
696 le16_to_cpu
697 (path->
698 usDeviceTag),
699 caps);
700 }
701 }
702 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
703 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
704 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
705 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
706 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
707 (ctx->bios + data_offset +
708 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
709 ATOM_I2C_RECORD *i2c_record;
710 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
711 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
712 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
713 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
714 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
715 (ctx->bios + data_offset +
716 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
717 int enum_id;
718
719 router.router_id = router_obj_id;
720 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
721 enum_id++) {
722 if (le16_to_cpu(path->usConnObjectId) ==
723 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
724 break;
725 }
726
727 while (record->ucRecordType > 0 &&
728 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
729 switch (record->ucRecordType) {
730 case ATOM_I2C_RECORD_TYPE:
731 i2c_record =
732 (ATOM_I2C_RECORD *)
733 record;
734 i2c_config =
735 (ATOM_I2C_ID_CONFIG_ACCESS *)
736 &i2c_record->sucI2cId;
737 router.i2c_info =
738 radeon_lookup_i2c_gpio(rdev,
739 i2c_config->
740 ucAccess);
741 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
742 break;
743 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
744 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
745 record;
746 router.ddc_valid = true;
747 router.ddc_mux_type = ddc_path->ucMuxType;
748 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
749 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
750 break;
751 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
752 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
753 record;
754 router.cd_valid = true;
755 router.cd_mux_type = cd_path->ucMuxType;
756 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
757 router.cd_mux_state = cd_path->ucMuxState[enum_id];
758 break;
759 }
760 record = (ATOM_COMMON_RECORD_HEADER *)
761 ((char *)record + record->ucRecordSize);
762 }
763 }
764 }
765 }
766 }
767
768 /* look up gpio for ddc, hpd */
769 ddc_bus.valid = false;
770 hpd.hpd = RADEON_HPD_NONE;
771 if ((le16_to_cpu(path->usDeviceTag) &
772 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
773 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
774 if (le16_to_cpu(path->usConnObjectId) ==
775 le16_to_cpu(con_obj->asObjects[j].
776 usObjectID)) {
777 ATOM_COMMON_RECORD_HEADER
778 *record =
779 (ATOM_COMMON_RECORD_HEADER
780 *)
781 (ctx->bios + data_offset +
782 le16_to_cpu(con_obj->
783 asObjects[j].
784 usRecordOffset));
785 ATOM_I2C_RECORD *i2c_record;
786 ATOM_HPD_INT_RECORD *hpd_record;
787 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
788
789 while (record->ucRecordType > 0
790 && record->
791 ucRecordType <=
792 ATOM_MAX_OBJECT_RECORD_NUMBER) {
793 switch (record->ucRecordType) {
794 case ATOM_I2C_RECORD_TYPE:
795 i2c_record =
796 (ATOM_I2C_RECORD *)
797 record;
798 i2c_config =
799 (ATOM_I2C_ID_CONFIG_ACCESS *)
800 &i2c_record->sucI2cId;
801 ddc_bus = radeon_lookup_i2c_gpio(rdev,
802 i2c_config->
803 ucAccess);
804 break;
805 case ATOM_HPD_INT_RECORD_TYPE:
806 hpd_record =
807 (ATOM_HPD_INT_RECORD *)
808 record;
809 gpio = radeon_lookup_gpio(rdev,
810 hpd_record->ucHPDIntGPIOID);
811 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
812 hpd.plugged_state = hpd_record->ucPlugged_PinState;
813 break;
814 }
815 record =
816 (ATOM_COMMON_RECORD_HEADER
817 *) ((char *)record
818 +
819 record->
820 ucRecordSize);
821 }
822 break;
823 }
824 }
825 }
826
827 /* needed for aux chan transactions */
828 ddc_bus.hpd = hpd.hpd;
829
830 conn_id = le16_to_cpu(path->usConnObjectId);
831
832 if (!radeon_atom_apply_quirks
833 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
834 &ddc_bus, &conn_id, &hpd))
835 continue;
836
837 radeon_add_atom_connector(dev,
838 conn_id,
839 le16_to_cpu(path->
840 usDeviceTag),
841 connector_type, &ddc_bus,
842 igp_lane_info,
843 connector_object_id,
844 &hpd,
845 &router);
846
847 }
848 }
849
850 radeon_link_encoder_connector(dev);
851
852 return true;
853 }
854
855 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
856 int connector_type,
857 uint16_t devices)
858 {
859 struct radeon_device *rdev = dev->dev_private;
860
861 if (rdev->flags & RADEON_IS_IGP) {
862 return supported_devices_connector_object_id_convert
863 [connector_type];
864 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
865 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
866 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
867 struct radeon_mode_info *mode_info = &rdev->mode_info;
868 struct atom_context *ctx = mode_info->atom_context;
869 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
870 uint16_t size, data_offset;
871 uint8_t frev, crev;
872 ATOM_XTMDS_INFO *xtmds;
873
874 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
875 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
876
877 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
878 if (connector_type == DRM_MODE_CONNECTOR_DVII)
879 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
880 else
881 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
882 } else {
883 if (connector_type == DRM_MODE_CONNECTOR_DVII)
884 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
885 else
886 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
887 }
888 } else
889 return supported_devices_connector_object_id_convert
890 [connector_type];
891 } else {
892 return supported_devices_connector_object_id_convert
893 [connector_type];
894 }
895 }
896
897 struct bios_connector {
898 bool valid;
899 uint16_t line_mux;
900 uint16_t devices;
901 int connector_type;
902 struct radeon_i2c_bus_rec ddc_bus;
903 struct radeon_hpd hpd;
904 };
905
906 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
907 drm_device
908 *dev)
909 {
910 struct radeon_device *rdev = dev->dev_private;
911 struct radeon_mode_info *mode_info = &rdev->mode_info;
912 struct atom_context *ctx = mode_info->atom_context;
913 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
914 uint16_t size, data_offset;
915 uint8_t frev, crev;
916 uint16_t device_support;
917 uint8_t dac;
918 union atom_supported_devices *supported_devices;
919 int i, j, max_device;
920 struct bios_connector *bios_connectors;
921 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
922 struct radeon_router router;
923
924 router.ddc_valid = false;
925 router.cd_valid = false;
926
927 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
928 if (!bios_connectors)
929 return false;
930
931 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
932 &data_offset)) {
933 kfree(bios_connectors);
934 return false;
935 }
936
937 supported_devices =
938 (union atom_supported_devices *)(ctx->bios + data_offset);
939
940 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
941
942 if (frev > 1)
943 max_device = ATOM_MAX_SUPPORTED_DEVICE;
944 else
945 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
946
947 for (i = 0; i < max_device; i++) {
948 ATOM_CONNECTOR_INFO_I2C ci =
949 supported_devices->info.asConnInfo[i];
950
951 bios_connectors[i].valid = false;
952
953 if (!(device_support & (1 << i))) {
954 continue;
955 }
956
957 if (i == ATOM_DEVICE_CV_INDEX) {
958 DRM_DEBUG_KMS("Skipping Component Video\n");
959 continue;
960 }
961
962 bios_connectors[i].connector_type =
963 supported_devices_connector_convert[ci.sucConnectorInfo.
964 sbfAccess.
965 bfConnectorType];
966
967 if (bios_connectors[i].connector_type ==
968 DRM_MODE_CONNECTOR_Unknown)
969 continue;
970
971 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
972
973 bios_connectors[i].line_mux =
974 ci.sucI2cId.ucAccess;
975
976 /* give tv unique connector ids */
977 if (i == ATOM_DEVICE_TV1_INDEX) {
978 bios_connectors[i].ddc_bus.valid = false;
979 bios_connectors[i].line_mux = 50;
980 } else if (i == ATOM_DEVICE_TV2_INDEX) {
981 bios_connectors[i].ddc_bus.valid = false;
982 bios_connectors[i].line_mux = 51;
983 } else if (i == ATOM_DEVICE_CV_INDEX) {
984 bios_connectors[i].ddc_bus.valid = false;
985 bios_connectors[i].line_mux = 52;
986 } else
987 bios_connectors[i].ddc_bus =
988 radeon_lookup_i2c_gpio(rdev,
989 bios_connectors[i].line_mux);
990
991 if ((crev > 1) && (frev > 1)) {
992 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
993 switch (isb) {
994 case 0x4:
995 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
996 break;
997 case 0xa:
998 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
999 break;
1000 default:
1001 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1002 break;
1003 }
1004 } else {
1005 if (i == ATOM_DEVICE_DFP1_INDEX)
1006 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1007 else if (i == ATOM_DEVICE_DFP2_INDEX)
1008 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1009 else
1010 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1011 }
1012
1013 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1014 * shared with a DVI port, we'll pick up the DVI connector when we
1015 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1016 */
1017 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1018 bios_connectors[i].connector_type =
1019 DRM_MODE_CONNECTOR_VGA;
1020
1021 if (!radeon_atom_apply_quirks
1022 (dev, (1 << i), &bios_connectors[i].connector_type,
1023 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1024 &bios_connectors[i].hpd))
1025 continue;
1026
1027 bios_connectors[i].valid = true;
1028 bios_connectors[i].devices = (1 << i);
1029
1030 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1031 radeon_add_atom_encoder(dev,
1032 radeon_get_encoder_enum(dev,
1033 (1 << i),
1034 dac),
1035 (1 << i),
1036 0);
1037 else
1038 radeon_add_legacy_encoder(dev,
1039 radeon_get_encoder_enum(dev,
1040 (1 << i),
1041 dac),
1042 (1 << i));
1043 }
1044
1045 /* combine shared connectors */
1046 for (i = 0; i < max_device; i++) {
1047 if (bios_connectors[i].valid) {
1048 for (j = 0; j < max_device; j++) {
1049 if (bios_connectors[j].valid && (i != j)) {
1050 if (bios_connectors[i].line_mux ==
1051 bios_connectors[j].line_mux) {
1052 /* make sure not to combine LVDS */
1053 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1054 bios_connectors[i].line_mux = 53;
1055 bios_connectors[i].ddc_bus.valid = false;
1056 continue;
1057 }
1058 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1059 bios_connectors[j].line_mux = 53;
1060 bios_connectors[j].ddc_bus.valid = false;
1061 continue;
1062 }
1063 /* combine analog and digital for DVI-I */
1064 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1065 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1066 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1067 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1068 bios_connectors[i].devices |=
1069 bios_connectors[j].devices;
1070 bios_connectors[i].connector_type =
1071 DRM_MODE_CONNECTOR_DVII;
1072 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1073 bios_connectors[i].hpd =
1074 bios_connectors[j].hpd;
1075 bios_connectors[j].valid = false;
1076 }
1077 }
1078 }
1079 }
1080 }
1081 }
1082
1083 /* add the connectors */
1084 for (i = 0; i < max_device; i++) {
1085 if (bios_connectors[i].valid) {
1086 uint16_t connector_object_id =
1087 atombios_get_connector_object_id(dev,
1088 bios_connectors[i].connector_type,
1089 bios_connectors[i].devices);
1090 radeon_add_atom_connector(dev,
1091 bios_connectors[i].line_mux,
1092 bios_connectors[i].devices,
1093 bios_connectors[i].
1094 connector_type,
1095 &bios_connectors[i].ddc_bus,
1096 0,
1097 connector_object_id,
1098 &bios_connectors[i].hpd,
1099 &router);
1100 }
1101 }
1102
1103 radeon_link_encoder_connector(dev);
1104
1105 kfree(bios_connectors);
1106 return true;
1107 }
1108
1109 union firmware_info {
1110 ATOM_FIRMWARE_INFO info;
1111 ATOM_FIRMWARE_INFO_V1_2 info_12;
1112 ATOM_FIRMWARE_INFO_V1_3 info_13;
1113 ATOM_FIRMWARE_INFO_V1_4 info_14;
1114 ATOM_FIRMWARE_INFO_V2_1 info_21;
1115 ATOM_FIRMWARE_INFO_V2_2 info_22;
1116 };
1117
1118 bool radeon_atom_get_clock_info(struct drm_device *dev)
1119 {
1120 struct radeon_device *rdev = dev->dev_private;
1121 struct radeon_mode_info *mode_info = &rdev->mode_info;
1122 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1123 union firmware_info *firmware_info;
1124 uint8_t frev, crev;
1125 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1126 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1127 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1128 struct radeon_pll *spll = &rdev->clock.spll;
1129 struct radeon_pll *mpll = &rdev->clock.mpll;
1130 uint16_t data_offset;
1131
1132 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1133 &frev, &crev, &data_offset)) {
1134 firmware_info =
1135 (union firmware_info *)(mode_info->atom_context->bios +
1136 data_offset);
1137 /* pixel clocks */
1138 p1pll->reference_freq =
1139 le16_to_cpu(firmware_info->info.usReferenceClock);
1140 p1pll->reference_div = 0;
1141
1142 if (crev < 2)
1143 p1pll->pll_out_min =
1144 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1145 else
1146 p1pll->pll_out_min =
1147 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1148 p1pll->pll_out_max =
1149 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1150
1151 if (crev >= 4) {
1152 p1pll->lcd_pll_out_min =
1153 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1154 if (p1pll->lcd_pll_out_min == 0)
1155 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1156 p1pll->lcd_pll_out_max =
1157 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1158 if (p1pll->lcd_pll_out_max == 0)
1159 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1160 } else {
1161 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1162 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1163 }
1164
1165 if (p1pll->pll_out_min == 0) {
1166 if (ASIC_IS_AVIVO(rdev))
1167 p1pll->pll_out_min = 64800;
1168 else
1169 p1pll->pll_out_min = 20000;
1170 } else if (p1pll->pll_out_min > 64800) {
1171 /* Limiting the pll output range is a good thing generally as
1172 * it limits the number of possible pll combinations for a given
1173 * frequency presumably to the ones that work best on each card.
1174 * However, certain duallink DVI monitors seem to like
1175 * pll combinations that would be limited by this at least on
1176 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1177 * family.
1178 */
1179 p1pll->pll_out_min = 64800;
1180 }
1181
1182 p1pll->pll_in_min =
1183 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1184 p1pll->pll_in_max =
1185 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1186
1187 *p2pll = *p1pll;
1188
1189 /* system clock */
1190 if (ASIC_IS_DCE4(rdev))
1191 spll->reference_freq =
1192 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1193 else
1194 spll->reference_freq =
1195 le16_to_cpu(firmware_info->info.usReferenceClock);
1196 spll->reference_div = 0;
1197
1198 spll->pll_out_min =
1199 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1200 spll->pll_out_max =
1201 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1202
1203 /* ??? */
1204 if (spll->pll_out_min == 0) {
1205 if (ASIC_IS_AVIVO(rdev))
1206 spll->pll_out_min = 64800;
1207 else
1208 spll->pll_out_min = 20000;
1209 }
1210
1211 spll->pll_in_min =
1212 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1213 spll->pll_in_max =
1214 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1215
1216 /* memory clock */
1217 if (ASIC_IS_DCE4(rdev))
1218 mpll->reference_freq =
1219 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1220 else
1221 mpll->reference_freq =
1222 le16_to_cpu(firmware_info->info.usReferenceClock);
1223 mpll->reference_div = 0;
1224
1225 mpll->pll_out_min =
1226 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1227 mpll->pll_out_max =
1228 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1229
1230 /* ??? */
1231 if (mpll->pll_out_min == 0) {
1232 if (ASIC_IS_AVIVO(rdev))
1233 mpll->pll_out_min = 64800;
1234 else
1235 mpll->pll_out_min = 20000;
1236 }
1237
1238 mpll->pll_in_min =
1239 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1240 mpll->pll_in_max =
1241 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1242
1243 rdev->clock.default_sclk =
1244 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1245 rdev->clock.default_mclk =
1246 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1247
1248 if (ASIC_IS_DCE4(rdev)) {
1249 rdev->clock.default_dispclk =
1250 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1251 if (rdev->clock.default_dispclk == 0) {
1252 if (ASIC_IS_DCE5(rdev))
1253 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1254 else
1255 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1256 }
1257 rdev->clock.dp_extclk =
1258 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1259 }
1260 *dcpll = *p1pll;
1261
1262 return true;
1263 }
1264
1265 return false;
1266 }
1267
1268 union igp_info {
1269 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1270 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1271 };
1272
1273 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1274 {
1275 struct radeon_mode_info *mode_info = &rdev->mode_info;
1276 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1277 union igp_info *igp_info;
1278 u8 frev, crev;
1279 u16 data_offset;
1280
1281 /* sideport is AMD only */
1282 if (rdev->family == CHIP_RS600)
1283 return false;
1284
1285 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1286 &frev, &crev, &data_offset)) {
1287 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1288 data_offset);
1289 switch (crev) {
1290 case 1:
1291 if (igp_info->info.ulBootUpMemoryClock)
1292 return true;
1293 break;
1294 case 2:
1295 if (igp_info->info_2.ulBootUpSidePortClock)
1296 return true;
1297 break;
1298 default:
1299 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1300 break;
1301 }
1302 }
1303 return false;
1304 }
1305
1306 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1307 struct radeon_encoder_int_tmds *tmds)
1308 {
1309 struct drm_device *dev = encoder->base.dev;
1310 struct radeon_device *rdev = dev->dev_private;
1311 struct radeon_mode_info *mode_info = &rdev->mode_info;
1312 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1313 uint16_t data_offset;
1314 struct _ATOM_TMDS_INFO *tmds_info;
1315 uint8_t frev, crev;
1316 uint16_t maxfreq;
1317 int i;
1318
1319 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1320 &frev, &crev, &data_offset)) {
1321 tmds_info =
1322 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1323 data_offset);
1324
1325 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1326 for (i = 0; i < 4; i++) {
1327 tmds->tmds_pll[i].freq =
1328 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1329 tmds->tmds_pll[i].value =
1330 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1331 tmds->tmds_pll[i].value |=
1332 (tmds_info->asMiscInfo[i].
1333 ucPLL_VCO_Gain & 0x3f) << 6;
1334 tmds->tmds_pll[i].value |=
1335 (tmds_info->asMiscInfo[i].
1336 ucPLL_DutyCycle & 0xf) << 12;
1337 tmds->tmds_pll[i].value |=
1338 (tmds_info->asMiscInfo[i].
1339 ucPLL_VoltageSwing & 0xf) << 16;
1340
1341 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1342 tmds->tmds_pll[i].freq,
1343 tmds->tmds_pll[i].value);
1344
1345 if (maxfreq == tmds->tmds_pll[i].freq) {
1346 tmds->tmds_pll[i].freq = 0xffffffff;
1347 break;
1348 }
1349 }
1350 return true;
1351 }
1352 return false;
1353 }
1354
1355 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1356 struct radeon_atom_ss *ss,
1357 int id)
1358 {
1359 struct radeon_mode_info *mode_info = &rdev->mode_info;
1360 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1361 uint16_t data_offset, size;
1362 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1363 uint8_t frev, crev;
1364 int i, num_indices;
1365
1366 memset(ss, 0, sizeof(struct radeon_atom_ss));
1367 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1368 &frev, &crev, &data_offset)) {
1369 ss_info =
1370 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1371
1372 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1373 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1374
1375 for (i = 0; i < num_indices; i++) {
1376 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1377 ss->percentage =
1378 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1379 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1380 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1381 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1382 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1383 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1384 return true;
1385 }
1386 }
1387 }
1388 return false;
1389 }
1390
1391 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1392 struct radeon_atom_ss *ss,
1393 int id)
1394 {
1395 struct radeon_mode_info *mode_info = &rdev->mode_info;
1396 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1397 u16 data_offset, size;
1398 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1399 u8 frev, crev;
1400 u16 percentage = 0, rate = 0;
1401
1402 /* get any igp specific overrides */
1403 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1404 &frev, &crev, &data_offset)) {
1405 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1406 (mode_info->atom_context->bios + data_offset);
1407 switch (id) {
1408 case ASIC_INTERNAL_SS_ON_TMDS:
1409 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1410 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1411 break;
1412 case ASIC_INTERNAL_SS_ON_HDMI:
1413 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1414 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1415 break;
1416 case ASIC_INTERNAL_SS_ON_LVDS:
1417 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1418 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1419 break;
1420 }
1421 if (percentage)
1422 ss->percentage = percentage;
1423 if (rate)
1424 ss->rate = rate;
1425 }
1426 }
1427
1428 union asic_ss_info {
1429 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1430 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1431 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1432 };
1433
1434 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1435 struct radeon_atom_ss *ss,
1436 int id, u32 clock)
1437 {
1438 struct radeon_mode_info *mode_info = &rdev->mode_info;
1439 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1440 uint16_t data_offset, size;
1441 union asic_ss_info *ss_info;
1442 uint8_t frev, crev;
1443 int i, num_indices;
1444
1445 memset(ss, 0, sizeof(struct radeon_atom_ss));
1446 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1447 &frev, &crev, &data_offset)) {
1448
1449 ss_info =
1450 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1451
1452 switch (frev) {
1453 case 1:
1454 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1455 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1456
1457 for (i = 0; i < num_indices; i++) {
1458 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1459 (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) {
1460 ss->percentage =
1461 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1462 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1463 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1464 return true;
1465 }
1466 }
1467 break;
1468 case 2:
1469 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1470 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1471 for (i = 0; i < num_indices; i++) {
1472 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1473 (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) {
1474 ss->percentage =
1475 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1476 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1477 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1478 return true;
1479 }
1480 }
1481 break;
1482 case 3:
1483 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1484 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1485 for (i = 0; i < num_indices; i++) {
1486 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1487 (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) {
1488 ss->percentage =
1489 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1490 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1491 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1492 if (rdev->flags & RADEON_IS_IGP)
1493 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1494 return true;
1495 }
1496 }
1497 break;
1498 default:
1499 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1500 break;
1501 }
1502
1503 }
1504 return false;
1505 }
1506
1507 union lvds_info {
1508 struct _ATOM_LVDS_INFO info;
1509 struct _ATOM_LVDS_INFO_V12 info_12;
1510 };
1511
1512 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1513 radeon_encoder
1514 *encoder)
1515 {
1516 struct drm_device *dev = encoder->base.dev;
1517 struct radeon_device *rdev = dev->dev_private;
1518 struct radeon_mode_info *mode_info = &rdev->mode_info;
1519 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1520 uint16_t data_offset, misc;
1521 union lvds_info *lvds_info;
1522 uint8_t frev, crev;
1523 struct radeon_encoder_atom_dig *lvds = NULL;
1524 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1525
1526 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1527 &frev, &crev, &data_offset)) {
1528 lvds_info =
1529 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1530 lvds =
1531 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1532
1533 if (!lvds)
1534 return NULL;
1535
1536 lvds->native_mode.clock =
1537 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1538 lvds->native_mode.hdisplay =
1539 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1540 lvds->native_mode.vdisplay =
1541 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1542 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1543 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1544 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1545 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1546 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1547 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1548 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1549 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1550 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1551 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1552 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1553 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1554 lvds->panel_pwr_delay =
1555 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1556 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1557
1558 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1559 if (misc & ATOM_VSYNC_POLARITY)
1560 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1561 if (misc & ATOM_HSYNC_POLARITY)
1562 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1563 if (misc & ATOM_COMPOSITESYNC)
1564 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1565 if (misc & ATOM_INTERLACE)
1566 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1567 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1568 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1569
1570 lvds->native_mode.width_mm = lvds_info->info.sLCDTiming.usImageHSize;
1571 lvds->native_mode.height_mm = lvds_info->info.sLCDTiming.usImageVSize;
1572
1573 /* set crtc values */
1574 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1575
1576 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1577
1578 encoder->native_mode = lvds->native_mode;
1579
1580 if (encoder_enum == 2)
1581 lvds->linkb = true;
1582 else
1583 lvds->linkb = false;
1584
1585 /* parse the lcd record table */
1586 if (lvds_info->info.usModePatchTableOffset) {
1587 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1588 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1589 bool bad_record = false;
1590 u8 *record = (u8 *)(mode_info->atom_context->bios +
1591 data_offset +
1592 lvds_info->info.usModePatchTableOffset);
1593 while (*record != ATOM_RECORD_END_TYPE) {
1594 switch (*record) {
1595 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1596 record += sizeof(ATOM_PATCH_RECORD_MODE);
1597 break;
1598 case LCD_RTS_RECORD_TYPE:
1599 record += sizeof(ATOM_LCD_RTS_RECORD);
1600 break;
1601 case LCD_CAP_RECORD_TYPE:
1602 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1603 break;
1604 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1605 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1606 if (fake_edid_record->ucFakeEDIDLength) {
1607 struct edid *edid;
1608 int edid_size =
1609 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1610 edid = kmalloc(edid_size, GFP_KERNEL);
1611 if (edid) {
1612 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1613 fake_edid_record->ucFakeEDIDLength);
1614
1615 if (drm_edid_is_valid(edid))
1616 rdev->mode_info.bios_hardcoded_edid = edid;
1617 else
1618 kfree(edid);
1619 }
1620 }
1621 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1622 break;
1623 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1624 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1625 lvds->native_mode.width_mm = panel_res_record->usHSize;
1626 lvds->native_mode.height_mm = panel_res_record->usVSize;
1627 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1628 break;
1629 default:
1630 DRM_ERROR("Bad LCD record %d\n", *record);
1631 bad_record = true;
1632 break;
1633 }
1634 if (bad_record)
1635 break;
1636 }
1637 }
1638 }
1639 return lvds;
1640 }
1641
1642 struct radeon_encoder_primary_dac *
1643 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1644 {
1645 struct drm_device *dev = encoder->base.dev;
1646 struct radeon_device *rdev = dev->dev_private;
1647 struct radeon_mode_info *mode_info = &rdev->mode_info;
1648 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1649 uint16_t data_offset;
1650 struct _COMPASSIONATE_DATA *dac_info;
1651 uint8_t frev, crev;
1652 uint8_t bg, dac;
1653 struct radeon_encoder_primary_dac *p_dac = NULL;
1654
1655 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1656 &frev, &crev, &data_offset)) {
1657 dac_info = (struct _COMPASSIONATE_DATA *)
1658 (mode_info->atom_context->bios + data_offset);
1659
1660 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1661
1662 if (!p_dac)
1663 return NULL;
1664
1665 bg = dac_info->ucDAC1_BG_Adjustment;
1666 dac = dac_info->ucDAC1_DAC_Adjustment;
1667 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1668
1669 }
1670 return p_dac;
1671 }
1672
1673 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1674 struct drm_display_mode *mode)
1675 {
1676 struct radeon_mode_info *mode_info = &rdev->mode_info;
1677 ATOM_ANALOG_TV_INFO *tv_info;
1678 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1679 ATOM_DTD_FORMAT *dtd_timings;
1680 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1681 u8 frev, crev;
1682 u16 data_offset, misc;
1683
1684 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1685 &frev, &crev, &data_offset))
1686 return false;
1687
1688 switch (crev) {
1689 case 1:
1690 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1691 if (index >= MAX_SUPPORTED_TV_TIMING)
1692 return false;
1693
1694 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1695 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1696 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1697 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1698 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1699
1700 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1701 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1702 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1703 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1704 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1705
1706 mode->flags = 0;
1707 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1708 if (misc & ATOM_VSYNC_POLARITY)
1709 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1710 if (misc & ATOM_HSYNC_POLARITY)
1711 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1712 if (misc & ATOM_COMPOSITESYNC)
1713 mode->flags |= DRM_MODE_FLAG_CSYNC;
1714 if (misc & ATOM_INTERLACE)
1715 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1716 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1717 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1718
1719 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1720
1721 if (index == 1) {
1722 /* PAL timings appear to have wrong values for totals */
1723 mode->crtc_htotal -= 1;
1724 mode->crtc_vtotal -= 1;
1725 }
1726 break;
1727 case 2:
1728 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1729 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1730 return false;
1731
1732 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1733 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1734 le16_to_cpu(dtd_timings->usHBlanking_Time);
1735 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1736 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1737 le16_to_cpu(dtd_timings->usHSyncOffset);
1738 mode->crtc_hsync_end = mode->crtc_hsync_start +
1739 le16_to_cpu(dtd_timings->usHSyncWidth);
1740
1741 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1742 le16_to_cpu(dtd_timings->usVBlanking_Time);
1743 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1744 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1745 le16_to_cpu(dtd_timings->usVSyncOffset);
1746 mode->crtc_vsync_end = mode->crtc_vsync_start +
1747 le16_to_cpu(dtd_timings->usVSyncWidth);
1748
1749 mode->flags = 0;
1750 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1751 if (misc & ATOM_VSYNC_POLARITY)
1752 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1753 if (misc & ATOM_HSYNC_POLARITY)
1754 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1755 if (misc & ATOM_COMPOSITESYNC)
1756 mode->flags |= DRM_MODE_FLAG_CSYNC;
1757 if (misc & ATOM_INTERLACE)
1758 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1759 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1760 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1761
1762 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1763 break;
1764 }
1765 return true;
1766 }
1767
1768 enum radeon_tv_std
1769 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1770 {
1771 struct radeon_mode_info *mode_info = &rdev->mode_info;
1772 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1773 uint16_t data_offset;
1774 uint8_t frev, crev;
1775 struct _ATOM_ANALOG_TV_INFO *tv_info;
1776 enum radeon_tv_std tv_std = TV_STD_NTSC;
1777
1778 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1779 &frev, &crev, &data_offset)) {
1780
1781 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1782 (mode_info->atom_context->bios + data_offset);
1783
1784 switch (tv_info->ucTV_BootUpDefaultStandard) {
1785 case ATOM_TV_NTSC:
1786 tv_std = TV_STD_NTSC;
1787 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1788 break;
1789 case ATOM_TV_NTSCJ:
1790 tv_std = TV_STD_NTSC_J;
1791 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1792 break;
1793 case ATOM_TV_PAL:
1794 tv_std = TV_STD_PAL;
1795 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1796 break;
1797 case ATOM_TV_PALM:
1798 tv_std = TV_STD_PAL_M;
1799 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1800 break;
1801 case ATOM_TV_PALN:
1802 tv_std = TV_STD_PAL_N;
1803 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1804 break;
1805 case ATOM_TV_PALCN:
1806 tv_std = TV_STD_PAL_CN;
1807 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1808 break;
1809 case ATOM_TV_PAL60:
1810 tv_std = TV_STD_PAL_60;
1811 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1812 break;
1813 case ATOM_TV_SECAM:
1814 tv_std = TV_STD_SECAM;
1815 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1816 break;
1817 default:
1818 tv_std = TV_STD_NTSC;
1819 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1820 break;
1821 }
1822 }
1823 return tv_std;
1824 }
1825
1826 struct radeon_encoder_tv_dac *
1827 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1828 {
1829 struct drm_device *dev = encoder->base.dev;
1830 struct radeon_device *rdev = dev->dev_private;
1831 struct radeon_mode_info *mode_info = &rdev->mode_info;
1832 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1833 uint16_t data_offset;
1834 struct _COMPASSIONATE_DATA *dac_info;
1835 uint8_t frev, crev;
1836 uint8_t bg, dac;
1837 struct radeon_encoder_tv_dac *tv_dac = NULL;
1838
1839 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1840 &frev, &crev, &data_offset)) {
1841
1842 dac_info = (struct _COMPASSIONATE_DATA *)
1843 (mode_info->atom_context->bios + data_offset);
1844
1845 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1846
1847 if (!tv_dac)
1848 return NULL;
1849
1850 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1851 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1852 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1853
1854 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1855 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1856 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1857
1858 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1859 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1860 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1861
1862 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1863 }
1864 return tv_dac;
1865 }
1866
1867 static const char *thermal_controller_names[] = {
1868 "NONE",
1869 "lm63",
1870 "adm1032",
1871 "adm1030",
1872 "max6649",
1873 "lm64",
1874 "f75375",
1875 "asc7xxx",
1876 };
1877
1878 static const char *pp_lib_thermal_controller_names[] = {
1879 "NONE",
1880 "lm63",
1881 "adm1032",
1882 "adm1030",
1883 "max6649",
1884 "lm64",
1885 "f75375",
1886 "RV6xx",
1887 "RV770",
1888 "adt7473",
1889 "NONE",
1890 "External GPIO",
1891 "Evergreen",
1892 "emc2103",
1893 "Sumo",
1894 "Northern Islands",
1895 };
1896
1897 union power_info {
1898 struct _ATOM_POWERPLAY_INFO info;
1899 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1900 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1901 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1902 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1903 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1904 };
1905
1906 union pplib_clock_info {
1907 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1908 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1909 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1910 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1911 };
1912
1913 union pplib_power_state {
1914 struct _ATOM_PPLIB_STATE v1;
1915 struct _ATOM_PPLIB_STATE_V2 v2;
1916 };
1917
1918 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1919 int state_index,
1920 u32 misc, u32 misc2)
1921 {
1922 rdev->pm.power_state[state_index].misc = misc;
1923 rdev->pm.power_state[state_index].misc2 = misc2;
1924 /* order matters! */
1925 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1926 rdev->pm.power_state[state_index].type =
1927 POWER_STATE_TYPE_POWERSAVE;
1928 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1929 rdev->pm.power_state[state_index].type =
1930 POWER_STATE_TYPE_BATTERY;
1931 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1932 rdev->pm.power_state[state_index].type =
1933 POWER_STATE_TYPE_BATTERY;
1934 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1935 rdev->pm.power_state[state_index].type =
1936 POWER_STATE_TYPE_BALANCED;
1937 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1938 rdev->pm.power_state[state_index].type =
1939 POWER_STATE_TYPE_PERFORMANCE;
1940 rdev->pm.power_state[state_index].flags &=
1941 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1942 }
1943 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1944 rdev->pm.power_state[state_index].type =
1945 POWER_STATE_TYPE_BALANCED;
1946 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1947 rdev->pm.power_state[state_index].type =
1948 POWER_STATE_TYPE_DEFAULT;
1949 rdev->pm.default_power_state_index = state_index;
1950 rdev->pm.power_state[state_index].default_clock_mode =
1951 &rdev->pm.power_state[state_index].clock_info[0];
1952 } else if (state_index == 0) {
1953 rdev->pm.power_state[state_index].clock_info[0].flags |=
1954 RADEON_PM_MODE_NO_DISPLAY;
1955 }
1956 }
1957
1958 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1959 {
1960 struct radeon_mode_info *mode_info = &rdev->mode_info;
1961 u32 misc, misc2 = 0;
1962 int num_modes = 0, i;
1963 int state_index = 0;
1964 struct radeon_i2c_bus_rec i2c_bus;
1965 union power_info *power_info;
1966 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1967 u16 data_offset;
1968 u8 frev, crev;
1969
1970 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1971 &frev, &crev, &data_offset))
1972 return state_index;
1973 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1974
1975 /* add the i2c bus for thermal/fan chip */
1976 if (power_info->info.ucOverdriveThermalController > 0) {
1977 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1978 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1979 power_info->info.ucOverdriveControllerAddress >> 1);
1980 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1981 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1982 if (rdev->pm.i2c_bus) {
1983 struct i2c_board_info info = { };
1984 const char *name = thermal_controller_names[power_info->info.
1985 ucOverdriveThermalController];
1986 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1987 strlcpy(info.type, name, sizeof(info.type));
1988 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1989 }
1990 }
1991 num_modes = power_info->info.ucNumOfPowerModeEntries;
1992 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1993 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1994 /* last mode is usually default, array is low to high */
1995 for (i = 0; i < num_modes; i++) {
1996 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1997 switch (frev) {
1998 case 1:
1999 rdev->pm.power_state[state_index].num_clock_modes = 1;
2000 rdev->pm.power_state[state_index].clock_info[0].mclk =
2001 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2002 rdev->pm.power_state[state_index].clock_info[0].sclk =
2003 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2004 /* skip invalid modes */
2005 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2006 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2007 continue;
2008 rdev->pm.power_state[state_index].pcie_lanes =
2009 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2010 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2011 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2012 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2013 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2014 VOLTAGE_GPIO;
2015 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2016 radeon_lookup_gpio(rdev,
2017 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2018 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2019 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2020 true;
2021 else
2022 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2023 false;
2024 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2025 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2026 VOLTAGE_VDDC;
2027 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2028 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2029 }
2030 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2031 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2032 state_index++;
2033 break;
2034 case 2:
2035 rdev->pm.power_state[state_index].num_clock_modes = 1;
2036 rdev->pm.power_state[state_index].clock_info[0].mclk =
2037 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2038 rdev->pm.power_state[state_index].clock_info[0].sclk =
2039 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2040 /* skip invalid modes */
2041 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2042 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2043 continue;
2044 rdev->pm.power_state[state_index].pcie_lanes =
2045 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2046 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2047 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2048 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2049 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2050 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2051 VOLTAGE_GPIO;
2052 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2053 radeon_lookup_gpio(rdev,
2054 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2055 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2056 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2057 true;
2058 else
2059 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2060 false;
2061 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2062 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2063 VOLTAGE_VDDC;
2064 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2065 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2066 }
2067 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2068 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2069 state_index++;
2070 break;
2071 case 3:
2072 rdev->pm.power_state[state_index].num_clock_modes = 1;
2073 rdev->pm.power_state[state_index].clock_info[0].mclk =
2074 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2075 rdev->pm.power_state[state_index].clock_info[0].sclk =
2076 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2077 /* skip invalid modes */
2078 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2079 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2080 continue;
2081 rdev->pm.power_state[state_index].pcie_lanes =
2082 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2083 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2084 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2085 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2086 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2087 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2088 VOLTAGE_GPIO;
2089 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2090 radeon_lookup_gpio(rdev,
2091 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2092 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2093 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2094 true;
2095 else
2096 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2097 false;
2098 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2099 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2100 VOLTAGE_VDDC;
2101 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2102 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2103 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2104 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2105 true;
2106 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2107 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2108 }
2109 }
2110 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2111 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2112 state_index++;
2113 break;
2114 }
2115 }
2116 /* last mode is usually default */
2117 if (rdev->pm.default_power_state_index == -1) {
2118 rdev->pm.power_state[state_index - 1].type =
2119 POWER_STATE_TYPE_DEFAULT;
2120 rdev->pm.default_power_state_index = state_index - 1;
2121 rdev->pm.power_state[state_index - 1].default_clock_mode =
2122 &rdev->pm.power_state[state_index - 1].clock_info[0];
2123 rdev->pm.power_state[state_index].flags &=
2124 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2125 rdev->pm.power_state[state_index].misc = 0;
2126 rdev->pm.power_state[state_index].misc2 = 0;
2127 }
2128 return state_index;
2129 }
2130
2131 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2132 ATOM_PPLIB_THERMALCONTROLLER *controller)
2133 {
2134 struct radeon_i2c_bus_rec i2c_bus;
2135
2136 /* add the i2c bus for thermal/fan chip */
2137 if (controller->ucType > 0) {
2138 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2139 DRM_INFO("Internal thermal controller %s fan control\n",
2140 (controller->ucFanParameters &
2141 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2142 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2143 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2144 DRM_INFO("Internal thermal controller %s fan control\n",
2145 (controller->ucFanParameters &
2146 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2147 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2148 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2149 DRM_INFO("Internal thermal controller %s fan control\n",
2150 (controller->ucFanParameters &
2151 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2152 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2153 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2154 DRM_INFO("Internal thermal controller %s fan control\n",
2155 (controller->ucFanParameters &
2156 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2157 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2158 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2159 DRM_INFO("Internal thermal controller %s fan control\n",
2160 (controller->ucFanParameters &
2161 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2162 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2163 } else if ((controller->ucType ==
2164 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2165 (controller->ucType ==
2166 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2167 (controller->ucType ==
2168 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2169 DRM_INFO("Special thermal controller config\n");
2170 } else {
2171 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2172 pp_lib_thermal_controller_names[controller->ucType],
2173 controller->ucI2cAddress >> 1,
2174 (controller->ucFanParameters &
2175 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2176 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2177 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2178 if (rdev->pm.i2c_bus) {
2179 struct i2c_board_info info = { };
2180 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2181 info.addr = controller->ucI2cAddress >> 1;
2182 strlcpy(info.type, name, sizeof(info.type));
2183 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2184 }
2185 }
2186 }
2187 }
2188
2189 static u16 radeon_atombios_get_default_vddc(struct radeon_device *rdev)
2190 {
2191 struct radeon_mode_info *mode_info = &rdev->mode_info;
2192 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2193 u8 frev, crev;
2194 u16 data_offset;
2195 union firmware_info *firmware_info;
2196 u16 vddc = 0;
2197
2198 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2199 &frev, &crev, &data_offset)) {
2200 firmware_info =
2201 (union firmware_info *)(mode_info->atom_context->bios +
2202 data_offset);
2203 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
2204 }
2205
2206 return vddc;
2207 }
2208
2209 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2210 int state_index, int mode_index,
2211 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2212 {
2213 int j;
2214 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2215 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2216 u16 vddc = radeon_atombios_get_default_vddc(rdev);
2217
2218 rdev->pm.power_state[state_index].misc = misc;
2219 rdev->pm.power_state[state_index].misc2 = misc2;
2220 rdev->pm.power_state[state_index].pcie_lanes =
2221 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2222 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2223 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2224 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2225 rdev->pm.power_state[state_index].type =
2226 POWER_STATE_TYPE_BATTERY;
2227 break;
2228 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2229 rdev->pm.power_state[state_index].type =
2230 POWER_STATE_TYPE_BALANCED;
2231 break;
2232 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2233 rdev->pm.power_state[state_index].type =
2234 POWER_STATE_TYPE_PERFORMANCE;
2235 break;
2236 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2237 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2238 rdev->pm.power_state[state_index].type =
2239 POWER_STATE_TYPE_PERFORMANCE;
2240 break;
2241 }
2242 rdev->pm.power_state[state_index].flags = 0;
2243 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2244 rdev->pm.power_state[state_index].flags |=
2245 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2246 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2247 rdev->pm.power_state[state_index].type =
2248 POWER_STATE_TYPE_DEFAULT;
2249 rdev->pm.default_power_state_index = state_index;
2250 rdev->pm.power_state[state_index].default_clock_mode =
2251 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2252 if (ASIC_IS_DCE5(rdev)) {
2253 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2254 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2255 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2256 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2257 } else {
2258 /* patch the table values with the default slck/mclk from firmware info */
2259 for (j = 0; j < mode_index; j++) {
2260 rdev->pm.power_state[state_index].clock_info[j].mclk =
2261 rdev->clock.default_mclk;
2262 rdev->pm.power_state[state_index].clock_info[j].sclk =
2263 rdev->clock.default_sclk;
2264 if (vddc)
2265 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2266 vddc;
2267 }
2268 }
2269 }
2270 }
2271
2272 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2273 int state_index, int mode_index,
2274 union pplib_clock_info *clock_info)
2275 {
2276 u32 sclk, mclk;
2277
2278 if (rdev->flags & RADEON_IS_IGP) {
2279 if (rdev->family >= CHIP_PALM) {
2280 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2281 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2282 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2283 } else {
2284 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2285 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2286 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2287 }
2288 } else if (ASIC_IS_DCE4(rdev)) {
2289 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2290 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2291 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2292 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2293 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2294 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2295 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2296 VOLTAGE_SW;
2297 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2298 clock_info->evergreen.usVDDC;
2299 } else {
2300 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2301 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2302 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2303 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2304 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2305 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2306 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2307 VOLTAGE_SW;
2308 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2309 clock_info->r600.usVDDC;
2310 }
2311
2312 if (rdev->flags & RADEON_IS_IGP) {
2313 /* skip invalid modes */
2314 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2315 return false;
2316 } else {
2317 /* skip invalid modes */
2318 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2319 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2320 return false;
2321 }
2322 return true;
2323 }
2324
2325 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2326 {
2327 struct radeon_mode_info *mode_info = &rdev->mode_info;
2328 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2329 union pplib_power_state *power_state;
2330 int i, j;
2331 int state_index = 0, mode_index = 0;
2332 union pplib_clock_info *clock_info;
2333 bool valid;
2334 union power_info *power_info;
2335 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2336 u16 data_offset;
2337 u8 frev, crev;
2338
2339 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2340 &frev, &crev, &data_offset))
2341 return state_index;
2342 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2343
2344 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2345 /* first mode is usually default, followed by low to high */
2346 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2347 mode_index = 0;
2348 power_state = (union pplib_power_state *)
2349 (mode_info->atom_context->bios + data_offset +
2350 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2351 i * power_info->pplib.ucStateEntrySize);
2352 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2353 (mode_info->atom_context->bios + data_offset +
2354 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2355 (power_state->v1.ucNonClockStateIndex *
2356 power_info->pplib.ucNonClockSize));
2357 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2358 clock_info = (union pplib_clock_info *)
2359 (mode_info->atom_context->bios + data_offset +
2360 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2361 (power_state->v1.ucClockStateIndices[j] *
2362 power_info->pplib.ucClockInfoSize));
2363 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2364 state_index, mode_index,
2365 clock_info);
2366 if (valid)
2367 mode_index++;
2368 }
2369 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2370 if (mode_index) {
2371 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2372 non_clock_info);
2373 state_index++;
2374 }
2375 }
2376 /* if multiple clock modes, mark the lowest as no display */
2377 for (i = 0; i < state_index; i++) {
2378 if (rdev->pm.power_state[i].num_clock_modes > 1)
2379 rdev->pm.power_state[i].clock_info[0].flags |=
2380 RADEON_PM_MODE_NO_DISPLAY;
2381 }
2382 /* first mode is usually default */
2383 if (rdev->pm.default_power_state_index == -1) {
2384 rdev->pm.power_state[0].type =
2385 POWER_STATE_TYPE_DEFAULT;
2386 rdev->pm.default_power_state_index = 0;
2387 rdev->pm.power_state[0].default_clock_mode =
2388 &rdev->pm.power_state[0].clock_info[0];
2389 }
2390 return state_index;
2391 }
2392
2393 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2394 {
2395 struct radeon_mode_info *mode_info = &rdev->mode_info;
2396 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2397 union pplib_power_state *power_state;
2398 int i, j, non_clock_array_index, clock_array_index;
2399 int state_index = 0, mode_index = 0;
2400 union pplib_clock_info *clock_info;
2401 struct StateArray *state_array;
2402 struct ClockInfoArray *clock_info_array;
2403 struct NonClockInfoArray *non_clock_info_array;
2404 bool valid;
2405 union power_info *power_info;
2406 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2407 u16 data_offset;
2408 u8 frev, crev;
2409
2410 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2411 &frev, &crev, &data_offset))
2412 return state_index;
2413 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2414
2415 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2416 state_array = (struct StateArray *)
2417 (mode_info->atom_context->bios + data_offset +
2418 power_info->pplib.usStateArrayOffset);
2419 clock_info_array = (struct ClockInfoArray *)
2420 (mode_info->atom_context->bios + data_offset +
2421 power_info->pplib.usClockInfoArrayOffset);
2422 non_clock_info_array = (struct NonClockInfoArray *)
2423 (mode_info->atom_context->bios + data_offset +
2424 power_info->pplib.usNonClockInfoArrayOffset);
2425 for (i = 0; i < state_array->ucNumEntries; i++) {
2426 mode_index = 0;
2427 power_state = (union pplib_power_state *)&state_array->states[i];
2428 /* XXX this might be an inagua bug... */
2429 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2430 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2431 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2432 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2433 clock_array_index = power_state->v2.clockInfoIndex[j];
2434 /* XXX this might be an inagua bug... */
2435 if (clock_array_index >= clock_info_array->ucNumEntries)
2436 continue;
2437 clock_info = (union pplib_clock_info *)
2438 &clock_info_array->clockInfo[clock_array_index];
2439 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2440 state_index, mode_index,
2441 clock_info);
2442 if (valid)
2443 mode_index++;
2444 }
2445 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2446 if (mode_index) {
2447 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2448 non_clock_info);
2449 state_index++;
2450 }
2451 }
2452 /* if multiple clock modes, mark the lowest as no display */
2453 for (i = 0; i < state_index; i++) {
2454 if (rdev->pm.power_state[i].num_clock_modes > 1)
2455 rdev->pm.power_state[i].clock_info[0].flags |=
2456 RADEON_PM_MODE_NO_DISPLAY;
2457 }
2458 /* first mode is usually default */
2459 if (rdev->pm.default_power_state_index == -1) {
2460 rdev->pm.power_state[0].type =
2461 POWER_STATE_TYPE_DEFAULT;
2462 rdev->pm.default_power_state_index = 0;
2463 rdev->pm.power_state[0].default_clock_mode =
2464 &rdev->pm.power_state[0].clock_info[0];
2465 }
2466 return state_index;
2467 }
2468
2469 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2470 {
2471 struct radeon_mode_info *mode_info = &rdev->mode_info;
2472 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2473 u16 data_offset;
2474 u8 frev, crev;
2475 int state_index = 0;
2476
2477 rdev->pm.default_power_state_index = -1;
2478
2479 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2480 &frev, &crev, &data_offset)) {
2481 switch (frev) {
2482 case 1:
2483 case 2:
2484 case 3:
2485 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2486 break;
2487 case 4:
2488 case 5:
2489 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2490 break;
2491 case 6:
2492 state_index = radeon_atombios_parse_power_table_6(rdev);
2493 break;
2494 default:
2495 break;
2496 }
2497 } else {
2498 /* add the default mode */
2499 rdev->pm.power_state[state_index].type =
2500 POWER_STATE_TYPE_DEFAULT;
2501 rdev->pm.power_state[state_index].num_clock_modes = 1;
2502 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2503 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2504 rdev->pm.power_state[state_index].default_clock_mode =
2505 &rdev->pm.power_state[state_index].clock_info[0];
2506 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2507 rdev->pm.power_state[state_index].pcie_lanes = 16;
2508 rdev->pm.default_power_state_index = state_index;
2509 rdev->pm.power_state[state_index].flags = 0;
2510 state_index++;
2511 }
2512
2513 rdev->pm.num_power_states = state_index;
2514
2515 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2516 rdev->pm.current_clock_mode_index = 0;
2517 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2518 }
2519
2520 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2521 {
2522 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2523 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2524
2525 args.ucEnable = enable;
2526
2527 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2528 }
2529
2530 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2531 {
2532 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2533 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2534
2535 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2536 return args.ulReturnEngineClock;
2537 }
2538
2539 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2540 {
2541 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2542 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2543
2544 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2545 return args.ulReturnMemoryClock;
2546 }
2547
2548 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2549 uint32_t eng_clock)
2550 {
2551 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2552 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2553
2554 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2555
2556 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2557 }
2558
2559 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2560 uint32_t mem_clock)
2561 {
2562 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2563 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2564
2565 if (rdev->flags & RADEON_IS_IGP)
2566 return;
2567
2568 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2569
2570 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2571 }
2572
2573 union set_voltage {
2574 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2575 struct _SET_VOLTAGE_PARAMETERS v1;
2576 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2577 };
2578
2579 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2580 {
2581 union set_voltage args;
2582 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2583 u8 frev, crev, volt_index = level;
2584
2585 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2586 return;
2587
2588 switch (crev) {
2589 case 1:
2590 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2591 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2592 args.v1.ucVoltageIndex = volt_index;
2593 break;
2594 case 2:
2595 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2596 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2597 args.v2.usVoltageLevel = cpu_to_le16(level);
2598 break;
2599 default:
2600 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2601 return;
2602 }
2603
2604 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2605 }
2606
2607
2608
2609 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2610 {
2611 struct radeon_device *rdev = dev->dev_private;
2612 uint32_t bios_2_scratch, bios_6_scratch;
2613
2614 if (rdev->family >= CHIP_R600) {
2615 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2616 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2617 } else {
2618 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2619 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2620 }
2621
2622 /* let the bios control the backlight */
2623 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2624
2625 /* tell the bios not to handle mode switching */
2626 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2627
2628 if (rdev->family >= CHIP_R600) {
2629 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2630 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2631 } else {
2632 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2633 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2634 }
2635
2636 }
2637
2638 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2639 {
2640 uint32_t scratch_reg;
2641 int i;
2642
2643 if (rdev->family >= CHIP_R600)
2644 scratch_reg = R600_BIOS_0_SCRATCH;
2645 else
2646 scratch_reg = RADEON_BIOS_0_SCRATCH;
2647
2648 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2649 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2650 }
2651
2652 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2653 {
2654 uint32_t scratch_reg;
2655 int i;
2656
2657 if (rdev->family >= CHIP_R600)
2658 scratch_reg = R600_BIOS_0_SCRATCH;
2659 else
2660 scratch_reg = RADEON_BIOS_0_SCRATCH;
2661
2662 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2663 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2664 }
2665
2666 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2667 {
2668 struct drm_device *dev = encoder->dev;
2669 struct radeon_device *rdev = dev->dev_private;
2670 uint32_t bios_6_scratch;
2671
2672 if (rdev->family >= CHIP_R600)
2673 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2674 else
2675 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2676
2677 if (lock)
2678 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2679 else
2680 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2681
2682 if (rdev->family >= CHIP_R600)
2683 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2684 else
2685 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2686 }
2687
2688 /* at some point we may want to break this out into individual functions */
2689 void
2690 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2691 struct drm_encoder *encoder,
2692 bool connected)
2693 {
2694 struct drm_device *dev = connector->dev;
2695 struct radeon_device *rdev = dev->dev_private;
2696 struct radeon_connector *radeon_connector =
2697 to_radeon_connector(connector);
2698 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2699 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2700
2701 if (rdev->family >= CHIP_R600) {
2702 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2703 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2704 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2705 } else {
2706 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2707 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2708 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2709 }
2710
2711 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2712 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2713 if (connected) {
2714 DRM_DEBUG_KMS("TV1 connected\n");
2715 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2716 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2717 } else {
2718 DRM_DEBUG_KMS("TV1 disconnected\n");
2719 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2720 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2721 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2722 }
2723 }
2724 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2725 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2726 if (connected) {
2727 DRM_DEBUG_KMS("CV connected\n");
2728 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2729 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2730 } else {
2731 DRM_DEBUG_KMS("CV disconnected\n");
2732 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2733 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2734 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2735 }
2736 }
2737 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2738 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2739 if (connected) {
2740 DRM_DEBUG_KMS("LCD1 connected\n");
2741 bios_0_scratch |= ATOM_S0_LCD1;
2742 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2743 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2744 } else {
2745 DRM_DEBUG_KMS("LCD1 disconnected\n");
2746 bios_0_scratch &= ~ATOM_S0_LCD1;
2747 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2748 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2749 }
2750 }
2751 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2752 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2753 if (connected) {
2754 DRM_DEBUG_KMS("CRT1 connected\n");
2755 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2756 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2757 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2758 } else {
2759 DRM_DEBUG_KMS("CRT1 disconnected\n");
2760 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2761 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2762 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2763 }
2764 }
2765 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2766 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2767 if (connected) {
2768 DRM_DEBUG_KMS("CRT2 connected\n");
2769 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2770 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2771 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2772 } else {
2773 DRM_DEBUG_KMS("CRT2 disconnected\n");
2774 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2775 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2776 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2777 }
2778 }
2779 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2780 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2781 if (connected) {
2782 DRM_DEBUG_KMS("DFP1 connected\n");
2783 bios_0_scratch |= ATOM_S0_DFP1;
2784 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2785 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2786 } else {
2787 DRM_DEBUG_KMS("DFP1 disconnected\n");
2788 bios_0_scratch &= ~ATOM_S0_DFP1;
2789 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2790 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2791 }
2792 }
2793 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2794 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2795 if (connected) {
2796 DRM_DEBUG_KMS("DFP2 connected\n");
2797 bios_0_scratch |= ATOM_S0_DFP2;
2798 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2799 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2800 } else {
2801 DRM_DEBUG_KMS("DFP2 disconnected\n");
2802 bios_0_scratch &= ~ATOM_S0_DFP2;
2803 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2804 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2805 }
2806 }
2807 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2808 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2809 if (connected) {
2810 DRM_DEBUG_KMS("DFP3 connected\n");
2811 bios_0_scratch |= ATOM_S0_DFP3;
2812 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2813 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2814 } else {
2815 DRM_DEBUG_KMS("DFP3 disconnected\n");
2816 bios_0_scratch &= ~ATOM_S0_DFP3;
2817 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2818 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2819 }
2820 }
2821 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2822 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2823 if (connected) {
2824 DRM_DEBUG_KMS("DFP4 connected\n");
2825 bios_0_scratch |= ATOM_S0_DFP4;
2826 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2827 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2828 } else {
2829 DRM_DEBUG_KMS("DFP4 disconnected\n");
2830 bios_0_scratch &= ~ATOM_S0_DFP4;
2831 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2832 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2833 }
2834 }
2835 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2836 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2837 if (connected) {
2838 DRM_DEBUG_KMS("DFP5 connected\n");
2839 bios_0_scratch |= ATOM_S0_DFP5;
2840 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2841 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2842 } else {
2843 DRM_DEBUG_KMS("DFP5 disconnected\n");
2844 bios_0_scratch &= ~ATOM_S0_DFP5;
2845 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2846 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2847 }
2848 }
2849
2850 if (rdev->family >= CHIP_R600) {
2851 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2852 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2853 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2854 } else {
2855 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2856 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2857 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2858 }
2859 }
2860
2861 void
2862 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2863 {
2864 struct drm_device *dev = encoder->dev;
2865 struct radeon_device *rdev = dev->dev_private;
2866 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2867 uint32_t bios_3_scratch;
2868
2869 if (rdev->family >= CHIP_R600)
2870 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2871 else
2872 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2873
2874 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2875 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2876 bios_3_scratch |= (crtc << 18);
2877 }
2878 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2879 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2880 bios_3_scratch |= (crtc << 24);
2881 }
2882 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2883 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2884 bios_3_scratch |= (crtc << 16);
2885 }
2886 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2887 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2888 bios_3_scratch |= (crtc << 20);
2889 }
2890 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2891 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2892 bios_3_scratch |= (crtc << 17);
2893 }
2894 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2895 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2896 bios_3_scratch |= (crtc << 19);
2897 }
2898 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2899 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2900 bios_3_scratch |= (crtc << 23);
2901 }
2902 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2903 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2904 bios_3_scratch |= (crtc << 25);
2905 }
2906
2907 if (rdev->family >= CHIP_R600)
2908 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2909 else
2910 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2911 }
2912
2913 void
2914 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2915 {
2916 struct drm_device *dev = encoder->dev;
2917 struct radeon_device *rdev = dev->dev_private;
2918 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2919 uint32_t bios_2_scratch;
2920
2921 if (rdev->family >= CHIP_R600)
2922 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2923 else
2924 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2925
2926 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2927 if (on)
2928 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2929 else
2930 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2931 }
2932 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2933 if (on)
2934 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2935 else
2936 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2937 }
2938 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2939 if (on)
2940 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2941 else
2942 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2943 }
2944 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2945 if (on)
2946 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2947 else
2948 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2949 }
2950 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2951 if (on)
2952 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2953 else
2954 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2955 }
2956 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2957 if (on)
2958 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2959 else
2960 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2961 }
2962 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2963 if (on)
2964 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2965 else
2966 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2967 }
2968 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2969 if (on)
2970 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2971 else
2972 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2973 }
2974 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2975 if (on)
2976 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2977 else
2978 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2979 }
2980 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2981 if (on)
2982 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2983 else
2984 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2985 }
2986
2987 if (rdev->family >= CHIP_R600)
2988 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2989 else
2990 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2991 }
Linux kernel - Deliverables
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