2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_id(struct drm_device
*dev
, uint32_t supported_device
,
37 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
39 radeon_add_atom_encoder(struct drm_device
*dev
, uint32_t encoder_id
,
40 uint32_t supported_device
);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device
*dev
,
45 uint32_t connector_id
,
46 uint32_t supported_device
,
48 struct radeon_i2c_bus_rec
*i2c_bus
,
49 bool linkb
, uint32_t igp_lane_info
);
51 /* from radeon_legacy_encoder.c */
53 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_id
,
54 uint32_t supported_device
);
56 union atom_supported_devices
{
57 struct _ATOM_SUPPORTED_DEVICES_INFO info
;
58 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2
;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1
;
62 static inline struct radeon_i2c_bus_rec
radeon_lookup_gpio(struct drm_device
65 struct radeon_device
*rdev
= dev
->dev_private
;
66 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
67 ATOM_GPIO_I2C_ASSIGMENT gpio
;
68 struct radeon_i2c_bus_rec i2c
;
69 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
70 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
73 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
76 atom_parse_data_header(ctx
, index
, NULL
, NULL
, NULL
, &data_offset
);
78 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
80 gpio
= i2c_info
->asGPIO_Info
[id
];
82 i2c
.mask_clk_reg
= le16_to_cpu(gpio
.usClkMaskRegisterIndex
) * 4;
83 i2c
.mask_data_reg
= le16_to_cpu(gpio
.usDataMaskRegisterIndex
) * 4;
84 i2c
.put_clk_reg
= le16_to_cpu(gpio
.usClkEnRegisterIndex
) * 4;
85 i2c
.put_data_reg
= le16_to_cpu(gpio
.usDataEnRegisterIndex
) * 4;
86 i2c
.get_clk_reg
= le16_to_cpu(gpio
.usClkY_RegisterIndex
) * 4;
87 i2c
.get_data_reg
= le16_to_cpu(gpio
.usDataY_RegisterIndex
) * 4;
88 i2c
.a_clk_reg
= le16_to_cpu(gpio
.usClkA_RegisterIndex
) * 4;
89 i2c
.a_data_reg
= le16_to_cpu(gpio
.usDataA_RegisterIndex
) * 4;
90 i2c
.mask_clk_mask
= (1 << gpio
.ucClkMaskShift
);
91 i2c
.mask_data_mask
= (1 << gpio
.ucDataMaskShift
);
92 i2c
.put_clk_mask
= (1 << gpio
.ucClkEnShift
);
93 i2c
.put_data_mask
= (1 << gpio
.ucDataEnShift
);
94 i2c
.get_clk_mask
= (1 << gpio
.ucClkY_Shift
);
95 i2c
.get_data_mask
= (1 << gpio
.ucDataY_Shift
);
96 i2c
.a_clk_mask
= (1 << gpio
.ucClkA_Shift
);
97 i2c
.a_data_mask
= (1 << gpio
.ucDataA_Shift
);
103 static bool radeon_atom_apply_quirks(struct drm_device
*dev
,
104 uint32_t supported_device
,
106 struct radeon_i2c_bus_rec
*i2c_bus
,
110 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
111 if ((dev
->pdev
->device
== 0x791e) &&
112 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
113 (dev
->pdev
->subsystem_device
== 0x826d)) {
114 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
115 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
116 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
119 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
120 if ((dev
->pdev
->device
== 0x7941) &&
121 (dev
->pdev
->subsystem_vendor
== 0x147b) &&
122 (dev
->pdev
->subsystem_device
== 0x2412)) {
123 if (*connector_type
== DRM_MODE_CONNECTOR_DVII
)
127 /* Falcon NW laptop lists vga ddc line for LVDS */
128 if ((dev
->pdev
->device
== 0x5653) &&
129 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
130 (dev
->pdev
->subsystem_device
== 0x0291)) {
131 if (*connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
132 i2c_bus
->valid
= false;
138 if ((dev
->pdev
->device
== 0x71C5) &&
139 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
140 (dev
->pdev
->subsystem_device
== 0x0080)) {
141 if ((supported_device
== ATOM_DEVICE_CRT1_SUPPORT
) ||
142 (supported_device
== ATOM_DEVICE_DFP2_SUPPORT
))
146 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
147 if ((dev
->pdev
->device
== 0x9598) &&
148 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
149 (dev
->pdev
->subsystem_device
== 0x01da)) {
150 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
151 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
155 /* ASUS HD 3450 board lists the DVI port as HDMI */
156 if ((dev
->pdev
->device
== 0x95C5) &&
157 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
158 (dev
->pdev
->subsystem_device
== 0x01e2)) {
159 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
160 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
164 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
165 * HDMI + VGA reporting as HDMI
167 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
168 if (supported_device
& (ATOM_DEVICE_CRT_SUPPORT
)) {
169 *connector_type
= DRM_MODE_CONNECTOR_VGA
;
177 const int supported_devices_connector_convert
[] = {
178 DRM_MODE_CONNECTOR_Unknown
,
179 DRM_MODE_CONNECTOR_VGA
,
180 DRM_MODE_CONNECTOR_DVII
,
181 DRM_MODE_CONNECTOR_DVID
,
182 DRM_MODE_CONNECTOR_DVIA
,
183 DRM_MODE_CONNECTOR_SVIDEO
,
184 DRM_MODE_CONNECTOR_Composite
,
185 DRM_MODE_CONNECTOR_LVDS
,
186 DRM_MODE_CONNECTOR_Unknown
,
187 DRM_MODE_CONNECTOR_Unknown
,
188 DRM_MODE_CONNECTOR_HDMIA
,
189 DRM_MODE_CONNECTOR_HDMIB
,
190 DRM_MODE_CONNECTOR_Unknown
,
191 DRM_MODE_CONNECTOR_Unknown
,
192 DRM_MODE_CONNECTOR_9PinDIN
,
193 DRM_MODE_CONNECTOR_DisplayPort
196 const int object_connector_convert
[] = {
197 DRM_MODE_CONNECTOR_Unknown
,
198 DRM_MODE_CONNECTOR_DVII
,
199 DRM_MODE_CONNECTOR_DVII
,
200 DRM_MODE_CONNECTOR_DVID
,
201 DRM_MODE_CONNECTOR_DVID
,
202 DRM_MODE_CONNECTOR_VGA
,
203 DRM_MODE_CONNECTOR_Composite
,
204 DRM_MODE_CONNECTOR_SVIDEO
,
205 DRM_MODE_CONNECTOR_Unknown
,
206 DRM_MODE_CONNECTOR_Unknown
,
207 DRM_MODE_CONNECTOR_9PinDIN
,
208 DRM_MODE_CONNECTOR_Unknown
,
209 DRM_MODE_CONNECTOR_HDMIA
,
210 DRM_MODE_CONNECTOR_HDMIB
,
211 DRM_MODE_CONNECTOR_LVDS
,
212 DRM_MODE_CONNECTOR_9PinDIN
,
213 DRM_MODE_CONNECTOR_Unknown
,
214 DRM_MODE_CONNECTOR_Unknown
,
215 DRM_MODE_CONNECTOR_Unknown
,
216 DRM_MODE_CONNECTOR_DisplayPort
219 bool radeon_get_atom_connector_info_from_object_table(struct drm_device
*dev
)
221 struct radeon_device
*rdev
= dev
->dev_private
;
222 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
223 struct atom_context
*ctx
= mode_info
->atom_context
;
224 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
225 uint16_t size
, data_offset
;
226 uint8_t frev
, crev
, line_mux
= 0;
227 ATOM_CONNECTOR_OBJECT_TABLE
*con_obj
;
228 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
229 ATOM_OBJECT_HEADER
*obj_header
;
230 int i
, j
, path_size
, device_support
;
232 uint16_t igp_lane_info
, conn_id
;
234 struct radeon_i2c_bus_rec ddc_bus
;
236 atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
);
238 if (data_offset
== 0)
244 obj_header
= (ATOM_OBJECT_HEADER
*) (ctx
->bios
+ data_offset
);
245 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
246 (ctx
->bios
+ data_offset
+
247 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
248 con_obj
= (ATOM_CONNECTOR_OBJECT_TABLE
*)
249 (ctx
->bios
+ data_offset
+
250 le16_to_cpu(obj_header
->usConnectorObjectTableOffset
));
251 device_support
= le16_to_cpu(obj_header
->usDeviceSupport
);
254 for (i
= 0; i
< path_obj
->ucNumOfDispPath
; i
++) {
255 uint8_t *addr
= (uint8_t *) path_obj
->asDispPath
;
256 ATOM_DISPLAY_OBJECT_PATH
*path
;
258 path
= (ATOM_DISPLAY_OBJECT_PATH
*) addr
;
259 path_size
+= le16_to_cpu(path
->usSize
);
262 if (device_support
& le16_to_cpu(path
->usDeviceTag
)) {
263 uint8_t con_obj_id
, con_obj_num
, con_obj_type
;
266 (le16_to_cpu(path
->usConnObjectId
) & OBJECT_ID_MASK
)
269 (le16_to_cpu(path
->usConnObjectId
) & ENUM_ID_MASK
)
272 (le16_to_cpu(path
->usConnObjectId
) &
273 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
275 /* TODO CV support */
276 if (le16_to_cpu(path
->usDeviceTag
) ==
277 ATOM_DEVICE_CV_SUPPORT
)
280 if ((rdev
->family
== CHIP_RS780
) &&
282 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR
)) {
283 uint16_t igp_offset
= 0;
284 ATOM_INTEGRATED_SYSTEM_INFO_V2
*igp_obj
;
287 GetIndexIntoMasterTable(DATA
,
288 IntegratedSystemInfo
);
290 atom_parse_data_header(ctx
, index
, &size
, &frev
,
295 (ATOM_INTEGRATED_SYSTEM_INFO_V2
296 *) (ctx
->bios
+ igp_offset
);
299 uint32_t slot_config
, ct
;
301 if (con_obj_num
== 1)
310 ct
= (slot_config
>> 16) & 0xff;
312 object_connector_convert
315 slot_config
& 0xffff;
323 object_connector_convert
[con_obj_id
];
326 if (connector_type
== DRM_MODE_CONNECTOR_Unknown
)
329 for (j
= 0; j
< ((le16_to_cpu(path
->usSize
) - 8) / 2);
331 uint8_t enc_obj_id
, enc_obj_num
, enc_obj_type
;
334 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
335 OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
337 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
338 ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
340 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
341 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
343 /* FIXME: add support for router objects */
344 if (enc_obj_type
== GRAPH_OBJECT_TYPE_ENCODER
) {
345 if (enc_obj_num
== 2)
350 radeon_add_atom_encoder(dev
,
359 /* look up gpio for ddc */
360 if ((le16_to_cpu(path
->usDeviceTag
) &
361 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
363 for (j
= 0; j
< con_obj
->ucNumberOfObjects
; j
++) {
364 if (le16_to_cpu(path
->usConnObjectId
) ==
365 le16_to_cpu(con_obj
->asObjects
[j
].
367 ATOM_COMMON_RECORD_HEADER
369 (ATOM_COMMON_RECORD_HEADER
371 (ctx
->bios
+ data_offset
+
372 le16_to_cpu(con_obj
->
375 ATOM_I2C_RECORD
*i2c_record
;
377 while (record
->ucRecordType
> 0
380 ATOM_MAX_OBJECT_RECORD_NUMBER
) {
383 case ATOM_I2C_RECORD_TYPE
:
394 (ATOM_COMMON_RECORD_HEADER
406 if ((le16_to_cpu(path
->usDeviceTag
) ==
407 ATOM_DEVICE_TV1_SUPPORT
)
408 || (le16_to_cpu(path
->usDeviceTag
) ==
409 ATOM_DEVICE_TV2_SUPPORT
)
410 || (le16_to_cpu(path
->usDeviceTag
) ==
411 ATOM_DEVICE_CV_SUPPORT
))
412 ddc_bus
.valid
= false;
414 ddc_bus
= radeon_lookup_gpio(dev
, line_mux
);
416 conn_id
= le16_to_cpu(path
->usConnObjectId
);
418 if (!radeon_atom_apply_quirks
419 (dev
, le16_to_cpu(path
->usDeviceTag
), &connector_type
,
423 radeon_add_atom_connector(dev
,
427 connector_type
, &ddc_bus
,
428 linkb
, igp_lane_info
);
433 radeon_link_encoder_connector(dev
);
438 struct bios_connector
{
443 struct radeon_i2c_bus_rec ddc_bus
;
446 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
450 struct radeon_device
*rdev
= dev
->dev_private
;
451 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
452 struct atom_context
*ctx
= mode_info
->atom_context
;
453 int index
= GetIndexIntoMasterTable(DATA
, SupportedDevicesInfo
);
454 uint16_t size
, data_offset
;
456 uint16_t device_support
;
458 union atom_supported_devices
*supported_devices
;
460 struct bios_connector bios_connectors
[ATOM_MAX_SUPPORTED_DEVICE
];
462 atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
);
465 (union atom_supported_devices
*)(ctx
->bios
+ data_offset
);
467 device_support
= le16_to_cpu(supported_devices
->info
.usDeviceSupport
);
469 for (i
= 0; i
< ATOM_MAX_SUPPORTED_DEVICE
; i
++) {
470 ATOM_CONNECTOR_INFO_I2C ci
=
471 supported_devices
->info
.asConnInfo
[i
];
473 bios_connectors
[i
].valid
= false;
475 if (!(device_support
& (1 << i
))) {
479 if (i
== ATOM_DEVICE_CV_INDEX
) {
480 DRM_DEBUG("Skipping Component Video\n");
484 bios_connectors
[i
].connector_type
=
485 supported_devices_connector_convert
[ci
.sucConnectorInfo
.
489 if (bios_connectors
[i
].connector_type
==
490 DRM_MODE_CONNECTOR_Unknown
)
493 dac
= ci
.sucConnectorInfo
.sbfAccess
.bfAssociatedDAC
;
495 if ((rdev
->family
== CHIP_RS690
) ||
496 (rdev
->family
== CHIP_RS740
)) {
497 if ((i
== ATOM_DEVICE_DFP2_INDEX
)
498 && (ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
== 2))
499 bios_connectors
[i
].line_mux
=
500 ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
+ 1;
501 else if ((i
== ATOM_DEVICE_DFP3_INDEX
)
502 && (ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
== 1))
503 bios_connectors
[i
].line_mux
=
504 ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
+ 1;
506 bios_connectors
[i
].line_mux
=
507 ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
;
509 bios_connectors
[i
].line_mux
=
510 ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
;
512 /* give tv unique connector ids */
513 if (i
== ATOM_DEVICE_TV1_INDEX
) {
514 bios_connectors
[i
].ddc_bus
.valid
= false;
515 bios_connectors
[i
].line_mux
= 50;
516 } else if (i
== ATOM_DEVICE_TV2_INDEX
) {
517 bios_connectors
[i
].ddc_bus
.valid
= false;
518 bios_connectors
[i
].line_mux
= 51;
519 } else if (i
== ATOM_DEVICE_CV_INDEX
) {
520 bios_connectors
[i
].ddc_bus
.valid
= false;
521 bios_connectors
[i
].line_mux
= 52;
523 bios_connectors
[i
].ddc_bus
=
524 radeon_lookup_gpio(dev
,
525 bios_connectors
[i
].line_mux
);
527 /* Always set the connector type to VGA for CRT1/CRT2. if they are
528 * shared with a DVI port, we'll pick up the DVI connector when we
529 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
531 if (i
== ATOM_DEVICE_CRT1_INDEX
|| i
== ATOM_DEVICE_CRT2_INDEX
)
532 bios_connectors
[i
].connector_type
=
533 DRM_MODE_CONNECTOR_VGA
;
535 if (!radeon_atom_apply_quirks
536 (dev
, (1 << i
), &bios_connectors
[i
].connector_type
,
537 &bios_connectors
[i
].ddc_bus
, &bios_connectors
[i
].line_mux
))
540 bios_connectors
[i
].valid
= true;
541 bios_connectors
[i
].devices
= (1 << i
);
543 if (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
)
544 radeon_add_atom_encoder(dev
,
545 radeon_get_encoder_id(dev
,
550 radeon_add_legacy_encoder(dev
,
551 radeon_get_encoder_id(dev
,
558 /* combine shared connectors */
559 for (i
= 0; i
< ATOM_MAX_SUPPORTED_DEVICE
; i
++) {
560 if (bios_connectors
[i
].valid
) {
561 for (j
= 0; j
< ATOM_MAX_SUPPORTED_DEVICE
; j
++) {
562 if (bios_connectors
[j
].valid
&& (i
!= j
)) {
563 if (bios_connectors
[i
].line_mux
==
564 bios_connectors
[j
].line_mux
) {
565 if (((bios_connectors
[i
].
567 (ATOM_DEVICE_DFP_SUPPORT
))
568 && (bios_connectors
[j
].
570 (ATOM_DEVICE_CRT_SUPPORT
)))
572 ((bios_connectors
[j
].
574 (ATOM_DEVICE_DFP_SUPPORT
))
575 && (bios_connectors
[i
].
577 (ATOM_DEVICE_CRT_SUPPORT
)))) {
584 DRM_MODE_CONNECTOR_DVII
;
594 /* add the connectors */
595 for (i
= 0; i
< ATOM_MAX_SUPPORTED_DEVICE
; i
++) {
596 if (bios_connectors
[i
].valid
)
597 radeon_add_atom_connector(dev
,
598 bios_connectors
[i
].line_mux
,
599 bios_connectors
[i
].devices
,
602 &bios_connectors
[i
].ddc_bus
,
606 radeon_link_encoder_connector(dev
);
611 union firmware_info
{
612 ATOM_FIRMWARE_INFO info
;
613 ATOM_FIRMWARE_INFO_V1_2 info_12
;
614 ATOM_FIRMWARE_INFO_V1_3 info_13
;
615 ATOM_FIRMWARE_INFO_V1_4 info_14
;
618 bool radeon_atom_get_clock_info(struct drm_device
*dev
)
620 struct radeon_device
*rdev
= dev
->dev_private
;
621 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
622 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
623 union firmware_info
*firmware_info
;
625 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
626 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
627 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
628 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
629 uint16_t data_offset
;
631 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
632 &crev
, &data_offset
);
635 (union firmware_info
*)(mode_info
->atom_context
->bios
+
640 p1pll
->reference_freq
=
641 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
642 p1pll
->reference_div
= 0;
646 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Output
);
649 le32_to_cpu(firmware_info
->info_12
.ulMinPixelClockPLL_Output
);
651 le32_to_cpu(firmware_info
->info
.ulMaxPixelClockPLL_Output
);
653 if (p1pll
->pll_out_min
== 0) {
654 if (ASIC_IS_AVIVO(rdev
))
655 p1pll
->pll_out_min
= 64800;
657 p1pll
->pll_out_min
= 20000;
658 } else if (p1pll
->pll_out_min
> 64800) {
659 /* Limiting the pll output range is a good thing generally as
660 * it limits the number of possible pll combinations for a given
661 * frequency presumably to the ones that work best on each card.
662 * However, certain duallink DVI monitors seem to like
663 * pll combinations that would be limited by this at least on
664 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
667 p1pll
->pll_out_min
= 64800;
671 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Input
);
673 le16_to_cpu(firmware_info
->info
.usMaxPixelClockPLL_Input
);
678 spll
->reference_freq
=
679 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
680 spll
->reference_div
= 0;
683 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Output
);
685 le32_to_cpu(firmware_info
->info
.ulMaxEngineClockPLL_Output
);
688 if (spll
->pll_out_min
== 0) {
689 if (ASIC_IS_AVIVO(rdev
))
690 spll
->pll_out_min
= 64800;
692 spll
->pll_out_min
= 20000;
696 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Input
);
698 le16_to_cpu(firmware_info
->info
.usMaxEngineClockPLL_Input
);
701 mpll
->reference_freq
=
702 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
703 mpll
->reference_div
= 0;
706 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Output
);
708 le32_to_cpu(firmware_info
->info
.ulMaxMemoryClockPLL_Output
);
711 if (mpll
->pll_out_min
== 0) {
712 if (ASIC_IS_AVIVO(rdev
))
713 mpll
->pll_out_min
= 64800;
715 mpll
->pll_out_min
= 20000;
719 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Input
);
721 le16_to_cpu(firmware_info
->info
.usMaxMemoryClockPLL_Input
);
723 rdev
->clock
.default_sclk
=
724 le32_to_cpu(firmware_info
->info
.ulDefaultEngineClock
);
725 rdev
->clock
.default_mclk
=
726 le32_to_cpu(firmware_info
->info
.ulDefaultMemoryClock
);
733 bool radeon_atombios_get_tmds_info(struct radeon_encoder
*encoder
,
734 struct radeon_encoder_int_tmds
*tmds
)
736 struct drm_device
*dev
= encoder
->base
.dev
;
737 struct radeon_device
*rdev
= dev
->dev_private
;
738 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
739 int index
= GetIndexIntoMasterTable(DATA
, TMDS_Info
);
740 uint16_t data_offset
;
741 struct _ATOM_TMDS_INFO
*tmds_info
;
746 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
747 &crev
, &data_offset
);
750 (struct _ATOM_TMDS_INFO
*)(mode_info
->atom_context
->bios
+
754 maxfreq
= le16_to_cpu(tmds_info
->usMaxFrequency
);
755 for (i
= 0; i
< 4; i
++) {
756 tmds
->tmds_pll
[i
].freq
=
757 le16_to_cpu(tmds_info
->asMiscInfo
[i
].usFrequency
);
758 tmds
->tmds_pll
[i
].value
=
759 tmds_info
->asMiscInfo
[i
].ucPLL_ChargePump
& 0x3f;
760 tmds
->tmds_pll
[i
].value
|=
761 (tmds_info
->asMiscInfo
[i
].
762 ucPLL_VCO_Gain
& 0x3f) << 6;
763 tmds
->tmds_pll
[i
].value
|=
764 (tmds_info
->asMiscInfo
[i
].
765 ucPLL_DutyCycle
& 0xf) << 12;
766 tmds
->tmds_pll
[i
].value
|=
767 (tmds_info
->asMiscInfo
[i
].
768 ucPLL_VoltageSwing
& 0xf) << 16;
770 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
771 tmds
->tmds_pll
[i
].freq
,
772 tmds
->tmds_pll
[i
].value
);
774 if (maxfreq
== tmds
->tmds_pll
[i
].freq
) {
775 tmds
->tmds_pll
[i
].freq
= 0xffffffff;
784 static struct radeon_atom_ss
*radeon_atombios_get_ss_info(struct
789 struct drm_device
*dev
= encoder
->base
.dev
;
790 struct radeon_device
*rdev
= dev
->dev_private
;
791 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
792 int index
= GetIndexIntoMasterTable(DATA
, PPLL_SS_Info
);
793 uint16_t data_offset
;
794 struct _ATOM_SPREAD_SPECTRUM_INFO
*ss_info
;
796 struct radeon_atom_ss
*ss
= NULL
;
798 if (id
> ATOM_MAX_SS_ENTRY
)
801 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
802 &crev
, &data_offset
);
805 (struct _ATOM_SPREAD_SPECTRUM_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
809 kzalloc(sizeof(struct radeon_atom_ss
), GFP_KERNEL
);
814 ss
->percentage
= le16_to_cpu(ss_info
->asSS_Info
[id
].usSpreadSpectrumPercentage
);
815 ss
->type
= ss_info
->asSS_Info
[id
].ucSpreadSpectrumType
;
816 ss
->step
= ss_info
->asSS_Info
[id
].ucSS_Step
;
817 ss
->delay
= ss_info
->asSS_Info
[id
].ucSS_Delay
;
818 ss
->range
= ss_info
->asSS_Info
[id
].ucSS_Range
;
819 ss
->refdiv
= ss_info
->asSS_Info
[id
].ucRecommendedRef_Div
;
825 struct _ATOM_LVDS_INFO info
;
826 struct _ATOM_LVDS_INFO_V12 info_12
;
829 struct radeon_encoder_atom_dig
*radeon_atombios_get_lvds_info(struct
833 struct drm_device
*dev
= encoder
->base
.dev
;
834 struct radeon_device
*rdev
= dev
->dev_private
;
835 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
836 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
837 uint16_t data_offset
;
838 union lvds_info
*lvds_info
;
840 struct radeon_encoder_atom_dig
*lvds
= NULL
;
842 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
843 &crev
, &data_offset
);
846 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
850 kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
855 lvds
->native_mode
.clock
=
856 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
857 lvds
->native_mode
.hdisplay
=
858 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
859 lvds
->native_mode
.vdisplay
=
860 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
861 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
862 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
863 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
864 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
865 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
866 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
867 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
868 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
869 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
870 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
871 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
872 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
873 lvds
->panel_pwr_delay
=
874 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
875 lvds
->lvds_misc
= lvds_info
->info
.ucLVDS_Misc
;
876 /* set crtc values */
877 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
879 lvds
->ss
= radeon_atombios_get_ss_info(encoder
, lvds_info
->info
.ucSS_Id
);
881 encoder
->native_mode
= lvds
->native_mode
;
886 struct radeon_encoder_primary_dac
*
887 radeon_atombios_get_primary_dac_info(struct radeon_encoder
*encoder
)
889 struct drm_device
*dev
= encoder
->base
.dev
;
890 struct radeon_device
*rdev
= dev
->dev_private
;
891 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
892 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
893 uint16_t data_offset
;
894 struct _COMPASSIONATE_DATA
*dac_info
;
897 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
899 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
, &crev
, &data_offset
);
901 dac_info
= (struct _COMPASSIONATE_DATA
*)(mode_info
->atom_context
->bios
+ data_offset
);
904 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
), GFP_KERNEL
);
909 bg
= dac_info
->ucDAC1_BG_Adjustment
;
910 dac
= dac_info
->ucDAC1_DAC_Adjustment
;
911 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
917 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
918 struct drm_display_mode
*mode
)
920 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
921 ATOM_ANALOG_TV_INFO
*tv_info
;
922 ATOM_ANALOG_TV_INFO_V1_2
*tv_info_v1_2
;
923 ATOM_DTD_FORMAT
*dtd_timings
;
924 int data_index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
926 u16 data_offset
, misc
;
928 atom_parse_data_header(mode_info
->atom_context
, data_index
, NULL
, &frev
, &crev
, &data_offset
);
932 tv_info
= (ATOM_ANALOG_TV_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
933 if (index
> MAX_SUPPORTED_TV_TIMING
)
936 mode
->crtc_htotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Total
);
937 mode
->crtc_hdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Disp
);
938 mode
->crtc_hsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
);
939 mode
->crtc_hsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
) +
940 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncWidth
);
942 mode
->crtc_vtotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Total
);
943 mode
->crtc_vdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Disp
);
944 mode
->crtc_vsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
);
945 mode
->crtc_vsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
) +
946 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncWidth
);
949 misc
= le16_to_cpu(tv_info
->aModeTimings
[index
].susModeMiscInfo
.usAccess
);
950 if (misc
& ATOM_VSYNC_POLARITY
)
951 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
952 if (misc
& ATOM_HSYNC_POLARITY
)
953 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
954 if (misc
& ATOM_COMPOSITESYNC
)
955 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
956 if (misc
& ATOM_INTERLACE
)
957 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
958 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
959 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
961 mode
->clock
= le16_to_cpu(tv_info
->aModeTimings
[index
].usPixelClock
) * 10;
964 /* PAL timings appear to have wrong values for totals */
965 mode
->crtc_htotal
-= 1;
966 mode
->crtc_vtotal
-= 1;
970 tv_info_v1_2
= (ATOM_ANALOG_TV_INFO_V1_2
*)(mode_info
->atom_context
->bios
+ data_offset
);
971 if (index
> MAX_SUPPORTED_TV_TIMING_V1_2
)
974 dtd_timings
= &tv_info_v1_2
->aModeTimings
[index
];
975 mode
->crtc_htotal
= le16_to_cpu(dtd_timings
->usHActive
) +
976 le16_to_cpu(dtd_timings
->usHBlanking_Time
);
977 mode
->crtc_hdisplay
= le16_to_cpu(dtd_timings
->usHActive
);
978 mode
->crtc_hsync_start
= le16_to_cpu(dtd_timings
->usHActive
) +
979 le16_to_cpu(dtd_timings
->usHSyncOffset
);
980 mode
->crtc_hsync_end
= mode
->crtc_hsync_start
+
981 le16_to_cpu(dtd_timings
->usHSyncWidth
);
983 mode
->crtc_vtotal
= le16_to_cpu(dtd_timings
->usVActive
) +
984 le16_to_cpu(dtd_timings
->usVBlanking_Time
);
985 mode
->crtc_vdisplay
= le16_to_cpu(dtd_timings
->usVActive
);
986 mode
->crtc_vsync_start
= le16_to_cpu(dtd_timings
->usVActive
) +
987 le16_to_cpu(dtd_timings
->usVSyncOffset
);
988 mode
->crtc_vsync_end
= mode
->crtc_vsync_start
+
989 le16_to_cpu(dtd_timings
->usVSyncWidth
);
992 misc
= le16_to_cpu(dtd_timings
->susModeMiscInfo
.usAccess
);
993 if (misc
& ATOM_VSYNC_POLARITY
)
994 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
995 if (misc
& ATOM_HSYNC_POLARITY
)
996 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
997 if (misc
& ATOM_COMPOSITESYNC
)
998 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
999 if (misc
& ATOM_INTERLACE
)
1000 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1001 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1002 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1004 mode
->clock
= le16_to_cpu(dtd_timings
->usPixClk
) * 10;
1010 struct radeon_encoder_tv_dac
*
1011 radeon_atombios_get_tv_dac_info(struct radeon_encoder
*encoder
)
1013 struct drm_device
*dev
= encoder
->base
.dev
;
1014 struct radeon_device
*rdev
= dev
->dev_private
;
1015 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1016 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1017 uint16_t data_offset
;
1018 struct _COMPASSIONATE_DATA
*dac_info
;
1021 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1023 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
, &crev
, &data_offset
);
1025 dac_info
= (struct _COMPASSIONATE_DATA
*)(mode_info
->atom_context
->bios
+ data_offset
);
1028 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1033 bg
= dac_info
->ucDAC2_CRT2_BG_Adjustment
;
1034 dac
= dac_info
->ucDAC2_CRT2_DAC_Adjustment
;
1035 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1037 bg
= dac_info
->ucDAC2_PAL_BG_Adjustment
;
1038 dac
= dac_info
->ucDAC2_PAL_DAC_Adjustment
;
1039 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1041 bg
= dac_info
->ucDAC2_NTSC_BG_Adjustment
;
1042 dac
= dac_info
->ucDAC2_NTSC_DAC_Adjustment
;
1043 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1049 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
)
1051 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args
;
1052 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicClockGating
);
1054 args
.ucEnable
= enable
;
1056 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1059 void radeon_atom_static_pwrmgt_setup(struct radeon_device
*rdev
, int enable
)
1061 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args
;
1062 int index
= GetIndexIntoMasterTable(COMMAND
, EnableASIC_StaticPwrMgt
);
1064 args
.ucEnable
= enable
;
1066 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1069 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
,
1072 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
1073 int index
= GetIndexIntoMasterTable(COMMAND
, SetEngineClock
);
1075 args
.ulTargetEngineClock
= eng_clock
; /* 10 khz */
1077 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1080 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
,
1083 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
1084 int index
= GetIndexIntoMasterTable(COMMAND
, SetMemoryClock
);
1086 if (rdev
->flags
& RADEON_IS_IGP
)
1089 args
.ulTargetMemoryClock
= mem_clock
; /* 10 khz */
1091 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1094 void radeon_atom_initialize_bios_scratch_regs(struct drm_device
*dev
)
1096 struct radeon_device
*rdev
= dev
->dev_private
;
1097 uint32_t bios_2_scratch
, bios_6_scratch
;
1099 if (rdev
->family
>= CHIP_R600
) {
1100 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
1101 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1103 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
1104 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1107 /* let the bios control the backlight */
1108 bios_2_scratch
&= ~ATOM_S2_VRI_BRIGHT_ENABLE
;
1110 /* tell the bios not to handle mode switching */
1111 bios_6_scratch
|= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
| ATOM_S6_ACC_MODE
);
1113 if (rdev
->family
>= CHIP_R600
) {
1114 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
1115 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1117 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
1118 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1123 void radeon_save_bios_scratch_regs(struct radeon_device
*rdev
)
1125 uint32_t scratch_reg
;
1128 if (rdev
->family
>= CHIP_R600
)
1129 scratch_reg
= R600_BIOS_0_SCRATCH
;
1131 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
1133 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
1134 rdev
->bios_scratch
[i
] = RREG32(scratch_reg
+ (i
* 4));
1137 void radeon_restore_bios_scratch_regs(struct radeon_device
*rdev
)
1139 uint32_t scratch_reg
;
1142 if (rdev
->family
>= CHIP_R600
)
1143 scratch_reg
= R600_BIOS_0_SCRATCH
;
1145 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
1147 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
1148 WREG32(scratch_reg
+ (i
* 4), rdev
->bios_scratch
[i
]);
1151 void radeon_atom_output_lock(struct drm_encoder
*encoder
, bool lock
)
1153 struct drm_device
*dev
= encoder
->dev
;
1154 struct radeon_device
*rdev
= dev
->dev_private
;
1155 uint32_t bios_6_scratch
;
1157 if (rdev
->family
>= CHIP_R600
)
1158 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1160 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1163 bios_6_scratch
|= ATOM_S6_CRITICAL_STATE
;
1165 bios_6_scratch
&= ~ATOM_S6_CRITICAL_STATE
;
1167 if (rdev
->family
>= CHIP_R600
)
1168 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1170 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1173 /* at some point we may want to break this out into individual functions */
1175 radeon_atombios_connected_scratch_regs(struct drm_connector
*connector
,
1176 struct drm_encoder
*encoder
,
1179 struct drm_device
*dev
= connector
->dev
;
1180 struct radeon_device
*rdev
= dev
->dev_private
;
1181 struct radeon_connector
*radeon_connector
=
1182 to_radeon_connector(connector
);
1183 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1184 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
1186 if (rdev
->family
>= CHIP_R600
) {
1187 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
1188 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
1189 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1191 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
1192 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
1193 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1196 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
1197 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
1199 DRM_DEBUG("TV1 connected\n");
1200 bios_3_scratch
|= ATOM_S3_TV1_ACTIVE
;
1201 bios_6_scratch
|= ATOM_S6_ACC_REQ_TV1
;
1203 DRM_DEBUG("TV1 disconnected\n");
1204 bios_0_scratch
&= ~ATOM_S0_TV1_MASK
;
1205 bios_3_scratch
&= ~ATOM_S3_TV1_ACTIVE
;
1206 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_TV1
;
1209 if ((radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) &&
1210 (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
)) {
1212 DRM_DEBUG("CV connected\n");
1213 bios_3_scratch
|= ATOM_S3_CV_ACTIVE
;
1214 bios_6_scratch
|= ATOM_S6_ACC_REQ_CV
;
1216 DRM_DEBUG("CV disconnected\n");
1217 bios_0_scratch
&= ~ATOM_S0_CV_MASK
;
1218 bios_3_scratch
&= ~ATOM_S3_CV_ACTIVE
;
1219 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CV
;
1222 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
1223 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
1225 DRM_DEBUG("LCD1 connected\n");
1226 bios_0_scratch
|= ATOM_S0_LCD1
;
1227 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
1228 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
1230 DRM_DEBUG("LCD1 disconnected\n");
1231 bios_0_scratch
&= ~ATOM_S0_LCD1
;
1232 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
1233 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
1236 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
1237 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
1239 DRM_DEBUG("CRT1 connected\n");
1240 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
1241 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
1242 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
1244 DRM_DEBUG("CRT1 disconnected\n");
1245 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
1246 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
1247 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
1250 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
1251 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
1253 DRM_DEBUG("CRT2 connected\n");
1254 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
1255 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
1256 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
1258 DRM_DEBUG("CRT2 disconnected\n");
1259 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
1260 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
1261 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
1264 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
1265 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
1267 DRM_DEBUG("DFP1 connected\n");
1268 bios_0_scratch
|= ATOM_S0_DFP1
;
1269 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
1270 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
1272 DRM_DEBUG("DFP1 disconnected\n");
1273 bios_0_scratch
&= ~ATOM_S0_DFP1
;
1274 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
1275 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
1278 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
1279 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
1281 DRM_DEBUG("DFP2 connected\n");
1282 bios_0_scratch
|= ATOM_S0_DFP2
;
1283 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
1284 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
1286 DRM_DEBUG("DFP2 disconnected\n");
1287 bios_0_scratch
&= ~ATOM_S0_DFP2
;
1288 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
1289 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
1292 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
1293 (radeon_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
1295 DRM_DEBUG("DFP3 connected\n");
1296 bios_0_scratch
|= ATOM_S0_DFP3
;
1297 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
1298 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
1300 DRM_DEBUG("DFP3 disconnected\n");
1301 bios_0_scratch
&= ~ATOM_S0_DFP3
;
1302 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
1303 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
1306 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
1307 (radeon_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
1309 DRM_DEBUG("DFP4 connected\n");
1310 bios_0_scratch
|= ATOM_S0_DFP4
;
1311 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
1312 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
1314 DRM_DEBUG("DFP4 disconnected\n");
1315 bios_0_scratch
&= ~ATOM_S0_DFP4
;
1316 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
1317 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
1320 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
1321 (radeon_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
1323 DRM_DEBUG("DFP5 connected\n");
1324 bios_0_scratch
|= ATOM_S0_DFP5
;
1325 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
1326 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
1328 DRM_DEBUG("DFP5 disconnected\n");
1329 bios_0_scratch
&= ~ATOM_S0_DFP5
;
1330 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
1331 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
1335 if (rdev
->family
>= CHIP_R600
) {
1336 WREG32(R600_BIOS_0_SCRATCH
, bios_0_scratch
);
1337 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
1338 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1340 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
1341 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
1342 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1347 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
1349 struct drm_device
*dev
= encoder
->dev
;
1350 struct radeon_device
*rdev
= dev
->dev_private
;
1351 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1352 uint32_t bios_3_scratch
;
1354 if (rdev
->family
>= CHIP_R600
)
1355 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
1357 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
1359 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1360 bios_3_scratch
&= ~ATOM_S3_TV1_CRTC_ACTIVE
;
1361 bios_3_scratch
|= (crtc
<< 18);
1363 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1364 bios_3_scratch
&= ~ATOM_S3_CV_CRTC_ACTIVE
;
1365 bios_3_scratch
|= (crtc
<< 24);
1367 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1368 bios_3_scratch
&= ~ATOM_S3_CRT1_CRTC_ACTIVE
;
1369 bios_3_scratch
|= (crtc
<< 16);
1371 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1372 bios_3_scratch
&= ~ATOM_S3_CRT2_CRTC_ACTIVE
;
1373 bios_3_scratch
|= (crtc
<< 20);
1375 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1376 bios_3_scratch
&= ~ATOM_S3_LCD1_CRTC_ACTIVE
;
1377 bios_3_scratch
|= (crtc
<< 17);
1379 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
1380 bios_3_scratch
&= ~ATOM_S3_DFP1_CRTC_ACTIVE
;
1381 bios_3_scratch
|= (crtc
<< 19);
1383 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
1384 bios_3_scratch
&= ~ATOM_S3_DFP2_CRTC_ACTIVE
;
1385 bios_3_scratch
|= (crtc
<< 23);
1387 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
1388 bios_3_scratch
&= ~ATOM_S3_DFP3_CRTC_ACTIVE
;
1389 bios_3_scratch
|= (crtc
<< 25);
1392 if (rdev
->family
>= CHIP_R600
)
1393 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
1395 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
1399 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
1401 struct drm_device
*dev
= encoder
->dev
;
1402 struct radeon_device
*rdev
= dev
->dev_private
;
1403 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1404 uint32_t bios_2_scratch
;
1406 if (rdev
->family
>= CHIP_R600
)
1407 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
1409 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
1411 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1413 bios_2_scratch
&= ~ATOM_S2_TV1_DPMS_STATE
;
1415 bios_2_scratch
|= ATOM_S2_TV1_DPMS_STATE
;
1417 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1419 bios_2_scratch
&= ~ATOM_S2_CV_DPMS_STATE
;
1421 bios_2_scratch
|= ATOM_S2_CV_DPMS_STATE
;
1423 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1425 bios_2_scratch
&= ~ATOM_S2_CRT1_DPMS_STATE
;
1427 bios_2_scratch
|= ATOM_S2_CRT1_DPMS_STATE
;
1429 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1431 bios_2_scratch
&= ~ATOM_S2_CRT2_DPMS_STATE
;
1433 bios_2_scratch
|= ATOM_S2_CRT2_DPMS_STATE
;
1435 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1437 bios_2_scratch
&= ~ATOM_S2_LCD1_DPMS_STATE
;
1439 bios_2_scratch
|= ATOM_S2_LCD1_DPMS_STATE
;
1441 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
1443 bios_2_scratch
&= ~ATOM_S2_DFP1_DPMS_STATE
;
1445 bios_2_scratch
|= ATOM_S2_DFP1_DPMS_STATE
;
1447 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
1449 bios_2_scratch
&= ~ATOM_S2_DFP2_DPMS_STATE
;
1451 bios_2_scratch
|= ATOM_S2_DFP2_DPMS_STATE
;
1453 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
1455 bios_2_scratch
&= ~ATOM_S2_DFP3_DPMS_STATE
;
1457 bios_2_scratch
|= ATOM_S2_DFP3_DPMS_STATE
;
1459 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) {
1461 bios_2_scratch
&= ~ATOM_S2_DFP4_DPMS_STATE
;
1463 bios_2_scratch
|= ATOM_S2_DFP4_DPMS_STATE
;
1465 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) {
1467 bios_2_scratch
&= ~ATOM_S2_DFP5_DPMS_STATE
;
1469 bios_2_scratch
|= ATOM_S2_DFP5_DPMS_STATE
;
1472 if (rdev
->family
>= CHIP_R600
)
1473 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
1475 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);