2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/radeon_drm.h>
31 #include "atom-bits.h"
34 radeon_add_atom_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
35 uint32_t supported_device
, u16 caps
);
37 /* from radeon_legacy_encoder.c */
39 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
40 uint32_t supported_device
);
42 union atom_supported_devices
{
43 struct _ATOM_SUPPORTED_DEVICES_INFO info
;
44 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2
;
45 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1
;
48 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device
*rdev
,
49 ATOM_GPIO_I2C_ASSIGMENT
*gpio
,
52 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
53 if ((rdev
->family
== CHIP_R420
) ||
54 (rdev
->family
== CHIP_R423
) ||
55 (rdev
->family
== CHIP_RV410
)) {
56 if ((le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x0018) ||
57 (le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x0019) ||
58 (le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x001a)) {
59 gpio
->ucClkMaskShift
= 0x19;
60 gpio
->ucDataMaskShift
= 0x18;
64 /* some evergreen boards have bad data for this entry */
65 if (ASIC_IS_DCE4(rdev
)) {
67 (le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x1936) &&
68 (gpio
->sucI2cId
.ucAccess
== 0)) {
69 gpio
->sucI2cId
.ucAccess
= 0x97;
70 gpio
->ucDataMaskShift
= 8;
71 gpio
->ucDataEnShift
= 8;
72 gpio
->ucDataY_Shift
= 8;
73 gpio
->ucDataA_Shift
= 8;
77 /* some DCE3 boards have bad data for this entry */
78 if (ASIC_IS_DCE3(rdev
)) {
80 (le16_to_cpu(gpio
->usClkMaskRegisterIndex
) == 0x1fda) &&
81 (gpio
->sucI2cId
.ucAccess
== 0x94))
82 gpio
->sucI2cId
.ucAccess
= 0x14;
86 static struct radeon_i2c_bus_rec
radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT
*gpio
)
88 struct radeon_i2c_bus_rec i2c
;
90 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
92 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
) * 4;
93 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
) * 4;
94 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
) * 4;
95 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
) * 4;
96 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
) * 4;
97 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
) * 4;
98 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
) * 4;
99 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
) * 4;
100 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
101 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
102 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
103 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
104 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
105 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
106 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
107 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
109 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
110 i2c
.hw_capable
= true;
112 i2c
.hw_capable
= false;
114 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
119 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
121 if (i2c
.mask_clk_reg
)
129 static struct radeon_i2c_bus_rec
radeon_lookup_i2c_gpio(struct radeon_device
*rdev
,
132 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
133 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
134 struct radeon_i2c_bus_rec i2c
;
135 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
136 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
137 uint16_t data_offset
, size
;
140 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
143 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
144 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
146 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
147 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
149 gpio
= &i2c_info
->asGPIO_Info
[0];
150 for (i
= 0; i
< num_indices
; i
++) {
152 radeon_lookup_i2c_gpio_quirks(rdev
, gpio
, i
);
154 if (gpio
->sucI2cId
.ucAccess
== id
) {
155 i2c
= radeon_get_bus_rec_for_i2c_gpio(gpio
);
158 gpio
= (ATOM_GPIO_I2C_ASSIGMENT
*)
159 ((u8
*)gpio
+ sizeof(ATOM_GPIO_I2C_ASSIGMENT
));
166 void radeon_atombios_i2c_init(struct radeon_device
*rdev
)
168 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
169 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
170 struct radeon_i2c_bus_rec i2c
;
171 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
172 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
173 uint16_t data_offset
, size
;
177 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
178 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
180 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
181 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
183 gpio
= &i2c_info
->asGPIO_Info
[0];
184 for (i
= 0; i
< num_indices
; i
++) {
185 radeon_lookup_i2c_gpio_quirks(rdev
, gpio
, i
);
187 i2c
= radeon_get_bus_rec_for_i2c_gpio(gpio
);
190 sprintf(stmp
, "0x%x", i2c
.i2c_id
);
191 rdev
->i2c_bus
[i
] = radeon_i2c_create(rdev
->ddev
, &i2c
, stmp
);
193 gpio
= (ATOM_GPIO_I2C_ASSIGMENT
*)
194 ((u8
*)gpio
+ sizeof(ATOM_GPIO_I2C_ASSIGMENT
));
199 struct radeon_gpio_rec
radeon_atombios_lookup_gpio(struct radeon_device
*rdev
,
202 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
203 struct radeon_gpio_rec gpio
;
204 int index
= GetIndexIntoMasterTable(DATA
, GPIO_Pin_LUT
);
205 struct _ATOM_GPIO_PIN_LUT
*gpio_info
;
206 ATOM_GPIO_PIN_ASSIGNMENT
*pin
;
207 u16 data_offset
, size
;
210 memset(&gpio
, 0, sizeof(struct radeon_gpio_rec
));
213 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
214 gpio_info
= (struct _ATOM_GPIO_PIN_LUT
*)(ctx
->bios
+ data_offset
);
216 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
217 sizeof(ATOM_GPIO_PIN_ASSIGNMENT
);
219 pin
= gpio_info
->asGPIO_Pin
;
220 for (i
= 0; i
< num_indices
; i
++) {
221 if (id
== pin
->ucGPIO_ID
) {
222 gpio
.id
= pin
->ucGPIO_ID
;
223 gpio
.reg
= le16_to_cpu(pin
->usGpioPin_AIndex
) * 4;
224 gpio
.shift
= pin
->ucGpioPinBitShift
;
225 gpio
.mask
= (1 << pin
->ucGpioPinBitShift
);
229 pin
= (ATOM_GPIO_PIN_ASSIGNMENT
*)
230 ((u8
*)pin
+ sizeof(ATOM_GPIO_PIN_ASSIGNMENT
));
237 static struct radeon_hpd
radeon_atom_get_hpd_info_from_gpio(struct radeon_device
*rdev
,
238 struct radeon_gpio_rec
*gpio
)
240 struct radeon_hpd hpd
;
243 memset(&hpd
, 0, sizeof(struct radeon_hpd
));
245 if (ASIC_IS_DCE6(rdev
))
246 reg
= SI_DC_GPIO_HPD_A
;
247 else if (ASIC_IS_DCE4(rdev
))
248 reg
= EVERGREEN_DC_GPIO_HPD_A
;
250 reg
= AVIVO_DC_GPIO_HPD_A
;
253 if (gpio
->reg
== reg
) {
256 hpd
.hpd
= RADEON_HPD_1
;
259 hpd
.hpd
= RADEON_HPD_2
;
262 hpd
.hpd
= RADEON_HPD_3
;
265 hpd
.hpd
= RADEON_HPD_4
;
268 hpd
.hpd
= RADEON_HPD_5
;
271 hpd
.hpd
= RADEON_HPD_6
;
274 hpd
.hpd
= RADEON_HPD_NONE
;
278 hpd
.hpd
= RADEON_HPD_NONE
;
282 static bool radeon_atom_apply_quirks(struct drm_device
*dev
,
283 uint32_t supported_device
,
285 struct radeon_i2c_bus_rec
*i2c_bus
,
287 struct radeon_hpd
*hpd
)
290 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
291 if ((dev
->pdev
->device
== 0x791e) &&
292 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
293 (dev
->pdev
->subsystem_device
== 0x826d)) {
294 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
295 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
296 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
299 /* Asrock RS600 board lists the DVI port as HDMI */
300 if ((dev
->pdev
->device
== 0x7941) &&
301 (dev
->pdev
->subsystem_vendor
== 0x1849) &&
302 (dev
->pdev
->subsystem_device
== 0x7941)) {
303 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
304 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
305 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
308 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
309 if ((dev
->pdev
->device
== 0x796e) &&
310 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
311 (dev
->pdev
->subsystem_device
== 0x7302)) {
312 if ((supported_device
== ATOM_DEVICE_DFP2_SUPPORT
) ||
313 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
317 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
318 if ((dev
->pdev
->device
== 0x7941) &&
319 (dev
->pdev
->subsystem_vendor
== 0x147b) &&
320 (dev
->pdev
->subsystem_device
== 0x2412)) {
321 if (*connector_type
== DRM_MODE_CONNECTOR_DVII
)
325 /* Falcon NW laptop lists vga ddc line for LVDS */
326 if ((dev
->pdev
->device
== 0x5653) &&
327 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
328 (dev
->pdev
->subsystem_device
== 0x0291)) {
329 if (*connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
330 i2c_bus
->valid
= false;
335 /* HIS X1300 is DVI+VGA, not DVI+DVI */
336 if ((dev
->pdev
->device
== 0x7146) &&
337 (dev
->pdev
->subsystem_vendor
== 0x17af) &&
338 (dev
->pdev
->subsystem_device
== 0x2058)) {
339 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
343 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
344 if ((dev
->pdev
->device
== 0x7142) &&
345 (dev
->pdev
->subsystem_vendor
== 0x1458) &&
346 (dev
->pdev
->subsystem_device
== 0x2134)) {
347 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
353 if ((dev
->pdev
->device
== 0x71C5) &&
354 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
355 (dev
->pdev
->subsystem_device
== 0x0080)) {
356 if ((supported_device
== ATOM_DEVICE_CRT1_SUPPORT
) ||
357 (supported_device
== ATOM_DEVICE_DFP2_SUPPORT
))
359 if (supported_device
== ATOM_DEVICE_CRT2_SUPPORT
)
363 /* mac rv630, rv730, others */
364 if ((supported_device
== ATOM_DEVICE_TV1_SUPPORT
) &&
365 (*connector_type
== DRM_MODE_CONNECTOR_DVII
)) {
366 *connector_type
= DRM_MODE_CONNECTOR_9PinDIN
;
367 *line_mux
= CONNECTOR_7PIN_DIN_ENUM_ID1
;
370 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
371 if ((dev
->pdev
->device
== 0x9598) &&
372 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
373 (dev
->pdev
->subsystem_device
== 0x01da)) {
374 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
375 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
379 /* ASUS HD 3600 board lists the DVI port as HDMI */
380 if ((dev
->pdev
->device
== 0x9598) &&
381 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
382 (dev
->pdev
->subsystem_device
== 0x01e4)) {
383 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
384 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
388 /* ASUS HD 3450 board lists the DVI port as HDMI */
389 if ((dev
->pdev
->device
== 0x95C5) &&
390 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
391 (dev
->pdev
->subsystem_device
== 0x01e2)) {
392 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
393 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
397 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
398 * HDMI + VGA reporting as HDMI
400 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
401 if (supported_device
& (ATOM_DEVICE_CRT_SUPPORT
)) {
402 *connector_type
= DRM_MODE_CONNECTOR_VGA
;
407 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
408 * on the laptop and a DVI port on the docking station and
409 * both share the same encoder, hpd pin, and ddc line.
410 * So while the bios table is technically correct,
411 * we drop the DVI port here since xrandr has no concept of
412 * encoders and will try and drive both connectors
413 * with different crtcs which isn't possible on the hardware
414 * side and leaves no crtcs for LVDS or VGA.
416 if (((dev
->pdev
->device
== 0x95c4) || (dev
->pdev
->device
== 0x9591)) &&
417 (dev
->pdev
->subsystem_vendor
== 0x1025) &&
418 (dev
->pdev
->subsystem_device
== 0x013c)) {
419 if ((*connector_type
== DRM_MODE_CONNECTOR_DVII
) &&
420 (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)) {
421 /* actually it's a DVI-D port not DVI-I */
422 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
427 /* XFX Pine Group device rv730 reports no VGA DDC lines
428 * even though they are wired up to record 0x93
430 if ((dev
->pdev
->device
== 0x9498) &&
431 (dev
->pdev
->subsystem_vendor
== 0x1682) &&
432 (dev
->pdev
->subsystem_device
== 0x2452) &&
433 (i2c_bus
->valid
== false) &&
434 !(supported_device
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))) {
435 struct radeon_device
*rdev
= dev
->dev_private
;
436 *i2c_bus
= radeon_lookup_i2c_gpio(rdev
, 0x93);
439 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
440 if (((dev
->pdev
->device
== 0x9802) ||
441 (dev
->pdev
->device
== 0x9805) ||
442 (dev
->pdev
->device
== 0x9806)) &&
443 (dev
->pdev
->subsystem_vendor
== 0x1734) &&
444 (dev
->pdev
->subsystem_device
== 0x11bd)) {
445 if (*connector_type
== DRM_MODE_CONNECTOR_VGA
) {
446 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
448 } else if (*connector_type
== DRM_MODE_CONNECTOR_DVID
) {
449 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
456 static const int supported_devices_connector_convert
[] = {
457 DRM_MODE_CONNECTOR_Unknown
,
458 DRM_MODE_CONNECTOR_VGA
,
459 DRM_MODE_CONNECTOR_DVII
,
460 DRM_MODE_CONNECTOR_DVID
,
461 DRM_MODE_CONNECTOR_DVIA
,
462 DRM_MODE_CONNECTOR_SVIDEO
,
463 DRM_MODE_CONNECTOR_Composite
,
464 DRM_MODE_CONNECTOR_LVDS
,
465 DRM_MODE_CONNECTOR_Unknown
,
466 DRM_MODE_CONNECTOR_Unknown
,
467 DRM_MODE_CONNECTOR_HDMIA
,
468 DRM_MODE_CONNECTOR_HDMIB
,
469 DRM_MODE_CONNECTOR_Unknown
,
470 DRM_MODE_CONNECTOR_Unknown
,
471 DRM_MODE_CONNECTOR_9PinDIN
,
472 DRM_MODE_CONNECTOR_DisplayPort
475 static const uint16_t supported_devices_connector_object_id_convert
[] = {
476 CONNECTOR_OBJECT_ID_NONE
,
477 CONNECTOR_OBJECT_ID_VGA
,
478 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
, /* not all boards support DL */
479 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
, /* not all boards support DL */
480 CONNECTOR_OBJECT_ID_VGA
, /* technically DVI-A */
481 CONNECTOR_OBJECT_ID_COMPOSITE
,
482 CONNECTOR_OBJECT_ID_SVIDEO
,
483 CONNECTOR_OBJECT_ID_LVDS
,
484 CONNECTOR_OBJECT_ID_9PIN_DIN
,
485 CONNECTOR_OBJECT_ID_9PIN_DIN
,
486 CONNECTOR_OBJECT_ID_DISPLAYPORT
,
487 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
,
488 CONNECTOR_OBJECT_ID_HDMI_TYPE_B
,
489 CONNECTOR_OBJECT_ID_SVIDEO
492 static const int object_connector_convert
[] = {
493 DRM_MODE_CONNECTOR_Unknown
,
494 DRM_MODE_CONNECTOR_DVII
,
495 DRM_MODE_CONNECTOR_DVII
,
496 DRM_MODE_CONNECTOR_DVID
,
497 DRM_MODE_CONNECTOR_DVID
,
498 DRM_MODE_CONNECTOR_VGA
,
499 DRM_MODE_CONNECTOR_Composite
,
500 DRM_MODE_CONNECTOR_SVIDEO
,
501 DRM_MODE_CONNECTOR_Unknown
,
502 DRM_MODE_CONNECTOR_Unknown
,
503 DRM_MODE_CONNECTOR_9PinDIN
,
504 DRM_MODE_CONNECTOR_Unknown
,
505 DRM_MODE_CONNECTOR_HDMIA
,
506 DRM_MODE_CONNECTOR_HDMIB
,
507 DRM_MODE_CONNECTOR_LVDS
,
508 DRM_MODE_CONNECTOR_9PinDIN
,
509 DRM_MODE_CONNECTOR_Unknown
,
510 DRM_MODE_CONNECTOR_Unknown
,
511 DRM_MODE_CONNECTOR_Unknown
,
512 DRM_MODE_CONNECTOR_DisplayPort
,
513 DRM_MODE_CONNECTOR_eDP
,
514 DRM_MODE_CONNECTOR_Unknown
517 bool radeon_get_atom_connector_info_from_object_table(struct drm_device
*dev
)
519 struct radeon_device
*rdev
= dev
->dev_private
;
520 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
521 struct atom_context
*ctx
= mode_info
->atom_context
;
522 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
523 u16 size
, data_offset
;
525 ATOM_CONNECTOR_OBJECT_TABLE
*con_obj
;
526 ATOM_ENCODER_OBJECT_TABLE
*enc_obj
;
527 ATOM_OBJECT_TABLE
*router_obj
;
528 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
529 ATOM_OBJECT_HEADER
*obj_header
;
530 int i
, j
, k
, path_size
, device_support
;
532 u16 igp_lane_info
, conn_id
, connector_object_id
;
533 struct radeon_i2c_bus_rec ddc_bus
;
534 struct radeon_router router
;
535 struct radeon_gpio_rec gpio
;
536 struct radeon_hpd hpd
;
538 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
))
544 obj_header
= (ATOM_OBJECT_HEADER
*) (ctx
->bios
+ data_offset
);
545 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
546 (ctx
->bios
+ data_offset
+
547 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
548 con_obj
= (ATOM_CONNECTOR_OBJECT_TABLE
*)
549 (ctx
->bios
+ data_offset
+
550 le16_to_cpu(obj_header
->usConnectorObjectTableOffset
));
551 enc_obj
= (ATOM_ENCODER_OBJECT_TABLE
*)
552 (ctx
->bios
+ data_offset
+
553 le16_to_cpu(obj_header
->usEncoderObjectTableOffset
));
554 router_obj
= (ATOM_OBJECT_TABLE
*)
555 (ctx
->bios
+ data_offset
+
556 le16_to_cpu(obj_header
->usRouterObjectTableOffset
));
557 device_support
= le16_to_cpu(obj_header
->usDeviceSupport
);
560 for (i
= 0; i
< path_obj
->ucNumOfDispPath
; i
++) {
561 uint8_t *addr
= (uint8_t *) path_obj
->asDispPath
;
562 ATOM_DISPLAY_OBJECT_PATH
*path
;
564 path
= (ATOM_DISPLAY_OBJECT_PATH
*) addr
;
565 path_size
+= le16_to_cpu(path
->usSize
);
567 if (device_support
& le16_to_cpu(path
->usDeviceTag
)) {
568 uint8_t con_obj_id
, con_obj_num
, con_obj_type
;
571 (le16_to_cpu(path
->usConnObjectId
) & OBJECT_ID_MASK
)
574 (le16_to_cpu(path
->usConnObjectId
) & ENUM_ID_MASK
)
577 (le16_to_cpu(path
->usConnObjectId
) &
578 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
580 /* TODO CV support */
581 if (le16_to_cpu(path
->usDeviceTag
) ==
582 ATOM_DEVICE_CV_SUPPORT
)
586 if ((rdev
->flags
& RADEON_IS_IGP
) &&
588 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR
)) {
589 uint16_t igp_offset
= 0;
590 ATOM_INTEGRATED_SYSTEM_INFO_V2
*igp_obj
;
593 GetIndexIntoMasterTable(DATA
,
594 IntegratedSystemInfo
);
596 if (atom_parse_data_header(ctx
, index
, &size
, &frev
,
597 &crev
, &igp_offset
)) {
601 (ATOM_INTEGRATED_SYSTEM_INFO_V2
602 *) (ctx
->bios
+ igp_offset
);
605 uint32_t slot_config
, ct
;
607 if (con_obj_num
== 1)
616 ct
= (slot_config
>> 16) & 0xff;
618 object_connector_convert
620 connector_object_id
= ct
;
622 slot_config
& 0xffff;
630 object_connector_convert
[con_obj_id
];
631 connector_object_id
= con_obj_id
;
636 object_connector_convert
[con_obj_id
];
637 connector_object_id
= con_obj_id
;
640 if (connector_type
== DRM_MODE_CONNECTOR_Unknown
)
643 router
.ddc_valid
= false;
644 router
.cd_valid
= false;
645 for (j
= 0; j
< ((le16_to_cpu(path
->usSize
) - 8) / 2); j
++) {
646 uint8_t grph_obj_id
, grph_obj_num
, grph_obj_type
;
649 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
650 OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
652 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
653 ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
655 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
656 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
658 if (grph_obj_type
== GRAPH_OBJECT_TYPE_ENCODER
) {
659 for (k
= 0; k
< enc_obj
->ucNumberOfObjects
; k
++) {
660 u16 encoder_obj
= le16_to_cpu(enc_obj
->asObjects
[k
].usObjectID
);
661 if (le16_to_cpu(path
->usGraphicObjIds
[j
]) == encoder_obj
) {
662 ATOM_COMMON_RECORD_HEADER
*record
= (ATOM_COMMON_RECORD_HEADER
*)
663 (ctx
->bios
+ data_offset
+
664 le16_to_cpu(enc_obj
->asObjects
[k
].usRecordOffset
));
665 ATOM_ENCODER_CAP_RECORD
*cap_record
;
668 while (record
->ucRecordSize
> 0 &&
669 record
->ucRecordType
> 0 &&
670 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
671 switch (record
->ucRecordType
) {
672 case ATOM_ENCODER_CAP_RECORD_TYPE
:
673 cap_record
=(ATOM_ENCODER_CAP_RECORD
*)
675 caps
= le16_to_cpu(cap_record
->usEncoderCap
);
678 record
= (ATOM_COMMON_RECORD_HEADER
*)
679 ((char *)record
+ record
->ucRecordSize
);
681 radeon_add_atom_encoder(dev
,
689 } else if (grph_obj_type
== GRAPH_OBJECT_TYPE_ROUTER
) {
690 for (k
= 0; k
< router_obj
->ucNumberOfObjects
; k
++) {
691 u16 router_obj_id
= le16_to_cpu(router_obj
->asObjects
[k
].usObjectID
);
692 if (le16_to_cpu(path
->usGraphicObjIds
[j
]) == router_obj_id
) {
693 ATOM_COMMON_RECORD_HEADER
*record
= (ATOM_COMMON_RECORD_HEADER
*)
694 (ctx
->bios
+ data_offset
+
695 le16_to_cpu(router_obj
->asObjects
[k
].usRecordOffset
));
696 ATOM_I2C_RECORD
*i2c_record
;
697 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
698 ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*ddc_path
;
699 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
*cd_path
;
700 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*router_src_dst_table
=
701 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*)
702 (ctx
->bios
+ data_offset
+
703 le16_to_cpu(router_obj
->asObjects
[k
].usSrcDstTableOffset
));
704 u8
*num_dst_objs
= (u8
*)
705 ((u8
*)router_src_dst_table
+ 1 +
706 (router_src_dst_table
->ucNumberOfSrc
* 2));
707 u16
*dst_objs
= (u16
*)(num_dst_objs
+ 1);
710 router
.router_id
= router_obj_id
;
711 for (enum_id
= 0; enum_id
< (*num_dst_objs
); enum_id
++) {
712 if (le16_to_cpu(path
->usConnObjectId
) ==
713 le16_to_cpu(dst_objs
[enum_id
]))
717 while (record
->ucRecordSize
> 0 &&
718 record
->ucRecordType
> 0 &&
719 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
720 switch (record
->ucRecordType
) {
721 case ATOM_I2C_RECORD_TYPE
:
726 (ATOM_I2C_ID_CONFIG_ACCESS
*)
727 &i2c_record
->sucI2cId
;
729 radeon_lookup_i2c_gpio(rdev
,
732 router
.i2c_addr
= i2c_record
->ucI2CAddr
>> 1;
734 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE
:
735 ddc_path
= (ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*)
737 router
.ddc_valid
= true;
738 router
.ddc_mux_type
= ddc_path
->ucMuxType
;
739 router
.ddc_mux_control_pin
= ddc_path
->ucMuxControlPin
;
740 router
.ddc_mux_state
= ddc_path
->ucMuxState
[enum_id
];
742 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE
:
743 cd_path
= (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
*)
745 router
.cd_valid
= true;
746 router
.cd_mux_type
= cd_path
->ucMuxType
;
747 router
.cd_mux_control_pin
= cd_path
->ucMuxControlPin
;
748 router
.cd_mux_state
= cd_path
->ucMuxState
[enum_id
];
751 record
= (ATOM_COMMON_RECORD_HEADER
*)
752 ((char *)record
+ record
->ucRecordSize
);
759 /* look up gpio for ddc, hpd */
760 ddc_bus
.valid
= false;
761 hpd
.hpd
= RADEON_HPD_NONE
;
762 if ((le16_to_cpu(path
->usDeviceTag
) &
763 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) == 0) {
764 for (j
= 0; j
< con_obj
->ucNumberOfObjects
; j
++) {
765 if (le16_to_cpu(path
->usConnObjectId
) ==
766 le16_to_cpu(con_obj
->asObjects
[j
].
768 ATOM_COMMON_RECORD_HEADER
770 (ATOM_COMMON_RECORD_HEADER
772 (ctx
->bios
+ data_offset
+
773 le16_to_cpu(con_obj
->
776 ATOM_I2C_RECORD
*i2c_record
;
777 ATOM_HPD_INT_RECORD
*hpd_record
;
778 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
780 while (record
->ucRecordSize
> 0 &&
781 record
->ucRecordType
> 0 &&
782 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
783 switch (record
->ucRecordType
) {
784 case ATOM_I2C_RECORD_TYPE
:
789 (ATOM_I2C_ID_CONFIG_ACCESS
*)
790 &i2c_record
->sucI2cId
;
791 ddc_bus
= radeon_lookup_i2c_gpio(rdev
,
795 case ATOM_HPD_INT_RECORD_TYPE
:
797 (ATOM_HPD_INT_RECORD
*)
799 gpio
= radeon_atombios_lookup_gpio(rdev
,
800 hpd_record
->ucHPDIntGPIOID
);
801 hpd
= radeon_atom_get_hpd_info_from_gpio(rdev
, &gpio
);
802 hpd
.plugged_state
= hpd_record
->ucPlugged_PinState
;
806 (ATOM_COMMON_RECORD_HEADER
817 /* needed for aux chan transactions */
818 ddc_bus
.hpd
= hpd
.hpd
;
820 conn_id
= le16_to_cpu(path
->usConnObjectId
);
822 if (!radeon_atom_apply_quirks
823 (dev
, le16_to_cpu(path
->usDeviceTag
), &connector_type
,
824 &ddc_bus
, &conn_id
, &hpd
))
827 radeon_add_atom_connector(dev
,
831 connector_type
, &ddc_bus
,
840 radeon_link_encoder_connector(dev
);
842 radeon_setup_mst_connector(dev
);
846 static uint16_t atombios_get_connector_object_id(struct drm_device
*dev
,
850 struct radeon_device
*rdev
= dev
->dev_private
;
852 if (rdev
->flags
& RADEON_IS_IGP
) {
853 return supported_devices_connector_object_id_convert
855 } else if (((connector_type
== DRM_MODE_CONNECTOR_DVII
) ||
856 (connector_type
== DRM_MODE_CONNECTOR_DVID
)) &&
857 (devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
858 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
859 struct atom_context
*ctx
= mode_info
->atom_context
;
860 int index
= GetIndexIntoMasterTable(DATA
, XTMDS_Info
);
861 uint16_t size
, data_offset
;
863 ATOM_XTMDS_INFO
*xtmds
;
865 if (atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
)) {
866 xtmds
= (ATOM_XTMDS_INFO
*)(ctx
->bios
+ data_offset
);
868 if (xtmds
->ucSupportedLink
& ATOM_XTMDS_SUPPORTED_DUALLINK
) {
869 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
870 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
872 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
874 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
875 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
877 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
880 return supported_devices_connector_object_id_convert
883 return supported_devices_connector_object_id_convert
888 struct bios_connector
{
893 struct radeon_i2c_bus_rec ddc_bus
;
894 struct radeon_hpd hpd
;
897 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
901 struct radeon_device
*rdev
= dev
->dev_private
;
902 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
903 struct atom_context
*ctx
= mode_info
->atom_context
;
904 int index
= GetIndexIntoMasterTable(DATA
, SupportedDevicesInfo
);
905 uint16_t size
, data_offset
;
907 uint16_t device_support
;
909 union atom_supported_devices
*supported_devices
;
910 int i
, j
, max_device
;
911 struct bios_connector
*bios_connectors
;
912 size_t bc_size
= sizeof(*bios_connectors
) * ATOM_MAX_SUPPORTED_DEVICE
;
913 struct radeon_router router
;
915 router
.ddc_valid
= false;
916 router
.cd_valid
= false;
918 bios_connectors
= kzalloc(bc_size
, GFP_KERNEL
);
919 if (!bios_connectors
)
922 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
,
924 kfree(bios_connectors
);
929 (union atom_supported_devices
*)(ctx
->bios
+ data_offset
);
931 device_support
= le16_to_cpu(supported_devices
->info
.usDeviceSupport
);
934 max_device
= ATOM_MAX_SUPPORTED_DEVICE
;
936 max_device
= ATOM_MAX_SUPPORTED_DEVICE_INFO
;
938 for (i
= 0; i
< max_device
; i
++) {
939 ATOM_CONNECTOR_INFO_I2C ci
=
940 supported_devices
->info
.asConnInfo
[i
];
942 bios_connectors
[i
].valid
= false;
944 if (!(device_support
& (1 << i
))) {
948 if (i
== ATOM_DEVICE_CV_INDEX
) {
949 DRM_DEBUG_KMS("Skipping Component Video\n");
953 bios_connectors
[i
].connector_type
=
954 supported_devices_connector_convert
[ci
.sucConnectorInfo
.
958 if (bios_connectors
[i
].connector_type
==
959 DRM_MODE_CONNECTOR_Unknown
)
962 dac
= ci
.sucConnectorInfo
.sbfAccess
.bfAssociatedDAC
;
964 bios_connectors
[i
].line_mux
=
965 ci
.sucI2cId
.ucAccess
;
967 /* give tv unique connector ids */
968 if (i
== ATOM_DEVICE_TV1_INDEX
) {
969 bios_connectors
[i
].ddc_bus
.valid
= false;
970 bios_connectors
[i
].line_mux
= 50;
971 } else if (i
== ATOM_DEVICE_TV2_INDEX
) {
972 bios_connectors
[i
].ddc_bus
.valid
= false;
973 bios_connectors
[i
].line_mux
= 51;
974 } else if (i
== ATOM_DEVICE_CV_INDEX
) {
975 bios_connectors
[i
].ddc_bus
.valid
= false;
976 bios_connectors
[i
].line_mux
= 52;
978 bios_connectors
[i
].ddc_bus
=
979 radeon_lookup_i2c_gpio(rdev
,
980 bios_connectors
[i
].line_mux
);
982 if ((crev
> 1) && (frev
> 1)) {
983 u8 isb
= supported_devices
->info_2d1
.asIntSrcInfo
[i
].ucIntSrcBitmap
;
986 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
989 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
992 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
996 if (i
== ATOM_DEVICE_DFP1_INDEX
)
997 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
998 else if (i
== ATOM_DEVICE_DFP2_INDEX
)
999 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
1001 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
1004 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1005 * shared with a DVI port, we'll pick up the DVI connector when we
1006 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1008 if (i
== ATOM_DEVICE_CRT1_INDEX
|| i
== ATOM_DEVICE_CRT2_INDEX
)
1009 bios_connectors
[i
].connector_type
=
1010 DRM_MODE_CONNECTOR_VGA
;
1012 if (!radeon_atom_apply_quirks
1013 (dev
, (1 << i
), &bios_connectors
[i
].connector_type
,
1014 &bios_connectors
[i
].ddc_bus
, &bios_connectors
[i
].line_mux
,
1015 &bios_connectors
[i
].hpd
))
1018 bios_connectors
[i
].valid
= true;
1019 bios_connectors
[i
].devices
= (1 << i
);
1021 if (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
)
1022 radeon_add_atom_encoder(dev
,
1023 radeon_get_encoder_enum(dev
,
1029 radeon_add_legacy_encoder(dev
,
1030 radeon_get_encoder_enum(dev
,
1036 /* combine shared connectors */
1037 for (i
= 0; i
< max_device
; i
++) {
1038 if (bios_connectors
[i
].valid
) {
1039 for (j
= 0; j
< max_device
; j
++) {
1040 if (bios_connectors
[j
].valid
&& (i
!= j
)) {
1041 if (bios_connectors
[i
].line_mux
==
1042 bios_connectors
[j
].line_mux
) {
1043 /* make sure not to combine LVDS */
1044 if (bios_connectors
[i
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1045 bios_connectors
[i
].line_mux
= 53;
1046 bios_connectors
[i
].ddc_bus
.valid
= false;
1049 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1050 bios_connectors
[j
].line_mux
= 53;
1051 bios_connectors
[j
].ddc_bus
.valid
= false;
1054 /* combine analog and digital for DVI-I */
1055 if (((bios_connectors
[i
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
1056 (bios_connectors
[j
].devices
& (ATOM_DEVICE_CRT_SUPPORT
))) ||
1057 ((bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
1058 (bios_connectors
[i
].devices
& (ATOM_DEVICE_CRT_SUPPORT
)))) {
1059 bios_connectors
[i
].devices
|=
1060 bios_connectors
[j
].devices
;
1061 bios_connectors
[i
].connector_type
=
1062 DRM_MODE_CONNECTOR_DVII
;
1063 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
))
1064 bios_connectors
[i
].hpd
=
1065 bios_connectors
[j
].hpd
;
1066 bios_connectors
[j
].valid
= false;
1074 /* add the connectors */
1075 for (i
= 0; i
< max_device
; i
++) {
1076 if (bios_connectors
[i
].valid
) {
1077 uint16_t connector_object_id
=
1078 atombios_get_connector_object_id(dev
,
1079 bios_connectors
[i
].connector_type
,
1080 bios_connectors
[i
].devices
);
1081 radeon_add_atom_connector(dev
,
1082 bios_connectors
[i
].line_mux
,
1083 bios_connectors
[i
].devices
,
1086 &bios_connectors
[i
].ddc_bus
,
1088 connector_object_id
,
1089 &bios_connectors
[i
].hpd
,
1094 radeon_link_encoder_connector(dev
);
1096 kfree(bios_connectors
);
1100 union firmware_info
{
1101 ATOM_FIRMWARE_INFO info
;
1102 ATOM_FIRMWARE_INFO_V1_2 info_12
;
1103 ATOM_FIRMWARE_INFO_V1_3 info_13
;
1104 ATOM_FIRMWARE_INFO_V1_4 info_14
;
1105 ATOM_FIRMWARE_INFO_V2_1 info_21
;
1106 ATOM_FIRMWARE_INFO_V2_2 info_22
;
1110 struct _ATOM_INTEGRATED_SYSTEM_INFO info
;
1111 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2
;
1112 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6
;
1113 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7
;
1114 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8
;
1117 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device
*rdev
)
1119 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1120 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1121 union igp_info
*igp_info
;
1125 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1126 &frev
, &crev
, &data_offset
)) {
1127 igp_info
= (union igp_info
*)(mode_info
->atom_context
->bios
+
1129 rdev
->clock
.vco_freq
=
1130 le32_to_cpu(igp_info
->info_6
.ulDentistVCOFreq
);
1134 bool radeon_atom_get_clock_info(struct drm_device
*dev
)
1136 struct radeon_device
*rdev
= dev
->dev_private
;
1137 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1138 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
1139 union firmware_info
*firmware_info
;
1141 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
1142 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
1143 struct radeon_pll
*dcpll
= &rdev
->clock
.dcpll
;
1144 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
1145 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
1146 uint16_t data_offset
;
1148 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1149 &frev
, &crev
, &data_offset
)) {
1151 (union firmware_info
*)(mode_info
->atom_context
->bios
+
1154 p1pll
->reference_freq
=
1155 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1156 p1pll
->reference_div
= 0;
1159 p1pll
->pll_out_min
=
1160 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Output
);
1162 p1pll
->pll_out_min
=
1163 le32_to_cpu(firmware_info
->info_12
.ulMinPixelClockPLL_Output
);
1164 p1pll
->pll_out_max
=
1165 le32_to_cpu(firmware_info
->info
.ulMaxPixelClockPLL_Output
);
1168 p1pll
->lcd_pll_out_min
=
1169 le16_to_cpu(firmware_info
->info_14
.usLcdMinPixelClockPLL_Output
) * 100;
1170 if (p1pll
->lcd_pll_out_min
== 0)
1171 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1172 p1pll
->lcd_pll_out_max
=
1173 le16_to_cpu(firmware_info
->info_14
.usLcdMaxPixelClockPLL_Output
) * 100;
1174 if (p1pll
->lcd_pll_out_max
== 0)
1175 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1177 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1178 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1181 if (p1pll
->pll_out_min
== 0) {
1182 if (ASIC_IS_AVIVO(rdev
))
1183 p1pll
->pll_out_min
= 64800;
1185 p1pll
->pll_out_min
= 20000;
1189 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Input
);
1191 le16_to_cpu(firmware_info
->info
.usMaxPixelClockPLL_Input
);
1196 if (ASIC_IS_DCE4(rdev
))
1197 spll
->reference_freq
=
1198 le16_to_cpu(firmware_info
->info_21
.usCoreReferenceClock
);
1200 spll
->reference_freq
=
1201 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1202 spll
->reference_div
= 0;
1205 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Output
);
1207 le32_to_cpu(firmware_info
->info
.ulMaxEngineClockPLL_Output
);
1210 if (spll
->pll_out_min
== 0) {
1211 if (ASIC_IS_AVIVO(rdev
))
1212 spll
->pll_out_min
= 64800;
1214 spll
->pll_out_min
= 20000;
1218 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Input
);
1220 le16_to_cpu(firmware_info
->info
.usMaxEngineClockPLL_Input
);
1223 if (ASIC_IS_DCE4(rdev
))
1224 mpll
->reference_freq
=
1225 le16_to_cpu(firmware_info
->info_21
.usMemoryReferenceClock
);
1227 mpll
->reference_freq
=
1228 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1229 mpll
->reference_div
= 0;
1232 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Output
);
1234 le32_to_cpu(firmware_info
->info
.ulMaxMemoryClockPLL_Output
);
1237 if (mpll
->pll_out_min
== 0) {
1238 if (ASIC_IS_AVIVO(rdev
))
1239 mpll
->pll_out_min
= 64800;
1241 mpll
->pll_out_min
= 20000;
1245 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Input
);
1247 le16_to_cpu(firmware_info
->info
.usMaxMemoryClockPLL_Input
);
1249 rdev
->clock
.default_sclk
=
1250 le32_to_cpu(firmware_info
->info
.ulDefaultEngineClock
);
1251 rdev
->clock
.default_mclk
=
1252 le32_to_cpu(firmware_info
->info
.ulDefaultMemoryClock
);
1254 if (ASIC_IS_DCE4(rdev
)) {
1255 rdev
->clock
.default_dispclk
=
1256 le32_to_cpu(firmware_info
->info_21
.ulDefaultDispEngineClkFreq
);
1257 if (rdev
->clock
.default_dispclk
== 0) {
1258 if (ASIC_IS_DCE6(rdev
))
1259 rdev
->clock
.default_dispclk
= 60000; /* 600 Mhz */
1260 else if (ASIC_IS_DCE5(rdev
))
1261 rdev
->clock
.default_dispclk
= 54000; /* 540 Mhz */
1263 rdev
->clock
.default_dispclk
= 60000; /* 600 Mhz */
1265 /* set a reasonable default for DP */
1266 if (ASIC_IS_DCE6(rdev
) && (rdev
->clock
.default_dispclk
< 53900)) {
1267 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1268 rdev
->clock
.default_dispclk
/ 100);
1269 rdev
->clock
.default_dispclk
= 60000;
1271 rdev
->clock
.dp_extclk
=
1272 le16_to_cpu(firmware_info
->info_21
.usUniphyDPModeExtClkFreq
);
1273 rdev
->clock
.current_dispclk
= rdev
->clock
.default_dispclk
;
1277 rdev
->clock
.max_pixel_clock
= le16_to_cpu(firmware_info
->info
.usMaxPixelClock
);
1278 if (rdev
->clock
.max_pixel_clock
== 0)
1279 rdev
->clock
.max_pixel_clock
= 40000;
1281 /* not technically a clock, but... */
1282 rdev
->mode_info
.firmware_flags
=
1283 le16_to_cpu(firmware_info
->info
.usFirmwareCapability
.susAccess
);
1285 if (ASIC_IS_DCE8(rdev
))
1286 rdev
->clock
.vco_freq
=
1287 le32_to_cpu(firmware_info
->info_22
.ulGPUPLL_OutputFreq
);
1288 else if (ASIC_IS_DCE5(rdev
))
1289 rdev
->clock
.vco_freq
= rdev
->clock
.current_dispclk
;
1290 else if (ASIC_IS_DCE41(rdev
))
1291 radeon_atombios_get_dentist_vco_freq(rdev
);
1293 rdev
->clock
.vco_freq
= rdev
->clock
.current_dispclk
;
1295 if (rdev
->clock
.vco_freq
== 0)
1296 rdev
->clock
.vco_freq
= 360000; /* 3.6 GHz */
1304 bool radeon_atombios_sideport_present(struct radeon_device
*rdev
)
1306 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1307 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1308 union igp_info
*igp_info
;
1312 /* sideport is AMD only */
1313 if (rdev
->family
== CHIP_RS600
)
1316 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1317 &frev
, &crev
, &data_offset
)) {
1318 igp_info
= (union igp_info
*)(mode_info
->atom_context
->bios
+
1322 if (le32_to_cpu(igp_info
->info
.ulBootUpMemoryClock
))
1326 if (le32_to_cpu(igp_info
->info_2
.ulBootUpSidePortClock
))
1330 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
1337 bool radeon_atombios_get_tmds_info(struct radeon_encoder
*encoder
,
1338 struct radeon_encoder_int_tmds
*tmds
)
1340 struct drm_device
*dev
= encoder
->base
.dev
;
1341 struct radeon_device
*rdev
= dev
->dev_private
;
1342 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1343 int index
= GetIndexIntoMasterTable(DATA
, TMDS_Info
);
1344 uint16_t data_offset
;
1345 struct _ATOM_TMDS_INFO
*tmds_info
;
1350 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1351 &frev
, &crev
, &data_offset
)) {
1353 (struct _ATOM_TMDS_INFO
*)(mode_info
->atom_context
->bios
+
1356 maxfreq
= le16_to_cpu(tmds_info
->usMaxFrequency
);
1357 for (i
= 0; i
< 4; i
++) {
1358 tmds
->tmds_pll
[i
].freq
=
1359 le16_to_cpu(tmds_info
->asMiscInfo
[i
].usFrequency
);
1360 tmds
->tmds_pll
[i
].value
=
1361 tmds_info
->asMiscInfo
[i
].ucPLL_ChargePump
& 0x3f;
1362 tmds
->tmds_pll
[i
].value
|=
1363 (tmds_info
->asMiscInfo
[i
].
1364 ucPLL_VCO_Gain
& 0x3f) << 6;
1365 tmds
->tmds_pll
[i
].value
|=
1366 (tmds_info
->asMiscInfo
[i
].
1367 ucPLL_DutyCycle
& 0xf) << 12;
1368 tmds
->tmds_pll
[i
].value
|=
1369 (tmds_info
->asMiscInfo
[i
].
1370 ucPLL_VoltageSwing
& 0xf) << 16;
1372 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1373 tmds
->tmds_pll
[i
].freq
,
1374 tmds
->tmds_pll
[i
].value
);
1376 if (maxfreq
== tmds
->tmds_pll
[i
].freq
) {
1377 tmds
->tmds_pll
[i
].freq
= 0xffffffff;
1386 bool radeon_atombios_get_ppll_ss_info(struct radeon_device
*rdev
,
1387 struct radeon_atom_ss
*ss
,
1390 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1391 int index
= GetIndexIntoMasterTable(DATA
, PPLL_SS_Info
);
1392 uint16_t data_offset
, size
;
1393 struct _ATOM_SPREAD_SPECTRUM_INFO
*ss_info
;
1394 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
*ss_assign
;
1398 memset(ss
, 0, sizeof(struct radeon_atom_ss
));
1399 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1400 &frev
, &crev
, &data_offset
)) {
1402 (struct _ATOM_SPREAD_SPECTRUM_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1404 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1405 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT
);
1406 ss_assign
= (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
*)
1407 ((u8
*)&ss_info
->asSS_Info
[0]);
1408 for (i
= 0; i
< num_indices
; i
++) {
1409 if (ss_assign
->ucSS_Id
== id
) {
1411 le16_to_cpu(ss_assign
->usSpreadSpectrumPercentage
);
1412 ss
->type
= ss_assign
->ucSpreadSpectrumType
;
1413 ss
->step
= ss_assign
->ucSS_Step
;
1414 ss
->delay
= ss_assign
->ucSS_Delay
;
1415 ss
->range
= ss_assign
->ucSS_Range
;
1416 ss
->refdiv
= ss_assign
->ucRecommendedRef_Div
;
1419 ss_assign
= (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
*)
1420 ((u8
*)ss_assign
+ sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
));
1426 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device
*rdev
,
1427 struct radeon_atom_ss
*ss
,
1430 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1431 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1432 u16 data_offset
, size
;
1433 union igp_info
*igp_info
;
1435 u16 percentage
= 0, rate
= 0;
1437 /* get any igp specific overrides */
1438 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1439 &frev
, &crev
, &data_offset
)) {
1440 igp_info
= (union igp_info
*)
1441 (mode_info
->atom_context
->bios
+ data_offset
);
1445 case ASIC_INTERNAL_SS_ON_TMDS
:
1446 percentage
= le16_to_cpu(igp_info
->info_6
.usDVISSPercentage
);
1447 rate
= le16_to_cpu(igp_info
->info_6
.usDVISSpreadRateIn10Hz
);
1449 case ASIC_INTERNAL_SS_ON_HDMI
:
1450 percentage
= le16_to_cpu(igp_info
->info_6
.usHDMISSPercentage
);
1451 rate
= le16_to_cpu(igp_info
->info_6
.usHDMISSpreadRateIn10Hz
);
1453 case ASIC_INTERNAL_SS_ON_LVDS
:
1454 percentage
= le16_to_cpu(igp_info
->info_6
.usLvdsSSPercentage
);
1455 rate
= le16_to_cpu(igp_info
->info_6
.usLvdsSSpreadRateIn10Hz
);
1461 case ASIC_INTERNAL_SS_ON_TMDS
:
1462 percentage
= le16_to_cpu(igp_info
->info_7
.usDVISSPercentage
);
1463 rate
= le16_to_cpu(igp_info
->info_7
.usDVISSpreadRateIn10Hz
);
1465 case ASIC_INTERNAL_SS_ON_HDMI
:
1466 percentage
= le16_to_cpu(igp_info
->info_7
.usHDMISSPercentage
);
1467 rate
= le16_to_cpu(igp_info
->info_7
.usHDMISSpreadRateIn10Hz
);
1469 case ASIC_INTERNAL_SS_ON_LVDS
:
1470 percentage
= le16_to_cpu(igp_info
->info_7
.usLvdsSSPercentage
);
1471 rate
= le16_to_cpu(igp_info
->info_7
.usLvdsSSpreadRateIn10Hz
);
1477 case ASIC_INTERNAL_SS_ON_TMDS
:
1478 percentage
= le16_to_cpu(igp_info
->info_8
.usDVISSPercentage
);
1479 rate
= le16_to_cpu(igp_info
->info_8
.usDVISSpreadRateIn10Hz
);
1481 case ASIC_INTERNAL_SS_ON_HDMI
:
1482 percentage
= le16_to_cpu(igp_info
->info_8
.usHDMISSPercentage
);
1483 rate
= le16_to_cpu(igp_info
->info_8
.usHDMISSpreadRateIn10Hz
);
1485 case ASIC_INTERNAL_SS_ON_LVDS
:
1486 percentage
= le16_to_cpu(igp_info
->info_8
.usLvdsSSPercentage
);
1487 rate
= le16_to_cpu(igp_info
->info_8
.usLvdsSSpreadRateIn10Hz
);
1492 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
1496 ss
->percentage
= percentage
;
1502 union asic_ss_info
{
1503 struct _ATOM_ASIC_INTERNAL_SS_INFO info
;
1504 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2
;
1505 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3
;
1508 union asic_ss_assignment
{
1509 struct _ATOM_ASIC_SS_ASSIGNMENT v1
;
1510 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2
;
1511 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3
;
1514 bool radeon_atombios_get_asic_ss_info(struct radeon_device
*rdev
,
1515 struct radeon_atom_ss
*ss
,
1518 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1519 int index
= GetIndexIntoMasterTable(DATA
, ASIC_InternalSS_Info
);
1520 uint16_t data_offset
, size
;
1521 union asic_ss_info
*ss_info
;
1522 union asic_ss_assignment
*ss_assign
;
1526 if (id
== ASIC_INTERNAL_MEMORY_SS
) {
1527 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT
))
1530 if (id
== ASIC_INTERNAL_ENGINE_SS
) {
1531 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT
))
1535 memset(ss
, 0, sizeof(struct radeon_atom_ss
));
1536 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1537 &frev
, &crev
, &data_offset
)) {
1540 (union asic_ss_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1544 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1545 sizeof(ATOM_ASIC_SS_ASSIGNMENT
);
1547 ss_assign
= (union asic_ss_assignment
*)((u8
*)&ss_info
->info
.asSpreadSpectrum
[0]);
1548 for (i
= 0; i
< num_indices
; i
++) {
1549 if ((ss_assign
->v1
.ucClockIndication
== id
) &&
1550 (clock
<= le32_to_cpu(ss_assign
->v1
.ulTargetClockRange
))) {
1552 le16_to_cpu(ss_assign
->v1
.usSpreadSpectrumPercentage
);
1553 ss
->type
= ss_assign
->v1
.ucSpreadSpectrumMode
;
1554 ss
->rate
= le16_to_cpu(ss_assign
->v1
.usSpreadRateInKhz
);
1555 ss
->percentage_divider
= 100;
1558 ss_assign
= (union asic_ss_assignment
*)
1559 ((u8
*)ss_assign
+ sizeof(ATOM_ASIC_SS_ASSIGNMENT
));
1563 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1564 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2
);
1565 ss_assign
= (union asic_ss_assignment
*)((u8
*)&ss_info
->info_2
.asSpreadSpectrum
[0]);
1566 for (i
= 0; i
< num_indices
; i
++) {
1567 if ((ss_assign
->v2
.ucClockIndication
== id
) &&
1568 (clock
<= le32_to_cpu(ss_assign
->v2
.ulTargetClockRange
))) {
1570 le16_to_cpu(ss_assign
->v2
.usSpreadSpectrumPercentage
);
1571 ss
->type
= ss_assign
->v2
.ucSpreadSpectrumMode
;
1572 ss
->rate
= le16_to_cpu(ss_assign
->v2
.usSpreadRateIn10Hz
);
1573 ss
->percentage_divider
= 100;
1575 ((id
== ASIC_INTERNAL_ENGINE_SS
) ||
1576 (id
== ASIC_INTERNAL_MEMORY_SS
)))
1580 ss_assign
= (union asic_ss_assignment
*)
1581 ((u8
*)ss_assign
+ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2
));
1585 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1586 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3
);
1587 ss_assign
= (union asic_ss_assignment
*)((u8
*)&ss_info
->info_3
.asSpreadSpectrum
[0]);
1588 for (i
= 0; i
< num_indices
; i
++) {
1589 if ((ss_assign
->v3
.ucClockIndication
== id
) &&
1590 (clock
<= le32_to_cpu(ss_assign
->v3
.ulTargetClockRange
))) {
1592 le16_to_cpu(ss_assign
->v3
.usSpreadSpectrumPercentage
);
1593 ss
->type
= ss_assign
->v3
.ucSpreadSpectrumMode
;
1594 ss
->rate
= le16_to_cpu(ss_assign
->v3
.usSpreadRateIn10Hz
);
1595 if (ss_assign
->v3
.ucSpreadSpectrumMode
&
1596 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK
)
1597 ss
->percentage_divider
= 1000;
1599 ss
->percentage_divider
= 100;
1600 if ((id
== ASIC_INTERNAL_ENGINE_SS
) ||
1601 (id
== ASIC_INTERNAL_MEMORY_SS
))
1603 if (rdev
->flags
& RADEON_IS_IGP
)
1604 radeon_atombios_get_igp_ss_overrides(rdev
, ss
, id
);
1607 ss_assign
= (union asic_ss_assignment
*)
1608 ((u8
*)ss_assign
+ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3
));
1612 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev
, crev
);
1621 struct _ATOM_LVDS_INFO info
;
1622 struct _ATOM_LVDS_INFO_V12 info_12
;
1625 struct radeon_encoder_atom_dig
*radeon_atombios_get_lvds_info(struct
1629 struct drm_device
*dev
= encoder
->base
.dev
;
1630 struct radeon_device
*rdev
= dev
->dev_private
;
1631 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1632 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
1633 uint16_t data_offset
, misc
;
1634 union lvds_info
*lvds_info
;
1636 struct radeon_encoder_atom_dig
*lvds
= NULL
;
1637 int encoder_enum
= (encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1639 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1640 &frev
, &crev
, &data_offset
)) {
1642 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1644 kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
1649 lvds
->native_mode
.clock
=
1650 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
1651 lvds
->native_mode
.hdisplay
=
1652 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
1653 lvds
->native_mode
.vdisplay
=
1654 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
1655 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
1656 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
1657 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
1658 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
1659 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
1660 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
1661 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
1662 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
1663 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
1664 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncOffset
);
1665 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
1666 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
1667 lvds
->panel_pwr_delay
=
1668 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
1669 lvds
->lcd_misc
= lvds_info
->info
.ucLVDS_Misc
;
1671 misc
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.susModeMiscInfo
.usAccess
);
1672 if (misc
& ATOM_VSYNC_POLARITY
)
1673 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
1674 if (misc
& ATOM_HSYNC_POLARITY
)
1675 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
1676 if (misc
& ATOM_COMPOSITESYNC
)
1677 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_CSYNC
;
1678 if (misc
& ATOM_INTERLACE
)
1679 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
1680 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1681 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_DBLSCAN
;
1683 lvds
->native_mode
.width_mm
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.usImageHSize
);
1684 lvds
->native_mode
.height_mm
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.usImageVSize
);
1686 /* set crtc values */
1687 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1689 lvds
->lcd_ss_id
= lvds_info
->info
.ucSS_Id
;
1691 encoder
->native_mode
= lvds
->native_mode
;
1693 if (encoder_enum
== 2)
1696 lvds
->linkb
= false;
1698 /* parse the lcd record table */
1699 if (le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
)) {
1700 ATOM_FAKE_EDID_PATCH_RECORD
*fake_edid_record
;
1701 ATOM_PANEL_RESOLUTION_PATCH_RECORD
*panel_res_record
;
1702 bool bad_record
= false;
1705 if ((frev
== 1) && (crev
< 2))
1707 record
= (u8
*)(mode_info
->atom_context
->bios
+
1708 le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
));
1711 record
= (u8
*)(mode_info
->atom_context
->bios
+
1713 le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
));
1714 while (*record
!= ATOM_RECORD_END_TYPE
) {
1716 case LCD_MODE_PATCH_RECORD_MODE_TYPE
:
1717 record
+= sizeof(ATOM_PATCH_RECORD_MODE
);
1719 case LCD_RTS_RECORD_TYPE
:
1720 record
+= sizeof(ATOM_LCD_RTS_RECORD
);
1722 case LCD_CAP_RECORD_TYPE
:
1723 record
+= sizeof(ATOM_LCD_MODE_CONTROL_CAP
);
1725 case LCD_FAKE_EDID_PATCH_RECORD_TYPE
:
1726 fake_edid_record
= (ATOM_FAKE_EDID_PATCH_RECORD
*)record
;
1727 if (fake_edid_record
->ucFakeEDIDLength
) {
1730 max((int)EDID_LENGTH
, (int)fake_edid_record
->ucFakeEDIDLength
);
1731 edid
= kmalloc(edid_size
, GFP_KERNEL
);
1733 memcpy((u8
*)edid
, (u8
*)&fake_edid_record
->ucFakeEDIDString
[0],
1734 fake_edid_record
->ucFakeEDIDLength
);
1736 if (drm_edid_is_valid(edid
)) {
1737 rdev
->mode_info
.bios_hardcoded_edid
= edid
;
1738 rdev
->mode_info
.bios_hardcoded_edid_size
= edid_size
;
1743 record
+= fake_edid_record
->ucFakeEDIDLength
?
1744 fake_edid_record
->ucFakeEDIDLength
+ 2 :
1745 sizeof(ATOM_FAKE_EDID_PATCH_RECORD
);
1747 case LCD_PANEL_RESOLUTION_RECORD_TYPE
:
1748 panel_res_record
= (ATOM_PANEL_RESOLUTION_PATCH_RECORD
*)record
;
1749 lvds
->native_mode
.width_mm
= panel_res_record
->usHSize
;
1750 lvds
->native_mode
.height_mm
= panel_res_record
->usVSize
;
1751 record
+= sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD
);
1754 DRM_ERROR("Bad LCD record %d\n", *record
);
1766 struct radeon_encoder_primary_dac
*
1767 radeon_atombios_get_primary_dac_info(struct radeon_encoder
*encoder
)
1769 struct drm_device
*dev
= encoder
->base
.dev
;
1770 struct radeon_device
*rdev
= dev
->dev_private
;
1771 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1772 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1773 uint16_t data_offset
;
1774 struct _COMPASSIONATE_DATA
*dac_info
;
1777 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
1779 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1780 &frev
, &crev
, &data_offset
)) {
1781 dac_info
= (struct _COMPASSIONATE_DATA
*)
1782 (mode_info
->atom_context
->bios
+ data_offset
);
1784 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
), GFP_KERNEL
);
1789 bg
= dac_info
->ucDAC1_BG_Adjustment
;
1790 dac
= dac_info
->ucDAC1_DAC_Adjustment
;
1791 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
1797 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
1798 struct drm_display_mode
*mode
)
1800 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1801 ATOM_ANALOG_TV_INFO
*tv_info
;
1802 ATOM_ANALOG_TV_INFO_V1_2
*tv_info_v1_2
;
1803 ATOM_DTD_FORMAT
*dtd_timings
;
1804 int data_index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1806 u16 data_offset
, misc
;
1808 if (!atom_parse_data_header(mode_info
->atom_context
, data_index
, NULL
,
1809 &frev
, &crev
, &data_offset
))
1814 tv_info
= (ATOM_ANALOG_TV_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1815 if (index
>= MAX_SUPPORTED_TV_TIMING
)
1818 mode
->crtc_htotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Total
);
1819 mode
->crtc_hdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Disp
);
1820 mode
->crtc_hsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
);
1821 mode
->crtc_hsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
) +
1822 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncWidth
);
1824 mode
->crtc_vtotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Total
);
1825 mode
->crtc_vdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Disp
);
1826 mode
->crtc_vsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
);
1827 mode
->crtc_vsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
) +
1828 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncWidth
);
1831 misc
= le16_to_cpu(tv_info
->aModeTimings
[index
].susModeMiscInfo
.usAccess
);
1832 if (misc
& ATOM_VSYNC_POLARITY
)
1833 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1834 if (misc
& ATOM_HSYNC_POLARITY
)
1835 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1836 if (misc
& ATOM_COMPOSITESYNC
)
1837 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1838 if (misc
& ATOM_INTERLACE
)
1839 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1840 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1841 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1843 mode
->crtc_clock
= mode
->clock
=
1844 le16_to_cpu(tv_info
->aModeTimings
[index
].usPixelClock
) * 10;
1847 /* PAL timings appear to have wrong values for totals */
1848 mode
->crtc_htotal
-= 1;
1849 mode
->crtc_vtotal
-= 1;
1853 tv_info_v1_2
= (ATOM_ANALOG_TV_INFO_V1_2
*)(mode_info
->atom_context
->bios
+ data_offset
);
1854 if (index
>= MAX_SUPPORTED_TV_TIMING_V1_2
)
1857 dtd_timings
= &tv_info_v1_2
->aModeTimings
[index
];
1858 mode
->crtc_htotal
= le16_to_cpu(dtd_timings
->usHActive
) +
1859 le16_to_cpu(dtd_timings
->usHBlanking_Time
);
1860 mode
->crtc_hdisplay
= le16_to_cpu(dtd_timings
->usHActive
);
1861 mode
->crtc_hsync_start
= le16_to_cpu(dtd_timings
->usHActive
) +
1862 le16_to_cpu(dtd_timings
->usHSyncOffset
);
1863 mode
->crtc_hsync_end
= mode
->crtc_hsync_start
+
1864 le16_to_cpu(dtd_timings
->usHSyncWidth
);
1866 mode
->crtc_vtotal
= le16_to_cpu(dtd_timings
->usVActive
) +
1867 le16_to_cpu(dtd_timings
->usVBlanking_Time
);
1868 mode
->crtc_vdisplay
= le16_to_cpu(dtd_timings
->usVActive
);
1869 mode
->crtc_vsync_start
= le16_to_cpu(dtd_timings
->usVActive
) +
1870 le16_to_cpu(dtd_timings
->usVSyncOffset
);
1871 mode
->crtc_vsync_end
= mode
->crtc_vsync_start
+
1872 le16_to_cpu(dtd_timings
->usVSyncWidth
);
1875 misc
= le16_to_cpu(dtd_timings
->susModeMiscInfo
.usAccess
);
1876 if (misc
& ATOM_VSYNC_POLARITY
)
1877 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1878 if (misc
& ATOM_HSYNC_POLARITY
)
1879 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1880 if (misc
& ATOM_COMPOSITESYNC
)
1881 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1882 if (misc
& ATOM_INTERLACE
)
1883 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1884 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1885 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1887 mode
->crtc_clock
= mode
->clock
=
1888 le16_to_cpu(dtd_timings
->usPixClk
) * 10;
1895 radeon_atombios_get_tv_info(struct radeon_device
*rdev
)
1897 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1898 int index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1899 uint16_t data_offset
;
1901 struct _ATOM_ANALOG_TV_INFO
*tv_info
;
1902 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
1904 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1905 &frev
, &crev
, &data_offset
)) {
1907 tv_info
= (struct _ATOM_ANALOG_TV_INFO
*)
1908 (mode_info
->atom_context
->bios
+ data_offset
);
1910 switch (tv_info
->ucTV_BootUpDefaultStandard
) {
1912 tv_std
= TV_STD_NTSC
;
1913 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1916 tv_std
= TV_STD_NTSC_J
;
1917 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1920 tv_std
= TV_STD_PAL
;
1921 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1924 tv_std
= TV_STD_PAL_M
;
1925 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1928 tv_std
= TV_STD_PAL_N
;
1929 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1932 tv_std
= TV_STD_PAL_CN
;
1933 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1936 tv_std
= TV_STD_PAL_60
;
1937 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1940 tv_std
= TV_STD_SECAM
;
1941 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1944 tv_std
= TV_STD_NTSC
;
1945 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1952 struct radeon_encoder_tv_dac
*
1953 radeon_atombios_get_tv_dac_info(struct radeon_encoder
*encoder
)
1955 struct drm_device
*dev
= encoder
->base
.dev
;
1956 struct radeon_device
*rdev
= dev
->dev_private
;
1957 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1958 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1959 uint16_t data_offset
;
1960 struct _COMPASSIONATE_DATA
*dac_info
;
1963 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1965 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1966 &frev
, &crev
, &data_offset
)) {
1968 dac_info
= (struct _COMPASSIONATE_DATA
*)
1969 (mode_info
->atom_context
->bios
+ data_offset
);
1971 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1976 bg
= dac_info
->ucDAC2_CRT2_BG_Adjustment
;
1977 dac
= dac_info
->ucDAC2_CRT2_DAC_Adjustment
;
1978 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1980 bg
= dac_info
->ucDAC2_PAL_BG_Adjustment
;
1981 dac
= dac_info
->ucDAC2_PAL_DAC_Adjustment
;
1982 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1984 bg
= dac_info
->ucDAC2_NTSC_BG_Adjustment
;
1985 dac
= dac_info
->ucDAC2_NTSC_DAC_Adjustment
;
1986 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1988 tv_dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
1993 static const char *thermal_controller_names
[] = {
2004 static const char *pp_lib_thermal_controller_names
[] = {
2027 struct _ATOM_POWERPLAY_INFO info
;
2028 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
2029 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
2030 struct _ATOM_PPLIB_POWERPLAYTABLE pplib
;
2031 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2
;
2032 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3
;
2035 union pplib_clock_info
{
2036 struct _ATOM_PPLIB_R600_CLOCK_INFO r600
;
2037 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780
;
2038 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen
;
2039 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo
;
2040 struct _ATOM_PPLIB_SI_CLOCK_INFO si
;
2041 struct _ATOM_PPLIB_CI_CLOCK_INFO ci
;
2044 union pplib_power_state
{
2045 struct _ATOM_PPLIB_STATE v1
;
2046 struct _ATOM_PPLIB_STATE_V2 v2
;
2049 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device
*rdev
,
2051 u32 misc
, u32 misc2
)
2053 rdev
->pm
.power_state
[state_index
].misc
= misc
;
2054 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
2055 /* order matters! */
2056 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
2057 rdev
->pm
.power_state
[state_index
].type
=
2058 POWER_STATE_TYPE_POWERSAVE
;
2059 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
2060 rdev
->pm
.power_state
[state_index
].type
=
2061 POWER_STATE_TYPE_BATTERY
;
2062 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
2063 rdev
->pm
.power_state
[state_index
].type
=
2064 POWER_STATE_TYPE_BATTERY
;
2065 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
2066 rdev
->pm
.power_state
[state_index
].type
=
2067 POWER_STATE_TYPE_BALANCED
;
2068 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
) {
2069 rdev
->pm
.power_state
[state_index
].type
=
2070 POWER_STATE_TYPE_PERFORMANCE
;
2071 rdev
->pm
.power_state
[state_index
].flags
&=
2072 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2074 if (misc2
& ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE
)
2075 rdev
->pm
.power_state
[state_index
].type
=
2076 POWER_STATE_TYPE_BALANCED
;
2077 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
2078 rdev
->pm
.power_state
[state_index
].type
=
2079 POWER_STATE_TYPE_DEFAULT
;
2080 rdev
->pm
.default_power_state_index
= state_index
;
2081 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2082 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2083 } else if (state_index
== 0) {
2084 rdev
->pm
.power_state
[state_index
].clock_info
[0].flags
|=
2085 RADEON_PM_MODE_NO_DISPLAY
;
2089 static int radeon_atombios_parse_power_table_1_3(struct radeon_device
*rdev
)
2091 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2092 u32 misc
, misc2
= 0;
2093 int num_modes
= 0, i
;
2094 int state_index
= 0;
2095 struct radeon_i2c_bus_rec i2c_bus
;
2096 union power_info
*power_info
;
2097 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2101 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2102 &frev
, &crev
, &data_offset
))
2104 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
2106 /* add the i2c bus for thermal/fan chip */
2107 if ((power_info
->info
.ucOverdriveThermalController
> 0) &&
2108 (power_info
->info
.ucOverdriveThermalController
< ARRAY_SIZE(thermal_controller_names
))) {
2109 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2110 thermal_controller_names
[power_info
->info
.ucOverdriveThermalController
],
2111 power_info
->info
.ucOverdriveControllerAddress
>> 1);
2112 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, power_info
->info
.ucOverdriveI2cLine
);
2113 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
2114 if (rdev
->pm
.i2c_bus
) {
2115 struct i2c_board_info info
= { };
2116 const char *name
= thermal_controller_names
[power_info
->info
.
2117 ucOverdriveThermalController
];
2118 info
.addr
= power_info
->info
.ucOverdriveControllerAddress
>> 1;
2119 strlcpy(info
.type
, name
, sizeof(info
.type
));
2120 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
2123 num_modes
= power_info
->info
.ucNumOfPowerModeEntries
;
2124 if (num_modes
> ATOM_MAX_NUMBEROF_POWER_BLOCK
)
2125 num_modes
= ATOM_MAX_NUMBEROF_POWER_BLOCK
;
2128 rdev
->pm
.power_state
= kzalloc(sizeof(struct radeon_power_state
) * num_modes
, GFP_KERNEL
);
2129 if (!rdev
->pm
.power_state
)
2131 /* last mode is usually default, array is low to high */
2132 for (i
= 0; i
< num_modes
; i
++) {
2133 rdev
->pm
.power_state
[state_index
].clock_info
=
2134 kzalloc(sizeof(struct radeon_pm_clock_info
) * 1, GFP_KERNEL
);
2135 if (!rdev
->pm
.power_state
[state_index
].clock_info
)
2137 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2138 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2141 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2142 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usMemoryClock
);
2143 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2144 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usEngineClock
);
2145 /* skip invalid modes */
2146 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2147 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2149 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2150 power_info
->info
.asPowerPlayInfo
[i
].ucNumPciELanes
;
2151 misc
= le32_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].ulMiscInfo
);
2152 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
2153 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
2154 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2156 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
2157 radeon_atombios_lookup_gpio(rdev
,
2158 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
2159 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
2160 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2163 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2165 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
2166 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2168 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
2169 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
2171 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2172 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, 0);
2176 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2177 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMemoryClock
);
2178 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2179 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulEngineClock
);
2180 /* skip invalid modes */
2181 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2182 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2184 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2185 power_info
->info_2
.asPowerPlayInfo
[i
].ucNumPciELanes
;
2186 misc
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo
);
2187 misc2
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo2
);
2188 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
2189 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
2190 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2192 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
2193 radeon_atombios_lookup_gpio(rdev
,
2194 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
2195 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
2196 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2199 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2201 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
2202 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2204 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
2205 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
2207 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2208 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, misc2
);
2212 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2213 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMemoryClock
);
2214 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2215 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulEngineClock
);
2216 /* skip invalid modes */
2217 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2218 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2220 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2221 power_info
->info_3
.asPowerPlayInfo
[i
].ucNumPciELanes
;
2222 misc
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo
);
2223 misc2
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo2
);
2224 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
2225 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
2226 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2228 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
2229 radeon_atombios_lookup_gpio(rdev
,
2230 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
2231 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
2232 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2235 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2237 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
2238 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
2240 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
2241 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
2242 if (misc2
& ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN
) {
2243 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_enabled
=
2245 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_id
=
2246 power_info
->info_3
.asPowerPlayInfo
[i
].ucVDDCI_VoltageDropIndex
;
2249 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2250 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, misc2
);
2255 /* last mode is usually default */
2256 if (rdev
->pm
.default_power_state_index
== -1) {
2257 rdev
->pm
.power_state
[state_index
- 1].type
=
2258 POWER_STATE_TYPE_DEFAULT
;
2259 rdev
->pm
.default_power_state_index
= state_index
- 1;
2260 rdev
->pm
.power_state
[state_index
- 1].default_clock_mode
=
2261 &rdev
->pm
.power_state
[state_index
- 1].clock_info
[0];
2262 rdev
->pm
.power_state
[state_index
].flags
&=
2263 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2264 rdev
->pm
.power_state
[state_index
].misc
= 0;
2265 rdev
->pm
.power_state
[state_index
].misc2
= 0;
2270 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device
*rdev
,
2271 ATOM_PPLIB_THERMALCONTROLLER
*controller
)
2273 struct radeon_i2c_bus_rec i2c_bus
;
2275 /* add the i2c bus for thermal/fan chip */
2276 if (controller
->ucType
> 0) {
2277 if (controller
->ucFanParameters
& ATOM_PP_FANPARAMETERS_NOFAN
)
2278 rdev
->pm
.no_fan
= true;
2279 rdev
->pm
.fan_pulses_per_revolution
=
2280 controller
->ucFanParameters
& ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK
;
2281 if (rdev
->pm
.fan_pulses_per_revolution
) {
2282 rdev
->pm
.fan_min_rpm
= controller
->ucFanMinRPM
;
2283 rdev
->pm
.fan_max_rpm
= controller
->ucFanMaxRPM
;
2285 if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV6xx
) {
2286 DRM_INFO("Internal thermal controller %s fan control\n",
2287 (controller
->ucFanParameters
&
2288 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2289 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV6XX
;
2290 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV770
) {
2291 DRM_INFO("Internal thermal controller %s fan control\n",
2292 (controller
->ucFanParameters
&
2293 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2294 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV770
;
2295 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_EVERGREEN
) {
2296 DRM_INFO("Internal thermal controller %s fan control\n",
2297 (controller
->ucFanParameters
&
2298 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2299 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_EVERGREEN
;
2300 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_SUMO
) {
2301 DRM_INFO("Internal thermal controller %s fan control\n",
2302 (controller
->ucFanParameters
&
2303 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2304 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_SUMO
;
2305 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_NISLANDS
) {
2306 DRM_INFO("Internal thermal controller %s fan control\n",
2307 (controller
->ucFanParameters
&
2308 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2309 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NI
;
2310 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_SISLANDS
) {
2311 DRM_INFO("Internal thermal controller %s fan control\n",
2312 (controller
->ucFanParameters
&
2313 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2314 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_SI
;
2315 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_CISLANDS
) {
2316 DRM_INFO("Internal thermal controller %s fan control\n",
2317 (controller
->ucFanParameters
&
2318 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2319 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_CI
;
2320 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_KAVERI
) {
2321 DRM_INFO("Internal thermal controller %s fan control\n",
2322 (controller
->ucFanParameters
&
2323 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2324 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_KV
;
2325 } else if (controller
->ucType
==
2326 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO
) {
2327 DRM_INFO("External GPIO thermal controller %s fan control\n",
2328 (controller
->ucFanParameters
&
2329 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2330 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_EXTERNAL_GPIO
;
2331 } else if (controller
->ucType
==
2332 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL
) {
2333 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2334 (controller
->ucFanParameters
&
2335 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2336 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_ADT7473_WITH_INTERNAL
;
2337 } else if (controller
->ucType
==
2338 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL
) {
2339 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2340 (controller
->ucFanParameters
&
2341 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2342 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_EMC2103_WITH_INTERNAL
;
2343 } else if (controller
->ucType
< ARRAY_SIZE(pp_lib_thermal_controller_names
)) {
2344 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2345 pp_lib_thermal_controller_names
[controller
->ucType
],
2346 controller
->ucI2cAddress
>> 1,
2347 (controller
->ucFanParameters
&
2348 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2349 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_EXTERNAL
;
2350 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, controller
->ucI2cLine
);
2351 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
2352 if (rdev
->pm
.i2c_bus
) {
2353 struct i2c_board_info info
= { };
2354 const char *name
= pp_lib_thermal_controller_names
[controller
->ucType
];
2355 info
.addr
= controller
->ucI2cAddress
>> 1;
2356 strlcpy(info
.type
, name
, sizeof(info
.type
));
2357 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
2360 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2362 controller
->ucI2cAddress
>> 1,
2363 (controller
->ucFanParameters
&
2364 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2369 void radeon_atombios_get_default_voltages(struct radeon_device
*rdev
,
2370 u16
*vddc
, u16
*vddci
, u16
*mvdd
)
2372 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2373 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
2376 union firmware_info
*firmware_info
;
2382 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2383 &frev
, &crev
, &data_offset
)) {
2385 (union firmware_info
*)(mode_info
->atom_context
->bios
+
2387 *vddc
= le16_to_cpu(firmware_info
->info_14
.usBootUpVDDCVoltage
);
2388 if ((frev
== 2) && (crev
>= 2)) {
2389 *vddci
= le16_to_cpu(firmware_info
->info_22
.usBootUpVDDCIVoltage
);
2390 *mvdd
= le16_to_cpu(firmware_info
->info_22
.usBootUpMVDDCVoltage
);
2395 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device
*rdev
,
2396 int state_index
, int mode_index
,
2397 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
)
2400 u32 misc
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
2401 u32 misc2
= le16_to_cpu(non_clock_info
->usClassification
);
2402 u16 vddc
, vddci
, mvdd
;
2404 radeon_atombios_get_default_voltages(rdev
, &vddc
, &vddci
, &mvdd
);
2406 rdev
->pm
.power_state
[state_index
].misc
= misc
;
2407 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
2408 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2409 ((misc
& ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
) >>
2410 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
) + 1;
2411 switch (misc2
& ATOM_PPLIB_CLASSIFICATION_UI_MASK
) {
2412 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
:
2413 rdev
->pm
.power_state
[state_index
].type
=
2414 POWER_STATE_TYPE_BATTERY
;
2416 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
:
2417 rdev
->pm
.power_state
[state_index
].type
=
2418 POWER_STATE_TYPE_BALANCED
;
2420 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
:
2421 rdev
->pm
.power_state
[state_index
].type
=
2422 POWER_STATE_TYPE_PERFORMANCE
;
2424 case ATOM_PPLIB_CLASSIFICATION_UI_NONE
:
2425 if (misc2
& ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
2426 rdev
->pm
.power_state
[state_index
].type
=
2427 POWER_STATE_TYPE_PERFORMANCE
;
2430 rdev
->pm
.power_state
[state_index
].flags
= 0;
2431 if (misc
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
)
2432 rdev
->pm
.power_state
[state_index
].flags
|=
2433 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2434 if (misc2
& ATOM_PPLIB_CLASSIFICATION_BOOT
) {
2435 rdev
->pm
.power_state
[state_index
].type
=
2436 POWER_STATE_TYPE_DEFAULT
;
2437 rdev
->pm
.default_power_state_index
= state_index
;
2438 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2439 &rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
- 1];
2440 if ((rdev
->family
>= CHIP_BARTS
) && !(rdev
->flags
& RADEON_IS_IGP
)) {
2441 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2442 rdev
->pm
.default_sclk
= rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
;
2443 rdev
->pm
.default_mclk
= rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
;
2444 rdev
->pm
.default_vddc
= rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.voltage
;
2445 rdev
->pm
.default_vddci
= rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci
;
2449 if (ASIC_IS_DCE4(rdev
))
2450 radeon_atom_get_max_voltage(rdev
,
2451 SET_VOLTAGE_TYPE_ASIC_VDDCI
,
2453 /* patch the table values with the default sclk/mclk from firmware info */
2454 for (j
= 0; j
< mode_index
; j
++) {
2455 rdev
->pm
.power_state
[state_index
].clock_info
[j
].mclk
=
2456 rdev
->clock
.default_mclk
;
2457 rdev
->pm
.power_state
[state_index
].clock_info
[j
].sclk
=
2458 rdev
->clock
.default_sclk
;
2460 rdev
->pm
.power_state
[state_index
].clock_info
[j
].voltage
.voltage
=
2463 rdev
->pm
.power_state
[state_index
].clock_info
[j
].voltage
.vddci
=
2470 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device
*rdev
,
2471 int state_index
, int mode_index
,
2472 union pplib_clock_info
*clock_info
)
2477 if (rdev
->flags
& RADEON_IS_IGP
) {
2478 if (rdev
->family
>= CHIP_PALM
) {
2479 sclk
= le16_to_cpu(clock_info
->sumo
.usEngineClockLow
);
2480 sclk
|= clock_info
->sumo
.ucEngineClockHigh
<< 16;
2481 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2483 sclk
= le16_to_cpu(clock_info
->rs780
.usLowEngineClockLow
);
2484 sclk
|= clock_info
->rs780
.ucLowEngineClockHigh
<< 16;
2485 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2487 } else if (rdev
->family
>= CHIP_BONAIRE
) {
2488 sclk
= le16_to_cpu(clock_info
->ci
.usEngineClockLow
);
2489 sclk
|= clock_info
->ci
.ucEngineClockHigh
<< 16;
2490 mclk
= le16_to_cpu(clock_info
->ci
.usMemoryClockLow
);
2491 mclk
|= clock_info
->ci
.ucMemoryClockHigh
<< 16;
2492 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2493 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2494 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2496 } else if (rdev
->family
>= CHIP_TAHITI
) {
2497 sclk
= le16_to_cpu(clock_info
->si
.usEngineClockLow
);
2498 sclk
|= clock_info
->si
.ucEngineClockHigh
<< 16;
2499 mclk
= le16_to_cpu(clock_info
->si
.usMemoryClockLow
);
2500 mclk
|= clock_info
->si
.ucMemoryClockHigh
<< 16;
2501 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2502 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2503 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2505 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2506 le16_to_cpu(clock_info
->si
.usVDDC
);
2507 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.vddci
=
2508 le16_to_cpu(clock_info
->si
.usVDDCI
);
2509 } else if (rdev
->family
>= CHIP_CEDAR
) {
2510 sclk
= le16_to_cpu(clock_info
->evergreen
.usEngineClockLow
);
2511 sclk
|= clock_info
->evergreen
.ucEngineClockHigh
<< 16;
2512 mclk
= le16_to_cpu(clock_info
->evergreen
.usMemoryClockLow
);
2513 mclk
|= clock_info
->evergreen
.ucMemoryClockHigh
<< 16;
2514 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2515 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2516 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2518 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2519 le16_to_cpu(clock_info
->evergreen
.usVDDC
);
2520 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.vddci
=
2521 le16_to_cpu(clock_info
->evergreen
.usVDDCI
);
2523 sclk
= le16_to_cpu(clock_info
->r600
.usEngineClockLow
);
2524 sclk
|= clock_info
->r600
.ucEngineClockHigh
<< 16;
2525 mclk
= le16_to_cpu(clock_info
->r600
.usMemoryClockLow
);
2526 mclk
|= clock_info
->r600
.ucMemoryClockHigh
<< 16;
2527 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2528 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2529 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2531 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2532 le16_to_cpu(clock_info
->r600
.usVDDC
);
2535 /* patch up vddc if necessary */
2536 switch (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
) {
2537 case ATOM_VIRTUAL_VOLTAGE_ID0
:
2538 case ATOM_VIRTUAL_VOLTAGE_ID1
:
2539 case ATOM_VIRTUAL_VOLTAGE_ID2
:
2540 case ATOM_VIRTUAL_VOLTAGE_ID3
:
2541 case ATOM_VIRTUAL_VOLTAGE_ID4
:
2542 case ATOM_VIRTUAL_VOLTAGE_ID5
:
2543 case ATOM_VIRTUAL_VOLTAGE_ID6
:
2544 case ATOM_VIRTUAL_VOLTAGE_ID7
:
2545 if (radeon_atom_get_max_vddc(rdev
, VOLTAGE_TYPE_VDDC
,
2546 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
,
2548 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
= vddc
;
2554 if (rdev
->flags
& RADEON_IS_IGP
) {
2555 /* skip invalid modes */
2556 if (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0)
2559 /* skip invalid modes */
2560 if ((rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
== 0) ||
2561 (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0))
2567 static int radeon_atombios_parse_power_table_4_5(struct radeon_device
*rdev
)
2569 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2570 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
2571 union pplib_power_state
*power_state
;
2573 int state_index
= 0, mode_index
= 0;
2574 union pplib_clock_info
*clock_info
;
2576 union power_info
*power_info
;
2577 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2581 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2582 &frev
, &crev
, &data_offset
))
2584 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
2586 radeon_atombios_add_pplib_thermal_controller(rdev
, &power_info
->pplib
.sThermalController
);
2587 if (power_info
->pplib
.ucNumStates
== 0)
2589 rdev
->pm
.power_state
= kzalloc(sizeof(struct radeon_power_state
) *
2590 power_info
->pplib
.ucNumStates
, GFP_KERNEL
);
2591 if (!rdev
->pm
.power_state
)
2593 /* first mode is usually default, followed by low to high */
2594 for (i
= 0; i
< power_info
->pplib
.ucNumStates
; i
++) {
2596 power_state
= (union pplib_power_state
*)
2597 (mode_info
->atom_context
->bios
+ data_offset
+
2598 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
) +
2599 i
* power_info
->pplib
.ucStateEntrySize
);
2600 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2601 (mode_info
->atom_context
->bios
+ data_offset
+
2602 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
) +
2603 (power_state
->v1
.ucNonClockStateIndex
*
2604 power_info
->pplib
.ucNonClockSize
));
2605 rdev
->pm
.power_state
[i
].clock_info
= kzalloc(sizeof(struct radeon_pm_clock_info
) *
2606 ((power_info
->pplib
.ucStateEntrySize
- 1) ?
2607 (power_info
->pplib
.ucStateEntrySize
- 1) : 1),
2609 if (!rdev
->pm
.power_state
[i
].clock_info
)
2611 if (power_info
->pplib
.ucStateEntrySize
- 1) {
2612 for (j
= 0; j
< (power_info
->pplib
.ucStateEntrySize
- 1); j
++) {
2613 clock_info
= (union pplib_clock_info
*)
2614 (mode_info
->atom_context
->bios
+ data_offset
+
2615 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
) +
2616 (power_state
->v1
.ucClockStateIndices
[j
] *
2617 power_info
->pplib
.ucClockInfoSize
));
2618 valid
= radeon_atombios_parse_pplib_clock_info(rdev
,
2619 state_index
, mode_index
,
2625 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2626 rdev
->clock
.default_mclk
;
2627 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2628 rdev
->clock
.default_sclk
;
2631 rdev
->pm
.power_state
[state_index
].num_clock_modes
= mode_index
;
2633 radeon_atombios_parse_pplib_non_clock_info(rdev
, state_index
, mode_index
,
2638 /* if multiple clock modes, mark the lowest as no display */
2639 for (i
= 0; i
< state_index
; i
++) {
2640 if (rdev
->pm
.power_state
[i
].num_clock_modes
> 1)
2641 rdev
->pm
.power_state
[i
].clock_info
[0].flags
|=
2642 RADEON_PM_MODE_NO_DISPLAY
;
2644 /* first mode is usually default */
2645 if (rdev
->pm
.default_power_state_index
== -1) {
2646 rdev
->pm
.power_state
[0].type
=
2647 POWER_STATE_TYPE_DEFAULT
;
2648 rdev
->pm
.default_power_state_index
= 0;
2649 rdev
->pm
.power_state
[0].default_clock_mode
=
2650 &rdev
->pm
.power_state
[0].clock_info
[0];
2655 static int radeon_atombios_parse_power_table_6(struct radeon_device
*rdev
)
2657 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2658 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
2659 union pplib_power_state
*power_state
;
2660 int i
, j
, non_clock_array_index
, clock_array_index
;
2661 int state_index
= 0, mode_index
= 0;
2662 union pplib_clock_info
*clock_info
;
2663 struct _StateArray
*state_array
;
2664 struct _ClockInfoArray
*clock_info_array
;
2665 struct _NonClockInfoArray
*non_clock_info_array
;
2667 union power_info
*power_info
;
2668 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2671 u8
*power_state_offset
;
2673 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2674 &frev
, &crev
, &data_offset
))
2676 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
2678 radeon_atombios_add_pplib_thermal_controller(rdev
, &power_info
->pplib
.sThermalController
);
2679 state_array
= (struct _StateArray
*)
2680 (mode_info
->atom_context
->bios
+ data_offset
+
2681 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
));
2682 clock_info_array
= (struct _ClockInfoArray
*)
2683 (mode_info
->atom_context
->bios
+ data_offset
+
2684 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
));
2685 non_clock_info_array
= (struct _NonClockInfoArray
*)
2686 (mode_info
->atom_context
->bios
+ data_offset
+
2687 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
));
2688 if (state_array
->ucNumEntries
== 0)
2690 rdev
->pm
.power_state
= kzalloc(sizeof(struct radeon_power_state
) *
2691 state_array
->ucNumEntries
, GFP_KERNEL
);
2692 if (!rdev
->pm
.power_state
)
2694 power_state_offset
= (u8
*)state_array
->states
;
2695 for (i
= 0; i
< state_array
->ucNumEntries
; i
++) {
2697 power_state
= (union pplib_power_state
*)power_state_offset
;
2698 non_clock_array_index
= power_state
->v2
.nonClockInfoIndex
;
2699 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2700 &non_clock_info_array
->nonClockInfo
[non_clock_array_index
];
2701 rdev
->pm
.power_state
[i
].clock_info
= kzalloc(sizeof(struct radeon_pm_clock_info
) *
2702 (power_state
->v2
.ucNumDPMLevels
?
2703 power_state
->v2
.ucNumDPMLevels
: 1),
2705 if (!rdev
->pm
.power_state
[i
].clock_info
)
2707 if (power_state
->v2
.ucNumDPMLevels
) {
2708 for (j
= 0; j
< power_state
->v2
.ucNumDPMLevels
; j
++) {
2709 clock_array_index
= power_state
->v2
.clockInfoIndex
[j
];
2710 clock_info
= (union pplib_clock_info
*)
2711 &clock_info_array
->clockInfo
[clock_array_index
* clock_info_array
->ucEntrySize
];
2712 valid
= radeon_atombios_parse_pplib_clock_info(rdev
,
2713 state_index
, mode_index
,
2719 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
2720 rdev
->clock
.default_mclk
;
2721 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
2722 rdev
->clock
.default_sclk
;
2725 rdev
->pm
.power_state
[state_index
].num_clock_modes
= mode_index
;
2727 radeon_atombios_parse_pplib_non_clock_info(rdev
, state_index
, mode_index
,
2731 power_state_offset
+= 2 + power_state
->v2
.ucNumDPMLevels
;
2733 /* if multiple clock modes, mark the lowest as no display */
2734 for (i
= 0; i
< state_index
; i
++) {
2735 if (rdev
->pm
.power_state
[i
].num_clock_modes
> 1)
2736 rdev
->pm
.power_state
[i
].clock_info
[0].flags
|=
2737 RADEON_PM_MODE_NO_DISPLAY
;
2739 /* first mode is usually default */
2740 if (rdev
->pm
.default_power_state_index
== -1) {
2741 rdev
->pm
.power_state
[0].type
=
2742 POWER_STATE_TYPE_DEFAULT
;
2743 rdev
->pm
.default_power_state_index
= 0;
2744 rdev
->pm
.power_state
[0].default_clock_mode
=
2745 &rdev
->pm
.power_state
[0].clock_info
[0];
2750 void radeon_atombios_get_power_modes(struct radeon_device
*rdev
)
2752 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2753 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2756 int state_index
= 0;
2758 rdev
->pm
.default_power_state_index
= -1;
2760 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2761 &frev
, &crev
, &data_offset
)) {
2766 state_index
= radeon_atombios_parse_power_table_1_3(rdev
);
2770 state_index
= radeon_atombios_parse_power_table_4_5(rdev
);
2773 state_index
= radeon_atombios_parse_power_table_6(rdev
);
2780 if (state_index
== 0) {
2781 rdev
->pm
.power_state
= kzalloc(sizeof(struct radeon_power_state
), GFP_KERNEL
);
2782 if (rdev
->pm
.power_state
) {
2783 rdev
->pm
.power_state
[0].clock_info
=
2784 kzalloc(sizeof(struct radeon_pm_clock_info
) * 1, GFP_KERNEL
);
2785 if (rdev
->pm
.power_state
[0].clock_info
) {
2786 /* add the default mode */
2787 rdev
->pm
.power_state
[state_index
].type
=
2788 POWER_STATE_TYPE_DEFAULT
;
2789 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2790 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= rdev
->clock
.default_mclk
;
2791 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= rdev
->clock
.default_sclk
;
2792 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2793 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2794 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2795 rdev
->pm
.power_state
[state_index
].pcie_lanes
= 16;
2796 rdev
->pm
.default_power_state_index
= state_index
;
2797 rdev
->pm
.power_state
[state_index
].flags
= 0;
2803 rdev
->pm
.num_power_states
= state_index
;
2805 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
2806 rdev
->pm
.current_clock_mode_index
= 0;
2807 if (rdev
->pm
.default_power_state_index
>= 0)
2808 rdev
->pm
.current_vddc
=
2809 rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
2811 rdev
->pm
.current_vddc
= 0;
2814 union get_clock_dividers
{
2815 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1
;
2816 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2
;
2817 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3
;
2818 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4
;
2819 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5
;
2820 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in
;
2821 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out
;
2824 int radeon_atom_get_clock_dividers(struct radeon_device
*rdev
,
2828 struct atom_clock_dividers
*dividers
)
2830 union get_clock_dividers args
;
2831 int index
= GetIndexIntoMasterTable(COMMAND
, ComputeMemoryEnginePLL
);
2834 memset(&args
, 0, sizeof(args
));
2835 memset(dividers
, 0, sizeof(struct atom_clock_dividers
));
2837 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2843 args
.v1
.ucAction
= clock_type
;
2844 args
.v1
.ulClock
= cpu_to_le32(clock
); /* 10 khz */
2846 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2848 dividers
->post_div
= args
.v1
.ucPostDiv
;
2849 dividers
->fb_div
= args
.v1
.ucFbDiv
;
2850 dividers
->enable_post_div
= true;
2855 /* r6xx, r7xx, evergreen, ni, si */
2856 if (rdev
->family
<= CHIP_RV770
) {
2857 args
.v2
.ucAction
= clock_type
;
2858 args
.v2
.ulClock
= cpu_to_le32(clock
); /* 10 khz */
2860 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2862 dividers
->post_div
= args
.v2
.ucPostDiv
;
2863 dividers
->fb_div
= le16_to_cpu(args
.v2
.usFbDiv
);
2864 dividers
->ref_div
= args
.v2
.ucAction
;
2865 if (rdev
->family
== CHIP_RV770
) {
2866 dividers
->enable_post_div
= (le32_to_cpu(args
.v2
.ulClock
) & (1 << 24)) ?
2868 dividers
->vco_mode
= (le32_to_cpu(args
.v2
.ulClock
) & (1 << 25)) ? 1 : 0;
2870 dividers
->enable_post_div
= (dividers
->fb_div
& 1) ? true : false;
2872 if (clock_type
== COMPUTE_ENGINE_PLL_PARAM
) {
2873 args
.v3
.ulClockParams
= cpu_to_le32((clock_type
<< 24) | clock
);
2875 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2877 dividers
->post_div
= args
.v3
.ucPostDiv
;
2878 dividers
->enable_post_div
= (args
.v3
.ucCntlFlag
&
2879 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN
) ? true : false;
2880 dividers
->enable_dithen
= (args
.v3
.ucCntlFlag
&
2881 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE
) ? false : true;
2882 dividers
->whole_fb_div
= le16_to_cpu(args
.v3
.ulFbDiv
.usFbDiv
);
2883 dividers
->frac_fb_div
= le16_to_cpu(args
.v3
.ulFbDiv
.usFbDivFrac
);
2884 dividers
->ref_div
= args
.v3
.ucRefDiv
;
2885 dividers
->vco_mode
= (args
.v3
.ucCntlFlag
&
2886 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE
) ? 1 : 0;
2888 /* for SI we use ComputeMemoryClockParam for memory plls */
2889 if (rdev
->family
>= CHIP_TAHITI
)
2891 args
.v5
.ulClockParams
= cpu_to_le32((clock_type
<< 24) | clock
);
2893 args
.v5
.ucInputFlag
= ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN
;
2895 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2897 dividers
->post_div
= args
.v5
.ucPostDiv
;
2898 dividers
->enable_post_div
= (args
.v5
.ucCntlFlag
&
2899 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN
) ? true : false;
2900 dividers
->enable_dithen
= (args
.v5
.ucCntlFlag
&
2901 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE
) ? false : true;
2902 dividers
->whole_fb_div
= le16_to_cpu(args
.v5
.ulFbDiv
.usFbDiv
);
2903 dividers
->frac_fb_div
= le16_to_cpu(args
.v5
.ulFbDiv
.usFbDivFrac
);
2904 dividers
->ref_div
= args
.v5
.ucRefDiv
;
2905 dividers
->vco_mode
= (args
.v5
.ucCntlFlag
&
2906 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE
) ? 1 : 0;
2912 args
.v4
.ulClock
= cpu_to_le32(clock
); /* 10 khz */
2914 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2916 dividers
->post_divider
= dividers
->post_div
= args
.v4
.ucPostDiv
;
2917 dividers
->real_clock
= le32_to_cpu(args
.v4
.ulClock
);
2921 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2922 args
.v6_in
.ulClock
.ulComputeClockFlag
= clock_type
;
2923 args
.v6_in
.ulClock
.ulClockFreq
= cpu_to_le32(clock
); /* 10 khz */
2925 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2927 dividers
->whole_fb_div
= le16_to_cpu(args
.v6_out
.ulFbDiv
.usFbDiv
);
2928 dividers
->frac_fb_div
= le16_to_cpu(args
.v6_out
.ulFbDiv
.usFbDivFrac
);
2929 dividers
->ref_div
= args
.v6_out
.ucPllRefDiv
;
2930 dividers
->post_div
= args
.v6_out
.ucPllPostDiv
;
2931 dividers
->flags
= args
.v6_out
.ucPllCntlFlag
;
2932 dividers
->real_clock
= le32_to_cpu(args
.v6_out
.ulClock
.ulClock
);
2933 dividers
->post_divider
= args
.v6_out
.ulClock
.ucPostDiv
;
2941 int radeon_atom_get_memory_pll_dividers(struct radeon_device
*rdev
,
2944 struct atom_mpll_param
*mpll_param
)
2946 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args
;
2947 int index
= GetIndexIntoMasterTable(COMMAND
, ComputeMemoryClockParam
);
2950 memset(&args
, 0, sizeof(args
));
2951 memset(mpll_param
, 0, sizeof(struct atom_mpll_param
));
2953 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2961 args
.ulClock
= cpu_to_le32(clock
); /* 10 khz */
2962 args
.ucInputFlag
= 0;
2964 args
.ucInputFlag
|= MPLL_INPUT_FLAG_STROBE_MODE_EN
;
2966 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2968 mpll_param
->clkfrac
= le16_to_cpu(args
.ulFbDiv
.usFbDivFrac
);
2969 mpll_param
->clkf
= le16_to_cpu(args
.ulFbDiv
.usFbDiv
);
2970 mpll_param
->post_div
= args
.ucPostDiv
;
2971 mpll_param
->dll_speed
= args
.ucDllSpeed
;
2972 mpll_param
->bwcntl
= args
.ucBWCntl
;
2973 mpll_param
->vco_mode
=
2974 (args
.ucPllCntlFlag
& MPLL_CNTL_FLAG_VCO_MODE_MASK
);
2975 mpll_param
->yclk_sel
=
2976 (args
.ucPllCntlFlag
& MPLL_CNTL_FLAG_BYPASS_DQ_PLL
) ? 1 : 0;
2978 (args
.ucPllCntlFlag
& MPLL_CNTL_FLAG_QDR_ENABLE
) ? 1 : 0;
2979 mpll_param
->half_rate
=
2980 (args
.ucPllCntlFlag
& MPLL_CNTL_FLAG_AD_HALF_RATE
) ? 1 : 0;
2992 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
)
2994 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args
;
2995 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicClockGating
);
2997 args
.ucEnable
= enable
;
2999 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3002 uint32_t radeon_atom_get_engine_clock(struct radeon_device
*rdev
)
3004 GET_ENGINE_CLOCK_PS_ALLOCATION args
;
3005 int index
= GetIndexIntoMasterTable(COMMAND
, GetEngineClock
);
3007 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3008 return le32_to_cpu(args
.ulReturnEngineClock
);
3011 uint32_t radeon_atom_get_memory_clock(struct radeon_device
*rdev
)
3013 GET_MEMORY_CLOCK_PS_ALLOCATION args
;
3014 int index
= GetIndexIntoMasterTable(COMMAND
, GetMemoryClock
);
3016 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3017 return le32_to_cpu(args
.ulReturnMemoryClock
);
3020 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
,
3023 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
3024 int index
= GetIndexIntoMasterTable(COMMAND
, SetEngineClock
);
3026 args
.ulTargetEngineClock
= cpu_to_le32(eng_clock
); /* 10 khz */
3028 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3031 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
,
3034 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
3035 int index
= GetIndexIntoMasterTable(COMMAND
, SetMemoryClock
);
3037 if (rdev
->flags
& RADEON_IS_IGP
)
3040 args
.ulTargetMemoryClock
= cpu_to_le32(mem_clock
); /* 10 khz */
3042 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3045 void radeon_atom_set_engine_dram_timings(struct radeon_device
*rdev
,
3046 u32 eng_clock
, u32 mem_clock
)
3048 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
3049 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicMemorySettings
);
3052 memset(&args
, 0, sizeof(args
));
3054 tmp
= eng_clock
& SET_CLOCK_FREQ_MASK
;
3055 tmp
|= (COMPUTE_ENGINE_PLL_PARAM
<< 24);
3057 args
.ulTargetEngineClock
= cpu_to_le32(tmp
);
3059 args
.sReserved
.ulClock
= cpu_to_le32(mem_clock
& SET_CLOCK_FREQ_MASK
);
3061 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3064 void radeon_atom_update_memory_dll(struct radeon_device
*rdev
,
3068 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicMemorySettings
);
3070 args
= cpu_to_le32(mem_clock
); /* 10 khz */
3072 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3075 void radeon_atom_set_ac_timing(struct radeon_device
*rdev
,
3078 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
3079 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicMemorySettings
);
3080 u32 tmp
= mem_clock
| (COMPUTE_MEMORY_PLL_PARAM
<< 24);
3082 args
.ulTargetMemoryClock
= cpu_to_le32(tmp
); /* 10 khz */
3084 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3088 struct _SET_VOLTAGE_PS_ALLOCATION alloc
;
3089 struct _SET_VOLTAGE_PARAMETERS v1
;
3090 struct _SET_VOLTAGE_PARAMETERS_V2 v2
;
3091 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3
;
3094 void radeon_atom_set_voltage(struct radeon_device
*rdev
, u16 voltage_level
, u8 voltage_type
)
3096 union set_voltage args
;
3097 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
3098 u8 frev
, crev
, volt_index
= voltage_level
;
3100 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
3103 /* 0xff01 is a flag rather then an actual voltage */
3104 if (voltage_level
== 0xff01)
3109 args
.v1
.ucVoltageType
= voltage_type
;
3110 args
.v1
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_ALL_SOURCE
;
3111 args
.v1
.ucVoltageIndex
= volt_index
;
3114 args
.v2
.ucVoltageType
= voltage_type
;
3115 args
.v2
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE
;
3116 args
.v2
.usVoltageLevel
= cpu_to_le16(voltage_level
);
3119 args
.v3
.ucVoltageType
= voltage_type
;
3120 args
.v3
.ucVoltageMode
= ATOM_SET_VOLTAGE
;
3121 args
.v3
.usVoltageLevel
= cpu_to_le16(voltage_level
);
3124 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3128 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3131 int radeon_atom_get_max_vddc(struct radeon_device
*rdev
, u8 voltage_type
,
3132 u16 voltage_id
, u16
*voltage
)
3134 union set_voltage args
;
3135 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
3138 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
3145 args
.v2
.ucVoltageType
= SET_VOLTAGE_GET_MAX_VOLTAGE
;
3146 args
.v2
.ucVoltageMode
= 0;
3147 args
.v2
.usVoltageLevel
= 0;
3149 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3151 *voltage
= le16_to_cpu(args
.v2
.usVoltageLevel
);
3154 args
.v3
.ucVoltageType
= voltage_type
;
3155 args
.v3
.ucVoltageMode
= ATOM_GET_VOLTAGE_LEVEL
;
3156 args
.v3
.usVoltageLevel
= cpu_to_le16(voltage_id
);
3158 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3160 *voltage
= le16_to_cpu(args
.v3
.usVoltageLevel
);
3163 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3170 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device
*rdev
,
3174 return radeon_atom_get_max_vddc(rdev
, VOLTAGE_TYPE_VDDC
, leakage_idx
, voltage
);
3177 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device
*rdev
,
3180 union set_voltage args
;
3181 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
3184 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
3190 args
.v3
.ucVoltageType
= 0;
3191 args
.v3
.ucVoltageMode
= ATOM_GET_LEAKAGE_ID
;
3192 args
.v3
.usVoltageLevel
= 0;
3194 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3196 *leakage_id
= le16_to_cpu(args
.v3
.usVoltageLevel
);
3199 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3206 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device
*rdev
,
3207 u16
*vddc
, u16
*vddci
,
3208 u16 virtual_voltage_id
,
3209 u16 vbios_voltage_id
)
3211 int index
= GetIndexIntoMasterTable(DATA
, ASIC_ProfilingInfo
);
3213 u16 data_offset
, size
;
3215 ATOM_ASIC_PROFILING_INFO_V2_1
*profile
;
3216 u16
*leakage_bin
, *vddc_id_buf
, *vddc_buf
, *vddci_id_buf
, *vddci_buf
;
3221 if (!atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3222 &frev
, &crev
, &data_offset
))
3225 profile
= (ATOM_ASIC_PROFILING_INFO_V2_1
*)
3226 (rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3234 if (size
< sizeof(ATOM_ASIC_PROFILING_INFO_V2_1
))
3236 leakage_bin
= (u16
*)
3237 (rdev
->mode_info
.atom_context
->bios
+ data_offset
+
3238 le16_to_cpu(profile
->usLeakageBinArrayOffset
));
3239 vddc_id_buf
= (u16
*)
3240 (rdev
->mode_info
.atom_context
->bios
+ data_offset
+
3241 le16_to_cpu(profile
->usElbVDDC_IdArrayOffset
));
3243 (rdev
->mode_info
.atom_context
->bios
+ data_offset
+
3244 le16_to_cpu(profile
->usElbVDDC_LevelArrayOffset
));
3245 vddci_id_buf
= (u16
*)
3246 (rdev
->mode_info
.atom_context
->bios
+ data_offset
+
3247 le16_to_cpu(profile
->usElbVDDCI_IdArrayOffset
));
3249 (rdev
->mode_info
.atom_context
->bios
+ data_offset
+
3250 le16_to_cpu(profile
->usElbVDDCI_LevelArrayOffset
));
3252 if (profile
->ucElbVDDC_Num
> 0) {
3253 for (i
= 0; i
< profile
->ucElbVDDC_Num
; i
++) {
3254 if (vddc_id_buf
[i
] == virtual_voltage_id
) {
3255 for (j
= 0; j
< profile
->ucLeakageBinNum
; j
++) {
3256 if (vbios_voltage_id
<= leakage_bin
[j
]) {
3257 *vddc
= vddc_buf
[j
* profile
->ucElbVDDC_Num
+ i
];
3265 if (profile
->ucElbVDDCI_Num
> 0) {
3266 for (i
= 0; i
< profile
->ucElbVDDCI_Num
; i
++) {
3267 if (vddci_id_buf
[i
] == virtual_voltage_id
) {
3268 for (j
= 0; j
< profile
->ucLeakageBinNum
; j
++) {
3269 if (vbios_voltage_id
<= leakage_bin
[j
]) {
3270 *vddci
= vddci_buf
[j
* profile
->ucElbVDDCI_Num
+ i
];
3280 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3285 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3292 union get_voltage_info
{
3293 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in
;
3294 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out
;
3297 int radeon_atom_get_voltage_evv(struct radeon_device
*rdev
,
3298 u16 virtual_voltage_id
,
3301 int index
= GetIndexIntoMasterTable(COMMAND
, GetVoltageInfo
);
3303 u32 count
= rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.count
;
3304 union get_voltage_info args
;
3306 for (entry_id
= 0; entry_id
< count
; entry_id
++) {
3307 if (rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[entry_id
].v
==
3312 if (entry_id
>= count
)
3315 args
.in
.ucVoltageType
= VOLTAGE_TYPE_VDDC
;
3316 args
.in
.ucVoltageMode
= ATOM_GET_VOLTAGE_EVV_VOLTAGE
;
3317 args
.in
.usVoltageLevel
= cpu_to_le16(virtual_voltage_id
);
3318 args
.in
.ulSCLKFreq
=
3319 cpu_to_le32(rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[entry_id
].clk
);
3321 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3323 *voltage
= le16_to_cpu(args
.evv_out
.usVoltageLevel
);
3328 int radeon_atom_get_voltage_gpio_settings(struct radeon_device
*rdev
,
3329 u16 voltage_level
, u8 voltage_type
,
3330 u32
*gpio_value
, u32
*gpio_mask
)
3332 union set_voltage args
;
3333 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
3336 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
3343 args
.v2
.ucVoltageType
= voltage_type
;
3344 args
.v2
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK
;
3345 args
.v2
.usVoltageLevel
= cpu_to_le16(voltage_level
);
3347 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3349 *gpio_mask
= le32_to_cpu(*(u32
*)&args
.v2
);
3351 args
.v2
.ucVoltageType
= voltage_type
;
3352 args
.v2
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL
;
3353 args
.v2
.usVoltageLevel
= cpu_to_le16(voltage_level
);
3355 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
3357 *gpio_value
= le32_to_cpu(*(u32
*)&args
.v2
);
3360 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3367 union voltage_object_info
{
3368 struct _ATOM_VOLTAGE_OBJECT_INFO v1
;
3369 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2
;
3370 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3
;
3373 union voltage_object
{
3374 struct _ATOM_VOLTAGE_OBJECT v1
;
3375 struct _ATOM_VOLTAGE_OBJECT_V2 v2
;
3376 union _ATOM_VOLTAGE_OBJECT_V3 v3
;
3379 static ATOM_VOLTAGE_OBJECT
*atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO
*v1
,
3382 u32 size
= le16_to_cpu(v1
->sHeader
.usStructureSize
);
3383 u32 offset
= offsetof(ATOM_VOLTAGE_OBJECT_INFO
, asVoltageObj
[0]);
3384 u8
*start
= (u8
*)v1
;
3386 while (offset
< size
) {
3387 ATOM_VOLTAGE_OBJECT
*vo
= (ATOM_VOLTAGE_OBJECT
*)(start
+ offset
);
3388 if (vo
->ucVoltageType
== voltage_type
)
3390 offset
+= offsetof(ATOM_VOLTAGE_OBJECT
, asFormula
.ucVIDAdjustEntries
) +
3391 vo
->asFormula
.ucNumOfVoltageEntries
;
3396 static ATOM_VOLTAGE_OBJECT_V2
*atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2
*v2
,
3399 u32 size
= le16_to_cpu(v2
->sHeader
.usStructureSize
);
3400 u32 offset
= offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2
, asVoltageObj
[0]);
3401 u8
*start
= (u8
*)v2
;
3403 while (offset
< size
) {
3404 ATOM_VOLTAGE_OBJECT_V2
*vo
= (ATOM_VOLTAGE_OBJECT_V2
*)(start
+ offset
);
3405 if (vo
->ucVoltageType
== voltage_type
)
3407 offset
+= offsetof(ATOM_VOLTAGE_OBJECT_V2
, asFormula
.asVIDAdjustEntries
) +
3408 (vo
->asFormula
.ucNumOfVoltageEntries
* sizeof(VOLTAGE_LUT_ENTRY
));
3413 static ATOM_VOLTAGE_OBJECT_V3
*atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1
*v3
,
3414 u8 voltage_type
, u8 voltage_mode
)
3416 u32 size
= le16_to_cpu(v3
->sHeader
.usStructureSize
);
3417 u32 offset
= offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1
, asVoltageObj
[0]);
3418 u8
*start
= (u8
*)v3
;
3420 while (offset
< size
) {
3421 ATOM_VOLTAGE_OBJECT_V3
*vo
= (ATOM_VOLTAGE_OBJECT_V3
*)(start
+ offset
);
3422 if ((vo
->asGpioVoltageObj
.sHeader
.ucVoltageType
== voltage_type
) &&
3423 (vo
->asGpioVoltageObj
.sHeader
.ucVoltageMode
== voltage_mode
))
3425 offset
+= le16_to_cpu(vo
->asGpioVoltageObj
.sHeader
.usSize
);
3431 radeon_atom_is_voltage_gpio(struct radeon_device
*rdev
,
3432 u8 voltage_type
, u8 voltage_mode
)
3434 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
3436 u16 data_offset
, size
;
3437 union voltage_object_info
*voltage_info
;
3438 union voltage_object
*voltage_object
= NULL
;
3440 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3441 &frev
, &crev
, &data_offset
)) {
3442 voltage_info
= (union voltage_object_info
*)
3443 (rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3450 voltage_object
= (union voltage_object
*)
3451 atom_lookup_voltage_object_v1(&voltage_info
->v1
, voltage_type
);
3452 if (voltage_object
&&
3453 (voltage_object
->v1
.asControl
.ucVoltageControlId
== VOLTAGE_CONTROLLED_BY_GPIO
))
3457 voltage_object
= (union voltage_object
*)
3458 atom_lookup_voltage_object_v2(&voltage_info
->v2
, voltage_type
);
3459 if (voltage_object
&&
3460 (voltage_object
->v2
.asControl
.ucVoltageControlId
== VOLTAGE_CONTROLLED_BY_GPIO
))
3464 DRM_ERROR("unknown voltage object table\n");
3471 if (atom_lookup_voltage_object_v3(&voltage_info
->v3
,
3472 voltage_type
, voltage_mode
))
3476 DRM_ERROR("unknown voltage object table\n");
3481 DRM_ERROR("unknown voltage object table\n");
3489 int radeon_atom_get_svi2_info(struct radeon_device
*rdev
,
3491 u8
*svd_gpio_id
, u8
*svc_gpio_id
)
3493 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
3495 u16 data_offset
, size
;
3496 union voltage_object_info
*voltage_info
;
3497 union voltage_object
*voltage_object
= NULL
;
3499 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3500 &frev
, &crev
, &data_offset
)) {
3501 voltage_info
= (union voltage_object_info
*)
3502 (rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3508 voltage_object
= (union voltage_object
*)
3509 atom_lookup_voltage_object_v3(&voltage_info
->v3
,
3512 if (voltage_object
) {
3513 *svd_gpio_id
= voltage_object
->v3
.asSVID2Obj
.ucSVDGpioId
;
3514 *svc_gpio_id
= voltage_object
->v3
.asSVID2Obj
.ucSVCGpioId
;
3520 DRM_ERROR("unknown voltage object table\n");
3525 DRM_ERROR("unknown voltage object table\n");
3533 int radeon_atom_get_max_voltage(struct radeon_device
*rdev
,
3534 u8 voltage_type
, u16
*max_voltage
)
3536 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
3538 u16 data_offset
, size
;
3539 union voltage_object_info
*voltage_info
;
3540 union voltage_object
*voltage_object
= NULL
;
3542 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3543 &frev
, &crev
, &data_offset
)) {
3544 voltage_info
= (union voltage_object_info
*)
3545 (rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3549 voltage_object
= (union voltage_object
*)
3550 atom_lookup_voltage_object_v1(&voltage_info
->v1
, voltage_type
);
3551 if (voltage_object
) {
3552 ATOM_VOLTAGE_FORMULA
*formula
=
3553 &voltage_object
->v1
.asFormula
;
3554 if (formula
->ucFlag
& 1)
3556 le16_to_cpu(formula
->usVoltageBaseLevel
) +
3557 formula
->ucNumOfVoltageEntries
/ 2 *
3558 le16_to_cpu(formula
->usVoltageStep
);
3561 le16_to_cpu(formula
->usVoltageBaseLevel
) +
3562 (formula
->ucNumOfVoltageEntries
- 1) *
3563 le16_to_cpu(formula
->usVoltageStep
);
3568 voltage_object
= (union voltage_object
*)
3569 atom_lookup_voltage_object_v2(&voltage_info
->v2
, voltage_type
);
3570 if (voltage_object
) {
3571 ATOM_VOLTAGE_FORMULA_V2
*formula
=
3572 &voltage_object
->v2
.asFormula
;
3573 if (formula
->ucNumOfVoltageEntries
) {
3574 VOLTAGE_LUT_ENTRY
*lut
= (VOLTAGE_LUT_ENTRY
*)
3575 ((u8
*)&formula
->asVIDAdjustEntries
[0] +
3576 (sizeof(VOLTAGE_LUT_ENTRY
) * (formula
->ucNumOfVoltageEntries
- 1)));
3578 le16_to_cpu(lut
->usVoltageValue
);
3584 DRM_ERROR("unknown voltage object table\n");
3592 int radeon_atom_get_min_voltage(struct radeon_device
*rdev
,
3593 u8 voltage_type
, u16
*min_voltage
)
3595 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
3597 u16 data_offset
, size
;
3598 union voltage_object_info
*voltage_info
;
3599 union voltage_object
*voltage_object
= NULL
;
3601 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3602 &frev
, &crev
, &data_offset
)) {
3603 voltage_info
= (union voltage_object_info
*)
3604 (rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3608 voltage_object
= (union voltage_object
*)
3609 atom_lookup_voltage_object_v1(&voltage_info
->v1
, voltage_type
);
3610 if (voltage_object
) {
3611 ATOM_VOLTAGE_FORMULA
*formula
=
3612 &voltage_object
->v1
.asFormula
;
3614 le16_to_cpu(formula
->usVoltageBaseLevel
);
3619 voltage_object
= (union voltage_object
*)
3620 atom_lookup_voltage_object_v2(&voltage_info
->v2
, voltage_type
);
3621 if (voltage_object
) {
3622 ATOM_VOLTAGE_FORMULA_V2
*formula
=
3623 &voltage_object
->v2
.asFormula
;
3624 if (formula
->ucNumOfVoltageEntries
) {
3626 le16_to_cpu(formula
->asVIDAdjustEntries
[
3634 DRM_ERROR("unknown voltage object table\n");
3642 int radeon_atom_get_voltage_step(struct radeon_device
*rdev
,
3643 u8 voltage_type
, u16
*voltage_step
)
3645 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
3647 u16 data_offset
, size
;
3648 union voltage_object_info
*voltage_info
;
3649 union voltage_object
*voltage_object
= NULL
;
3651 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3652 &frev
, &crev
, &data_offset
)) {
3653 voltage_info
= (union voltage_object_info
*)
3654 (rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3658 voltage_object
= (union voltage_object
*)
3659 atom_lookup_voltage_object_v1(&voltage_info
->v1
, voltage_type
);
3660 if (voltage_object
) {
3661 ATOM_VOLTAGE_FORMULA
*formula
=
3662 &voltage_object
->v1
.asFormula
;
3663 if (formula
->ucFlag
& 1)
3665 (le16_to_cpu(formula
->usVoltageStep
) + 1) / 2;
3668 le16_to_cpu(formula
->usVoltageStep
);
3675 DRM_ERROR("unknown voltage object table\n");
3683 int radeon_atom_round_to_true_voltage(struct radeon_device
*rdev
,
3685 u16 nominal_voltage
,
3688 u16 min_voltage
, max_voltage
, voltage_step
;
3690 if (radeon_atom_get_max_voltage(rdev
, voltage_type
, &max_voltage
))
3692 if (radeon_atom_get_min_voltage(rdev
, voltage_type
, &min_voltage
))
3694 if (radeon_atom_get_voltage_step(rdev
, voltage_type
, &voltage_step
))
3697 if (nominal_voltage
<= min_voltage
)
3698 *true_voltage
= min_voltage
;
3699 else if (nominal_voltage
>= max_voltage
)
3700 *true_voltage
= max_voltage
;
3702 *true_voltage
= min_voltage
+
3703 ((nominal_voltage
- min_voltage
) / voltage_step
) *
3709 int radeon_atom_get_voltage_table(struct radeon_device
*rdev
,
3710 u8 voltage_type
, u8 voltage_mode
,
3711 struct atom_voltage_table
*voltage_table
)
3713 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
3715 u16 data_offset
, size
;
3717 union voltage_object_info
*voltage_info
;
3718 union voltage_object
*voltage_object
= NULL
;
3720 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3721 &frev
, &crev
, &data_offset
)) {
3722 voltage_info
= (union voltage_object_info
*)
3723 (rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3730 DRM_ERROR("old table version %d, %d\n", frev
, crev
);
3733 voltage_object
= (union voltage_object
*)
3734 atom_lookup_voltage_object_v2(&voltage_info
->v2
, voltage_type
);
3735 if (voltage_object
) {
3736 ATOM_VOLTAGE_FORMULA_V2
*formula
=
3737 &voltage_object
->v2
.asFormula
;
3738 VOLTAGE_LUT_ENTRY
*lut
;
3739 if (formula
->ucNumOfVoltageEntries
> MAX_VOLTAGE_ENTRIES
)
3741 lut
= &formula
->asVIDAdjustEntries
[0];
3742 for (i
= 0; i
< formula
->ucNumOfVoltageEntries
; i
++) {
3743 voltage_table
->entries
[i
].value
=
3744 le16_to_cpu(lut
->usVoltageValue
);
3745 ret
= radeon_atom_get_voltage_gpio_settings(rdev
,
3746 voltage_table
->entries
[i
].value
,
3748 &voltage_table
->entries
[i
].smio_low
,
3749 &voltage_table
->mask_low
);
3752 lut
= (VOLTAGE_LUT_ENTRY
*)
3753 ((u8
*)lut
+ sizeof(VOLTAGE_LUT_ENTRY
));
3755 voltage_table
->count
= formula
->ucNumOfVoltageEntries
;
3760 DRM_ERROR("unknown voltage object table\n");
3767 voltage_object
= (union voltage_object
*)
3768 atom_lookup_voltage_object_v3(&voltage_info
->v3
,
3769 voltage_type
, voltage_mode
);
3770 if (voltage_object
) {
3771 ATOM_GPIO_VOLTAGE_OBJECT_V3
*gpio
=
3772 &voltage_object
->v3
.asGpioVoltageObj
;
3773 VOLTAGE_LUT_ENTRY_V2
*lut
;
3774 if (gpio
->ucGpioEntryNum
> MAX_VOLTAGE_ENTRIES
)
3776 lut
= &gpio
->asVolGpioLut
[0];
3777 for (i
= 0; i
< gpio
->ucGpioEntryNum
; i
++) {
3778 voltage_table
->entries
[i
].value
=
3779 le16_to_cpu(lut
->usVoltageValue
);
3780 voltage_table
->entries
[i
].smio_low
=
3781 le32_to_cpu(lut
->ulVoltageId
);
3782 lut
= (VOLTAGE_LUT_ENTRY_V2
*)
3783 ((u8
*)lut
+ sizeof(VOLTAGE_LUT_ENTRY_V2
));
3785 voltage_table
->mask_low
= le32_to_cpu(gpio
->ulGpioMaskVal
);
3786 voltage_table
->count
= gpio
->ucGpioEntryNum
;
3787 voltage_table
->phase_delay
= gpio
->ucPhaseDelay
;
3792 DRM_ERROR("unknown voltage object table\n");
3797 DRM_ERROR("unknown voltage object table\n");
3805 struct _ATOM_VRAM_INFO_V3 v1_3
;
3806 struct _ATOM_VRAM_INFO_V4 v1_4
;
3807 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1
;
3810 int radeon_atom_get_memory_info(struct radeon_device
*rdev
,
3811 u8 module_index
, struct atom_memory_info
*mem_info
)
3813 int index
= GetIndexIntoMasterTable(DATA
, VRAM_Info
);
3815 u16 data_offset
, size
;
3816 union vram_info
*vram_info
;
3818 memset(mem_info
, 0, sizeof(struct atom_memory_info
));
3820 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3821 &frev
, &crev
, &data_offset
)) {
3822 vram_info
= (union vram_info
*)
3823 (rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3829 if (module_index
< vram_info
->v1_3
.ucNumOfVRAMModule
) {
3830 ATOM_VRAM_MODULE_V3
*vram_module
=
3831 (ATOM_VRAM_MODULE_V3
*)vram_info
->v1_3
.aVramInfo
;
3833 for (i
= 0; i
< module_index
; i
++) {
3834 if (le16_to_cpu(vram_module
->usSize
) == 0)
3836 vram_module
= (ATOM_VRAM_MODULE_V3
*)
3837 ((u8
*)vram_module
+ le16_to_cpu(vram_module
->usSize
));
3839 mem_info
->mem_vendor
= vram_module
->asMemory
.ucMemoryVenderID
& 0xf;
3840 mem_info
->mem_type
= vram_module
->asMemory
.ucMemoryType
& 0xf0;
3845 /* r7xx, evergreen */
3846 if (module_index
< vram_info
->v1_4
.ucNumOfVRAMModule
) {
3847 ATOM_VRAM_MODULE_V4
*vram_module
=
3848 (ATOM_VRAM_MODULE_V4
*)vram_info
->v1_4
.aVramInfo
;
3850 for (i
= 0; i
< module_index
; i
++) {
3851 if (le16_to_cpu(vram_module
->usModuleSize
) == 0)
3853 vram_module
= (ATOM_VRAM_MODULE_V4
*)
3854 ((u8
*)vram_module
+ le16_to_cpu(vram_module
->usModuleSize
));
3856 mem_info
->mem_vendor
= vram_module
->ucMemoryVenderID
& 0xf;
3857 mem_info
->mem_type
= vram_module
->ucMemoryType
& 0xf0;
3862 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3870 if (module_index
< vram_info
->v2_1
.ucNumOfVRAMModule
) {
3871 ATOM_VRAM_MODULE_V7
*vram_module
=
3872 (ATOM_VRAM_MODULE_V7
*)vram_info
->v2_1
.aVramInfo
;
3874 for (i
= 0; i
< module_index
; i
++) {
3875 if (le16_to_cpu(vram_module
->usModuleSize
) == 0)
3877 vram_module
= (ATOM_VRAM_MODULE_V7
*)
3878 ((u8
*)vram_module
+ le16_to_cpu(vram_module
->usModuleSize
));
3880 mem_info
->mem_vendor
= vram_module
->ucMemoryVenderID
& 0xf;
3881 mem_info
->mem_type
= vram_module
->ucMemoryType
& 0xf0;
3886 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3891 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3899 int radeon_atom_get_mclk_range_table(struct radeon_device
*rdev
,
3900 bool gddr5
, u8 module_index
,
3901 struct atom_memory_clock_range_table
*mclk_range_table
)
3903 int index
= GetIndexIntoMasterTable(DATA
, VRAM_Info
);
3905 u16 data_offset
, size
;
3906 union vram_info
*vram_info
;
3907 u32 mem_timing_size
= gddr5
?
3908 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2
) : sizeof(ATOM_MEMORY_TIMING_FORMAT
);
3910 memset(mclk_range_table
, 0, sizeof(struct atom_memory_clock_range_table
));
3912 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3913 &frev
, &crev
, &data_offset
)) {
3914 vram_info
= (union vram_info
*)
3915 (rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3920 DRM_ERROR("old table version %d, %d\n", frev
, crev
);
3923 /* r7xx, evergreen */
3924 if (module_index
< vram_info
->v1_4
.ucNumOfVRAMModule
) {
3925 ATOM_VRAM_MODULE_V4
*vram_module
=
3926 (ATOM_VRAM_MODULE_V4
*)vram_info
->v1_4
.aVramInfo
;
3927 ATOM_MEMORY_TIMING_FORMAT
*format
;
3929 for (i
= 0; i
< module_index
; i
++) {
3930 if (le16_to_cpu(vram_module
->usModuleSize
) == 0)
3932 vram_module
= (ATOM_VRAM_MODULE_V4
*)
3933 ((u8
*)vram_module
+ le16_to_cpu(vram_module
->usModuleSize
));
3935 mclk_range_table
->num_entries
= (u8
)
3936 ((le16_to_cpu(vram_module
->usModuleSize
) - offsetof(ATOM_VRAM_MODULE_V4
, asMemTiming
)) /
3938 format
= &vram_module
->asMemTiming
[0];
3939 for (i
= 0; i
< mclk_range_table
->num_entries
; i
++) {
3940 mclk_range_table
->mclk
[i
] = le32_to_cpu(format
->ulClkRange
);
3941 format
= (ATOM_MEMORY_TIMING_FORMAT
*)
3942 ((u8
*)format
+ mem_timing_size
);
3948 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3953 DRM_ERROR("new table version %d, %d\n", frev
, crev
);
3956 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
3964 #define MEM_ID_MASK 0xff000000
3965 #define MEM_ID_SHIFT 24
3966 #define CLOCK_RANGE_MASK 0x00ffffff
3967 #define CLOCK_RANGE_SHIFT 0
3968 #define LOW_NIBBLE_MASK 0xf
3969 #define DATA_EQU_PREV 0
3970 #define DATA_FROM_TABLE 4
3972 int radeon_atom_init_mc_reg_table(struct radeon_device
*rdev
,
3974 struct atom_mc_reg_table
*reg_table
)
3976 int index
= GetIndexIntoMasterTable(DATA
, VRAM_Info
);
3977 u8 frev
, crev
, num_entries
, t_mem_id
, num_ranges
= 0;
3979 u16 data_offset
, size
;
3980 union vram_info
*vram_info
;
3982 memset(reg_table
, 0, sizeof(struct atom_mc_reg_table
));
3984 if (atom_parse_data_header(rdev
->mode_info
.atom_context
, index
, &size
,
3985 &frev
, &crev
, &data_offset
)) {
3986 vram_info
= (union vram_info
*)
3987 (rdev
->mode_info
.atom_context
->bios
+ data_offset
);
3990 DRM_ERROR("old table version %d, %d\n", frev
, crev
);
3995 if (module_index
< vram_info
->v2_1
.ucNumOfVRAMModule
) {
3996 ATOM_INIT_REG_BLOCK
*reg_block
=
3997 (ATOM_INIT_REG_BLOCK
*)
3998 ((u8
*)vram_info
+ le16_to_cpu(vram_info
->v2_1
.usMemClkPatchTblOffset
));
3999 ATOM_MEMORY_SETTING_DATA_BLOCK
*reg_data
=
4000 (ATOM_MEMORY_SETTING_DATA_BLOCK
*)
4001 ((u8
*)reg_block
+ (2 * sizeof(u16
)) +
4002 le16_to_cpu(reg_block
->usRegIndexTblSize
));
4003 ATOM_INIT_REG_INDEX_FORMAT
*format
= ®_block
->asRegIndexBuf
[0];
4004 num_entries
= (u8
)((le16_to_cpu(reg_block
->usRegIndexTblSize
)) /
4005 sizeof(ATOM_INIT_REG_INDEX_FORMAT
)) - 1;
4006 if (num_entries
> VBIOS_MC_REGISTER_ARRAY_SIZE
)
4008 while (i
< num_entries
) {
4009 if (format
->ucPreRegDataLength
& ACCESS_PLACEHOLDER
)
4011 reg_table
->mc_reg_address
[i
].s1
=
4012 (u16
)(le16_to_cpu(format
->usRegIndex
));
4013 reg_table
->mc_reg_address
[i
].pre_reg_data
=
4014 (u8
)(format
->ucPreRegDataLength
);
4016 format
= (ATOM_INIT_REG_INDEX_FORMAT
*)
4017 ((u8
*)format
+ sizeof(ATOM_INIT_REG_INDEX_FORMAT
));
4019 reg_table
->last
= i
;
4020 while ((le32_to_cpu(*(u32
*)reg_data
) != END_OF_REG_DATA_BLOCK
) &&
4021 (num_ranges
< VBIOS_MAX_AC_TIMING_ENTRIES
)) {
4022 t_mem_id
= (u8
)((le32_to_cpu(*(u32
*)reg_data
) & MEM_ID_MASK
)
4024 if (module_index
== t_mem_id
) {
4025 reg_table
->mc_reg_table_entry
[num_ranges
].mclk_max
=
4026 (u32
)((le32_to_cpu(*(u32
*)reg_data
) & CLOCK_RANGE_MASK
)
4027 >> CLOCK_RANGE_SHIFT
);
4028 for (i
= 0, j
= 1; i
< reg_table
->last
; i
++) {
4029 if ((reg_table
->mc_reg_address
[i
].pre_reg_data
& LOW_NIBBLE_MASK
) == DATA_FROM_TABLE
) {
4030 reg_table
->mc_reg_table_entry
[num_ranges
].mc_data
[i
] =
4031 (u32
)le32_to_cpu(*((u32
*)reg_data
+ j
));
4033 } else if ((reg_table
->mc_reg_address
[i
].pre_reg_data
& LOW_NIBBLE_MASK
) == DATA_EQU_PREV
) {
4034 reg_table
->mc_reg_table_entry
[num_ranges
].mc_data
[i
] =
4035 reg_table
->mc_reg_table_entry
[num_ranges
].mc_data
[i
- 1];
4040 reg_data
= (ATOM_MEMORY_SETTING_DATA_BLOCK
*)
4041 ((u8
*)reg_data
+ le16_to_cpu(reg_block
->usRegDataBlkSize
));
4043 if (le32_to_cpu(*(u32
*)reg_data
) != END_OF_REG_DATA_BLOCK
)
4045 reg_table
->num_entries
= num_ranges
;
4050 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
4055 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
4063 void radeon_atom_initialize_bios_scratch_regs(struct drm_device
*dev
)
4065 struct radeon_device
*rdev
= dev
->dev_private
;
4066 uint32_t bios_2_scratch
, bios_6_scratch
;
4068 if (rdev
->family
>= CHIP_R600
) {
4069 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
4070 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
4072 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
4073 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
4076 /* let the bios control the backlight */
4077 bios_2_scratch
&= ~ATOM_S2_VRI_BRIGHT_ENABLE
;
4079 /* tell the bios not to handle mode switching */
4080 bios_6_scratch
|= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
;
4082 /* clear the vbios dpms state */
4083 if (ASIC_IS_DCE4(rdev
))
4084 bios_2_scratch
&= ~ATOM_S2_DEVICE_DPMS_STATE
;
4086 if (rdev
->family
>= CHIP_R600
) {
4087 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
4088 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
4090 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
4091 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
4096 void radeon_save_bios_scratch_regs(struct radeon_device
*rdev
)
4098 uint32_t scratch_reg
;
4101 if (rdev
->family
>= CHIP_R600
)
4102 scratch_reg
= R600_BIOS_0_SCRATCH
;
4104 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
4106 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
4107 rdev
->bios_scratch
[i
] = RREG32(scratch_reg
+ (i
* 4));
4110 void radeon_restore_bios_scratch_regs(struct radeon_device
*rdev
)
4112 uint32_t scratch_reg
;
4115 if (rdev
->family
>= CHIP_R600
)
4116 scratch_reg
= R600_BIOS_0_SCRATCH
;
4118 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
4120 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
4121 WREG32(scratch_reg
+ (i
* 4), rdev
->bios_scratch
[i
]);
4124 void radeon_atom_output_lock(struct drm_encoder
*encoder
, bool lock
)
4126 struct drm_device
*dev
= encoder
->dev
;
4127 struct radeon_device
*rdev
= dev
->dev_private
;
4128 uint32_t bios_6_scratch
;
4130 if (rdev
->family
>= CHIP_R600
)
4131 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
4133 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
4136 bios_6_scratch
|= ATOM_S6_CRITICAL_STATE
;
4137 bios_6_scratch
&= ~ATOM_S6_ACC_MODE
;
4139 bios_6_scratch
&= ~ATOM_S6_CRITICAL_STATE
;
4140 bios_6_scratch
|= ATOM_S6_ACC_MODE
;
4143 if (rdev
->family
>= CHIP_R600
)
4144 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
4146 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
4149 /* at some point we may want to break this out into individual functions */
4151 radeon_atombios_connected_scratch_regs(struct drm_connector
*connector
,
4152 struct drm_encoder
*encoder
,
4155 struct drm_device
*dev
= connector
->dev
;
4156 struct radeon_device
*rdev
= dev
->dev_private
;
4157 struct radeon_connector
*radeon_connector
=
4158 to_radeon_connector(connector
);
4159 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
4160 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
4162 if (rdev
->family
>= CHIP_R600
) {
4163 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
4164 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
4165 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
4167 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
4168 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
4169 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
4172 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
4173 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
4175 DRM_DEBUG_KMS("TV1 connected\n");
4176 bios_3_scratch
|= ATOM_S3_TV1_ACTIVE
;
4177 bios_6_scratch
|= ATOM_S6_ACC_REQ_TV1
;
4179 DRM_DEBUG_KMS("TV1 disconnected\n");
4180 bios_0_scratch
&= ~ATOM_S0_TV1_MASK
;
4181 bios_3_scratch
&= ~ATOM_S3_TV1_ACTIVE
;
4182 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_TV1
;
4185 if ((radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) &&
4186 (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
)) {
4188 DRM_DEBUG_KMS("CV connected\n");
4189 bios_3_scratch
|= ATOM_S3_CV_ACTIVE
;
4190 bios_6_scratch
|= ATOM_S6_ACC_REQ_CV
;
4192 DRM_DEBUG_KMS("CV disconnected\n");
4193 bios_0_scratch
&= ~ATOM_S0_CV_MASK
;
4194 bios_3_scratch
&= ~ATOM_S3_CV_ACTIVE
;
4195 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CV
;
4198 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
4199 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
4201 DRM_DEBUG_KMS("LCD1 connected\n");
4202 bios_0_scratch
|= ATOM_S0_LCD1
;
4203 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
4204 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
4206 DRM_DEBUG_KMS("LCD1 disconnected\n");
4207 bios_0_scratch
&= ~ATOM_S0_LCD1
;
4208 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
4209 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
4212 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
4213 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
4215 DRM_DEBUG_KMS("CRT1 connected\n");
4216 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
4217 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
4218 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
4220 DRM_DEBUG_KMS("CRT1 disconnected\n");
4221 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
4222 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
4223 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
4226 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
4227 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
4229 DRM_DEBUG_KMS("CRT2 connected\n");
4230 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
4231 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
4232 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
4234 DRM_DEBUG_KMS("CRT2 disconnected\n");
4235 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
4236 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
4237 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
4240 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
4241 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
4243 DRM_DEBUG_KMS("DFP1 connected\n");
4244 bios_0_scratch
|= ATOM_S0_DFP1
;
4245 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
4246 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
4248 DRM_DEBUG_KMS("DFP1 disconnected\n");
4249 bios_0_scratch
&= ~ATOM_S0_DFP1
;
4250 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
4251 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
4254 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
4255 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
4257 DRM_DEBUG_KMS("DFP2 connected\n");
4258 bios_0_scratch
|= ATOM_S0_DFP2
;
4259 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
4260 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
4262 DRM_DEBUG_KMS("DFP2 disconnected\n");
4263 bios_0_scratch
&= ~ATOM_S0_DFP2
;
4264 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
4265 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
4268 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
4269 (radeon_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
4271 DRM_DEBUG_KMS("DFP3 connected\n");
4272 bios_0_scratch
|= ATOM_S0_DFP3
;
4273 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
4274 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
4276 DRM_DEBUG_KMS("DFP3 disconnected\n");
4277 bios_0_scratch
&= ~ATOM_S0_DFP3
;
4278 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
4279 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
4282 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
4283 (radeon_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
4285 DRM_DEBUG_KMS("DFP4 connected\n");
4286 bios_0_scratch
|= ATOM_S0_DFP4
;
4287 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
4288 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
4290 DRM_DEBUG_KMS("DFP4 disconnected\n");
4291 bios_0_scratch
&= ~ATOM_S0_DFP4
;
4292 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
4293 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
4296 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
4297 (radeon_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
4299 DRM_DEBUG_KMS("DFP5 connected\n");
4300 bios_0_scratch
|= ATOM_S0_DFP5
;
4301 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
4302 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
4304 DRM_DEBUG_KMS("DFP5 disconnected\n");
4305 bios_0_scratch
&= ~ATOM_S0_DFP5
;
4306 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
4307 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
4310 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP6_SUPPORT
) &&
4311 (radeon_connector
->devices
& ATOM_DEVICE_DFP6_SUPPORT
)) {
4313 DRM_DEBUG_KMS("DFP6 connected\n");
4314 bios_0_scratch
|= ATOM_S0_DFP6
;
4315 bios_3_scratch
|= ATOM_S3_DFP6_ACTIVE
;
4316 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP6
;
4318 DRM_DEBUG_KMS("DFP6 disconnected\n");
4319 bios_0_scratch
&= ~ATOM_S0_DFP6
;
4320 bios_3_scratch
&= ~ATOM_S3_DFP6_ACTIVE
;
4321 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP6
;
4325 if (rdev
->family
>= CHIP_R600
) {
4326 WREG32(R600_BIOS_0_SCRATCH
, bios_0_scratch
);
4327 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
4328 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
4330 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
4331 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
4332 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
4337 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
4339 struct drm_device
*dev
= encoder
->dev
;
4340 struct radeon_device
*rdev
= dev
->dev_private
;
4341 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
4342 uint32_t bios_3_scratch
;
4344 if (ASIC_IS_DCE4(rdev
))
4347 if (rdev
->family
>= CHIP_R600
)
4348 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
4350 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
4352 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
4353 bios_3_scratch
&= ~ATOM_S3_TV1_CRTC_ACTIVE
;
4354 bios_3_scratch
|= (crtc
<< 18);
4356 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
4357 bios_3_scratch
&= ~ATOM_S3_CV_CRTC_ACTIVE
;
4358 bios_3_scratch
|= (crtc
<< 24);
4360 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
4361 bios_3_scratch
&= ~ATOM_S3_CRT1_CRTC_ACTIVE
;
4362 bios_3_scratch
|= (crtc
<< 16);
4364 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
4365 bios_3_scratch
&= ~ATOM_S3_CRT2_CRTC_ACTIVE
;
4366 bios_3_scratch
|= (crtc
<< 20);
4368 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
4369 bios_3_scratch
&= ~ATOM_S3_LCD1_CRTC_ACTIVE
;
4370 bios_3_scratch
|= (crtc
<< 17);
4372 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
4373 bios_3_scratch
&= ~ATOM_S3_DFP1_CRTC_ACTIVE
;
4374 bios_3_scratch
|= (crtc
<< 19);
4376 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
4377 bios_3_scratch
&= ~ATOM_S3_DFP2_CRTC_ACTIVE
;
4378 bios_3_scratch
|= (crtc
<< 23);
4380 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
4381 bios_3_scratch
&= ~ATOM_S3_DFP3_CRTC_ACTIVE
;
4382 bios_3_scratch
|= (crtc
<< 25);
4385 if (rdev
->family
>= CHIP_R600
)
4386 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
4388 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
4392 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
4394 struct drm_device
*dev
= encoder
->dev
;
4395 struct radeon_device
*rdev
= dev
->dev_private
;
4396 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
4397 uint32_t bios_2_scratch
;
4399 if (ASIC_IS_DCE4(rdev
))
4402 if (rdev
->family
>= CHIP_R600
)
4403 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
4405 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
4407 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
4409 bios_2_scratch
&= ~ATOM_S2_TV1_DPMS_STATE
;
4411 bios_2_scratch
|= ATOM_S2_TV1_DPMS_STATE
;
4413 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
4415 bios_2_scratch
&= ~ATOM_S2_CV_DPMS_STATE
;
4417 bios_2_scratch
|= ATOM_S2_CV_DPMS_STATE
;
4419 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
4421 bios_2_scratch
&= ~ATOM_S2_CRT1_DPMS_STATE
;
4423 bios_2_scratch
|= ATOM_S2_CRT1_DPMS_STATE
;
4425 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
4427 bios_2_scratch
&= ~ATOM_S2_CRT2_DPMS_STATE
;
4429 bios_2_scratch
|= ATOM_S2_CRT2_DPMS_STATE
;
4431 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
4433 bios_2_scratch
&= ~ATOM_S2_LCD1_DPMS_STATE
;
4435 bios_2_scratch
|= ATOM_S2_LCD1_DPMS_STATE
;
4437 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
4439 bios_2_scratch
&= ~ATOM_S2_DFP1_DPMS_STATE
;
4441 bios_2_scratch
|= ATOM_S2_DFP1_DPMS_STATE
;
4443 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
4445 bios_2_scratch
&= ~ATOM_S2_DFP2_DPMS_STATE
;
4447 bios_2_scratch
|= ATOM_S2_DFP2_DPMS_STATE
;
4449 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
4451 bios_2_scratch
&= ~ATOM_S2_DFP3_DPMS_STATE
;
4453 bios_2_scratch
|= ATOM_S2_DFP3_DPMS_STATE
;
4455 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) {
4457 bios_2_scratch
&= ~ATOM_S2_DFP4_DPMS_STATE
;
4459 bios_2_scratch
|= ATOM_S2_DFP4_DPMS_STATE
;
4461 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) {
4463 bios_2_scratch
&= ~ATOM_S2_DFP5_DPMS_STATE
;
4465 bios_2_scratch
|= ATOM_S2_DFP5_DPMS_STATE
;
4468 if (rdev
->family
>= CHIP_R600
)
4469 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
4471 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);