2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_id(struct drm_device
*dev
, uint32_t supported_device
,
37 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
39 radeon_add_atom_encoder(struct drm_device
*dev
, uint32_t encoder_id
,
40 uint32_t supported_device
);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device
*dev
,
45 uint32_t connector_id
,
46 uint32_t supported_device
,
48 struct radeon_i2c_bus_rec
*i2c_bus
,
49 bool linkb
, uint32_t igp_lane_info
,
50 uint16_t connector_object_id
,
51 struct radeon_hpd
*hpd
);
53 /* from radeon_legacy_encoder.c */
55 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_id
,
56 uint32_t supported_device
);
58 union atom_supported_devices
{
59 struct _ATOM_SUPPORTED_DEVICES_INFO info
;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2
;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1
;
64 static inline struct radeon_i2c_bus_rec
radeon_lookup_i2c_gpio(struct radeon_device
*rdev
,
67 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
68 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
69 struct radeon_i2c_bus_rec i2c
;
70 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
71 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
75 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
78 atom_parse_data_header(ctx
, index
, NULL
, NULL
, NULL
, &data_offset
);
80 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
83 for (i
= 0; i
< ATOM_MAX_SUPPORTED_DEVICE
; i
++) {
84 gpio
= &i2c_info
->asGPIO_Info
[i
];
86 if (gpio
->sucI2cId
.ucAccess
== id
) {
87 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
) * 4;
88 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
) * 4;
89 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
) * 4;
90 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
) * 4;
91 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
) * 4;
92 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
) * 4;
93 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
) * 4;
94 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
) * 4;
95 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
96 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
97 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
98 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
99 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
100 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
101 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
102 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
104 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
105 i2c
.hw_capable
= true;
107 i2c
.hw_capable
= false;
109 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
114 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
124 static inline struct radeon_gpio_rec
radeon_lookup_gpio(struct radeon_device
*rdev
,
127 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
128 struct radeon_gpio_rec gpio
;
129 int index
= GetIndexIntoMasterTable(DATA
, GPIO_Pin_LUT
);
130 struct _ATOM_GPIO_PIN_LUT
*gpio_info
;
131 ATOM_GPIO_PIN_ASSIGNMENT
*pin
;
132 u16 data_offset
, size
;
135 memset(&gpio
, 0, sizeof(struct radeon_gpio_rec
));
138 atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
);
140 gpio_info
= (struct _ATOM_GPIO_PIN_LUT
*)(ctx
->bios
+ data_offset
);
142 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT
);
144 for (i
= 0; i
< num_indices
; i
++) {
145 pin
= &gpio_info
->asGPIO_Pin
[i
];
146 if (id
== pin
->ucGPIO_ID
) {
147 gpio
.id
= pin
->ucGPIO_ID
;
148 gpio
.reg
= pin
->usGpioPin_AIndex
* 4;
149 gpio
.mask
= (1 << pin
->ucGpioPinBitShift
);
158 static struct radeon_hpd
radeon_atom_get_hpd_info_from_gpio(struct radeon_device
*rdev
,
159 struct radeon_gpio_rec
*gpio
)
161 struct radeon_hpd hpd
;
163 if (gpio
->reg
== AVIVO_DC_GPIO_HPD_A
) {
166 hpd
.hpd
= RADEON_HPD_1
;
169 hpd
.hpd
= RADEON_HPD_2
;
172 hpd
.hpd
= RADEON_HPD_3
;
175 hpd
.hpd
= RADEON_HPD_4
;
178 hpd
.hpd
= RADEON_HPD_5
;
181 hpd
.hpd
= RADEON_HPD_6
;
184 hpd
.hpd
= RADEON_HPD_NONE
;
188 hpd
.hpd
= RADEON_HPD_NONE
;
192 static bool radeon_atom_apply_quirks(struct drm_device
*dev
,
193 uint32_t supported_device
,
195 struct radeon_i2c_bus_rec
*i2c_bus
,
197 struct radeon_hpd
*hpd
)
200 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
201 if ((dev
->pdev
->device
== 0x791e) &&
202 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
203 (dev
->pdev
->subsystem_device
== 0x826d)) {
204 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
205 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
206 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
209 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
210 if ((dev
->pdev
->device
== 0x7941) &&
211 (dev
->pdev
->subsystem_vendor
== 0x147b) &&
212 (dev
->pdev
->subsystem_device
== 0x2412)) {
213 if (*connector_type
== DRM_MODE_CONNECTOR_DVII
)
217 /* Falcon NW laptop lists vga ddc line for LVDS */
218 if ((dev
->pdev
->device
== 0x5653) &&
219 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
220 (dev
->pdev
->subsystem_device
== 0x0291)) {
221 if (*connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
222 i2c_bus
->valid
= false;
227 /* HIS X1300 is DVI+VGA, not DVI+DVI */
228 if ((dev
->pdev
->device
== 0x7146) &&
229 (dev
->pdev
->subsystem_vendor
== 0x17af) &&
230 (dev
->pdev
->subsystem_device
== 0x2058)) {
231 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
235 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
236 if ((dev
->pdev
->device
== 0x7142) &&
237 (dev
->pdev
->subsystem_vendor
== 0x1458) &&
238 (dev
->pdev
->subsystem_device
== 0x2134)) {
239 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
245 if ((dev
->pdev
->device
== 0x71C5) &&
246 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
247 (dev
->pdev
->subsystem_device
== 0x0080)) {
248 if ((supported_device
== ATOM_DEVICE_CRT1_SUPPORT
) ||
249 (supported_device
== ATOM_DEVICE_DFP2_SUPPORT
))
253 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
254 if ((dev
->pdev
->device
== 0x9598) &&
255 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
256 (dev
->pdev
->subsystem_device
== 0x01da)) {
257 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
258 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
262 /* ASUS HD 3450 board lists the DVI port as HDMI */
263 if ((dev
->pdev
->device
== 0x95C5) &&
264 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
265 (dev
->pdev
->subsystem_device
== 0x01e2)) {
266 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
267 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
271 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
272 * HDMI + VGA reporting as HDMI
274 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
275 if (supported_device
& (ATOM_DEVICE_CRT_SUPPORT
)) {
276 *connector_type
= DRM_MODE_CONNECTOR_VGA
;
281 /* Acer laptop reports DVI-D as DVI-I */
282 if ((dev
->pdev
->device
== 0x95c4) &&
283 (dev
->pdev
->subsystem_vendor
== 0x1025) &&
284 (dev
->pdev
->subsystem_device
== 0x013c)) {
285 if ((*connector_type
== DRM_MODE_CONNECTOR_DVII
) &&
286 (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
))
287 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
293 const int supported_devices_connector_convert
[] = {
294 DRM_MODE_CONNECTOR_Unknown
,
295 DRM_MODE_CONNECTOR_VGA
,
296 DRM_MODE_CONNECTOR_DVII
,
297 DRM_MODE_CONNECTOR_DVID
,
298 DRM_MODE_CONNECTOR_DVIA
,
299 DRM_MODE_CONNECTOR_SVIDEO
,
300 DRM_MODE_CONNECTOR_Composite
,
301 DRM_MODE_CONNECTOR_LVDS
,
302 DRM_MODE_CONNECTOR_Unknown
,
303 DRM_MODE_CONNECTOR_Unknown
,
304 DRM_MODE_CONNECTOR_HDMIA
,
305 DRM_MODE_CONNECTOR_HDMIB
,
306 DRM_MODE_CONNECTOR_Unknown
,
307 DRM_MODE_CONNECTOR_Unknown
,
308 DRM_MODE_CONNECTOR_9PinDIN
,
309 DRM_MODE_CONNECTOR_DisplayPort
312 const uint16_t supported_devices_connector_object_id_convert
[] = {
313 CONNECTOR_OBJECT_ID_NONE
,
314 CONNECTOR_OBJECT_ID_VGA
,
315 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
, /* not all boards support DL */
316 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
, /* not all boards support DL */
317 CONNECTOR_OBJECT_ID_VGA
, /* technically DVI-A */
318 CONNECTOR_OBJECT_ID_COMPOSITE
,
319 CONNECTOR_OBJECT_ID_SVIDEO
,
320 CONNECTOR_OBJECT_ID_LVDS
,
321 CONNECTOR_OBJECT_ID_9PIN_DIN
,
322 CONNECTOR_OBJECT_ID_9PIN_DIN
,
323 CONNECTOR_OBJECT_ID_DISPLAYPORT
,
324 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
,
325 CONNECTOR_OBJECT_ID_HDMI_TYPE_B
,
326 CONNECTOR_OBJECT_ID_SVIDEO
329 const int object_connector_convert
[] = {
330 DRM_MODE_CONNECTOR_Unknown
,
331 DRM_MODE_CONNECTOR_DVII
,
332 DRM_MODE_CONNECTOR_DVII
,
333 DRM_MODE_CONNECTOR_DVID
,
334 DRM_MODE_CONNECTOR_DVID
,
335 DRM_MODE_CONNECTOR_VGA
,
336 DRM_MODE_CONNECTOR_Composite
,
337 DRM_MODE_CONNECTOR_SVIDEO
,
338 DRM_MODE_CONNECTOR_Unknown
,
339 DRM_MODE_CONNECTOR_Unknown
,
340 DRM_MODE_CONNECTOR_9PinDIN
,
341 DRM_MODE_CONNECTOR_Unknown
,
342 DRM_MODE_CONNECTOR_HDMIA
,
343 DRM_MODE_CONNECTOR_HDMIB
,
344 DRM_MODE_CONNECTOR_LVDS
,
345 DRM_MODE_CONNECTOR_9PinDIN
,
346 DRM_MODE_CONNECTOR_Unknown
,
347 DRM_MODE_CONNECTOR_Unknown
,
348 DRM_MODE_CONNECTOR_Unknown
,
349 DRM_MODE_CONNECTOR_DisplayPort
,
350 DRM_MODE_CONNECTOR_eDP
,
351 DRM_MODE_CONNECTOR_Unknown
354 bool radeon_get_atom_connector_info_from_object_table(struct drm_device
*dev
)
356 struct radeon_device
*rdev
= dev
->dev_private
;
357 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
358 struct atom_context
*ctx
= mode_info
->atom_context
;
359 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
360 u16 size
, data_offset
;
362 ATOM_CONNECTOR_OBJECT_TABLE
*con_obj
;
363 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
364 ATOM_OBJECT_HEADER
*obj_header
;
365 int i
, j
, path_size
, device_support
;
367 u16 igp_lane_info
, conn_id
, connector_object_id
;
369 struct radeon_i2c_bus_rec ddc_bus
;
370 struct radeon_gpio_rec gpio
;
371 struct radeon_hpd hpd
;
373 atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
);
375 if (data_offset
== 0)
381 obj_header
= (ATOM_OBJECT_HEADER
*) (ctx
->bios
+ data_offset
);
382 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
383 (ctx
->bios
+ data_offset
+
384 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
385 con_obj
= (ATOM_CONNECTOR_OBJECT_TABLE
*)
386 (ctx
->bios
+ data_offset
+
387 le16_to_cpu(obj_header
->usConnectorObjectTableOffset
));
388 device_support
= le16_to_cpu(obj_header
->usDeviceSupport
);
391 for (i
= 0; i
< path_obj
->ucNumOfDispPath
; i
++) {
392 uint8_t *addr
= (uint8_t *) path_obj
->asDispPath
;
393 ATOM_DISPLAY_OBJECT_PATH
*path
;
395 path
= (ATOM_DISPLAY_OBJECT_PATH
*) addr
;
396 path_size
+= le16_to_cpu(path
->usSize
);
398 if (device_support
& le16_to_cpu(path
->usDeviceTag
)) {
399 uint8_t con_obj_id
, con_obj_num
, con_obj_type
;
402 (le16_to_cpu(path
->usConnObjectId
) & OBJECT_ID_MASK
)
405 (le16_to_cpu(path
->usConnObjectId
) & ENUM_ID_MASK
)
408 (le16_to_cpu(path
->usConnObjectId
) &
409 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
411 /* TODO CV support */
412 if (le16_to_cpu(path
->usDeviceTag
) ==
413 ATOM_DEVICE_CV_SUPPORT
)
417 if ((rdev
->flags
& RADEON_IS_IGP
) &&
419 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR
)) {
420 uint16_t igp_offset
= 0;
421 ATOM_INTEGRATED_SYSTEM_INFO_V2
*igp_obj
;
424 GetIndexIntoMasterTable(DATA
,
425 IntegratedSystemInfo
);
427 atom_parse_data_header(ctx
, index
, &size
, &frev
,
432 (ATOM_INTEGRATED_SYSTEM_INFO_V2
433 *) (ctx
->bios
+ igp_offset
);
436 uint32_t slot_config
, ct
;
438 if (con_obj_num
== 1)
447 ct
= (slot_config
>> 16) & 0xff;
449 object_connector_convert
451 connector_object_id
= ct
;
453 slot_config
& 0xffff;
461 object_connector_convert
[con_obj_id
];
462 connector_object_id
= con_obj_id
;
465 if (connector_type
== DRM_MODE_CONNECTOR_Unknown
)
468 for (j
= 0; j
< ((le16_to_cpu(path
->usSize
) - 8) / 2);
470 uint8_t enc_obj_id
, enc_obj_num
, enc_obj_type
;
473 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
474 OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
476 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
477 ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
479 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
480 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
482 /* FIXME: add support for router objects */
483 if (enc_obj_type
== GRAPH_OBJECT_TYPE_ENCODER
) {
484 if (enc_obj_num
== 2)
489 radeon_add_atom_encoder(dev
,
498 /* look up gpio for ddc, hpd */
499 if ((le16_to_cpu(path
->usDeviceTag
) &
500 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) == 0) {
501 for (j
= 0; j
< con_obj
->ucNumberOfObjects
; j
++) {
502 if (le16_to_cpu(path
->usConnObjectId
) ==
503 le16_to_cpu(con_obj
->asObjects
[j
].
505 ATOM_COMMON_RECORD_HEADER
507 (ATOM_COMMON_RECORD_HEADER
509 (ctx
->bios
+ data_offset
+
510 le16_to_cpu(con_obj
->
513 ATOM_I2C_RECORD
*i2c_record
;
514 ATOM_HPD_INT_RECORD
*hpd_record
;
515 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
516 hpd
.hpd
= RADEON_HPD_NONE
;
518 while (record
->ucRecordType
> 0
521 ATOM_MAX_OBJECT_RECORD_NUMBER
) {
522 switch (record
->ucRecordType
) {
523 case ATOM_I2C_RECORD_TYPE
:
528 (ATOM_I2C_ID_CONFIG_ACCESS
*)
529 &i2c_record
->sucI2cId
;
530 ddc_bus
= radeon_lookup_i2c_gpio(rdev
,
534 case ATOM_HPD_INT_RECORD_TYPE
:
536 (ATOM_HPD_INT_RECORD
*)
538 gpio
= radeon_lookup_gpio(rdev
,
539 hpd_record
->ucHPDIntGPIOID
);
540 hpd
= radeon_atom_get_hpd_info_from_gpio(rdev
, &gpio
);
541 hpd
.plugged_state
= hpd_record
->ucPlugged_PinState
;
545 (ATOM_COMMON_RECORD_HEADER
555 hpd
.hpd
= RADEON_HPD_NONE
;
556 ddc_bus
.valid
= false;
559 conn_id
= le16_to_cpu(path
->usConnObjectId
);
561 if (!radeon_atom_apply_quirks
562 (dev
, le16_to_cpu(path
->usDeviceTag
), &connector_type
,
563 &ddc_bus
, &conn_id
, &hpd
))
566 radeon_add_atom_connector(dev
,
570 connector_type
, &ddc_bus
,
571 linkb
, igp_lane_info
,
578 radeon_link_encoder_connector(dev
);
583 static uint16_t atombios_get_connector_object_id(struct drm_device
*dev
,
587 struct radeon_device
*rdev
= dev
->dev_private
;
589 if (rdev
->flags
& RADEON_IS_IGP
) {
590 return supported_devices_connector_object_id_convert
592 } else if (((connector_type
== DRM_MODE_CONNECTOR_DVII
) ||
593 (connector_type
== DRM_MODE_CONNECTOR_DVID
)) &&
594 (devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
595 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
596 struct atom_context
*ctx
= mode_info
->atom_context
;
597 int index
= GetIndexIntoMasterTable(DATA
, XTMDS_Info
);
598 uint16_t size
, data_offset
;
600 ATOM_XTMDS_INFO
*xtmds
;
602 atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
);
603 xtmds
= (ATOM_XTMDS_INFO
*)(ctx
->bios
+ data_offset
);
605 if (xtmds
->ucSupportedLink
& ATOM_XTMDS_SUPPORTED_DUALLINK
) {
606 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
607 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
609 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
611 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
612 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
614 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
617 return supported_devices_connector_object_id_convert
622 struct bios_connector
{
627 struct radeon_i2c_bus_rec ddc_bus
;
628 struct radeon_hpd hpd
;
631 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
635 struct radeon_device
*rdev
= dev
->dev_private
;
636 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
637 struct atom_context
*ctx
= mode_info
->atom_context
;
638 int index
= GetIndexIntoMasterTable(DATA
, SupportedDevicesInfo
);
639 uint16_t size
, data_offset
;
641 uint16_t device_support
;
643 union atom_supported_devices
*supported_devices
;
644 int i
, j
, max_device
;
645 struct bios_connector bios_connectors
[ATOM_MAX_SUPPORTED_DEVICE
];
647 atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
);
650 (union atom_supported_devices
*)(ctx
->bios
+ data_offset
);
652 device_support
= le16_to_cpu(supported_devices
->info
.usDeviceSupport
);
655 max_device
= ATOM_MAX_SUPPORTED_DEVICE
;
657 max_device
= ATOM_MAX_SUPPORTED_DEVICE_INFO
;
659 for (i
= 0; i
< max_device
; i
++) {
660 ATOM_CONNECTOR_INFO_I2C ci
=
661 supported_devices
->info
.asConnInfo
[i
];
663 bios_connectors
[i
].valid
= false;
665 if (!(device_support
& (1 << i
))) {
669 if (i
== ATOM_DEVICE_CV_INDEX
) {
670 DRM_DEBUG("Skipping Component Video\n");
674 bios_connectors
[i
].connector_type
=
675 supported_devices_connector_convert
[ci
.sucConnectorInfo
.
679 if (bios_connectors
[i
].connector_type
==
680 DRM_MODE_CONNECTOR_Unknown
)
683 dac
= ci
.sucConnectorInfo
.sbfAccess
.bfAssociatedDAC
;
685 bios_connectors
[i
].line_mux
=
686 ci
.sucI2cId
.ucAccess
;
688 /* give tv unique connector ids */
689 if (i
== ATOM_DEVICE_TV1_INDEX
) {
690 bios_connectors
[i
].ddc_bus
.valid
= false;
691 bios_connectors
[i
].line_mux
= 50;
692 } else if (i
== ATOM_DEVICE_TV2_INDEX
) {
693 bios_connectors
[i
].ddc_bus
.valid
= false;
694 bios_connectors
[i
].line_mux
= 51;
695 } else if (i
== ATOM_DEVICE_CV_INDEX
) {
696 bios_connectors
[i
].ddc_bus
.valid
= false;
697 bios_connectors
[i
].line_mux
= 52;
699 bios_connectors
[i
].ddc_bus
=
700 radeon_lookup_i2c_gpio(rdev
,
701 bios_connectors
[i
].line_mux
);
703 if ((crev
> 1) && (frev
> 1)) {
704 u8 isb
= supported_devices
->info_2d1
.asIntSrcInfo
[i
].ucIntSrcBitmap
;
707 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
710 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
713 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
717 if (i
== ATOM_DEVICE_DFP1_INDEX
)
718 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
719 else if (i
== ATOM_DEVICE_DFP2_INDEX
)
720 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
722 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
725 /* Always set the connector type to VGA for CRT1/CRT2. if they are
726 * shared with a DVI port, we'll pick up the DVI connector when we
727 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
729 if (i
== ATOM_DEVICE_CRT1_INDEX
|| i
== ATOM_DEVICE_CRT2_INDEX
)
730 bios_connectors
[i
].connector_type
=
731 DRM_MODE_CONNECTOR_VGA
;
733 if (!radeon_atom_apply_quirks
734 (dev
, (1 << i
), &bios_connectors
[i
].connector_type
,
735 &bios_connectors
[i
].ddc_bus
, &bios_connectors
[i
].line_mux
,
736 &bios_connectors
[i
].hpd
))
739 bios_connectors
[i
].valid
= true;
740 bios_connectors
[i
].devices
= (1 << i
);
742 if (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
)
743 radeon_add_atom_encoder(dev
,
744 radeon_get_encoder_id(dev
,
749 radeon_add_legacy_encoder(dev
,
750 radeon_get_encoder_id(dev
,
756 /* combine shared connectors */
757 for (i
= 0; i
< max_device
; i
++) {
758 if (bios_connectors
[i
].valid
) {
759 for (j
= 0; j
< max_device
; j
++) {
760 if (bios_connectors
[j
].valid
&& (i
!= j
)) {
761 if (bios_connectors
[i
].line_mux
==
762 bios_connectors
[j
].line_mux
) {
763 /* make sure not to combine LVDS */
764 if (bios_connectors
[i
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
765 bios_connectors
[i
].line_mux
= 53;
766 bios_connectors
[i
].ddc_bus
.valid
= false;
769 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
770 bios_connectors
[j
].line_mux
= 53;
771 bios_connectors
[j
].ddc_bus
.valid
= false;
774 /* combine analog and digital for DVI-I */
775 if (((bios_connectors
[i
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
776 (bios_connectors
[j
].devices
& (ATOM_DEVICE_CRT_SUPPORT
))) ||
777 ((bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
778 (bios_connectors
[i
].devices
& (ATOM_DEVICE_CRT_SUPPORT
)))) {
779 bios_connectors
[i
].devices
|=
780 bios_connectors
[j
].devices
;
781 bios_connectors
[i
].connector_type
=
782 DRM_MODE_CONNECTOR_DVII
;
783 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
))
784 bios_connectors
[i
].hpd
=
785 bios_connectors
[j
].hpd
;
786 bios_connectors
[j
].valid
= false;
794 /* add the connectors */
795 for (i
= 0; i
< max_device
; i
++) {
796 if (bios_connectors
[i
].valid
) {
797 uint16_t connector_object_id
=
798 atombios_get_connector_object_id(dev
,
799 bios_connectors
[i
].connector_type
,
800 bios_connectors
[i
].devices
);
801 radeon_add_atom_connector(dev
,
802 bios_connectors
[i
].line_mux
,
803 bios_connectors
[i
].devices
,
806 &bios_connectors
[i
].ddc_bus
,
809 &bios_connectors
[i
].hpd
);
813 radeon_link_encoder_connector(dev
);
818 union firmware_info
{
819 ATOM_FIRMWARE_INFO info
;
820 ATOM_FIRMWARE_INFO_V1_2 info_12
;
821 ATOM_FIRMWARE_INFO_V1_3 info_13
;
822 ATOM_FIRMWARE_INFO_V1_4 info_14
;
825 bool radeon_atom_get_clock_info(struct drm_device
*dev
)
827 struct radeon_device
*rdev
= dev
->dev_private
;
828 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
829 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
830 union firmware_info
*firmware_info
;
832 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
833 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
834 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
835 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
836 uint16_t data_offset
;
838 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
839 &crev
, &data_offset
);
842 (union firmware_info
*)(mode_info
->atom_context
->bios
+
847 p1pll
->reference_freq
=
848 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
849 p1pll
->reference_div
= 0;
853 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Output
);
856 le32_to_cpu(firmware_info
->info_12
.ulMinPixelClockPLL_Output
);
858 le32_to_cpu(firmware_info
->info
.ulMaxPixelClockPLL_Output
);
860 if (p1pll
->pll_out_min
== 0) {
861 if (ASIC_IS_AVIVO(rdev
))
862 p1pll
->pll_out_min
= 64800;
864 p1pll
->pll_out_min
= 20000;
865 } else if (p1pll
->pll_out_min
> 64800) {
866 /* Limiting the pll output range is a good thing generally as
867 * it limits the number of possible pll combinations for a given
868 * frequency presumably to the ones that work best on each card.
869 * However, certain duallink DVI monitors seem to like
870 * pll combinations that would be limited by this at least on
871 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
875 p1pll
->pll_out_min
= 64800;
879 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Input
);
881 le16_to_cpu(firmware_info
->info
.usMaxPixelClockPLL_Input
);
886 spll
->reference_freq
=
887 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
888 spll
->reference_div
= 0;
891 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Output
);
893 le32_to_cpu(firmware_info
->info
.ulMaxEngineClockPLL_Output
);
896 if (spll
->pll_out_min
== 0) {
897 if (ASIC_IS_AVIVO(rdev
))
898 spll
->pll_out_min
= 64800;
900 spll
->pll_out_min
= 20000;
904 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Input
);
906 le16_to_cpu(firmware_info
->info
.usMaxEngineClockPLL_Input
);
909 mpll
->reference_freq
=
910 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
911 mpll
->reference_div
= 0;
914 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Output
);
916 le32_to_cpu(firmware_info
->info
.ulMaxMemoryClockPLL_Output
);
919 if (mpll
->pll_out_min
== 0) {
920 if (ASIC_IS_AVIVO(rdev
))
921 mpll
->pll_out_min
= 64800;
923 mpll
->pll_out_min
= 20000;
927 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Input
);
929 le16_to_cpu(firmware_info
->info
.usMaxMemoryClockPLL_Input
);
931 rdev
->clock
.default_sclk
=
932 le32_to_cpu(firmware_info
->info
.ulDefaultEngineClock
);
933 rdev
->clock
.default_mclk
=
934 le32_to_cpu(firmware_info
->info
.ulDefaultMemoryClock
);
942 struct _ATOM_INTEGRATED_SYSTEM_INFO info
;
943 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2
;
946 bool radeon_atombios_sideport_present(struct radeon_device
*rdev
)
948 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
949 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
950 union igp_info
*igp_info
;
954 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
955 &crev
, &data_offset
);
957 igp_info
= (union igp_info
*)(mode_info
->atom_context
->bios
+
963 if (igp_info
->info
.ucMemoryType
& 0xf0)
967 if (igp_info
->info_2
.ucMemoryType
& 0x0f)
971 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
978 bool radeon_atombios_get_tmds_info(struct radeon_encoder
*encoder
,
979 struct radeon_encoder_int_tmds
*tmds
)
981 struct drm_device
*dev
= encoder
->base
.dev
;
982 struct radeon_device
*rdev
= dev
->dev_private
;
983 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
984 int index
= GetIndexIntoMasterTable(DATA
, TMDS_Info
);
985 uint16_t data_offset
;
986 struct _ATOM_TMDS_INFO
*tmds_info
;
991 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
992 &crev
, &data_offset
);
995 (struct _ATOM_TMDS_INFO
*)(mode_info
->atom_context
->bios
+
999 maxfreq
= le16_to_cpu(tmds_info
->usMaxFrequency
);
1000 for (i
= 0; i
< 4; i
++) {
1001 tmds
->tmds_pll
[i
].freq
=
1002 le16_to_cpu(tmds_info
->asMiscInfo
[i
].usFrequency
);
1003 tmds
->tmds_pll
[i
].value
=
1004 tmds_info
->asMiscInfo
[i
].ucPLL_ChargePump
& 0x3f;
1005 tmds
->tmds_pll
[i
].value
|=
1006 (tmds_info
->asMiscInfo
[i
].
1007 ucPLL_VCO_Gain
& 0x3f) << 6;
1008 tmds
->tmds_pll
[i
].value
|=
1009 (tmds_info
->asMiscInfo
[i
].
1010 ucPLL_DutyCycle
& 0xf) << 12;
1011 tmds
->tmds_pll
[i
].value
|=
1012 (tmds_info
->asMiscInfo
[i
].
1013 ucPLL_VoltageSwing
& 0xf) << 16;
1015 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1016 tmds
->tmds_pll
[i
].freq
,
1017 tmds
->tmds_pll
[i
].value
);
1019 if (maxfreq
== tmds
->tmds_pll
[i
].freq
) {
1020 tmds
->tmds_pll
[i
].freq
= 0xffffffff;
1029 static struct radeon_atom_ss
*radeon_atombios_get_ss_info(struct
1034 struct drm_device
*dev
= encoder
->base
.dev
;
1035 struct radeon_device
*rdev
= dev
->dev_private
;
1036 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1037 int index
= GetIndexIntoMasterTable(DATA
, PPLL_SS_Info
);
1038 uint16_t data_offset
;
1039 struct _ATOM_SPREAD_SPECTRUM_INFO
*ss_info
;
1041 struct radeon_atom_ss
*ss
= NULL
;
1044 if (id
> ATOM_MAX_SS_ENTRY
)
1047 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
1048 &crev
, &data_offset
);
1051 (struct _ATOM_SPREAD_SPECTRUM_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1055 kzalloc(sizeof(struct radeon_atom_ss
), GFP_KERNEL
);
1060 for (i
= 0; i
< ATOM_MAX_SS_ENTRY
; i
++) {
1061 if (ss_info
->asSS_Info
[i
].ucSS_Id
== id
) {
1063 le16_to_cpu(ss_info
->asSS_Info
[i
].usSpreadSpectrumPercentage
);
1064 ss
->type
= ss_info
->asSS_Info
[i
].ucSpreadSpectrumType
;
1065 ss
->step
= ss_info
->asSS_Info
[i
].ucSS_Step
;
1066 ss
->delay
= ss_info
->asSS_Info
[i
].ucSS_Delay
;
1067 ss
->range
= ss_info
->asSS_Info
[i
].ucSS_Range
;
1068 ss
->refdiv
= ss_info
->asSS_Info
[i
].ucRecommendedRef_Div
;
1076 static void radeon_atom_apply_lvds_quirks(struct drm_device
*dev
,
1077 struct radeon_encoder_atom_dig
*lvds
)
1080 /* Toshiba A300-1BU laptop panel doesn't like new pll divider algo */
1081 if ((dev
->pdev
->device
== 0x95c4) &&
1082 (dev
->pdev
->subsystem_vendor
== 0x1179) &&
1083 (dev
->pdev
->subsystem_device
== 0xff50)) {
1084 if ((lvds
->native_mode
.hdisplay
== 1280) &&
1085 (lvds
->native_mode
.vdisplay
== 800))
1086 lvds
->pll_algo
= PLL_ALGO_LEGACY
;
1092 struct _ATOM_LVDS_INFO info
;
1093 struct _ATOM_LVDS_INFO_V12 info_12
;
1096 struct radeon_encoder_atom_dig
*radeon_atombios_get_lvds_info(struct
1100 struct drm_device
*dev
= encoder
->base
.dev
;
1101 struct radeon_device
*rdev
= dev
->dev_private
;
1102 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1103 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
1104 uint16_t data_offset
, misc
;
1105 union lvds_info
*lvds_info
;
1107 struct radeon_encoder_atom_dig
*lvds
= NULL
;
1109 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
1110 &crev
, &data_offset
);
1113 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1117 kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
1122 lvds
->native_mode
.clock
=
1123 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
1124 lvds
->native_mode
.hdisplay
=
1125 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
1126 lvds
->native_mode
.vdisplay
=
1127 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
1128 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
1129 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
1130 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
1131 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
1132 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
1133 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
1134 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
1135 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
1136 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
1137 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
1138 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
1139 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
1140 lvds
->panel_pwr_delay
=
1141 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
1142 lvds
->lvds_misc
= lvds_info
->info
.ucLVDS_Misc
;
1144 misc
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.susModeMiscInfo
.usAccess
);
1145 if (misc
& ATOM_VSYNC_POLARITY
)
1146 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
1147 if (misc
& ATOM_HSYNC_POLARITY
)
1148 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
1149 if (misc
& ATOM_COMPOSITESYNC
)
1150 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_CSYNC
;
1151 if (misc
& ATOM_INTERLACE
)
1152 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
1153 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1154 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_DBLSCAN
;
1156 /* set crtc values */
1157 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1159 lvds
->ss
= radeon_atombios_get_ss_info(encoder
, lvds_info
->info
.ucSS_Id
);
1161 if (ASIC_IS_AVIVO(rdev
)) {
1163 lvds
->pll_algo
= PLL_ALGO_AVIVO
;
1165 lvds
->pll_algo
= PLL_ALGO_LEGACY
;
1167 lvds
->pll_algo
= PLL_ALGO_LEGACY
;
1170 radeon_atom_apply_lvds_quirks(dev
, lvds
);
1172 encoder
->native_mode
= lvds
->native_mode
;
1177 struct radeon_encoder_primary_dac
*
1178 radeon_atombios_get_primary_dac_info(struct radeon_encoder
*encoder
)
1180 struct drm_device
*dev
= encoder
->base
.dev
;
1181 struct radeon_device
*rdev
= dev
->dev_private
;
1182 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1183 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1184 uint16_t data_offset
;
1185 struct _COMPASSIONATE_DATA
*dac_info
;
1188 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
1190 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
, &crev
, &data_offset
);
1192 dac_info
= (struct _COMPASSIONATE_DATA
*)(mode_info
->atom_context
->bios
+ data_offset
);
1195 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
), GFP_KERNEL
);
1200 bg
= dac_info
->ucDAC1_BG_Adjustment
;
1201 dac
= dac_info
->ucDAC1_DAC_Adjustment
;
1202 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
1208 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
1209 struct drm_display_mode
*mode
)
1211 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1212 ATOM_ANALOG_TV_INFO
*tv_info
;
1213 ATOM_ANALOG_TV_INFO_V1_2
*tv_info_v1_2
;
1214 ATOM_DTD_FORMAT
*dtd_timings
;
1215 int data_index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1217 u16 data_offset
, misc
;
1219 atom_parse_data_header(mode_info
->atom_context
, data_index
, NULL
, &frev
, &crev
, &data_offset
);
1223 tv_info
= (ATOM_ANALOG_TV_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1224 if (index
> MAX_SUPPORTED_TV_TIMING
)
1227 mode
->crtc_htotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Total
);
1228 mode
->crtc_hdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Disp
);
1229 mode
->crtc_hsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
);
1230 mode
->crtc_hsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
) +
1231 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncWidth
);
1233 mode
->crtc_vtotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Total
);
1234 mode
->crtc_vdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Disp
);
1235 mode
->crtc_vsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
);
1236 mode
->crtc_vsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
) +
1237 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncWidth
);
1240 misc
= le16_to_cpu(tv_info
->aModeTimings
[index
].susModeMiscInfo
.usAccess
);
1241 if (misc
& ATOM_VSYNC_POLARITY
)
1242 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1243 if (misc
& ATOM_HSYNC_POLARITY
)
1244 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1245 if (misc
& ATOM_COMPOSITESYNC
)
1246 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1247 if (misc
& ATOM_INTERLACE
)
1248 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1249 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1250 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1252 mode
->clock
= le16_to_cpu(tv_info
->aModeTimings
[index
].usPixelClock
) * 10;
1255 /* PAL timings appear to have wrong values for totals */
1256 mode
->crtc_htotal
-= 1;
1257 mode
->crtc_vtotal
-= 1;
1261 tv_info_v1_2
= (ATOM_ANALOG_TV_INFO_V1_2
*)(mode_info
->atom_context
->bios
+ data_offset
);
1262 if (index
> MAX_SUPPORTED_TV_TIMING_V1_2
)
1265 dtd_timings
= &tv_info_v1_2
->aModeTimings
[index
];
1266 mode
->crtc_htotal
= le16_to_cpu(dtd_timings
->usHActive
) +
1267 le16_to_cpu(dtd_timings
->usHBlanking_Time
);
1268 mode
->crtc_hdisplay
= le16_to_cpu(dtd_timings
->usHActive
);
1269 mode
->crtc_hsync_start
= le16_to_cpu(dtd_timings
->usHActive
) +
1270 le16_to_cpu(dtd_timings
->usHSyncOffset
);
1271 mode
->crtc_hsync_end
= mode
->crtc_hsync_start
+
1272 le16_to_cpu(dtd_timings
->usHSyncWidth
);
1274 mode
->crtc_vtotal
= le16_to_cpu(dtd_timings
->usVActive
) +
1275 le16_to_cpu(dtd_timings
->usVBlanking_Time
);
1276 mode
->crtc_vdisplay
= le16_to_cpu(dtd_timings
->usVActive
);
1277 mode
->crtc_vsync_start
= le16_to_cpu(dtd_timings
->usVActive
) +
1278 le16_to_cpu(dtd_timings
->usVSyncOffset
);
1279 mode
->crtc_vsync_end
= mode
->crtc_vsync_start
+
1280 le16_to_cpu(dtd_timings
->usVSyncWidth
);
1283 misc
= le16_to_cpu(dtd_timings
->susModeMiscInfo
.usAccess
);
1284 if (misc
& ATOM_VSYNC_POLARITY
)
1285 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1286 if (misc
& ATOM_HSYNC_POLARITY
)
1287 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1288 if (misc
& ATOM_COMPOSITESYNC
)
1289 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1290 if (misc
& ATOM_INTERLACE
)
1291 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1292 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1293 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1295 mode
->clock
= le16_to_cpu(dtd_timings
->usPixClk
) * 10;
1302 radeon_atombios_get_tv_info(struct radeon_device
*rdev
)
1304 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1305 int index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1306 uint16_t data_offset
;
1308 struct _ATOM_ANALOG_TV_INFO
*tv_info
;
1309 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
1311 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
, &crev
, &data_offset
);
1313 tv_info
= (struct _ATOM_ANALOG_TV_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1315 switch (tv_info
->ucTV_BootUpDefaultStandard
) {
1317 tv_std
= TV_STD_NTSC
;
1318 DRM_INFO("Default TV standard: NTSC\n");
1321 tv_std
= TV_STD_NTSC_J
;
1322 DRM_INFO("Default TV standard: NTSC-J\n");
1325 tv_std
= TV_STD_PAL
;
1326 DRM_INFO("Default TV standard: PAL\n");
1329 tv_std
= TV_STD_PAL_M
;
1330 DRM_INFO("Default TV standard: PAL-M\n");
1333 tv_std
= TV_STD_PAL_N
;
1334 DRM_INFO("Default TV standard: PAL-N\n");
1337 tv_std
= TV_STD_PAL_CN
;
1338 DRM_INFO("Default TV standard: PAL-CN\n");
1341 tv_std
= TV_STD_PAL_60
;
1342 DRM_INFO("Default TV standard: PAL-60\n");
1345 tv_std
= TV_STD_SECAM
;
1346 DRM_INFO("Default TV standard: SECAM\n");
1349 tv_std
= TV_STD_NTSC
;
1350 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1356 struct radeon_encoder_tv_dac
*
1357 radeon_atombios_get_tv_dac_info(struct radeon_encoder
*encoder
)
1359 struct drm_device
*dev
= encoder
->base
.dev
;
1360 struct radeon_device
*rdev
= dev
->dev_private
;
1361 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1362 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1363 uint16_t data_offset
;
1364 struct _COMPASSIONATE_DATA
*dac_info
;
1367 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1369 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
, &crev
, &data_offset
);
1371 dac_info
= (struct _COMPASSIONATE_DATA
*)(mode_info
->atom_context
->bios
+ data_offset
);
1374 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1379 bg
= dac_info
->ucDAC2_CRT2_BG_Adjustment
;
1380 dac
= dac_info
->ucDAC2_CRT2_DAC_Adjustment
;
1381 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1383 bg
= dac_info
->ucDAC2_PAL_BG_Adjustment
;
1384 dac
= dac_info
->ucDAC2_PAL_DAC_Adjustment
;
1385 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1387 bg
= dac_info
->ucDAC2_NTSC_BG_Adjustment
;
1388 dac
= dac_info
->ucDAC2_NTSC_DAC_Adjustment
;
1389 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1391 tv_dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
1397 struct _ATOM_POWERPLAY_INFO info
;
1398 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
1399 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
1400 struct _ATOM_PPLIB_POWERPLAYTABLE info_4
;
1403 void radeon_atombios_get_power_modes(struct radeon_device
*rdev
)
1405 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1406 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
1409 u32 misc
, misc2
= 0, sclk
, mclk
;
1410 union power_info
*power_info
;
1411 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
1412 struct _ATOM_PPLIB_STATE
*power_state
;
1413 int num_modes
= 0, i
, j
;
1414 int state_index
= 0, mode_index
= 0;
1416 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
, &crev
, &data_offset
);
1418 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1420 rdev
->pm
.default_power_state
= NULL
;
1421 rdev
->pm
.current_power_state
= NULL
;
1425 num_modes
= power_info
->info
.ucNumOfPowerModeEntries
;
1426 if (num_modes
> ATOM_MAX_NUMBEROF_POWER_BLOCK
)
1427 num_modes
= ATOM_MAX_NUMBEROF_POWER_BLOCK
;
1428 for (i
= 0; i
< num_modes
; i
++) {
1429 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
1432 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1433 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
1434 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usMemoryClock
);
1435 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
1436 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usEngineClock
);
1437 /* skip invalid modes */
1438 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
1439 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
1441 /* skip overclock modes for now */
1442 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
>
1443 rdev
->clock
.default_mclk
) ||
1444 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
>
1445 rdev
->clock
.default_sclk
))
1447 rdev
->pm
.power_state
[state_index
].non_clock_info
.pcie_lanes
=
1448 power_info
->info
.asPowerPlayInfo
[i
].ucNumPciELanes
;
1449 misc
= le32_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].ulMiscInfo
);
1450 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) {
1451 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1453 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
1454 radeon_lookup_gpio(rdev
,
1455 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
1456 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
1457 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1460 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1462 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
1463 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1465 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
1466 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
1468 /* order matters! */
1469 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
1470 rdev
->pm
.power_state
[state_index
].type
=
1471 POWER_STATE_TYPE_POWERSAVE
;
1472 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
1473 rdev
->pm
.power_state
[state_index
].type
=
1474 POWER_STATE_TYPE_BATTERY
;
1475 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
1476 rdev
->pm
.power_state
[state_index
].type
=
1477 POWER_STATE_TYPE_BATTERY
;
1478 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
1479 rdev
->pm
.power_state
[state_index
].type
=
1480 POWER_STATE_TYPE_BALANCED
;
1481 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
)
1482 rdev
->pm
.power_state
[state_index
].type
=
1483 POWER_STATE_TYPE_PERFORMANCE
;
1484 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
1485 rdev
->pm
.power_state
[state_index
].type
=
1486 POWER_STATE_TYPE_DEFAULT
;
1487 rdev
->pm
.default_power_state
= &rdev
->pm
.power_state
[state_index
];
1488 rdev
->pm
.current_power_state
= &rdev
->pm
.power_state
[state_index
];
1489 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
1490 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1491 rdev
->pm
.power_state
[state_index
].current_clock_mode
=
1492 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1497 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1498 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
1499 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMemoryClock
);
1500 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
1501 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulEngineClock
);
1502 /* skip invalid modes */
1503 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
1504 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
1506 /* skip overclock modes for now */
1507 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
>
1508 rdev
->clock
.default_mclk
) ||
1509 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
>
1510 rdev
->clock
.default_sclk
))
1512 rdev
->pm
.power_state
[state_index
].non_clock_info
.pcie_lanes
=
1513 power_info
->info_2
.asPowerPlayInfo
[i
].ucNumPciELanes
;
1514 misc
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo
);
1515 misc2
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo2
);
1516 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) {
1517 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1519 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
1520 radeon_lookup_gpio(rdev
,
1521 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
1522 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
1523 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1526 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1528 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
1529 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1531 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
1532 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
1534 /* order matters! */
1535 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
1536 rdev
->pm
.power_state
[state_index
].type
=
1537 POWER_STATE_TYPE_POWERSAVE
;
1538 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
1539 rdev
->pm
.power_state
[state_index
].type
=
1540 POWER_STATE_TYPE_BATTERY
;
1541 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
1542 rdev
->pm
.power_state
[state_index
].type
=
1543 POWER_STATE_TYPE_BATTERY
;
1544 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
1545 rdev
->pm
.power_state
[state_index
].type
=
1546 POWER_STATE_TYPE_BALANCED
;
1547 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
)
1548 rdev
->pm
.power_state
[state_index
].type
=
1549 POWER_STATE_TYPE_PERFORMANCE
;
1550 if (misc2
& ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE
)
1551 rdev
->pm
.power_state
[state_index
].type
=
1552 POWER_STATE_TYPE_BALANCED
;
1553 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
1554 rdev
->pm
.power_state
[state_index
].type
=
1555 POWER_STATE_TYPE_DEFAULT
;
1556 rdev
->pm
.default_power_state
= &rdev
->pm
.power_state
[state_index
];
1557 rdev
->pm
.current_power_state
= &rdev
->pm
.power_state
[state_index
];
1558 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
1559 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1560 rdev
->pm
.power_state
[state_index
].current_clock_mode
=
1561 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1566 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1567 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
1568 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMemoryClock
);
1569 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
1570 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulEngineClock
);
1571 /* skip invalid modes */
1572 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
1573 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
1575 /* skip overclock modes for now */
1576 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
>
1577 rdev
->clock
.default_mclk
) ||
1578 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
>
1579 rdev
->clock
.default_sclk
))
1581 rdev
->pm
.power_state
[state_index
].non_clock_info
.pcie_lanes
=
1582 power_info
->info_3
.asPowerPlayInfo
[i
].ucNumPciELanes
;
1583 misc
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo
);
1584 misc2
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo2
);
1585 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) {
1586 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1588 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
1589 radeon_lookup_gpio(rdev
,
1590 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
1591 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
1592 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1595 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1597 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
1598 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1600 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
1601 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
1602 if (misc2
& ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN
) {
1603 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_enabled
=
1605 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_id
=
1606 power_info
->info_3
.asPowerPlayInfo
[i
].ucVDDCI_VoltageDropIndex
;
1609 /* order matters! */
1610 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
1611 rdev
->pm
.power_state
[state_index
].type
=
1612 POWER_STATE_TYPE_POWERSAVE
;
1613 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
1614 rdev
->pm
.power_state
[state_index
].type
=
1615 POWER_STATE_TYPE_BATTERY
;
1616 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
1617 rdev
->pm
.power_state
[state_index
].type
=
1618 POWER_STATE_TYPE_BATTERY
;
1619 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
1620 rdev
->pm
.power_state
[state_index
].type
=
1621 POWER_STATE_TYPE_BALANCED
;
1622 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
)
1623 rdev
->pm
.power_state
[state_index
].type
=
1624 POWER_STATE_TYPE_PERFORMANCE
;
1625 if (misc2
& ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE
)
1626 rdev
->pm
.power_state
[state_index
].type
=
1627 POWER_STATE_TYPE_BALANCED
;
1628 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
1629 rdev
->pm
.power_state
[state_index
].type
=
1630 POWER_STATE_TYPE_DEFAULT
;
1631 rdev
->pm
.default_power_state
= &rdev
->pm
.power_state
[state_index
];
1632 rdev
->pm
.current_power_state
= &rdev
->pm
.power_state
[state_index
];
1633 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
1634 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1635 rdev
->pm
.power_state
[state_index
].current_clock_mode
=
1636 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1642 } else if (frev
== 4) {
1643 for (i
= 0; i
< power_info
->info_4
.ucNumStates
; i
++) {
1645 power_state
= (struct _ATOM_PPLIB_STATE
*)
1646 (mode_info
->atom_context
->bios
+
1648 le16_to_cpu(power_info
->info_4
.usStateArrayOffset
) +
1649 i
* power_info
->info_4
.ucStateEntrySize
);
1650 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
1651 (mode_info
->atom_context
->bios
+
1653 le16_to_cpu(power_info
->info_4
.usNonClockInfoArrayOffset
) +
1654 (power_state
->ucNonClockStateIndex
*
1655 power_info
->info_4
.ucNonClockSize
));
1656 for (j
= 0; j
< (power_info
->info_4
.ucStateEntrySize
- 1); j
++) {
1657 if (rdev
->flags
& RADEON_IS_IGP
) {
1658 struct _ATOM_PPLIB_RS780_CLOCK_INFO
*clock_info
=
1659 (struct _ATOM_PPLIB_RS780_CLOCK_INFO
*)
1660 (mode_info
->atom_context
->bios
+
1662 le16_to_cpu(power_info
->info_4
.usClockInfoArrayOffset
) +
1663 (power_state
->ucClockStateIndices
[j
] *
1664 power_info
->info_4
.ucClockInfoSize
));
1665 sclk
= le16_to_cpu(clock_info
->usLowEngineClockLow
);
1666 sclk
|= clock_info
->ucLowEngineClockHigh
<< 16;
1667 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
1668 /* skip invalid modes */
1669 if (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0)
1671 /* skip overclock modes for now */
1672 if (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
>
1673 rdev
->clock
.default_sclk
)
1675 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
1677 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
1681 struct _ATOM_PPLIB_R600_CLOCK_INFO
*clock_info
=
1682 (struct _ATOM_PPLIB_R600_CLOCK_INFO
*)
1683 (mode_info
->atom_context
->bios
+
1685 le16_to_cpu(power_info
->info_4
.usClockInfoArrayOffset
) +
1686 (power_state
->ucClockStateIndices
[j
] *
1687 power_info
->info_4
.ucClockInfoSize
));
1688 sclk
= le16_to_cpu(clock_info
->usEngineClockLow
);
1689 sclk
|= clock_info
->ucEngineClockHigh
<< 16;
1690 mclk
= le16_to_cpu(clock_info
->usMemoryClockLow
);
1691 mclk
|= clock_info
->ucMemoryClockHigh
<< 16;
1692 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
1693 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
1694 /* skip invalid modes */
1695 if ((rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
== 0) ||
1696 (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0))
1698 /* skip overclock modes for now */
1699 if ((rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
>
1700 rdev
->clock
.default_mclk
) ||
1701 (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
>
1702 rdev
->clock
.default_sclk
))
1704 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
1706 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
1711 rdev
->pm
.power_state
[state_index
].num_clock_modes
= mode_index
;
1713 misc
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
1714 misc2
= le16_to_cpu(non_clock_info
->usClassification
);
1715 rdev
->pm
.power_state
[state_index
].non_clock_info
.pcie_lanes
=
1716 ((misc
& ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
) >>
1717 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
) + 1;
1718 switch (misc2
& ATOM_PPLIB_CLASSIFICATION_UI_MASK
) {
1719 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
:
1720 rdev
->pm
.power_state
[state_index
].type
=
1721 POWER_STATE_TYPE_BATTERY
;
1723 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
:
1724 rdev
->pm
.power_state
[state_index
].type
=
1725 POWER_STATE_TYPE_BALANCED
;
1727 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
:
1728 rdev
->pm
.power_state
[state_index
].type
=
1729 POWER_STATE_TYPE_PERFORMANCE
;
1732 if (misc2
& ATOM_PPLIB_CLASSIFICATION_BOOT
) {
1733 rdev
->pm
.power_state
[state_index
].type
=
1734 POWER_STATE_TYPE_DEFAULT
;
1735 rdev
->pm
.default_power_state
= &rdev
->pm
.power_state
[state_index
];
1736 rdev
->pm
.current_power_state
= &rdev
->pm
.power_state
[state_index
];
1737 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
1738 &rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
- 1];
1739 rdev
->pm
.power_state
[state_index
].current_clock_mode
=
1740 &rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
- 1];
1747 /* XXX figure out some good default low power mode for cards w/out power tables */
1750 if (rdev
->pm
.default_power_state
== NULL
) {
1751 /* add the default mode */
1752 rdev
->pm
.power_state
[state_index
].type
=
1753 POWER_STATE_TYPE_DEFAULT
;
1754 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1755 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= rdev
->clock
.default_mclk
;
1756 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= rdev
->clock
.default_sclk
;
1757 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
1758 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1759 rdev
->pm
.power_state
[state_index
].current_clock_mode
=
1760 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1761 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
1762 if (rdev
->asic
->get_pcie_lanes
)
1763 rdev
->pm
.power_state
[state_index
].non_clock_info
.pcie_lanes
= radeon_get_pcie_lanes(rdev
);
1765 rdev
->pm
.power_state
[state_index
].non_clock_info
.pcie_lanes
= 16;
1766 rdev
->pm
.default_power_state
= &rdev
->pm
.power_state
[state_index
];
1767 rdev
->pm
.current_power_state
= &rdev
->pm
.power_state
[state_index
];
1770 rdev
->pm
.num_power_states
= state_index
;
1773 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
)
1775 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args
;
1776 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicClockGating
);
1778 args
.ucEnable
= enable
;
1780 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1783 uint32_t radeon_atom_get_engine_clock(struct radeon_device
*rdev
)
1785 GET_ENGINE_CLOCK_PS_ALLOCATION args
;
1786 int index
= GetIndexIntoMasterTable(COMMAND
, GetEngineClock
);
1788 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1789 return args
.ulReturnEngineClock
;
1792 uint32_t radeon_atom_get_memory_clock(struct radeon_device
*rdev
)
1794 GET_MEMORY_CLOCK_PS_ALLOCATION args
;
1795 int index
= GetIndexIntoMasterTable(COMMAND
, GetMemoryClock
);
1797 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1798 return args
.ulReturnMemoryClock
;
1801 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
,
1804 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
1805 int index
= GetIndexIntoMasterTable(COMMAND
, SetEngineClock
);
1807 args
.ulTargetEngineClock
= eng_clock
; /* 10 khz */
1809 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1812 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
,
1815 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
1816 int index
= GetIndexIntoMasterTable(COMMAND
, SetMemoryClock
);
1818 if (rdev
->flags
& RADEON_IS_IGP
)
1821 args
.ulTargetMemoryClock
= mem_clock
; /* 10 khz */
1823 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1826 void radeon_atom_initialize_bios_scratch_regs(struct drm_device
*dev
)
1828 struct radeon_device
*rdev
= dev
->dev_private
;
1829 uint32_t bios_2_scratch
, bios_6_scratch
;
1831 if (rdev
->family
>= CHIP_R600
) {
1832 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
1833 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1835 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
1836 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1839 /* let the bios control the backlight */
1840 bios_2_scratch
&= ~ATOM_S2_VRI_BRIGHT_ENABLE
;
1842 /* tell the bios not to handle mode switching */
1843 bios_6_scratch
|= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
| ATOM_S6_ACC_MODE
);
1845 if (rdev
->family
>= CHIP_R600
) {
1846 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
1847 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1849 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
1850 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1855 void radeon_save_bios_scratch_regs(struct radeon_device
*rdev
)
1857 uint32_t scratch_reg
;
1860 if (rdev
->family
>= CHIP_R600
)
1861 scratch_reg
= R600_BIOS_0_SCRATCH
;
1863 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
1865 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
1866 rdev
->bios_scratch
[i
] = RREG32(scratch_reg
+ (i
* 4));
1869 void radeon_restore_bios_scratch_regs(struct radeon_device
*rdev
)
1871 uint32_t scratch_reg
;
1874 if (rdev
->family
>= CHIP_R600
)
1875 scratch_reg
= R600_BIOS_0_SCRATCH
;
1877 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
1879 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
1880 WREG32(scratch_reg
+ (i
* 4), rdev
->bios_scratch
[i
]);
1883 void radeon_atom_output_lock(struct drm_encoder
*encoder
, bool lock
)
1885 struct drm_device
*dev
= encoder
->dev
;
1886 struct radeon_device
*rdev
= dev
->dev_private
;
1887 uint32_t bios_6_scratch
;
1889 if (rdev
->family
>= CHIP_R600
)
1890 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1892 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1895 bios_6_scratch
|= ATOM_S6_CRITICAL_STATE
;
1897 bios_6_scratch
&= ~ATOM_S6_CRITICAL_STATE
;
1899 if (rdev
->family
>= CHIP_R600
)
1900 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1902 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1905 /* at some point we may want to break this out into individual functions */
1907 radeon_atombios_connected_scratch_regs(struct drm_connector
*connector
,
1908 struct drm_encoder
*encoder
,
1911 struct drm_device
*dev
= connector
->dev
;
1912 struct radeon_device
*rdev
= dev
->dev_private
;
1913 struct radeon_connector
*radeon_connector
=
1914 to_radeon_connector(connector
);
1915 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1916 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
1918 if (rdev
->family
>= CHIP_R600
) {
1919 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
1920 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
1921 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1923 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
1924 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
1925 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1928 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
1929 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
1931 DRM_DEBUG("TV1 connected\n");
1932 bios_3_scratch
|= ATOM_S3_TV1_ACTIVE
;
1933 bios_6_scratch
|= ATOM_S6_ACC_REQ_TV1
;
1935 DRM_DEBUG("TV1 disconnected\n");
1936 bios_0_scratch
&= ~ATOM_S0_TV1_MASK
;
1937 bios_3_scratch
&= ~ATOM_S3_TV1_ACTIVE
;
1938 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_TV1
;
1941 if ((radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) &&
1942 (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
)) {
1944 DRM_DEBUG("CV connected\n");
1945 bios_3_scratch
|= ATOM_S3_CV_ACTIVE
;
1946 bios_6_scratch
|= ATOM_S6_ACC_REQ_CV
;
1948 DRM_DEBUG("CV disconnected\n");
1949 bios_0_scratch
&= ~ATOM_S0_CV_MASK
;
1950 bios_3_scratch
&= ~ATOM_S3_CV_ACTIVE
;
1951 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CV
;
1954 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
1955 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
1957 DRM_DEBUG("LCD1 connected\n");
1958 bios_0_scratch
|= ATOM_S0_LCD1
;
1959 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
1960 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
1962 DRM_DEBUG("LCD1 disconnected\n");
1963 bios_0_scratch
&= ~ATOM_S0_LCD1
;
1964 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
1965 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
1968 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
1969 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
1971 DRM_DEBUG("CRT1 connected\n");
1972 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
1973 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
1974 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
1976 DRM_DEBUG("CRT1 disconnected\n");
1977 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
1978 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
1979 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
1982 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
1983 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
1985 DRM_DEBUG("CRT2 connected\n");
1986 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
1987 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
1988 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
1990 DRM_DEBUG("CRT2 disconnected\n");
1991 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
1992 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
1993 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
1996 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
1997 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
1999 DRM_DEBUG("DFP1 connected\n");
2000 bios_0_scratch
|= ATOM_S0_DFP1
;
2001 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
2002 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
2004 DRM_DEBUG("DFP1 disconnected\n");
2005 bios_0_scratch
&= ~ATOM_S0_DFP1
;
2006 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
2007 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
2010 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
2011 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
2013 DRM_DEBUG("DFP2 connected\n");
2014 bios_0_scratch
|= ATOM_S0_DFP2
;
2015 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
2016 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
2018 DRM_DEBUG("DFP2 disconnected\n");
2019 bios_0_scratch
&= ~ATOM_S0_DFP2
;
2020 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
2021 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
2024 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
2025 (radeon_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
2027 DRM_DEBUG("DFP3 connected\n");
2028 bios_0_scratch
|= ATOM_S0_DFP3
;
2029 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
2030 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
2032 DRM_DEBUG("DFP3 disconnected\n");
2033 bios_0_scratch
&= ~ATOM_S0_DFP3
;
2034 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
2035 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
2038 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
2039 (radeon_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
2041 DRM_DEBUG("DFP4 connected\n");
2042 bios_0_scratch
|= ATOM_S0_DFP4
;
2043 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
2044 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
2046 DRM_DEBUG("DFP4 disconnected\n");
2047 bios_0_scratch
&= ~ATOM_S0_DFP4
;
2048 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
2049 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
2052 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
2053 (radeon_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
2055 DRM_DEBUG("DFP5 connected\n");
2056 bios_0_scratch
|= ATOM_S0_DFP5
;
2057 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
2058 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
2060 DRM_DEBUG("DFP5 disconnected\n");
2061 bios_0_scratch
&= ~ATOM_S0_DFP5
;
2062 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
2063 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
2067 if (rdev
->family
>= CHIP_R600
) {
2068 WREG32(R600_BIOS_0_SCRATCH
, bios_0_scratch
);
2069 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
2070 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2072 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
2073 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
2074 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2079 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
2081 struct drm_device
*dev
= encoder
->dev
;
2082 struct radeon_device
*rdev
= dev
->dev_private
;
2083 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2084 uint32_t bios_3_scratch
;
2086 if (rdev
->family
>= CHIP_R600
)
2087 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
2089 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
2091 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2092 bios_3_scratch
&= ~ATOM_S3_TV1_CRTC_ACTIVE
;
2093 bios_3_scratch
|= (crtc
<< 18);
2095 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2096 bios_3_scratch
&= ~ATOM_S3_CV_CRTC_ACTIVE
;
2097 bios_3_scratch
|= (crtc
<< 24);
2099 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2100 bios_3_scratch
&= ~ATOM_S3_CRT1_CRTC_ACTIVE
;
2101 bios_3_scratch
|= (crtc
<< 16);
2103 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2104 bios_3_scratch
&= ~ATOM_S3_CRT2_CRTC_ACTIVE
;
2105 bios_3_scratch
|= (crtc
<< 20);
2107 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
2108 bios_3_scratch
&= ~ATOM_S3_LCD1_CRTC_ACTIVE
;
2109 bios_3_scratch
|= (crtc
<< 17);
2111 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
2112 bios_3_scratch
&= ~ATOM_S3_DFP1_CRTC_ACTIVE
;
2113 bios_3_scratch
|= (crtc
<< 19);
2115 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
2116 bios_3_scratch
&= ~ATOM_S3_DFP2_CRTC_ACTIVE
;
2117 bios_3_scratch
|= (crtc
<< 23);
2119 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
2120 bios_3_scratch
&= ~ATOM_S3_DFP3_CRTC_ACTIVE
;
2121 bios_3_scratch
|= (crtc
<< 25);
2124 if (rdev
->family
>= CHIP_R600
)
2125 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
2127 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
2131 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
2133 struct drm_device
*dev
= encoder
->dev
;
2134 struct radeon_device
*rdev
= dev
->dev_private
;
2135 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2136 uint32_t bios_2_scratch
;
2138 if (rdev
->family
>= CHIP_R600
)
2139 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
2141 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
2143 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2145 bios_2_scratch
&= ~ATOM_S2_TV1_DPMS_STATE
;
2147 bios_2_scratch
|= ATOM_S2_TV1_DPMS_STATE
;
2149 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2151 bios_2_scratch
&= ~ATOM_S2_CV_DPMS_STATE
;
2153 bios_2_scratch
|= ATOM_S2_CV_DPMS_STATE
;
2155 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2157 bios_2_scratch
&= ~ATOM_S2_CRT1_DPMS_STATE
;
2159 bios_2_scratch
|= ATOM_S2_CRT1_DPMS_STATE
;
2161 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2163 bios_2_scratch
&= ~ATOM_S2_CRT2_DPMS_STATE
;
2165 bios_2_scratch
|= ATOM_S2_CRT2_DPMS_STATE
;
2167 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
2169 bios_2_scratch
&= ~ATOM_S2_LCD1_DPMS_STATE
;
2171 bios_2_scratch
|= ATOM_S2_LCD1_DPMS_STATE
;
2173 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
2175 bios_2_scratch
&= ~ATOM_S2_DFP1_DPMS_STATE
;
2177 bios_2_scratch
|= ATOM_S2_DFP1_DPMS_STATE
;
2179 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
2181 bios_2_scratch
&= ~ATOM_S2_DFP2_DPMS_STATE
;
2183 bios_2_scratch
|= ATOM_S2_DFP2_DPMS_STATE
;
2185 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
2187 bios_2_scratch
&= ~ATOM_S2_DFP3_DPMS_STATE
;
2189 bios_2_scratch
|= ATOM_S2_DFP3_DPMS_STATE
;
2191 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) {
2193 bios_2_scratch
&= ~ATOM_S2_DFP4_DPMS_STATE
;
2195 bios_2_scratch
|= ATOM_S2_DFP4_DPMS_STATE
;
2197 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) {
2199 bios_2_scratch
&= ~ATOM_S2_DFP5_DPMS_STATE
;
2201 bios_2_scratch
|= ATOM_S2_DFP5_DPMS_STATE
;
2204 if (rdev
->family
>= CHIP_R600
)
2205 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
2207 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);