2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_id(struct drm_device
*dev
, uint32_t supported_device
,
37 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
39 radeon_add_atom_encoder(struct drm_device
*dev
, uint32_t encoder_id
,
40 uint32_t supported_device
);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device
*dev
,
45 uint32_t connector_id
,
46 uint32_t supported_device
,
48 struct radeon_i2c_bus_rec
*i2c_bus
,
49 bool linkb
, uint32_t igp_lane_info
);
51 /* from radeon_legacy_encoder.c */
53 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_id
,
54 uint32_t supported_device
);
56 union atom_supported_devices
{
57 struct _ATOM_SUPPORTED_DEVICES_INFO info
;
58 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2
;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1
;
62 static inline struct radeon_i2c_bus_rec
radeon_lookup_gpio(struct drm_device
65 struct radeon_device
*rdev
= dev
->dev_private
;
66 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
67 ATOM_GPIO_I2C_ASSIGMENT gpio
;
68 struct radeon_i2c_bus_rec i2c
;
69 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
70 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
73 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
76 atom_parse_data_header(ctx
, index
, NULL
, NULL
, NULL
, &data_offset
);
78 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
80 gpio
= i2c_info
->asGPIO_Info
[id
];
82 i2c
.mask_clk_reg
= le16_to_cpu(gpio
.usClkMaskRegisterIndex
) * 4;
83 i2c
.mask_data_reg
= le16_to_cpu(gpio
.usDataMaskRegisterIndex
) * 4;
84 i2c
.put_clk_reg
= le16_to_cpu(gpio
.usClkEnRegisterIndex
) * 4;
85 i2c
.put_data_reg
= le16_to_cpu(gpio
.usDataEnRegisterIndex
) * 4;
86 i2c
.get_clk_reg
= le16_to_cpu(gpio
.usClkY_RegisterIndex
) * 4;
87 i2c
.get_data_reg
= le16_to_cpu(gpio
.usDataY_RegisterIndex
) * 4;
88 i2c
.a_clk_reg
= le16_to_cpu(gpio
.usClkA_RegisterIndex
) * 4;
89 i2c
.a_data_reg
= le16_to_cpu(gpio
.usDataA_RegisterIndex
) * 4;
90 i2c
.mask_clk_mask
= (1 << gpio
.ucClkMaskShift
);
91 i2c
.mask_data_mask
= (1 << gpio
.ucDataMaskShift
);
92 i2c
.put_clk_mask
= (1 << gpio
.ucClkEnShift
);
93 i2c
.put_data_mask
= (1 << gpio
.ucDataEnShift
);
94 i2c
.get_clk_mask
= (1 << gpio
.ucClkY_Shift
);
95 i2c
.get_data_mask
= (1 << gpio
.ucDataY_Shift
);
96 i2c
.a_clk_mask
= (1 << gpio
.ucClkA_Shift
);
97 i2c
.a_data_mask
= (1 << gpio
.ucDataA_Shift
);
103 static bool radeon_atom_apply_quirks(struct drm_device
*dev
,
104 uint32_t supported_device
,
106 struct radeon_i2c_bus_rec
*i2c_bus
,
110 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
111 if ((dev
->pdev
->device
== 0x791e) &&
112 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
113 (dev
->pdev
->subsystem_device
== 0x826d)) {
114 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
115 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
116 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
119 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
120 if ((dev
->pdev
->device
== 0x7941) &&
121 (dev
->pdev
->subsystem_vendor
== 0x147b) &&
122 (dev
->pdev
->subsystem_device
== 0x2412)) {
123 if (*connector_type
== DRM_MODE_CONNECTOR_DVII
)
127 /* Falcon NW laptop lists vga ddc line for LVDS */
128 if ((dev
->pdev
->device
== 0x5653) &&
129 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
130 (dev
->pdev
->subsystem_device
== 0x0291)) {
131 if (*connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
132 i2c_bus
->valid
= false;
138 if ((dev
->pdev
->device
== 0x71C5) &&
139 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
140 (dev
->pdev
->subsystem_device
== 0x0080)) {
141 if ((supported_device
== ATOM_DEVICE_CRT1_SUPPORT
) ||
142 (supported_device
== ATOM_DEVICE_DFP2_SUPPORT
))
146 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
147 if ((dev
->pdev
->device
== 0x9598) &&
148 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
149 (dev
->pdev
->subsystem_device
== 0x01da)) {
150 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
151 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
155 /* ASUS HD 3450 board lists the DVI port as HDMI */
156 if ((dev
->pdev
->device
== 0x95C5) &&
157 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
158 (dev
->pdev
->subsystem_device
== 0x01e2)) {
159 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
160 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
164 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
165 * HDMI + VGA reporting as HDMI
167 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
168 if (supported_device
& (ATOM_DEVICE_CRT_SUPPORT
)) {
169 *connector_type
= DRM_MODE_CONNECTOR_VGA
;
177 const int supported_devices_connector_convert
[] = {
178 DRM_MODE_CONNECTOR_Unknown
,
179 DRM_MODE_CONNECTOR_VGA
,
180 DRM_MODE_CONNECTOR_DVII
,
181 DRM_MODE_CONNECTOR_DVID
,
182 DRM_MODE_CONNECTOR_DVIA
,
183 DRM_MODE_CONNECTOR_SVIDEO
,
184 DRM_MODE_CONNECTOR_Composite
,
185 DRM_MODE_CONNECTOR_LVDS
,
186 DRM_MODE_CONNECTOR_Unknown
,
187 DRM_MODE_CONNECTOR_Unknown
,
188 DRM_MODE_CONNECTOR_HDMIA
,
189 DRM_MODE_CONNECTOR_HDMIB
,
190 DRM_MODE_CONNECTOR_Unknown
,
191 DRM_MODE_CONNECTOR_Unknown
,
192 DRM_MODE_CONNECTOR_9PinDIN
,
193 DRM_MODE_CONNECTOR_DisplayPort
196 const int object_connector_convert
[] = {
197 DRM_MODE_CONNECTOR_Unknown
,
198 DRM_MODE_CONNECTOR_DVII
,
199 DRM_MODE_CONNECTOR_DVII
,
200 DRM_MODE_CONNECTOR_DVID
,
201 DRM_MODE_CONNECTOR_DVID
,
202 DRM_MODE_CONNECTOR_VGA
,
203 DRM_MODE_CONNECTOR_Composite
,
204 DRM_MODE_CONNECTOR_SVIDEO
,
205 DRM_MODE_CONNECTOR_Unknown
,
206 DRM_MODE_CONNECTOR_Unknown
,
207 DRM_MODE_CONNECTOR_9PinDIN
,
208 DRM_MODE_CONNECTOR_Unknown
,
209 DRM_MODE_CONNECTOR_HDMIA
,
210 DRM_MODE_CONNECTOR_HDMIB
,
211 DRM_MODE_CONNECTOR_LVDS
,
212 DRM_MODE_CONNECTOR_9PinDIN
,
213 DRM_MODE_CONNECTOR_Unknown
,
214 DRM_MODE_CONNECTOR_Unknown
,
215 DRM_MODE_CONNECTOR_Unknown
,
216 DRM_MODE_CONNECTOR_DisplayPort
219 bool radeon_get_atom_connector_info_from_object_table(struct drm_device
*dev
)
221 struct radeon_device
*rdev
= dev
->dev_private
;
222 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
223 struct atom_context
*ctx
= mode_info
->atom_context
;
224 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
225 uint16_t size
, data_offset
;
226 uint8_t frev
, crev
, line_mux
= 0;
227 ATOM_CONNECTOR_OBJECT_TABLE
*con_obj
;
228 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
229 ATOM_OBJECT_HEADER
*obj_header
;
230 int i
, j
, path_size
, device_support
;
232 uint16_t igp_lane_info
, conn_id
;
234 struct radeon_i2c_bus_rec ddc_bus
;
236 atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
);
238 if (data_offset
== 0)
244 obj_header
= (ATOM_OBJECT_HEADER
*) (ctx
->bios
+ data_offset
);
245 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
246 (ctx
->bios
+ data_offset
+
247 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
248 con_obj
= (ATOM_CONNECTOR_OBJECT_TABLE
*)
249 (ctx
->bios
+ data_offset
+
250 le16_to_cpu(obj_header
->usConnectorObjectTableOffset
));
251 device_support
= le16_to_cpu(obj_header
->usDeviceSupport
);
254 for (i
= 0; i
< path_obj
->ucNumOfDispPath
; i
++) {
255 uint8_t *addr
= (uint8_t *) path_obj
->asDispPath
;
256 ATOM_DISPLAY_OBJECT_PATH
*path
;
258 path
= (ATOM_DISPLAY_OBJECT_PATH
*) addr
;
259 path_size
+= le16_to_cpu(path
->usSize
);
262 if (device_support
& le16_to_cpu(path
->usDeviceTag
)) {
263 uint8_t con_obj_id
, con_obj_num
, con_obj_type
;
266 (le16_to_cpu(path
->usConnObjectId
) & OBJECT_ID_MASK
)
269 (le16_to_cpu(path
->usConnObjectId
) & ENUM_ID_MASK
)
272 (le16_to_cpu(path
->usConnObjectId
) &
273 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
275 /* TODO CV support */
276 if (le16_to_cpu(path
->usDeviceTag
) ==
277 ATOM_DEVICE_CV_SUPPORT
)
281 if ((rdev
->flags
& RADEON_IS_IGP
) &&
283 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR
)) {
284 uint16_t igp_offset
= 0;
285 ATOM_INTEGRATED_SYSTEM_INFO_V2
*igp_obj
;
288 GetIndexIntoMasterTable(DATA
,
289 IntegratedSystemInfo
);
291 atom_parse_data_header(ctx
, index
, &size
, &frev
,
296 (ATOM_INTEGRATED_SYSTEM_INFO_V2
297 *) (ctx
->bios
+ igp_offset
);
300 uint32_t slot_config
, ct
;
302 if (con_obj_num
== 1)
311 ct
= (slot_config
>> 16) & 0xff;
313 object_connector_convert
316 slot_config
& 0xffff;
324 object_connector_convert
[con_obj_id
];
327 if (connector_type
== DRM_MODE_CONNECTOR_Unknown
)
330 for (j
= 0; j
< ((le16_to_cpu(path
->usSize
) - 8) / 2);
332 uint8_t enc_obj_id
, enc_obj_num
, enc_obj_type
;
335 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
336 OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
338 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
339 ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
341 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
342 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
344 /* FIXME: add support for router objects */
345 if (enc_obj_type
== GRAPH_OBJECT_TYPE_ENCODER
) {
346 if (enc_obj_num
== 2)
351 radeon_add_atom_encoder(dev
,
360 /* look up gpio for ddc */
361 if ((le16_to_cpu(path
->usDeviceTag
) &
362 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
364 for (j
= 0; j
< con_obj
->ucNumberOfObjects
; j
++) {
365 if (le16_to_cpu(path
->usConnObjectId
) ==
366 le16_to_cpu(con_obj
->asObjects
[j
].
368 ATOM_COMMON_RECORD_HEADER
370 (ATOM_COMMON_RECORD_HEADER
372 (ctx
->bios
+ data_offset
+
373 le16_to_cpu(con_obj
->
376 ATOM_I2C_RECORD
*i2c_record
;
378 while (record
->ucRecordType
> 0
381 ATOM_MAX_OBJECT_RECORD_NUMBER
) {
384 case ATOM_I2C_RECORD_TYPE
:
395 (ATOM_COMMON_RECORD_HEADER
407 if ((le16_to_cpu(path
->usDeviceTag
) ==
408 ATOM_DEVICE_TV1_SUPPORT
)
409 || (le16_to_cpu(path
->usDeviceTag
) ==
410 ATOM_DEVICE_TV2_SUPPORT
)
411 || (le16_to_cpu(path
->usDeviceTag
) ==
412 ATOM_DEVICE_CV_SUPPORT
))
413 ddc_bus
.valid
= false;
415 ddc_bus
= radeon_lookup_gpio(dev
, line_mux
);
417 conn_id
= le16_to_cpu(path
->usConnObjectId
);
419 if (!radeon_atom_apply_quirks
420 (dev
, le16_to_cpu(path
->usDeviceTag
), &connector_type
,
424 radeon_add_atom_connector(dev
,
428 connector_type
, &ddc_bus
,
429 linkb
, igp_lane_info
);
434 radeon_link_encoder_connector(dev
);
439 struct bios_connector
{
444 struct radeon_i2c_bus_rec ddc_bus
;
447 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
451 struct radeon_device
*rdev
= dev
->dev_private
;
452 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
453 struct atom_context
*ctx
= mode_info
->atom_context
;
454 int index
= GetIndexIntoMasterTable(DATA
, SupportedDevicesInfo
);
455 uint16_t size
, data_offset
;
457 uint16_t device_support
;
459 union atom_supported_devices
*supported_devices
;
461 struct bios_connector bios_connectors
[ATOM_MAX_SUPPORTED_DEVICE
];
463 atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
);
466 (union atom_supported_devices
*)(ctx
->bios
+ data_offset
);
468 device_support
= le16_to_cpu(supported_devices
->info
.usDeviceSupport
);
470 for (i
= 0; i
< ATOM_MAX_SUPPORTED_DEVICE
; i
++) {
471 ATOM_CONNECTOR_INFO_I2C ci
=
472 supported_devices
->info
.asConnInfo
[i
];
474 bios_connectors
[i
].valid
= false;
476 if (!(device_support
& (1 << i
))) {
480 if (i
== ATOM_DEVICE_CV_INDEX
) {
481 DRM_DEBUG("Skipping Component Video\n");
485 bios_connectors
[i
].connector_type
=
486 supported_devices_connector_convert
[ci
.sucConnectorInfo
.
490 if (bios_connectors
[i
].connector_type
==
491 DRM_MODE_CONNECTOR_Unknown
)
494 dac
= ci
.sucConnectorInfo
.sbfAccess
.bfAssociatedDAC
;
496 if ((rdev
->family
== CHIP_RS690
) ||
497 (rdev
->family
== CHIP_RS740
)) {
498 if ((i
== ATOM_DEVICE_DFP2_INDEX
)
499 && (ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
== 2))
500 bios_connectors
[i
].line_mux
=
501 ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
+ 1;
502 else if ((i
== ATOM_DEVICE_DFP3_INDEX
)
503 && (ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
== 1))
504 bios_connectors
[i
].line_mux
=
505 ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
+ 1;
507 bios_connectors
[i
].line_mux
=
508 ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
;
510 bios_connectors
[i
].line_mux
=
511 ci
.sucI2cId
.sbfAccess
.bfI2C_LineMux
;
513 /* give tv unique connector ids */
514 if (i
== ATOM_DEVICE_TV1_INDEX
) {
515 bios_connectors
[i
].ddc_bus
.valid
= false;
516 bios_connectors
[i
].line_mux
= 50;
517 } else if (i
== ATOM_DEVICE_TV2_INDEX
) {
518 bios_connectors
[i
].ddc_bus
.valid
= false;
519 bios_connectors
[i
].line_mux
= 51;
520 } else if (i
== ATOM_DEVICE_CV_INDEX
) {
521 bios_connectors
[i
].ddc_bus
.valid
= false;
522 bios_connectors
[i
].line_mux
= 52;
524 bios_connectors
[i
].ddc_bus
=
525 radeon_lookup_gpio(dev
,
526 bios_connectors
[i
].line_mux
);
528 /* Always set the connector type to VGA for CRT1/CRT2. if they are
529 * shared with a DVI port, we'll pick up the DVI connector when we
530 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
532 if (i
== ATOM_DEVICE_CRT1_INDEX
|| i
== ATOM_DEVICE_CRT2_INDEX
)
533 bios_connectors
[i
].connector_type
=
534 DRM_MODE_CONNECTOR_VGA
;
536 if (!radeon_atom_apply_quirks
537 (dev
, (1 << i
), &bios_connectors
[i
].connector_type
,
538 &bios_connectors
[i
].ddc_bus
, &bios_connectors
[i
].line_mux
))
541 bios_connectors
[i
].valid
= true;
542 bios_connectors
[i
].devices
= (1 << i
);
544 if (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
)
545 radeon_add_atom_encoder(dev
,
546 radeon_get_encoder_id(dev
,
551 radeon_add_legacy_encoder(dev
,
552 radeon_get_encoder_id(dev
,
559 /* combine shared connectors */
560 for (i
= 0; i
< ATOM_MAX_SUPPORTED_DEVICE
; i
++) {
561 if (bios_connectors
[i
].valid
) {
562 for (j
= 0; j
< ATOM_MAX_SUPPORTED_DEVICE
; j
++) {
563 if (bios_connectors
[j
].valid
&& (i
!= j
)) {
564 if (bios_connectors
[i
].line_mux
==
565 bios_connectors
[j
].line_mux
) {
566 if (((bios_connectors
[i
].
568 (ATOM_DEVICE_DFP_SUPPORT
))
569 && (bios_connectors
[j
].
571 (ATOM_DEVICE_CRT_SUPPORT
)))
573 ((bios_connectors
[j
].
575 (ATOM_DEVICE_DFP_SUPPORT
))
576 && (bios_connectors
[i
].
578 (ATOM_DEVICE_CRT_SUPPORT
)))) {
585 DRM_MODE_CONNECTOR_DVII
;
595 /* add the connectors */
596 for (i
= 0; i
< ATOM_MAX_SUPPORTED_DEVICE
; i
++) {
597 if (bios_connectors
[i
].valid
)
598 radeon_add_atom_connector(dev
,
599 bios_connectors
[i
].line_mux
,
600 bios_connectors
[i
].devices
,
603 &bios_connectors
[i
].ddc_bus
,
607 radeon_link_encoder_connector(dev
);
612 union firmware_info
{
613 ATOM_FIRMWARE_INFO info
;
614 ATOM_FIRMWARE_INFO_V1_2 info_12
;
615 ATOM_FIRMWARE_INFO_V1_3 info_13
;
616 ATOM_FIRMWARE_INFO_V1_4 info_14
;
619 bool radeon_atom_get_clock_info(struct drm_device
*dev
)
621 struct radeon_device
*rdev
= dev
->dev_private
;
622 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
623 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
624 union firmware_info
*firmware_info
;
626 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
627 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
628 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
629 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
630 uint16_t data_offset
;
632 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
633 &crev
, &data_offset
);
636 (union firmware_info
*)(mode_info
->atom_context
->bios
+
641 p1pll
->reference_freq
=
642 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
643 p1pll
->reference_div
= 0;
647 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Output
);
650 le32_to_cpu(firmware_info
->info_12
.ulMinPixelClockPLL_Output
);
652 le32_to_cpu(firmware_info
->info
.ulMaxPixelClockPLL_Output
);
654 if (p1pll
->pll_out_min
== 0) {
655 if (ASIC_IS_AVIVO(rdev
))
656 p1pll
->pll_out_min
= 64800;
658 p1pll
->pll_out_min
= 20000;
659 } else if (p1pll
->pll_out_min
> 64800) {
660 /* Limiting the pll output range is a good thing generally as
661 * it limits the number of possible pll combinations for a given
662 * frequency presumably to the ones that work best on each card.
663 * However, certain duallink DVI monitors seem to like
664 * pll combinations that would be limited by this at least on
665 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
668 p1pll
->pll_out_min
= 64800;
672 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Input
);
674 le16_to_cpu(firmware_info
->info
.usMaxPixelClockPLL_Input
);
679 spll
->reference_freq
=
680 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
681 spll
->reference_div
= 0;
684 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Output
);
686 le32_to_cpu(firmware_info
->info
.ulMaxEngineClockPLL_Output
);
689 if (spll
->pll_out_min
== 0) {
690 if (ASIC_IS_AVIVO(rdev
))
691 spll
->pll_out_min
= 64800;
693 spll
->pll_out_min
= 20000;
697 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Input
);
699 le16_to_cpu(firmware_info
->info
.usMaxEngineClockPLL_Input
);
702 mpll
->reference_freq
=
703 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
704 mpll
->reference_div
= 0;
707 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Output
);
709 le32_to_cpu(firmware_info
->info
.ulMaxMemoryClockPLL_Output
);
712 if (mpll
->pll_out_min
== 0) {
713 if (ASIC_IS_AVIVO(rdev
))
714 mpll
->pll_out_min
= 64800;
716 mpll
->pll_out_min
= 20000;
720 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Input
);
722 le16_to_cpu(firmware_info
->info
.usMaxMemoryClockPLL_Input
);
724 rdev
->clock
.default_sclk
=
725 le32_to_cpu(firmware_info
->info
.ulDefaultEngineClock
);
726 rdev
->clock
.default_mclk
=
727 le32_to_cpu(firmware_info
->info
.ulDefaultMemoryClock
);
734 bool radeon_atombios_get_tmds_info(struct radeon_encoder
*encoder
,
735 struct radeon_encoder_int_tmds
*tmds
)
737 struct drm_device
*dev
= encoder
->base
.dev
;
738 struct radeon_device
*rdev
= dev
->dev_private
;
739 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
740 int index
= GetIndexIntoMasterTable(DATA
, TMDS_Info
);
741 uint16_t data_offset
;
742 struct _ATOM_TMDS_INFO
*tmds_info
;
747 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
748 &crev
, &data_offset
);
751 (struct _ATOM_TMDS_INFO
*)(mode_info
->atom_context
->bios
+
755 maxfreq
= le16_to_cpu(tmds_info
->usMaxFrequency
);
756 for (i
= 0; i
< 4; i
++) {
757 tmds
->tmds_pll
[i
].freq
=
758 le16_to_cpu(tmds_info
->asMiscInfo
[i
].usFrequency
);
759 tmds
->tmds_pll
[i
].value
=
760 tmds_info
->asMiscInfo
[i
].ucPLL_ChargePump
& 0x3f;
761 tmds
->tmds_pll
[i
].value
|=
762 (tmds_info
->asMiscInfo
[i
].
763 ucPLL_VCO_Gain
& 0x3f) << 6;
764 tmds
->tmds_pll
[i
].value
|=
765 (tmds_info
->asMiscInfo
[i
].
766 ucPLL_DutyCycle
& 0xf) << 12;
767 tmds
->tmds_pll
[i
].value
|=
768 (tmds_info
->asMiscInfo
[i
].
769 ucPLL_VoltageSwing
& 0xf) << 16;
771 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
772 tmds
->tmds_pll
[i
].freq
,
773 tmds
->tmds_pll
[i
].value
);
775 if (maxfreq
== tmds
->tmds_pll
[i
].freq
) {
776 tmds
->tmds_pll
[i
].freq
= 0xffffffff;
785 static struct radeon_atom_ss
*radeon_atombios_get_ss_info(struct
790 struct drm_device
*dev
= encoder
->base
.dev
;
791 struct radeon_device
*rdev
= dev
->dev_private
;
792 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
793 int index
= GetIndexIntoMasterTable(DATA
, PPLL_SS_Info
);
794 uint16_t data_offset
;
795 struct _ATOM_SPREAD_SPECTRUM_INFO
*ss_info
;
797 struct radeon_atom_ss
*ss
= NULL
;
799 if (id
> ATOM_MAX_SS_ENTRY
)
802 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
803 &crev
, &data_offset
);
806 (struct _ATOM_SPREAD_SPECTRUM_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
810 kzalloc(sizeof(struct radeon_atom_ss
), GFP_KERNEL
);
815 ss
->percentage
= le16_to_cpu(ss_info
->asSS_Info
[id
].usSpreadSpectrumPercentage
);
816 ss
->type
= ss_info
->asSS_Info
[id
].ucSpreadSpectrumType
;
817 ss
->step
= ss_info
->asSS_Info
[id
].ucSS_Step
;
818 ss
->delay
= ss_info
->asSS_Info
[id
].ucSS_Delay
;
819 ss
->range
= ss_info
->asSS_Info
[id
].ucSS_Range
;
820 ss
->refdiv
= ss_info
->asSS_Info
[id
].ucRecommendedRef_Div
;
826 struct _ATOM_LVDS_INFO info
;
827 struct _ATOM_LVDS_INFO_V12 info_12
;
830 struct radeon_encoder_atom_dig
*radeon_atombios_get_lvds_info(struct
834 struct drm_device
*dev
= encoder
->base
.dev
;
835 struct radeon_device
*rdev
= dev
->dev_private
;
836 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
837 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
838 uint16_t data_offset
;
839 union lvds_info
*lvds_info
;
841 struct radeon_encoder_atom_dig
*lvds
= NULL
;
843 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
844 &crev
, &data_offset
);
847 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
851 kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
856 lvds
->native_mode
.clock
=
857 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
858 lvds
->native_mode
.hdisplay
=
859 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
860 lvds
->native_mode
.vdisplay
=
861 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
862 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
863 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
864 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
865 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
866 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
867 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
868 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
869 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
870 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
871 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
872 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
873 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
874 lvds
->panel_pwr_delay
=
875 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
876 lvds
->lvds_misc
= lvds_info
->info
.ucLVDS_Misc
;
877 /* set crtc values */
878 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
880 lvds
->ss
= radeon_atombios_get_ss_info(encoder
, lvds_info
->info
.ucSS_Id
);
882 encoder
->native_mode
= lvds
->native_mode
;
887 struct radeon_encoder_primary_dac
*
888 radeon_atombios_get_primary_dac_info(struct radeon_encoder
*encoder
)
890 struct drm_device
*dev
= encoder
->base
.dev
;
891 struct radeon_device
*rdev
= dev
->dev_private
;
892 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
893 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
894 uint16_t data_offset
;
895 struct _COMPASSIONATE_DATA
*dac_info
;
898 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
900 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
, &crev
, &data_offset
);
902 dac_info
= (struct _COMPASSIONATE_DATA
*)(mode_info
->atom_context
->bios
+ data_offset
);
905 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
), GFP_KERNEL
);
910 bg
= dac_info
->ucDAC1_BG_Adjustment
;
911 dac
= dac_info
->ucDAC1_DAC_Adjustment
;
912 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
918 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
919 struct drm_display_mode
*mode
)
921 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
922 ATOM_ANALOG_TV_INFO
*tv_info
;
923 ATOM_ANALOG_TV_INFO_V1_2
*tv_info_v1_2
;
924 ATOM_DTD_FORMAT
*dtd_timings
;
925 int data_index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
927 u16 data_offset
, misc
;
929 atom_parse_data_header(mode_info
->atom_context
, data_index
, NULL
, &frev
, &crev
, &data_offset
);
933 tv_info
= (ATOM_ANALOG_TV_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
934 if (index
> MAX_SUPPORTED_TV_TIMING
)
937 mode
->crtc_htotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Total
);
938 mode
->crtc_hdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Disp
);
939 mode
->crtc_hsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
);
940 mode
->crtc_hsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
) +
941 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncWidth
);
943 mode
->crtc_vtotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Total
);
944 mode
->crtc_vdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Disp
);
945 mode
->crtc_vsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
);
946 mode
->crtc_vsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
) +
947 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncWidth
);
950 misc
= le16_to_cpu(tv_info
->aModeTimings
[index
].susModeMiscInfo
.usAccess
);
951 if (misc
& ATOM_VSYNC_POLARITY
)
952 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
953 if (misc
& ATOM_HSYNC_POLARITY
)
954 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
955 if (misc
& ATOM_COMPOSITESYNC
)
956 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
957 if (misc
& ATOM_INTERLACE
)
958 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
959 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
960 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
962 mode
->clock
= le16_to_cpu(tv_info
->aModeTimings
[index
].usPixelClock
) * 10;
965 /* PAL timings appear to have wrong values for totals */
966 mode
->crtc_htotal
-= 1;
967 mode
->crtc_vtotal
-= 1;
971 tv_info_v1_2
= (ATOM_ANALOG_TV_INFO_V1_2
*)(mode_info
->atom_context
->bios
+ data_offset
);
972 if (index
> MAX_SUPPORTED_TV_TIMING_V1_2
)
975 dtd_timings
= &tv_info_v1_2
->aModeTimings
[index
];
976 mode
->crtc_htotal
= le16_to_cpu(dtd_timings
->usHActive
) +
977 le16_to_cpu(dtd_timings
->usHBlanking_Time
);
978 mode
->crtc_hdisplay
= le16_to_cpu(dtd_timings
->usHActive
);
979 mode
->crtc_hsync_start
= le16_to_cpu(dtd_timings
->usHActive
) +
980 le16_to_cpu(dtd_timings
->usHSyncOffset
);
981 mode
->crtc_hsync_end
= mode
->crtc_hsync_start
+
982 le16_to_cpu(dtd_timings
->usHSyncWidth
);
984 mode
->crtc_vtotal
= le16_to_cpu(dtd_timings
->usVActive
) +
985 le16_to_cpu(dtd_timings
->usVBlanking_Time
);
986 mode
->crtc_vdisplay
= le16_to_cpu(dtd_timings
->usVActive
);
987 mode
->crtc_vsync_start
= le16_to_cpu(dtd_timings
->usVActive
) +
988 le16_to_cpu(dtd_timings
->usVSyncOffset
);
989 mode
->crtc_vsync_end
= mode
->crtc_vsync_start
+
990 le16_to_cpu(dtd_timings
->usVSyncWidth
);
993 misc
= le16_to_cpu(dtd_timings
->susModeMiscInfo
.usAccess
);
994 if (misc
& ATOM_VSYNC_POLARITY
)
995 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
996 if (misc
& ATOM_HSYNC_POLARITY
)
997 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
998 if (misc
& ATOM_COMPOSITESYNC
)
999 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1000 if (misc
& ATOM_INTERLACE
)
1001 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1002 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1003 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1005 mode
->clock
= le16_to_cpu(dtd_timings
->usPixClk
) * 10;
1011 struct radeon_encoder_tv_dac
*
1012 radeon_atombios_get_tv_dac_info(struct radeon_encoder
*encoder
)
1014 struct drm_device
*dev
= encoder
->base
.dev
;
1015 struct radeon_device
*rdev
= dev
->dev_private
;
1016 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1017 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1018 uint16_t data_offset
;
1019 struct _COMPASSIONATE_DATA
*dac_info
;
1022 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1024 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
, &crev
, &data_offset
);
1026 dac_info
= (struct _COMPASSIONATE_DATA
*)(mode_info
->atom_context
->bios
+ data_offset
);
1029 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1034 bg
= dac_info
->ucDAC2_CRT2_BG_Adjustment
;
1035 dac
= dac_info
->ucDAC2_CRT2_DAC_Adjustment
;
1036 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1038 bg
= dac_info
->ucDAC2_PAL_BG_Adjustment
;
1039 dac
= dac_info
->ucDAC2_PAL_DAC_Adjustment
;
1040 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1042 bg
= dac_info
->ucDAC2_NTSC_BG_Adjustment
;
1043 dac
= dac_info
->ucDAC2_NTSC_DAC_Adjustment
;
1044 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1050 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
)
1052 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args
;
1053 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicClockGating
);
1055 args
.ucEnable
= enable
;
1057 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1060 void radeon_atom_static_pwrmgt_setup(struct radeon_device
*rdev
, int enable
)
1062 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args
;
1063 int index
= GetIndexIntoMasterTable(COMMAND
, EnableASIC_StaticPwrMgt
);
1065 args
.ucEnable
= enable
;
1067 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1070 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
,
1073 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
1074 int index
= GetIndexIntoMasterTable(COMMAND
, SetEngineClock
);
1076 args
.ulTargetEngineClock
= eng_clock
; /* 10 khz */
1078 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1081 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
,
1084 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
1085 int index
= GetIndexIntoMasterTable(COMMAND
, SetMemoryClock
);
1087 if (rdev
->flags
& RADEON_IS_IGP
)
1090 args
.ulTargetMemoryClock
= mem_clock
; /* 10 khz */
1092 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1095 void radeon_atom_initialize_bios_scratch_regs(struct drm_device
*dev
)
1097 struct radeon_device
*rdev
= dev
->dev_private
;
1098 uint32_t bios_2_scratch
, bios_6_scratch
;
1100 if (rdev
->family
>= CHIP_R600
) {
1101 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
1102 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1104 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
1105 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1108 /* let the bios control the backlight */
1109 bios_2_scratch
&= ~ATOM_S2_VRI_BRIGHT_ENABLE
;
1111 /* tell the bios not to handle mode switching */
1112 bios_6_scratch
|= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
| ATOM_S6_ACC_MODE
);
1114 if (rdev
->family
>= CHIP_R600
) {
1115 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
1116 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1118 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
1119 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1124 void radeon_save_bios_scratch_regs(struct radeon_device
*rdev
)
1126 uint32_t scratch_reg
;
1129 if (rdev
->family
>= CHIP_R600
)
1130 scratch_reg
= R600_BIOS_0_SCRATCH
;
1132 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
1134 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
1135 rdev
->bios_scratch
[i
] = RREG32(scratch_reg
+ (i
* 4));
1138 void radeon_restore_bios_scratch_regs(struct radeon_device
*rdev
)
1140 uint32_t scratch_reg
;
1143 if (rdev
->family
>= CHIP_R600
)
1144 scratch_reg
= R600_BIOS_0_SCRATCH
;
1146 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
1148 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
1149 WREG32(scratch_reg
+ (i
* 4), rdev
->bios_scratch
[i
]);
1152 void radeon_atom_output_lock(struct drm_encoder
*encoder
, bool lock
)
1154 struct drm_device
*dev
= encoder
->dev
;
1155 struct radeon_device
*rdev
= dev
->dev_private
;
1156 uint32_t bios_6_scratch
;
1158 if (rdev
->family
>= CHIP_R600
)
1159 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1161 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1164 bios_6_scratch
|= ATOM_S6_CRITICAL_STATE
;
1166 bios_6_scratch
&= ~ATOM_S6_CRITICAL_STATE
;
1168 if (rdev
->family
>= CHIP_R600
)
1169 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1171 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1174 /* at some point we may want to break this out into individual functions */
1176 radeon_atombios_connected_scratch_regs(struct drm_connector
*connector
,
1177 struct drm_encoder
*encoder
,
1180 struct drm_device
*dev
= connector
->dev
;
1181 struct radeon_device
*rdev
= dev
->dev_private
;
1182 struct radeon_connector
*radeon_connector
=
1183 to_radeon_connector(connector
);
1184 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1185 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
1187 if (rdev
->family
>= CHIP_R600
) {
1188 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
1189 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
1190 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1192 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
1193 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
1194 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1197 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
1198 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
1200 DRM_DEBUG("TV1 connected\n");
1201 bios_3_scratch
|= ATOM_S3_TV1_ACTIVE
;
1202 bios_6_scratch
|= ATOM_S6_ACC_REQ_TV1
;
1204 DRM_DEBUG("TV1 disconnected\n");
1205 bios_0_scratch
&= ~ATOM_S0_TV1_MASK
;
1206 bios_3_scratch
&= ~ATOM_S3_TV1_ACTIVE
;
1207 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_TV1
;
1210 if ((radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) &&
1211 (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
)) {
1213 DRM_DEBUG("CV connected\n");
1214 bios_3_scratch
|= ATOM_S3_CV_ACTIVE
;
1215 bios_6_scratch
|= ATOM_S6_ACC_REQ_CV
;
1217 DRM_DEBUG("CV disconnected\n");
1218 bios_0_scratch
&= ~ATOM_S0_CV_MASK
;
1219 bios_3_scratch
&= ~ATOM_S3_CV_ACTIVE
;
1220 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CV
;
1223 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
1224 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
1226 DRM_DEBUG("LCD1 connected\n");
1227 bios_0_scratch
|= ATOM_S0_LCD1
;
1228 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
1229 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
1231 DRM_DEBUG("LCD1 disconnected\n");
1232 bios_0_scratch
&= ~ATOM_S0_LCD1
;
1233 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
1234 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
1237 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
1238 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
1240 DRM_DEBUG("CRT1 connected\n");
1241 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
1242 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
1243 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
1245 DRM_DEBUG("CRT1 disconnected\n");
1246 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
1247 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
1248 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
1251 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
1252 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
1254 DRM_DEBUG("CRT2 connected\n");
1255 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
1256 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
1257 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
1259 DRM_DEBUG("CRT2 disconnected\n");
1260 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
1261 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
1262 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
1265 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
1266 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
1268 DRM_DEBUG("DFP1 connected\n");
1269 bios_0_scratch
|= ATOM_S0_DFP1
;
1270 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
1271 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
1273 DRM_DEBUG("DFP1 disconnected\n");
1274 bios_0_scratch
&= ~ATOM_S0_DFP1
;
1275 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
1276 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
1279 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
1280 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
1282 DRM_DEBUG("DFP2 connected\n");
1283 bios_0_scratch
|= ATOM_S0_DFP2
;
1284 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
1285 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
1287 DRM_DEBUG("DFP2 disconnected\n");
1288 bios_0_scratch
&= ~ATOM_S0_DFP2
;
1289 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
1290 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
1293 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
1294 (radeon_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
1296 DRM_DEBUG("DFP3 connected\n");
1297 bios_0_scratch
|= ATOM_S0_DFP3
;
1298 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
1299 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
1301 DRM_DEBUG("DFP3 disconnected\n");
1302 bios_0_scratch
&= ~ATOM_S0_DFP3
;
1303 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
1304 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
1307 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
1308 (radeon_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
1310 DRM_DEBUG("DFP4 connected\n");
1311 bios_0_scratch
|= ATOM_S0_DFP4
;
1312 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
1313 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
1315 DRM_DEBUG("DFP4 disconnected\n");
1316 bios_0_scratch
&= ~ATOM_S0_DFP4
;
1317 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
1318 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
1321 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
1322 (radeon_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
1324 DRM_DEBUG("DFP5 connected\n");
1325 bios_0_scratch
|= ATOM_S0_DFP5
;
1326 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
1327 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
1329 DRM_DEBUG("DFP5 disconnected\n");
1330 bios_0_scratch
&= ~ATOM_S0_DFP5
;
1331 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
1332 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
1336 if (rdev
->family
>= CHIP_R600
) {
1337 WREG32(R600_BIOS_0_SCRATCH
, bios_0_scratch
);
1338 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
1339 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1341 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
1342 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
1343 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1348 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
1350 struct drm_device
*dev
= encoder
->dev
;
1351 struct radeon_device
*rdev
= dev
->dev_private
;
1352 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1353 uint32_t bios_3_scratch
;
1355 if (rdev
->family
>= CHIP_R600
)
1356 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
1358 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
1360 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1361 bios_3_scratch
&= ~ATOM_S3_TV1_CRTC_ACTIVE
;
1362 bios_3_scratch
|= (crtc
<< 18);
1364 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1365 bios_3_scratch
&= ~ATOM_S3_CV_CRTC_ACTIVE
;
1366 bios_3_scratch
|= (crtc
<< 24);
1368 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1369 bios_3_scratch
&= ~ATOM_S3_CRT1_CRTC_ACTIVE
;
1370 bios_3_scratch
|= (crtc
<< 16);
1372 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1373 bios_3_scratch
&= ~ATOM_S3_CRT2_CRTC_ACTIVE
;
1374 bios_3_scratch
|= (crtc
<< 20);
1376 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1377 bios_3_scratch
&= ~ATOM_S3_LCD1_CRTC_ACTIVE
;
1378 bios_3_scratch
|= (crtc
<< 17);
1380 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
1381 bios_3_scratch
&= ~ATOM_S3_DFP1_CRTC_ACTIVE
;
1382 bios_3_scratch
|= (crtc
<< 19);
1384 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
1385 bios_3_scratch
&= ~ATOM_S3_DFP2_CRTC_ACTIVE
;
1386 bios_3_scratch
|= (crtc
<< 23);
1388 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
1389 bios_3_scratch
&= ~ATOM_S3_DFP3_CRTC_ACTIVE
;
1390 bios_3_scratch
|= (crtc
<< 25);
1393 if (rdev
->family
>= CHIP_R600
)
1394 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
1396 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
1400 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
1402 struct drm_device
*dev
= encoder
->dev
;
1403 struct radeon_device
*rdev
= dev
->dev_private
;
1404 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1405 uint32_t bios_2_scratch
;
1407 if (rdev
->family
>= CHIP_R600
)
1408 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
1410 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
1412 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1414 bios_2_scratch
&= ~ATOM_S2_TV1_DPMS_STATE
;
1416 bios_2_scratch
|= ATOM_S2_TV1_DPMS_STATE
;
1418 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1420 bios_2_scratch
&= ~ATOM_S2_CV_DPMS_STATE
;
1422 bios_2_scratch
|= ATOM_S2_CV_DPMS_STATE
;
1424 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1426 bios_2_scratch
&= ~ATOM_S2_CRT1_DPMS_STATE
;
1428 bios_2_scratch
|= ATOM_S2_CRT1_DPMS_STATE
;
1430 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1432 bios_2_scratch
&= ~ATOM_S2_CRT2_DPMS_STATE
;
1434 bios_2_scratch
|= ATOM_S2_CRT2_DPMS_STATE
;
1436 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1438 bios_2_scratch
&= ~ATOM_S2_LCD1_DPMS_STATE
;
1440 bios_2_scratch
|= ATOM_S2_LCD1_DPMS_STATE
;
1442 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
1444 bios_2_scratch
&= ~ATOM_S2_DFP1_DPMS_STATE
;
1446 bios_2_scratch
|= ATOM_S2_DFP1_DPMS_STATE
;
1448 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
1450 bios_2_scratch
&= ~ATOM_S2_DFP2_DPMS_STATE
;
1452 bios_2_scratch
|= ATOM_S2_DFP2_DPMS_STATE
;
1454 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
1456 bios_2_scratch
&= ~ATOM_S2_DFP3_DPMS_STATE
;
1458 bios_2_scratch
|= ATOM_S2_DFP3_DPMS_STATE
;
1460 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) {
1462 bios_2_scratch
&= ~ATOM_S2_DFP4_DPMS_STATE
;
1464 bios_2_scratch
|= ATOM_S2_DFP4_DPMS_STATE
;
1466 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) {
1468 bios_2_scratch
&= ~ATOM_S2_DFP5_DPMS_STATE
;
1470 bios_2_scratch
|= ATOM_S2_DFP5_DPMS_STATE
;
1473 if (rdev
->family
>= CHIP_R600
)
1474 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
1476 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);