2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include "radeon_drm.h"
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_id(struct drm_device
*dev
, uint32_t supported_device
,
44 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device
*dev
,
49 uint32_t connector_id
,
50 uint32_t supported_device
,
52 struct radeon_i2c_bus_rec
*i2c_bus
,
53 uint16_t connector_object_id
,
54 struct radeon_hpd
*hpd
);
56 /* from radeon_legacy_encoder.c */
58 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_id
,
59 uint32_t supported_device
);
61 /* old legacy ATI BIOS routines */
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset
{
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE
,
67 COMBIOS_BIOS_SUPPORT_TABLE
,
68 COMBIOS_DAC_PROGRAMMING_TABLE
,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE
,
70 COMBIOS_CRTC_INFO_TABLE
,
71 COMBIOS_PLL_INFO_TABLE
,
72 COMBIOS_TV_INFO_TABLE
,
73 COMBIOS_DFP_INFO_TABLE
,
74 COMBIOS_HW_CONFIG_INFO_TABLE
,
75 COMBIOS_MULTIMEDIA_INFO_TABLE
,
76 COMBIOS_TV_STD_PATCH_TABLE
,
77 COMBIOS_LCD_INFO_TABLE
,
78 COMBIOS_MOBILE_INFO_TABLE
,
79 COMBIOS_PLL_INIT_TABLE
,
80 COMBIOS_MEM_CONFIG_TABLE
,
81 COMBIOS_SAVE_MASK_TABLE
,
82 COMBIOS_HARDCODED_EDID_TABLE
,
83 COMBIOS_ASIC_INIT_2_TABLE
,
84 COMBIOS_CONNECTOR_INFO_TABLE
,
85 COMBIOS_DYN_CLK_1_TABLE
,
86 COMBIOS_RESERVED_MEM_TABLE
,
87 COMBIOS_EXT_TMDS_INFO_TABLE
,
88 COMBIOS_MEM_CLK_INFO_TABLE
,
89 COMBIOS_EXT_DAC_INFO_TABLE
,
90 COMBIOS_MISC_INFO_TABLE
,
91 COMBIOS_CRT_INFO_TABLE
,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE
,
94 COMBIOS_FAN_SPEED_INFO_TABLE
,
95 COMBIOS_OVERDRIVE_INFO_TABLE
,
96 COMBIOS_OEM_INFO_TABLE
,
97 COMBIOS_DYN_CLK_2_TABLE
,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE
,
99 COMBIOS_I2C_INFO_TABLE
,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE
, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE
, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE
, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE
, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE
, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE
, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE
, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE
, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE
, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE
, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE
, /* offset from tmds power */
114 enum radeon_combios_ddc
{
124 enum radeon_combios_connector
{
125 CONNECTOR_NONE_LEGACY
,
126 CONNECTOR_PROPRIETARY_LEGACY
,
127 CONNECTOR_CRT_LEGACY
,
128 CONNECTOR_DVI_I_LEGACY
,
129 CONNECTOR_DVI_D_LEGACY
,
130 CONNECTOR_CTV_LEGACY
,
131 CONNECTOR_STV_LEGACY
,
132 CONNECTOR_UNSUPPORTED_LEGACY
135 const int legacy_connector_convert
[] = {
136 DRM_MODE_CONNECTOR_Unknown
,
137 DRM_MODE_CONNECTOR_DVID
,
138 DRM_MODE_CONNECTOR_VGA
,
139 DRM_MODE_CONNECTOR_DVII
,
140 DRM_MODE_CONNECTOR_DVID
,
141 DRM_MODE_CONNECTOR_Composite
,
142 DRM_MODE_CONNECTOR_SVIDEO
,
143 DRM_MODE_CONNECTOR_Unknown
,
146 static uint16_t combios_get_table_offset(struct drm_device
*dev
,
147 enum radeon_combios_table_offset table
)
149 struct radeon_device
*rdev
= dev
->dev_private
;
151 uint16_t offset
= 0, check_offset
;
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE
:
159 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0xc);
161 offset
= check_offset
;
163 case COMBIOS_BIOS_SUPPORT_TABLE
:
164 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x14);
166 offset
= check_offset
;
168 case COMBIOS_DAC_PROGRAMMING_TABLE
:
169 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2a);
171 offset
= check_offset
;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE
:
174 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2c);
176 offset
= check_offset
;
178 case COMBIOS_CRTC_INFO_TABLE
:
179 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2e);
181 offset
= check_offset
;
183 case COMBIOS_PLL_INFO_TABLE
:
184 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x30);
186 offset
= check_offset
;
188 case COMBIOS_TV_INFO_TABLE
:
189 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x32);
191 offset
= check_offset
;
193 case COMBIOS_DFP_INFO_TABLE
:
194 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x34);
196 offset
= check_offset
;
198 case COMBIOS_HW_CONFIG_INFO_TABLE
:
199 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x36);
201 offset
= check_offset
;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE
:
204 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x38);
206 offset
= check_offset
;
208 case COMBIOS_TV_STD_PATCH_TABLE
:
209 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x3e);
211 offset
= check_offset
;
213 case COMBIOS_LCD_INFO_TABLE
:
214 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x40);
216 offset
= check_offset
;
218 case COMBIOS_MOBILE_INFO_TABLE
:
219 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x42);
221 offset
= check_offset
;
223 case COMBIOS_PLL_INIT_TABLE
:
224 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x46);
226 offset
= check_offset
;
228 case COMBIOS_MEM_CONFIG_TABLE
:
229 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x48);
231 offset
= check_offset
;
233 case COMBIOS_SAVE_MASK_TABLE
:
234 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4a);
236 offset
= check_offset
;
238 case COMBIOS_HARDCODED_EDID_TABLE
:
239 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4c);
241 offset
= check_offset
;
243 case COMBIOS_ASIC_INIT_2_TABLE
:
244 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4e);
246 offset
= check_offset
;
248 case COMBIOS_CONNECTOR_INFO_TABLE
:
249 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x50);
251 offset
= check_offset
;
253 case COMBIOS_DYN_CLK_1_TABLE
:
254 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x52);
256 offset
= check_offset
;
258 case COMBIOS_RESERVED_MEM_TABLE
:
259 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x54);
261 offset
= check_offset
;
263 case COMBIOS_EXT_TMDS_INFO_TABLE
:
264 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x58);
266 offset
= check_offset
;
268 case COMBIOS_MEM_CLK_INFO_TABLE
:
269 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5a);
271 offset
= check_offset
;
273 case COMBIOS_EXT_DAC_INFO_TABLE
:
274 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5c);
276 offset
= check_offset
;
278 case COMBIOS_MISC_INFO_TABLE
:
279 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5e);
281 offset
= check_offset
;
283 case COMBIOS_CRT_INFO_TABLE
:
284 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x60);
286 offset
= check_offset
;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
:
289 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x62);
291 offset
= check_offset
;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE
:
294 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x64);
296 offset
= check_offset
;
298 case COMBIOS_FAN_SPEED_INFO_TABLE
:
299 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x66);
301 offset
= check_offset
;
303 case COMBIOS_OVERDRIVE_INFO_TABLE
:
304 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x68);
306 offset
= check_offset
;
308 case COMBIOS_OEM_INFO_TABLE
:
309 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6a);
311 offset
= check_offset
;
313 case COMBIOS_DYN_CLK_2_TABLE
:
314 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6c);
316 offset
= check_offset
;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE
:
319 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6e);
321 offset
= check_offset
;
323 case COMBIOS_I2C_INFO_TABLE
:
324 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x70);
326 offset
= check_offset
;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE
: /* offset from misc info */
331 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
333 rev
= RBIOS8(check_offset
);
335 check_offset
= RBIOS16(check_offset
+ 0x3);
337 offset
= check_offset
;
341 case COMBIOS_ASIC_INIT_4_TABLE
: /* offset from misc info */
343 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
345 rev
= RBIOS8(check_offset
);
347 check_offset
= RBIOS16(check_offset
+ 0x5);
349 offset
= check_offset
;
353 case COMBIOS_DETECTED_MEM_TABLE
: /* offset from misc info */
355 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
357 rev
= RBIOS8(check_offset
);
359 check_offset
= RBIOS16(check_offset
+ 0x7);
361 offset
= check_offset
;
365 case COMBIOS_ASIC_INIT_5_TABLE
: /* offset from misc info */
367 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
369 rev
= RBIOS8(check_offset
);
371 check_offset
= RBIOS16(check_offset
+ 0x9);
373 offset
= check_offset
;
377 case COMBIOS_RAM_RESET_TABLE
: /* offset from mem config */
379 combios_get_table_offset(dev
, COMBIOS_MEM_CONFIG_TABLE
);
381 while (RBIOS8(check_offset
++));
384 offset
= check_offset
;
387 case COMBIOS_POWERPLAY_INFO_TABLE
: /* offset from mobile info */
389 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
391 check_offset
= RBIOS16(check_offset
+ 0x11);
393 offset
= check_offset
;
396 case COMBIOS_GPIO_INFO_TABLE
: /* offset from mobile info */
398 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
400 check_offset
= RBIOS16(check_offset
+ 0x13);
402 offset
= check_offset
;
405 case COMBIOS_LCD_DDC_INFO_TABLE
: /* offset from mobile info */
407 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
409 check_offset
= RBIOS16(check_offset
+ 0x15);
411 offset
= check_offset
;
414 case COMBIOS_TMDS_POWER_TABLE
: /* offset from mobile info */
416 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
418 check_offset
= RBIOS16(check_offset
+ 0x17);
420 offset
= check_offset
;
423 case COMBIOS_TMDS_POWER_ON_TABLE
: /* offset from tmds power */
425 combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_TABLE
);
427 check_offset
= RBIOS16(check_offset
+ 0x2);
429 offset
= check_offset
;
432 case COMBIOS_TMDS_POWER_OFF_TABLE
: /* offset from tmds power */
434 combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_TABLE
);
436 check_offset
= RBIOS16(check_offset
+ 0x4);
438 offset
= check_offset
;
449 bool radeon_combios_check_hardcoded_edid(struct radeon_device
*rdev
)
453 edid_info
= combios_get_table_offset(rdev
->ddev
, COMBIOS_HARDCODED_EDID_TABLE
);
457 edid
= kmalloc(EDID_LENGTH
* (DRM_MAX_EDID_EXT_NUM
+ 1),
462 memcpy((unsigned char *)edid
,
463 (unsigned char *)(rdev
->bios
+ edid_info
), EDID_LENGTH
);
465 if (!drm_edid_is_valid(edid
)) {
470 rdev
->mode_info
.bios_hardcoded_edid
= edid
;
475 radeon_combios_get_hardcoded_edid(struct radeon_device
*rdev
)
477 if (rdev
->mode_info
.bios_hardcoded_edid
)
478 return rdev
->mode_info
.bios_hardcoded_edid
;
482 static struct radeon_i2c_bus_rec
combios_setup_i2c_bus(struct radeon_device
*rdev
,
485 struct radeon_i2c_bus_rec i2c
;
487 if (ddc_line
== RADEON_GPIOPAD_MASK
) {
488 i2c
.mask_clk_reg
= RADEON_GPIOPAD_MASK
;
489 i2c
.mask_data_reg
= RADEON_GPIOPAD_MASK
;
490 i2c
.a_clk_reg
= RADEON_GPIOPAD_A
;
491 i2c
.a_data_reg
= RADEON_GPIOPAD_A
;
492 i2c
.en_clk_reg
= RADEON_GPIOPAD_EN
;
493 i2c
.en_data_reg
= RADEON_GPIOPAD_EN
;
494 i2c
.y_clk_reg
= RADEON_GPIOPAD_Y
;
495 i2c
.y_data_reg
= RADEON_GPIOPAD_Y
;
496 } else if (ddc_line
== RADEON_MDGPIO_MASK
) {
497 i2c
.mask_clk_reg
= RADEON_MDGPIO_MASK
;
498 i2c
.mask_data_reg
= RADEON_MDGPIO_MASK
;
499 i2c
.a_clk_reg
= RADEON_MDGPIO_A
;
500 i2c
.a_data_reg
= RADEON_MDGPIO_A
;
501 i2c
.en_clk_reg
= RADEON_MDGPIO_EN
;
502 i2c
.en_data_reg
= RADEON_MDGPIO_EN
;
503 i2c
.y_clk_reg
= RADEON_MDGPIO_Y
;
504 i2c
.y_data_reg
= RADEON_MDGPIO_Y
;
506 i2c
.mask_clk_mask
= RADEON_GPIO_EN_1
;
507 i2c
.mask_data_mask
= RADEON_GPIO_EN_0
;
508 i2c
.a_clk_mask
= RADEON_GPIO_A_1
;
509 i2c
.a_data_mask
= RADEON_GPIO_A_0
;
510 i2c
.en_clk_mask
= RADEON_GPIO_EN_1
;
511 i2c
.en_data_mask
= RADEON_GPIO_EN_0
;
512 i2c
.y_clk_mask
= RADEON_GPIO_Y_1
;
513 i2c
.y_data_mask
= RADEON_GPIO_Y_0
;
515 i2c
.mask_clk_reg
= ddc_line
;
516 i2c
.mask_data_reg
= ddc_line
;
517 i2c
.a_clk_reg
= ddc_line
;
518 i2c
.a_data_reg
= ddc_line
;
519 i2c
.en_clk_reg
= ddc_line
;
520 i2c
.en_data_reg
= ddc_line
;
521 i2c
.y_clk_reg
= ddc_line
;
522 i2c
.y_data_reg
= ddc_line
;
525 switch (rdev
->family
) {
533 case RADEON_GPIO_DVI_DDC
:
534 i2c
.hw_capable
= true;
537 i2c
.hw_capable
= false;
543 case RADEON_GPIO_DVI_DDC
:
544 case RADEON_GPIO_MONID
:
545 i2c
.hw_capable
= true;
548 i2c
.hw_capable
= false;
555 case RADEON_GPIO_VGA_DDC
:
556 case RADEON_GPIO_DVI_DDC
:
557 case RADEON_GPIO_CRT2_DDC
:
558 i2c
.hw_capable
= true;
561 i2c
.hw_capable
= false;
568 case RADEON_GPIO_VGA_DDC
:
569 case RADEON_GPIO_DVI_DDC
:
570 i2c
.hw_capable
= true;
573 i2c
.hw_capable
= false;
582 case RADEON_GPIO_VGA_DDC
:
583 case RADEON_GPIO_DVI_DDC
:
584 i2c
.hw_capable
= true;
586 case RADEON_GPIO_MONID
:
587 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
588 * reliably on some pre-r4xx hardware; not sure why.
590 i2c
.hw_capable
= false;
593 i2c
.hw_capable
= false;
598 i2c
.hw_capable
= false;
613 bool radeon_combios_get_clock_info(struct drm_device
*dev
)
615 struct radeon_device
*rdev
= dev
->dev_private
;
617 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
618 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
619 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
620 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
624 pll_info
= combios_get_table_offset(dev
, COMBIOS_PLL_INFO_TABLE
);
626 rev
= RBIOS8(pll_info
);
629 p1pll
->reference_freq
= RBIOS16(pll_info
+ 0xe);
630 p1pll
->reference_div
= RBIOS16(pll_info
+ 0x10);
631 p1pll
->pll_out_min
= RBIOS32(pll_info
+ 0x12);
632 p1pll
->pll_out_max
= RBIOS32(pll_info
+ 0x16);
633 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
634 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
637 p1pll
->pll_in_min
= RBIOS32(pll_info
+ 0x36);
638 p1pll
->pll_in_max
= RBIOS32(pll_info
+ 0x3a);
640 p1pll
->pll_in_min
= 40;
641 p1pll
->pll_in_max
= 500;
646 spll
->reference_freq
= RBIOS16(pll_info
+ 0x1a);
647 spll
->reference_div
= RBIOS16(pll_info
+ 0x1c);
648 spll
->pll_out_min
= RBIOS32(pll_info
+ 0x1e);
649 spll
->pll_out_max
= RBIOS32(pll_info
+ 0x22);
652 spll
->pll_in_min
= RBIOS32(pll_info
+ 0x48);
653 spll
->pll_in_max
= RBIOS32(pll_info
+ 0x4c);
656 spll
->pll_in_min
= 40;
657 spll
->pll_in_max
= 500;
661 mpll
->reference_freq
= RBIOS16(pll_info
+ 0x26);
662 mpll
->reference_div
= RBIOS16(pll_info
+ 0x28);
663 mpll
->pll_out_min
= RBIOS32(pll_info
+ 0x2a);
664 mpll
->pll_out_max
= RBIOS32(pll_info
+ 0x2e);
667 mpll
->pll_in_min
= RBIOS32(pll_info
+ 0x5a);
668 mpll
->pll_in_max
= RBIOS32(pll_info
+ 0x5e);
671 mpll
->pll_in_min
= 40;
672 mpll
->pll_in_max
= 500;
675 /* default sclk/mclk */
676 sclk
= RBIOS16(pll_info
+ 0xa);
677 mclk
= RBIOS16(pll_info
+ 0x8);
683 rdev
->clock
.default_sclk
= sclk
;
684 rdev
->clock
.default_mclk
= mclk
;
691 bool radeon_combios_sideport_present(struct radeon_device
*rdev
)
693 struct drm_device
*dev
= rdev
->ddev
;
696 igp_info
= combios_get_table_offset(dev
, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
);
699 if (RBIOS16(igp_info
+ 0x4))
705 static const uint32_t default_primarydac_adj
[CHIP_LAST
] = {
706 0x00000808, /* r100 */
707 0x00000808, /* rv100 */
708 0x00000808, /* rs100 */
709 0x00000808, /* rv200 */
710 0x00000808, /* rs200 */
711 0x00000808, /* r200 */
712 0x00000808, /* rv250 */
713 0x00000000, /* rs300 */
714 0x00000808, /* rv280 */
715 0x00000808, /* r300 */
716 0x00000808, /* r350 */
717 0x00000808, /* rv350 */
718 0x00000808, /* rv380 */
719 0x00000808, /* r420 */
720 0x00000808, /* r423 */
721 0x00000808, /* rv410 */
722 0x00000000, /* rs400 */
723 0x00000000, /* rs480 */
726 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device
*rdev
,
727 struct radeon_encoder_primary_dac
*p_dac
)
729 p_dac
->ps2_pdac_adj
= default_primarydac_adj
[rdev
->family
];
733 struct radeon_encoder_primary_dac
*radeon_combios_get_primary_dac_info(struct
737 struct drm_device
*dev
= encoder
->base
.dev
;
738 struct radeon_device
*rdev
= dev
->dev_private
;
740 uint8_t rev
, bg
, dac
;
741 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
744 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
),
750 /* check CRT table */
751 dac_info
= combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
753 rev
= RBIOS8(dac_info
) & 0x3;
755 bg
= RBIOS8(dac_info
+ 0x2) & 0xf;
756 dac
= (RBIOS8(dac_info
+ 0x2) >> 4) & 0xf;
757 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
759 bg
= RBIOS8(dac_info
+ 0x2) & 0xf;
760 dac
= RBIOS8(dac_info
+ 0x3) & 0xf;
761 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
766 if (!found
) /* fallback to defaults */
767 radeon_legacy_get_primary_dac_info_from_table(rdev
, p_dac
);
773 radeon_combios_get_tv_info(struct radeon_device
*rdev
)
775 struct drm_device
*dev
= rdev
->ddev
;
777 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
779 tv_info
= combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
781 if (RBIOS8(tv_info
+ 6) == 'T') {
782 switch (RBIOS8(tv_info
+ 7) & 0xf) {
784 tv_std
= TV_STD_NTSC
;
785 DRM_INFO("Default TV standard: NTSC\n");
789 DRM_INFO("Default TV standard: PAL\n");
792 tv_std
= TV_STD_PAL_M
;
793 DRM_INFO("Default TV standard: PAL-M\n");
796 tv_std
= TV_STD_PAL_60
;
797 DRM_INFO("Default TV standard: PAL-60\n");
800 tv_std
= TV_STD_NTSC_J
;
801 DRM_INFO("Default TV standard: NTSC-J\n");
804 tv_std
= TV_STD_SCART_PAL
;
805 DRM_INFO("Default TV standard: SCART-PAL\n");
808 tv_std
= TV_STD_NTSC
;
810 ("Unknown TV standard; defaulting to NTSC\n");
814 switch ((RBIOS8(tv_info
+ 9) >> 2) & 0x3) {
816 DRM_INFO("29.498928713 MHz TV ref clk\n");
819 DRM_INFO("28.636360000 MHz TV ref clk\n");
822 DRM_INFO("14.318180000 MHz TV ref clk\n");
825 DRM_INFO("27.000000000 MHz TV ref clk\n");
835 static const uint32_t default_tvdac_adj
[CHIP_LAST
] = {
836 0x00000000, /* r100 */
837 0x00280000, /* rv100 */
838 0x00000000, /* rs100 */
839 0x00880000, /* rv200 */
840 0x00000000, /* rs200 */
841 0x00000000, /* r200 */
842 0x00770000, /* rv250 */
843 0x00290000, /* rs300 */
844 0x00560000, /* rv280 */
845 0x00780000, /* r300 */
846 0x00770000, /* r350 */
847 0x00780000, /* rv350 */
848 0x00780000, /* rv380 */
849 0x01080000, /* r420 */
850 0x01080000, /* r423 */
851 0x01080000, /* rv410 */
852 0x00780000, /* rs400 */
853 0x00780000, /* rs480 */
856 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device
*rdev
,
857 struct radeon_encoder_tv_dac
*tv_dac
)
859 tv_dac
->ps2_tvdac_adj
= default_tvdac_adj
[rdev
->family
];
860 if ((rdev
->flags
& RADEON_IS_MOBILITY
) && (rdev
->family
== CHIP_RV250
))
861 tv_dac
->ps2_tvdac_adj
= 0x00880000;
862 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
863 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
867 struct radeon_encoder_tv_dac
*radeon_combios_get_tv_dac_info(struct
871 struct drm_device
*dev
= encoder
->base
.dev
;
872 struct radeon_device
*rdev
= dev
->dev_private
;
874 uint8_t rev
, bg
, dac
;
875 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
878 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
882 /* first check TV table */
883 dac_info
= combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
885 rev
= RBIOS8(dac_info
+ 0x3);
887 bg
= RBIOS8(dac_info
+ 0xc) & 0xf;
888 dac
= RBIOS8(dac_info
+ 0xd) & 0xf;
889 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
891 bg
= RBIOS8(dac_info
+ 0xe) & 0xf;
892 dac
= RBIOS8(dac_info
+ 0xf) & 0xf;
893 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
895 bg
= RBIOS8(dac_info
+ 0x10) & 0xf;
896 dac
= RBIOS8(dac_info
+ 0x11) & 0xf;
897 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
899 } else if (rev
> 1) {
900 bg
= RBIOS8(dac_info
+ 0xc) & 0xf;
901 dac
= (RBIOS8(dac_info
+ 0xc) >> 4) & 0xf;
902 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
904 bg
= RBIOS8(dac_info
+ 0xd) & 0xf;
905 dac
= (RBIOS8(dac_info
+ 0xd) >> 4) & 0xf;
906 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
908 bg
= RBIOS8(dac_info
+ 0xe) & 0xf;
909 dac
= (RBIOS8(dac_info
+ 0xe) >> 4) & 0xf;
910 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
913 tv_dac
->tv_std
= radeon_combios_get_tv_info(rdev
);
916 /* then check CRT table */
918 combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
920 rev
= RBIOS8(dac_info
) & 0x3;
922 bg
= RBIOS8(dac_info
+ 0x3) & 0xf;
923 dac
= (RBIOS8(dac_info
+ 0x3) >> 4) & 0xf;
924 tv_dac
->ps2_tvdac_adj
=
925 (bg
<< 16) | (dac
<< 20);
926 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
927 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
930 bg
= RBIOS8(dac_info
+ 0x4) & 0xf;
931 dac
= RBIOS8(dac_info
+ 0x5) & 0xf;
932 tv_dac
->ps2_tvdac_adj
=
933 (bg
<< 16) | (dac
<< 20);
934 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
935 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
939 DRM_INFO("No TV DAC info found in BIOS\n");
943 if (!found
) /* fallback to defaults */
944 radeon_legacy_get_tv_dac_info_from_table(rdev
, tv_dac
);
949 static struct radeon_encoder_lvds
*radeon_legacy_get_lvds_info_from_regs(struct
953 struct radeon_encoder_lvds
*lvds
= NULL
;
954 uint32_t fp_vert_stretch
, fp_horz_stretch
;
955 uint32_t ppll_div_sel
, ppll_val
;
956 uint32_t lvds_ss_gen_cntl
= RREG32(RADEON_LVDS_SS_GEN_CNTL
);
958 lvds
= kzalloc(sizeof(struct radeon_encoder_lvds
), GFP_KERNEL
);
963 fp_vert_stretch
= RREG32(RADEON_FP_VERT_STRETCH
);
964 fp_horz_stretch
= RREG32(RADEON_FP_HORZ_STRETCH
);
966 /* These should be fail-safe defaults, fingers crossed */
967 lvds
->panel_pwr_delay
= 200;
968 lvds
->panel_vcc_delay
= 2000;
970 lvds
->lvds_gen_cntl
= RREG32(RADEON_LVDS_GEN_CNTL
);
971 lvds
->panel_digon_delay
= (lvds_ss_gen_cntl
>> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT
) & 0xf;
972 lvds
->panel_blon_delay
= (lvds_ss_gen_cntl
>> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT
) & 0xf;
974 if (fp_vert_stretch
& RADEON_VERT_STRETCH_ENABLE
)
975 lvds
->native_mode
.vdisplay
=
976 ((fp_vert_stretch
& RADEON_VERT_PANEL_SIZE
) >>
977 RADEON_VERT_PANEL_SHIFT
) + 1;
979 lvds
->native_mode
.vdisplay
=
980 (RREG32(RADEON_CRTC_V_TOTAL_DISP
) >> 16) + 1;
982 if (fp_horz_stretch
& RADEON_HORZ_STRETCH_ENABLE
)
983 lvds
->native_mode
.hdisplay
=
984 (((fp_horz_stretch
& RADEON_HORZ_PANEL_SIZE
) >>
985 RADEON_HORZ_PANEL_SHIFT
) + 1) * 8;
987 lvds
->native_mode
.hdisplay
=
988 ((RREG32(RADEON_CRTC_H_TOTAL_DISP
) >> 16) + 1) * 8;
990 if ((lvds
->native_mode
.hdisplay
< 640) ||
991 (lvds
->native_mode
.vdisplay
< 480)) {
992 lvds
->native_mode
.hdisplay
= 640;
993 lvds
->native_mode
.vdisplay
= 480;
996 ppll_div_sel
= RREG8(RADEON_CLOCK_CNTL_INDEX
+ 1) & 0x3;
997 ppll_val
= RREG32_PLL(RADEON_PPLL_DIV_0
+ ppll_div_sel
);
998 if ((ppll_val
& 0x000707ff) == 0x1bb)
999 lvds
->use_bios_dividers
= false;
1001 lvds
->panel_ref_divider
=
1002 RREG32_PLL(RADEON_PPLL_REF_DIV
) & 0x3ff;
1003 lvds
->panel_post_divider
= (ppll_val
>> 16) & 0x7;
1004 lvds
->panel_fb_divider
= ppll_val
& 0x7ff;
1006 if ((lvds
->panel_ref_divider
!= 0) &&
1007 (lvds
->panel_fb_divider
> 3))
1008 lvds
->use_bios_dividers
= true;
1010 lvds
->panel_vcc_delay
= 200;
1012 DRM_INFO("Panel info derived from registers\n");
1013 DRM_INFO("Panel Size %dx%d\n", lvds
->native_mode
.hdisplay
,
1014 lvds
->native_mode
.vdisplay
);
1019 struct radeon_encoder_lvds
*radeon_combios_get_lvds_info(struct radeon_encoder
1022 struct drm_device
*dev
= encoder
->base
.dev
;
1023 struct radeon_device
*rdev
= dev
->dev_private
;
1025 uint32_t panel_setup
;
1028 struct radeon_encoder_lvds
*lvds
= NULL
;
1030 lcd_info
= combios_get_table_offset(dev
, COMBIOS_LCD_INFO_TABLE
);
1033 lvds
= kzalloc(sizeof(struct radeon_encoder_lvds
), GFP_KERNEL
);
1038 for (i
= 0; i
< 24; i
++)
1039 stmp
[i
] = RBIOS8(lcd_info
+ i
+ 1);
1042 DRM_INFO("Panel ID String: %s\n", stmp
);
1044 lvds
->native_mode
.hdisplay
= RBIOS16(lcd_info
+ 0x19);
1045 lvds
->native_mode
.vdisplay
= RBIOS16(lcd_info
+ 0x1b);
1047 DRM_INFO("Panel Size %dx%d\n", lvds
->native_mode
.hdisplay
,
1048 lvds
->native_mode
.vdisplay
);
1050 lvds
->panel_vcc_delay
= RBIOS16(lcd_info
+ 0x2c);
1051 lvds
->panel_vcc_delay
= min_t(u16
, lvds
->panel_vcc_delay
, 2000);
1053 lvds
->panel_pwr_delay
= RBIOS8(lcd_info
+ 0x24);
1054 lvds
->panel_digon_delay
= RBIOS16(lcd_info
+ 0x38) & 0xf;
1055 lvds
->panel_blon_delay
= (RBIOS16(lcd_info
+ 0x38) >> 4) & 0xf;
1057 lvds
->panel_ref_divider
= RBIOS16(lcd_info
+ 0x2e);
1058 lvds
->panel_post_divider
= RBIOS8(lcd_info
+ 0x30);
1059 lvds
->panel_fb_divider
= RBIOS16(lcd_info
+ 0x31);
1060 if ((lvds
->panel_ref_divider
!= 0) &&
1061 (lvds
->panel_fb_divider
> 3))
1062 lvds
->use_bios_dividers
= true;
1064 panel_setup
= RBIOS32(lcd_info
+ 0x39);
1065 lvds
->lvds_gen_cntl
= 0xff00;
1066 if (panel_setup
& 0x1)
1067 lvds
->lvds_gen_cntl
|= RADEON_LVDS_PANEL_FORMAT
;
1069 if ((panel_setup
>> 4) & 0x1)
1070 lvds
->lvds_gen_cntl
|= RADEON_LVDS_PANEL_TYPE
;
1072 switch ((panel_setup
>> 8) & 0x7) {
1074 lvds
->lvds_gen_cntl
|= RADEON_LVDS_NO_FM
;
1077 lvds
->lvds_gen_cntl
|= RADEON_LVDS_2_GREY
;
1080 lvds
->lvds_gen_cntl
|= RADEON_LVDS_4_GREY
;
1086 if ((panel_setup
>> 16) & 0x1)
1087 lvds
->lvds_gen_cntl
|= RADEON_LVDS_FP_POL_LOW
;
1089 if ((panel_setup
>> 17) & 0x1)
1090 lvds
->lvds_gen_cntl
|= RADEON_LVDS_LP_POL_LOW
;
1092 if ((panel_setup
>> 18) & 0x1)
1093 lvds
->lvds_gen_cntl
|= RADEON_LVDS_DTM_POL_LOW
;
1095 if ((panel_setup
>> 23) & 0x1)
1096 lvds
->lvds_gen_cntl
|= RADEON_LVDS_BL_CLK_SEL
;
1098 lvds
->lvds_gen_cntl
|= (panel_setup
& 0xf0000000);
1100 for (i
= 0; i
< 32; i
++) {
1101 tmp
= RBIOS16(lcd_info
+ 64 + i
* 2);
1105 if ((RBIOS16(tmp
) == lvds
->native_mode
.hdisplay
) &&
1106 (RBIOS16(tmp
+ 2) ==
1107 lvds
->native_mode
.vdisplay
)) {
1108 lvds
->native_mode
.htotal
= RBIOS16(tmp
+ 17) * 8;
1109 lvds
->native_mode
.hsync_start
= RBIOS16(tmp
+ 21) * 8;
1110 lvds
->native_mode
.hsync_end
= (RBIOS8(tmp
+ 23) +
1111 RBIOS16(tmp
+ 21)) * 8;
1113 lvds
->native_mode
.vtotal
= RBIOS16(tmp
+ 24);
1114 lvds
->native_mode
.vsync_start
= RBIOS16(tmp
+ 28) & 0x7ff;
1115 lvds
->native_mode
.vsync_end
=
1116 ((RBIOS16(tmp
+ 28) & 0xf800) >> 11) +
1117 (RBIOS16(tmp
+ 28) & 0x7ff);
1119 lvds
->native_mode
.clock
= RBIOS16(tmp
+ 9) * 10;
1120 lvds
->native_mode
.flags
= 0;
1121 /* set crtc values */
1122 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1127 DRM_INFO("No panel info found in BIOS\n");
1128 lvds
= radeon_legacy_get_lvds_info_from_regs(rdev
);
1132 encoder
->native_mode
= lvds
->native_mode
;
1136 static const struct radeon_tmds_pll default_tmds_pll
[CHIP_LAST
][4] = {
1137 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1138 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1139 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1140 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1141 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1142 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1143 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1144 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1145 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1146 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1147 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1148 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1149 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1150 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1151 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1152 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1153 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1154 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1157 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder
*encoder
,
1158 struct radeon_encoder_int_tmds
*tmds
)
1160 struct drm_device
*dev
= encoder
->base
.dev
;
1161 struct radeon_device
*rdev
= dev
->dev_private
;
1164 for (i
= 0; i
< 4; i
++) {
1165 tmds
->tmds_pll
[i
].value
=
1166 default_tmds_pll
[rdev
->family
][i
].value
;
1167 tmds
->tmds_pll
[i
].freq
= default_tmds_pll
[rdev
->family
][i
].freq
;
1173 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder
*encoder
,
1174 struct radeon_encoder_int_tmds
*tmds
)
1176 struct drm_device
*dev
= encoder
->base
.dev
;
1177 struct radeon_device
*rdev
= dev
->dev_private
;
1182 tmds_info
= combios_get_table_offset(dev
, COMBIOS_DFP_INFO_TABLE
);
1185 ver
= RBIOS8(tmds_info
);
1186 DRM_INFO("DFP table revision: %d\n", ver
);
1188 n
= RBIOS8(tmds_info
+ 5) + 1;
1191 for (i
= 0; i
< n
; i
++) {
1192 tmds
->tmds_pll
[i
].value
=
1193 RBIOS32(tmds_info
+ i
* 10 + 0x08);
1194 tmds
->tmds_pll
[i
].freq
=
1195 RBIOS16(tmds_info
+ i
* 10 + 0x10);
1196 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1197 tmds
->tmds_pll
[i
].freq
,
1198 tmds
->tmds_pll
[i
].value
);
1200 } else if (ver
== 4) {
1202 n
= RBIOS8(tmds_info
+ 5) + 1;
1205 for (i
= 0; i
< n
; i
++) {
1206 tmds
->tmds_pll
[i
].value
=
1207 RBIOS32(tmds_info
+ stride
+ 0x08);
1208 tmds
->tmds_pll
[i
].freq
=
1209 RBIOS16(tmds_info
+ stride
+ 0x10);
1214 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1215 tmds
->tmds_pll
[i
].freq
,
1216 tmds
->tmds_pll
[i
].value
);
1220 DRM_INFO("No TMDS info found in BIOS\n");
1226 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder
*encoder
,
1227 struct radeon_encoder_ext_tmds
*tmds
)
1229 struct drm_device
*dev
= encoder
->base
.dev
;
1230 struct radeon_device
*rdev
= dev
->dev_private
;
1231 struct radeon_i2c_bus_rec i2c_bus
;
1233 /* default for macs */
1234 i2c_bus
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_MONID
);
1235 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1237 /* XXX some macs have duallink chips */
1238 switch (rdev
->mode_info
.connector_table
) {
1239 case CT_POWERBOOK_EXTERNAL
:
1240 case CT_MINI_EXTERNAL
:
1242 tmds
->dvo_chip
= DVO_SIL164
;
1243 tmds
->slave_addr
= 0x70 >> 1; /* 7 bit addressing */
1250 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder
*encoder
,
1251 struct radeon_encoder_ext_tmds
*tmds
)
1253 struct drm_device
*dev
= encoder
->base
.dev
;
1254 struct radeon_device
*rdev
= dev
->dev_private
;
1256 uint8_t ver
, id
, blocks
, clk
, data
;
1258 enum radeon_combios_ddc gpio
;
1259 struct radeon_i2c_bus_rec i2c_bus
;
1261 tmds
->i2c_bus
= NULL
;
1262 if (rdev
->flags
& RADEON_IS_IGP
) {
1263 offset
= combios_get_table_offset(dev
, COMBIOS_I2C_INFO_TABLE
);
1265 ver
= RBIOS8(offset
);
1266 DRM_INFO("GPIO Table revision: %d\n", ver
);
1267 blocks
= RBIOS8(offset
+ 2);
1268 for (i
= 0; i
< blocks
; i
++) {
1269 id
= RBIOS8(offset
+ 3 + (i
* 5) + 0);
1271 clk
= RBIOS8(offset
+ 3 + (i
* 5) + 3);
1272 data
= RBIOS8(offset
+ 3 + (i
* 5) + 4);
1273 i2c_bus
.valid
= true;
1274 i2c_bus
.mask_clk_mask
= (1 << clk
);
1275 i2c_bus
.mask_data_mask
= (1 << data
);
1276 i2c_bus
.a_clk_mask
= (1 << clk
);
1277 i2c_bus
.a_data_mask
= (1 << data
);
1278 i2c_bus
.en_clk_mask
= (1 << clk
);
1279 i2c_bus
.en_data_mask
= (1 << data
);
1280 i2c_bus
.y_clk_mask
= (1 << clk
);
1281 i2c_bus
.y_data_mask
= (1 << data
);
1282 i2c_bus
.mask_clk_reg
= RADEON_GPIOPAD_MASK
;
1283 i2c_bus
.mask_data_reg
= RADEON_GPIOPAD_MASK
;
1284 i2c_bus
.a_clk_reg
= RADEON_GPIOPAD_A
;
1285 i2c_bus
.a_data_reg
= RADEON_GPIOPAD_A
;
1286 i2c_bus
.en_clk_reg
= RADEON_GPIOPAD_EN
;
1287 i2c_bus
.en_data_reg
= RADEON_GPIOPAD_EN
;
1288 i2c_bus
.y_clk_reg
= RADEON_GPIOPAD_Y
;
1289 i2c_bus
.y_data_reg
= RADEON_GPIOPAD_Y
;
1290 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1291 tmds
->dvo_chip
= DVO_SIL164
;
1292 tmds
->slave_addr
= 0x70 >> 1; /* 7 bit addressing */
1298 offset
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
1300 ver
= RBIOS8(offset
);
1301 DRM_INFO("External TMDS Table revision: %d\n", ver
);
1302 tmds
->slave_addr
= RBIOS8(offset
+ 4 + 2);
1303 tmds
->slave_addr
>>= 1; /* 7 bit addressing */
1304 gpio
= RBIOS8(offset
+ 4 + 3);
1307 i2c_bus
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_MONID
);
1308 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1311 i2c_bus
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1312 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1315 i2c_bus
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1316 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1319 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1320 if (rdev
->family
>= CHIP_R300
)
1321 i2c_bus
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_MONID
);
1323 i2c_bus
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_CRT2_DDC
);
1324 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1326 case DDC_LCD
: /* MM i2c */
1327 i2c_bus
.valid
= true;
1328 i2c_bus
.hw_capable
= true;
1329 i2c_bus
.mm_i2c
= true;
1330 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1333 DRM_ERROR("Unsupported gpio %d\n", gpio
);
1339 if (!tmds
->i2c_bus
) {
1340 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1347 bool radeon_get_legacy_connector_info_from_table(struct drm_device
*dev
)
1349 struct radeon_device
*rdev
= dev
->dev_private
;
1350 struct radeon_i2c_bus_rec ddc_i2c
;
1351 struct radeon_hpd hpd
;
1353 rdev
->mode_info
.connector_table
= radeon_connector_table
;
1354 if (rdev
->mode_info
.connector_table
== CT_NONE
) {
1355 #ifdef CONFIG_PPC_PMAC
1356 if (of_machine_is_compatible("PowerBook3,3")) {
1357 /* powerbook with VGA */
1358 rdev
->mode_info
.connector_table
= CT_POWERBOOK_VGA
;
1359 } else if (of_machine_is_compatible("PowerBook3,4") ||
1360 of_machine_is_compatible("PowerBook3,5")) {
1361 /* powerbook with internal tmds */
1362 rdev
->mode_info
.connector_table
= CT_POWERBOOK_INTERNAL
;
1363 } else if (of_machine_is_compatible("PowerBook5,1") ||
1364 of_machine_is_compatible("PowerBook5,2") ||
1365 of_machine_is_compatible("PowerBook5,3") ||
1366 of_machine_is_compatible("PowerBook5,4") ||
1367 of_machine_is_compatible("PowerBook5,5")) {
1368 /* powerbook with external single link tmds (sil164) */
1369 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1370 } else if (of_machine_is_compatible("PowerBook5,6")) {
1371 /* powerbook with external dual or single link tmds */
1372 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1373 } else if (of_machine_is_compatible("PowerBook5,7") ||
1374 of_machine_is_compatible("PowerBook5,8") ||
1375 of_machine_is_compatible("PowerBook5,9")) {
1376 /* PowerBook6,2 ? */
1377 /* powerbook with external dual link tmds (sil1178?) */
1378 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1379 } else if (of_machine_is_compatible("PowerBook4,1") ||
1380 of_machine_is_compatible("PowerBook4,2") ||
1381 of_machine_is_compatible("PowerBook4,3") ||
1382 of_machine_is_compatible("PowerBook6,3") ||
1383 of_machine_is_compatible("PowerBook6,5") ||
1384 of_machine_is_compatible("PowerBook6,7")) {
1386 rdev
->mode_info
.connector_table
= CT_IBOOK
;
1387 } else if (of_machine_is_compatible("PowerMac4,4")) {
1389 rdev
->mode_info
.connector_table
= CT_EMAC
;
1390 } else if (of_machine_is_compatible("PowerMac10,1")) {
1391 /* mini with internal tmds */
1392 rdev
->mode_info
.connector_table
= CT_MINI_INTERNAL
;
1393 } else if (of_machine_is_compatible("PowerMac10,2")) {
1394 /* mini with external tmds */
1395 rdev
->mode_info
.connector_table
= CT_MINI_EXTERNAL
;
1396 } else if (of_machine_is_compatible("PowerMac12,1")) {
1398 /* imac g5 isight */
1399 rdev
->mode_info
.connector_table
= CT_IMAC_G5_ISIGHT
;
1401 #endif /* CONFIG_PPC_PMAC */
1402 rdev
->mode_info
.connector_table
= CT_GENERIC
;
1405 switch (rdev
->mode_info
.connector_table
) {
1407 DRM_INFO("Connector Table: %d (generic)\n",
1408 rdev
->mode_info
.connector_table
);
1409 /* these are the most common settings */
1410 if (rdev
->flags
& RADEON_SINGLE_CRTC
) {
1411 /* VGA - primary dac */
1412 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1413 hpd
.hpd
= RADEON_HPD_NONE
;
1414 radeon_add_legacy_encoder(dev
,
1415 radeon_get_encoder_id(dev
,
1416 ATOM_DEVICE_CRT1_SUPPORT
,
1418 ATOM_DEVICE_CRT1_SUPPORT
);
1419 radeon_add_legacy_connector(dev
, 0,
1420 ATOM_DEVICE_CRT1_SUPPORT
,
1421 DRM_MODE_CONNECTOR_VGA
,
1423 CONNECTOR_OBJECT_ID_VGA
,
1425 } else if (rdev
->flags
& RADEON_IS_MOBILITY
) {
1427 ddc_i2c
= combios_setup_i2c_bus(rdev
, 0);
1428 hpd
.hpd
= RADEON_HPD_NONE
;
1429 radeon_add_legacy_encoder(dev
,
1430 radeon_get_encoder_id(dev
,
1431 ATOM_DEVICE_LCD1_SUPPORT
,
1433 ATOM_DEVICE_LCD1_SUPPORT
);
1434 radeon_add_legacy_connector(dev
, 0,
1435 ATOM_DEVICE_LCD1_SUPPORT
,
1436 DRM_MODE_CONNECTOR_LVDS
,
1438 CONNECTOR_OBJECT_ID_LVDS
,
1441 /* VGA - primary dac */
1442 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1443 hpd
.hpd
= RADEON_HPD_NONE
;
1444 radeon_add_legacy_encoder(dev
,
1445 radeon_get_encoder_id(dev
,
1446 ATOM_DEVICE_CRT1_SUPPORT
,
1448 ATOM_DEVICE_CRT1_SUPPORT
);
1449 radeon_add_legacy_connector(dev
, 1,
1450 ATOM_DEVICE_CRT1_SUPPORT
,
1451 DRM_MODE_CONNECTOR_VGA
,
1453 CONNECTOR_OBJECT_ID_VGA
,
1456 /* DVI-I - tv dac, int tmds */
1457 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1458 hpd
.hpd
= RADEON_HPD_1
;
1459 radeon_add_legacy_encoder(dev
,
1460 radeon_get_encoder_id(dev
,
1461 ATOM_DEVICE_DFP1_SUPPORT
,
1463 ATOM_DEVICE_DFP1_SUPPORT
);
1464 radeon_add_legacy_encoder(dev
,
1465 radeon_get_encoder_id(dev
,
1466 ATOM_DEVICE_CRT2_SUPPORT
,
1468 ATOM_DEVICE_CRT2_SUPPORT
);
1469 radeon_add_legacy_connector(dev
, 0,
1470 ATOM_DEVICE_DFP1_SUPPORT
|
1471 ATOM_DEVICE_CRT2_SUPPORT
,
1472 DRM_MODE_CONNECTOR_DVII
,
1474 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1477 /* VGA - primary dac */
1478 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1479 hpd
.hpd
= RADEON_HPD_NONE
;
1480 radeon_add_legacy_encoder(dev
,
1481 radeon_get_encoder_id(dev
,
1482 ATOM_DEVICE_CRT1_SUPPORT
,
1484 ATOM_DEVICE_CRT1_SUPPORT
);
1485 radeon_add_legacy_connector(dev
, 1,
1486 ATOM_DEVICE_CRT1_SUPPORT
,
1487 DRM_MODE_CONNECTOR_VGA
,
1489 CONNECTOR_OBJECT_ID_VGA
,
1493 if (rdev
->family
!= CHIP_R100
&& rdev
->family
!= CHIP_R200
) {
1495 ddc_i2c
.valid
= false;
1496 hpd
.hpd
= RADEON_HPD_NONE
;
1497 radeon_add_legacy_encoder(dev
,
1498 radeon_get_encoder_id(dev
,
1499 ATOM_DEVICE_TV1_SUPPORT
,
1501 ATOM_DEVICE_TV1_SUPPORT
);
1502 radeon_add_legacy_connector(dev
, 2,
1503 ATOM_DEVICE_TV1_SUPPORT
,
1504 DRM_MODE_CONNECTOR_SVIDEO
,
1506 CONNECTOR_OBJECT_ID_SVIDEO
,
1511 DRM_INFO("Connector Table: %d (ibook)\n",
1512 rdev
->mode_info
.connector_table
);
1514 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1515 hpd
.hpd
= RADEON_HPD_NONE
;
1516 radeon_add_legacy_encoder(dev
,
1517 radeon_get_encoder_id(dev
,
1518 ATOM_DEVICE_LCD1_SUPPORT
,
1520 ATOM_DEVICE_LCD1_SUPPORT
);
1521 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1522 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1523 CONNECTOR_OBJECT_ID_LVDS
,
1526 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1527 hpd
.hpd
= RADEON_HPD_NONE
;
1528 radeon_add_legacy_encoder(dev
,
1529 radeon_get_encoder_id(dev
,
1530 ATOM_DEVICE_CRT2_SUPPORT
,
1532 ATOM_DEVICE_CRT2_SUPPORT
);
1533 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1534 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1535 CONNECTOR_OBJECT_ID_VGA
,
1538 ddc_i2c
.valid
= false;
1539 hpd
.hpd
= RADEON_HPD_NONE
;
1540 radeon_add_legacy_encoder(dev
,
1541 radeon_get_encoder_id(dev
,
1542 ATOM_DEVICE_TV1_SUPPORT
,
1544 ATOM_DEVICE_TV1_SUPPORT
);
1545 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1546 DRM_MODE_CONNECTOR_SVIDEO
,
1548 CONNECTOR_OBJECT_ID_SVIDEO
,
1551 case CT_POWERBOOK_EXTERNAL
:
1552 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1553 rdev
->mode_info
.connector_table
);
1555 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1556 hpd
.hpd
= RADEON_HPD_NONE
;
1557 radeon_add_legacy_encoder(dev
,
1558 radeon_get_encoder_id(dev
,
1559 ATOM_DEVICE_LCD1_SUPPORT
,
1561 ATOM_DEVICE_LCD1_SUPPORT
);
1562 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1563 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1564 CONNECTOR_OBJECT_ID_LVDS
,
1566 /* DVI-I - primary dac, ext tmds */
1567 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1568 hpd
.hpd
= RADEON_HPD_2
; /* ??? */
1569 radeon_add_legacy_encoder(dev
,
1570 radeon_get_encoder_id(dev
,
1571 ATOM_DEVICE_DFP2_SUPPORT
,
1573 ATOM_DEVICE_DFP2_SUPPORT
);
1574 radeon_add_legacy_encoder(dev
,
1575 radeon_get_encoder_id(dev
,
1576 ATOM_DEVICE_CRT1_SUPPORT
,
1578 ATOM_DEVICE_CRT1_SUPPORT
);
1579 /* XXX some are SL */
1580 radeon_add_legacy_connector(dev
, 1,
1581 ATOM_DEVICE_DFP2_SUPPORT
|
1582 ATOM_DEVICE_CRT1_SUPPORT
,
1583 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1584 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
,
1587 ddc_i2c
.valid
= false;
1588 hpd
.hpd
= RADEON_HPD_NONE
;
1589 radeon_add_legacy_encoder(dev
,
1590 radeon_get_encoder_id(dev
,
1591 ATOM_DEVICE_TV1_SUPPORT
,
1593 ATOM_DEVICE_TV1_SUPPORT
);
1594 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1595 DRM_MODE_CONNECTOR_SVIDEO
,
1597 CONNECTOR_OBJECT_ID_SVIDEO
,
1600 case CT_POWERBOOK_INTERNAL
:
1601 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1602 rdev
->mode_info
.connector_table
);
1604 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1605 hpd
.hpd
= RADEON_HPD_NONE
;
1606 radeon_add_legacy_encoder(dev
,
1607 radeon_get_encoder_id(dev
,
1608 ATOM_DEVICE_LCD1_SUPPORT
,
1610 ATOM_DEVICE_LCD1_SUPPORT
);
1611 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1612 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1613 CONNECTOR_OBJECT_ID_LVDS
,
1615 /* DVI-I - primary dac, int tmds */
1616 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1617 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
1618 radeon_add_legacy_encoder(dev
,
1619 radeon_get_encoder_id(dev
,
1620 ATOM_DEVICE_DFP1_SUPPORT
,
1622 ATOM_DEVICE_DFP1_SUPPORT
);
1623 radeon_add_legacy_encoder(dev
,
1624 radeon_get_encoder_id(dev
,
1625 ATOM_DEVICE_CRT1_SUPPORT
,
1627 ATOM_DEVICE_CRT1_SUPPORT
);
1628 radeon_add_legacy_connector(dev
, 1,
1629 ATOM_DEVICE_DFP1_SUPPORT
|
1630 ATOM_DEVICE_CRT1_SUPPORT
,
1631 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1632 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1635 ddc_i2c
.valid
= false;
1636 hpd
.hpd
= RADEON_HPD_NONE
;
1637 radeon_add_legacy_encoder(dev
,
1638 radeon_get_encoder_id(dev
,
1639 ATOM_DEVICE_TV1_SUPPORT
,
1641 ATOM_DEVICE_TV1_SUPPORT
);
1642 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1643 DRM_MODE_CONNECTOR_SVIDEO
,
1645 CONNECTOR_OBJECT_ID_SVIDEO
,
1648 case CT_POWERBOOK_VGA
:
1649 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1650 rdev
->mode_info
.connector_table
);
1652 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1653 hpd
.hpd
= RADEON_HPD_NONE
;
1654 radeon_add_legacy_encoder(dev
,
1655 radeon_get_encoder_id(dev
,
1656 ATOM_DEVICE_LCD1_SUPPORT
,
1658 ATOM_DEVICE_LCD1_SUPPORT
);
1659 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1660 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1661 CONNECTOR_OBJECT_ID_LVDS
,
1663 /* VGA - primary dac */
1664 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1665 hpd
.hpd
= RADEON_HPD_NONE
;
1666 radeon_add_legacy_encoder(dev
,
1667 radeon_get_encoder_id(dev
,
1668 ATOM_DEVICE_CRT1_SUPPORT
,
1670 ATOM_DEVICE_CRT1_SUPPORT
);
1671 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT1_SUPPORT
,
1672 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1673 CONNECTOR_OBJECT_ID_VGA
,
1676 ddc_i2c
.valid
= false;
1677 hpd
.hpd
= RADEON_HPD_NONE
;
1678 radeon_add_legacy_encoder(dev
,
1679 radeon_get_encoder_id(dev
,
1680 ATOM_DEVICE_TV1_SUPPORT
,
1682 ATOM_DEVICE_TV1_SUPPORT
);
1683 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1684 DRM_MODE_CONNECTOR_SVIDEO
,
1686 CONNECTOR_OBJECT_ID_SVIDEO
,
1689 case CT_MINI_EXTERNAL
:
1690 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1691 rdev
->mode_info
.connector_table
);
1692 /* DVI-I - tv dac, ext tmds */
1693 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_CRT2_DDC
);
1694 hpd
.hpd
= RADEON_HPD_2
; /* ??? */
1695 radeon_add_legacy_encoder(dev
,
1696 radeon_get_encoder_id(dev
,
1697 ATOM_DEVICE_DFP2_SUPPORT
,
1699 ATOM_DEVICE_DFP2_SUPPORT
);
1700 radeon_add_legacy_encoder(dev
,
1701 radeon_get_encoder_id(dev
,
1702 ATOM_DEVICE_CRT2_SUPPORT
,
1704 ATOM_DEVICE_CRT2_SUPPORT
);
1705 /* XXX are any DL? */
1706 radeon_add_legacy_connector(dev
, 0,
1707 ATOM_DEVICE_DFP2_SUPPORT
|
1708 ATOM_DEVICE_CRT2_SUPPORT
,
1709 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1710 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1713 ddc_i2c
.valid
= false;
1714 hpd
.hpd
= RADEON_HPD_NONE
;
1715 radeon_add_legacy_encoder(dev
,
1716 radeon_get_encoder_id(dev
,
1717 ATOM_DEVICE_TV1_SUPPORT
,
1719 ATOM_DEVICE_TV1_SUPPORT
);
1720 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_TV1_SUPPORT
,
1721 DRM_MODE_CONNECTOR_SVIDEO
,
1723 CONNECTOR_OBJECT_ID_SVIDEO
,
1726 case CT_MINI_INTERNAL
:
1727 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1728 rdev
->mode_info
.connector_table
);
1729 /* DVI-I - tv dac, int tmds */
1730 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_CRT2_DDC
);
1731 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
1732 radeon_add_legacy_encoder(dev
,
1733 radeon_get_encoder_id(dev
,
1734 ATOM_DEVICE_DFP1_SUPPORT
,
1736 ATOM_DEVICE_DFP1_SUPPORT
);
1737 radeon_add_legacy_encoder(dev
,
1738 radeon_get_encoder_id(dev
,
1739 ATOM_DEVICE_CRT2_SUPPORT
,
1741 ATOM_DEVICE_CRT2_SUPPORT
);
1742 radeon_add_legacy_connector(dev
, 0,
1743 ATOM_DEVICE_DFP1_SUPPORT
|
1744 ATOM_DEVICE_CRT2_SUPPORT
,
1745 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1746 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1749 ddc_i2c
.valid
= false;
1750 hpd
.hpd
= RADEON_HPD_NONE
;
1751 radeon_add_legacy_encoder(dev
,
1752 radeon_get_encoder_id(dev
,
1753 ATOM_DEVICE_TV1_SUPPORT
,
1755 ATOM_DEVICE_TV1_SUPPORT
);
1756 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_TV1_SUPPORT
,
1757 DRM_MODE_CONNECTOR_SVIDEO
,
1759 CONNECTOR_OBJECT_ID_SVIDEO
,
1762 case CT_IMAC_G5_ISIGHT
:
1763 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1764 rdev
->mode_info
.connector_table
);
1765 /* DVI-D - int tmds */
1766 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_MONID
);
1767 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
1768 radeon_add_legacy_encoder(dev
,
1769 radeon_get_encoder_id(dev
,
1770 ATOM_DEVICE_DFP1_SUPPORT
,
1772 ATOM_DEVICE_DFP1_SUPPORT
);
1773 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_DFP1_SUPPORT
,
1774 DRM_MODE_CONNECTOR_DVID
, &ddc_i2c
,
1775 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
,
1778 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1779 hpd
.hpd
= RADEON_HPD_NONE
;
1780 radeon_add_legacy_encoder(dev
,
1781 radeon_get_encoder_id(dev
,
1782 ATOM_DEVICE_CRT2_SUPPORT
,
1784 ATOM_DEVICE_CRT2_SUPPORT
);
1785 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1786 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1787 CONNECTOR_OBJECT_ID_VGA
,
1790 ddc_i2c
.valid
= false;
1791 hpd
.hpd
= RADEON_HPD_NONE
;
1792 radeon_add_legacy_encoder(dev
,
1793 radeon_get_encoder_id(dev
,
1794 ATOM_DEVICE_TV1_SUPPORT
,
1796 ATOM_DEVICE_TV1_SUPPORT
);
1797 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1798 DRM_MODE_CONNECTOR_SVIDEO
,
1800 CONNECTOR_OBJECT_ID_SVIDEO
,
1804 DRM_INFO("Connector Table: %d (emac)\n",
1805 rdev
->mode_info
.connector_table
);
1806 /* VGA - primary dac */
1807 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1808 hpd
.hpd
= RADEON_HPD_NONE
;
1809 radeon_add_legacy_encoder(dev
,
1810 radeon_get_encoder_id(dev
,
1811 ATOM_DEVICE_CRT1_SUPPORT
,
1813 ATOM_DEVICE_CRT1_SUPPORT
);
1814 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_CRT1_SUPPORT
,
1815 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1816 CONNECTOR_OBJECT_ID_VGA
,
1819 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_CRT2_DDC
);
1820 hpd
.hpd
= RADEON_HPD_NONE
;
1821 radeon_add_legacy_encoder(dev
,
1822 radeon_get_encoder_id(dev
,
1823 ATOM_DEVICE_CRT2_SUPPORT
,
1825 ATOM_DEVICE_CRT2_SUPPORT
);
1826 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1827 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1828 CONNECTOR_OBJECT_ID_VGA
,
1831 ddc_i2c
.valid
= false;
1832 hpd
.hpd
= RADEON_HPD_NONE
;
1833 radeon_add_legacy_encoder(dev
,
1834 radeon_get_encoder_id(dev
,
1835 ATOM_DEVICE_TV1_SUPPORT
,
1837 ATOM_DEVICE_TV1_SUPPORT
);
1838 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1839 DRM_MODE_CONNECTOR_SVIDEO
,
1841 CONNECTOR_OBJECT_ID_SVIDEO
,
1845 DRM_INFO("Connector table: %d (invalid)\n",
1846 rdev
->mode_info
.connector_table
);
1850 radeon_link_encoder_connector(dev
);
1855 static bool radeon_apply_legacy_quirks(struct drm_device
*dev
,
1857 enum radeon_combios_connector
1859 struct radeon_i2c_bus_rec
*ddc_i2c
,
1860 struct radeon_hpd
*hpd
)
1862 struct radeon_device
*rdev
= dev
->dev_private
;
1864 /* XPRESS DDC quirks */
1865 if ((rdev
->family
== CHIP_RS400
||
1866 rdev
->family
== CHIP_RS480
) &&
1867 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_CRT2_DDC
)
1868 *ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_MONID
);
1869 else if ((rdev
->family
== CHIP_RS400
||
1870 rdev
->family
== CHIP_RS480
) &&
1871 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_MONID
) {
1872 *ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIOPAD_MASK
);
1873 ddc_i2c
->mask_clk_mask
= (0x20 << 8);
1874 ddc_i2c
->mask_data_mask
= 0x80;
1875 ddc_i2c
->a_clk_mask
= (0x20 << 8);
1876 ddc_i2c
->a_data_mask
= 0x80;
1877 ddc_i2c
->en_clk_mask
= (0x20 << 8);
1878 ddc_i2c
->en_data_mask
= 0x80;
1879 ddc_i2c
->y_clk_mask
= (0x20 << 8);
1880 ddc_i2c
->y_data_mask
= 0x80;
1883 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1884 if ((rdev
->family
>= CHIP_R300
) &&
1885 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_CRT2_DDC
)
1886 *ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1888 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1889 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1890 if (dev
->pdev
->device
== 0x515e &&
1891 dev
->pdev
->subsystem_vendor
== 0x1014) {
1892 if (*legacy_connector
== CONNECTOR_CRT_LEGACY
&&
1893 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_CRT2_DDC
)
1897 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1898 if (dev
->pdev
->device
== 0x5159 &&
1899 dev
->pdev
->subsystem_vendor
== 0x1002 &&
1900 dev
->pdev
->subsystem_device
== 0x013a) {
1901 if (*legacy_connector
== CONNECTOR_DVI_I_LEGACY
)
1902 *legacy_connector
= CONNECTOR_CRT_LEGACY
;
1906 /* X300 card with extra non-existent DVI port */
1907 if (dev
->pdev
->device
== 0x5B60 &&
1908 dev
->pdev
->subsystem_vendor
== 0x17af &&
1909 dev
->pdev
->subsystem_device
== 0x201e && bios_index
== 2) {
1910 if (*legacy_connector
== CONNECTOR_DVI_I_LEGACY
)
1917 static bool radeon_apply_legacy_tv_quirks(struct drm_device
*dev
)
1919 /* Acer 5102 has non-existent TV port */
1920 if (dev
->pdev
->device
== 0x5975 &&
1921 dev
->pdev
->subsystem_vendor
== 0x1025 &&
1922 dev
->pdev
->subsystem_device
== 0x009f)
1925 /* HP dc5750 has non-existent TV port */
1926 if (dev
->pdev
->device
== 0x5974 &&
1927 dev
->pdev
->subsystem_vendor
== 0x103c &&
1928 dev
->pdev
->subsystem_device
== 0x280a)
1931 /* MSI S270 has non-existent TV port */
1932 if (dev
->pdev
->device
== 0x5955 &&
1933 dev
->pdev
->subsystem_vendor
== 0x1462 &&
1934 dev
->pdev
->subsystem_device
== 0x0131)
1940 static uint16_t combios_check_dl_dvi(struct drm_device
*dev
, int is_dvi_d
)
1942 struct radeon_device
*rdev
= dev
->dev_private
;
1943 uint32_t ext_tmds_info
;
1945 if (rdev
->flags
& RADEON_IS_IGP
) {
1947 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
1949 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
1951 ext_tmds_info
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
1952 if (ext_tmds_info
) {
1953 uint8_t rev
= RBIOS8(ext_tmds_info
);
1954 uint8_t flags
= RBIOS8(ext_tmds_info
+ 4 + 5);
1957 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
1959 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
1963 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
1965 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
1970 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
1972 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
1975 bool radeon_get_legacy_connector_info_from_bios(struct drm_device
*dev
)
1977 struct radeon_device
*rdev
= dev
->dev_private
;
1978 uint32_t conn_info
, entry
, devices
;
1979 uint16_t tmp
, connector_object_id
;
1980 enum radeon_combios_ddc ddc_type
;
1981 enum radeon_combios_connector connector
;
1983 struct radeon_i2c_bus_rec ddc_i2c
;
1984 struct radeon_hpd hpd
;
1986 conn_info
= combios_get_table_offset(dev
, COMBIOS_CONNECTOR_INFO_TABLE
);
1988 for (i
= 0; i
< 4; i
++) {
1989 entry
= conn_info
+ 2 + i
* 2;
1991 if (!RBIOS16(entry
))
1994 tmp
= RBIOS16(entry
);
1996 connector
= (tmp
>> 12) & 0xf;
1998 ddc_type
= (tmp
>> 8) & 0xf;
2002 combios_setup_i2c_bus(rdev
, RADEON_GPIO_MONID
);
2006 combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
2010 combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
2014 combios_setup_i2c_bus(rdev
, RADEON_GPIO_CRT2_DDC
);
2020 switch (connector
) {
2021 case CONNECTOR_PROPRIETARY_LEGACY
:
2022 case CONNECTOR_DVI_I_LEGACY
:
2023 case CONNECTOR_DVI_D_LEGACY
:
2024 if ((tmp
>> 4) & 0x1)
2025 hpd
.hpd
= RADEON_HPD_2
;
2027 hpd
.hpd
= RADEON_HPD_1
;
2030 hpd
.hpd
= RADEON_HPD_NONE
;
2034 if (!radeon_apply_legacy_quirks(dev
, i
, &connector
,
2038 switch (connector
) {
2039 case CONNECTOR_PROPRIETARY_LEGACY
:
2040 if ((tmp
>> 4) & 0x1)
2041 devices
= ATOM_DEVICE_DFP2_SUPPORT
;
2043 devices
= ATOM_DEVICE_DFP1_SUPPORT
;
2044 radeon_add_legacy_encoder(dev
,
2045 radeon_get_encoder_id
2048 radeon_add_legacy_connector(dev
, i
, devices
,
2049 legacy_connector_convert
2052 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
,
2055 case CONNECTOR_CRT_LEGACY
:
2057 devices
= ATOM_DEVICE_CRT2_SUPPORT
;
2058 radeon_add_legacy_encoder(dev
,
2059 radeon_get_encoder_id
2061 ATOM_DEVICE_CRT2_SUPPORT
,
2063 ATOM_DEVICE_CRT2_SUPPORT
);
2065 devices
= ATOM_DEVICE_CRT1_SUPPORT
;
2066 radeon_add_legacy_encoder(dev
,
2067 radeon_get_encoder_id
2069 ATOM_DEVICE_CRT1_SUPPORT
,
2071 ATOM_DEVICE_CRT1_SUPPORT
);
2073 radeon_add_legacy_connector(dev
,
2076 legacy_connector_convert
2079 CONNECTOR_OBJECT_ID_VGA
,
2082 case CONNECTOR_DVI_I_LEGACY
:
2085 devices
|= ATOM_DEVICE_CRT2_SUPPORT
;
2086 radeon_add_legacy_encoder(dev
,
2087 radeon_get_encoder_id
2089 ATOM_DEVICE_CRT2_SUPPORT
,
2091 ATOM_DEVICE_CRT2_SUPPORT
);
2093 devices
|= ATOM_DEVICE_CRT1_SUPPORT
;
2094 radeon_add_legacy_encoder(dev
,
2095 radeon_get_encoder_id
2097 ATOM_DEVICE_CRT1_SUPPORT
,
2099 ATOM_DEVICE_CRT1_SUPPORT
);
2101 if ((tmp
>> 4) & 0x1) {
2102 devices
|= ATOM_DEVICE_DFP2_SUPPORT
;
2103 radeon_add_legacy_encoder(dev
,
2104 radeon_get_encoder_id
2106 ATOM_DEVICE_DFP2_SUPPORT
,
2108 ATOM_DEVICE_DFP2_SUPPORT
);
2109 connector_object_id
= combios_check_dl_dvi(dev
, 0);
2111 devices
|= ATOM_DEVICE_DFP1_SUPPORT
;
2112 radeon_add_legacy_encoder(dev
,
2113 radeon_get_encoder_id
2115 ATOM_DEVICE_DFP1_SUPPORT
,
2117 ATOM_DEVICE_DFP1_SUPPORT
);
2118 connector_object_id
= CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
2120 radeon_add_legacy_connector(dev
,
2123 legacy_connector_convert
2126 connector_object_id
,
2129 case CONNECTOR_DVI_D_LEGACY
:
2130 if ((tmp
>> 4) & 0x1) {
2131 devices
= ATOM_DEVICE_DFP2_SUPPORT
;
2132 connector_object_id
= combios_check_dl_dvi(dev
, 1);
2134 devices
= ATOM_DEVICE_DFP1_SUPPORT
;
2135 connector_object_id
= CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
2137 radeon_add_legacy_encoder(dev
,
2138 radeon_get_encoder_id
2141 radeon_add_legacy_connector(dev
, i
, devices
,
2142 legacy_connector_convert
2145 connector_object_id
,
2148 case CONNECTOR_CTV_LEGACY
:
2149 case CONNECTOR_STV_LEGACY
:
2150 radeon_add_legacy_encoder(dev
,
2151 radeon_get_encoder_id
2153 ATOM_DEVICE_TV1_SUPPORT
,
2155 ATOM_DEVICE_TV1_SUPPORT
);
2156 radeon_add_legacy_connector(dev
, i
,
2157 ATOM_DEVICE_TV1_SUPPORT
,
2158 legacy_connector_convert
2161 CONNECTOR_OBJECT_ID_SVIDEO
,
2165 DRM_ERROR("Unknown connector type: %d\n",
2172 uint16_t tmds_info
=
2173 combios_get_table_offset(dev
, COMBIOS_DFP_INFO_TABLE
);
2175 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2177 radeon_add_legacy_encoder(dev
,
2178 radeon_get_encoder_id(dev
,
2179 ATOM_DEVICE_CRT1_SUPPORT
,
2181 ATOM_DEVICE_CRT1_SUPPORT
);
2182 radeon_add_legacy_encoder(dev
,
2183 radeon_get_encoder_id(dev
,
2184 ATOM_DEVICE_DFP1_SUPPORT
,
2186 ATOM_DEVICE_DFP1_SUPPORT
);
2188 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
2189 hpd
.hpd
= RADEON_HPD_NONE
;
2190 radeon_add_legacy_connector(dev
,
2192 ATOM_DEVICE_CRT1_SUPPORT
|
2193 ATOM_DEVICE_DFP1_SUPPORT
,
2194 DRM_MODE_CONNECTOR_DVII
,
2196 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
2200 combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
2201 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2203 radeon_add_legacy_encoder(dev
,
2204 radeon_get_encoder_id(dev
,
2205 ATOM_DEVICE_CRT1_SUPPORT
,
2207 ATOM_DEVICE_CRT1_SUPPORT
);
2208 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
2209 hpd
.hpd
= RADEON_HPD_NONE
;
2210 radeon_add_legacy_connector(dev
,
2212 ATOM_DEVICE_CRT1_SUPPORT
,
2213 DRM_MODE_CONNECTOR_VGA
,
2215 CONNECTOR_OBJECT_ID_VGA
,
2218 DRM_DEBUG("No connector info found\n");
2224 if (rdev
->flags
& RADEON_IS_MOBILITY
|| rdev
->flags
& RADEON_IS_IGP
) {
2226 combios_get_table_offset(dev
, COMBIOS_LCD_INFO_TABLE
);
2228 uint16_t lcd_ddc_info
=
2229 combios_get_table_offset(dev
,
2230 COMBIOS_LCD_DDC_INFO_TABLE
);
2232 radeon_add_legacy_encoder(dev
,
2233 radeon_get_encoder_id(dev
,
2234 ATOM_DEVICE_LCD1_SUPPORT
,
2236 ATOM_DEVICE_LCD1_SUPPORT
);
2239 ddc_type
= RBIOS8(lcd_ddc_info
+ 2);
2243 combios_setup_i2c_bus
2244 (rdev
, RADEON_GPIO_MONID
);
2248 combios_setup_i2c_bus
2249 (rdev
, RADEON_GPIO_DVI_DDC
);
2253 combios_setup_i2c_bus
2254 (rdev
, RADEON_GPIO_VGA_DDC
);
2258 combios_setup_i2c_bus
2259 (rdev
, RADEON_GPIO_CRT2_DDC
);
2263 combios_setup_i2c_bus
2264 (rdev
, RADEON_GPIOPAD_MASK
);
2265 ddc_i2c
.mask_clk_mask
=
2266 RBIOS32(lcd_ddc_info
+ 3);
2267 ddc_i2c
.mask_data_mask
=
2268 RBIOS32(lcd_ddc_info
+ 7);
2269 ddc_i2c
.a_clk_mask
=
2270 RBIOS32(lcd_ddc_info
+ 3);
2271 ddc_i2c
.a_data_mask
=
2272 RBIOS32(lcd_ddc_info
+ 7);
2273 ddc_i2c
.en_clk_mask
=
2274 RBIOS32(lcd_ddc_info
+ 3);
2275 ddc_i2c
.en_data_mask
=
2276 RBIOS32(lcd_ddc_info
+ 7);
2277 ddc_i2c
.y_clk_mask
=
2278 RBIOS32(lcd_ddc_info
+ 3);
2279 ddc_i2c
.y_data_mask
=
2280 RBIOS32(lcd_ddc_info
+ 7);
2284 combios_setup_i2c_bus
2285 (rdev
, RADEON_MDGPIO_MASK
);
2286 ddc_i2c
.mask_clk_mask
=
2287 RBIOS32(lcd_ddc_info
+ 3);
2288 ddc_i2c
.mask_data_mask
=
2289 RBIOS32(lcd_ddc_info
+ 7);
2290 ddc_i2c
.a_clk_mask
=
2291 RBIOS32(lcd_ddc_info
+ 3);
2292 ddc_i2c
.a_data_mask
=
2293 RBIOS32(lcd_ddc_info
+ 7);
2294 ddc_i2c
.en_clk_mask
=
2295 RBIOS32(lcd_ddc_info
+ 3);
2296 ddc_i2c
.en_data_mask
=
2297 RBIOS32(lcd_ddc_info
+ 7);
2298 ddc_i2c
.y_clk_mask
=
2299 RBIOS32(lcd_ddc_info
+ 3);
2300 ddc_i2c
.y_data_mask
=
2301 RBIOS32(lcd_ddc_info
+ 7);
2304 ddc_i2c
.valid
= false;
2307 DRM_DEBUG("LCD DDC Info Table found!\n");
2309 ddc_i2c
.valid
= false;
2311 hpd
.hpd
= RADEON_HPD_NONE
;
2312 radeon_add_legacy_connector(dev
,
2314 ATOM_DEVICE_LCD1_SUPPORT
,
2315 DRM_MODE_CONNECTOR_LVDS
,
2317 CONNECTOR_OBJECT_ID_LVDS
,
2322 /* check TV table */
2323 if (rdev
->family
!= CHIP_R100
&& rdev
->family
!= CHIP_R200
) {
2325 combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
2327 if (RBIOS8(tv_info
+ 6) == 'T') {
2328 if (radeon_apply_legacy_tv_quirks(dev
)) {
2329 hpd
.hpd
= RADEON_HPD_NONE
;
2330 radeon_add_legacy_encoder(dev
,
2331 radeon_get_encoder_id
2333 ATOM_DEVICE_TV1_SUPPORT
,
2335 ATOM_DEVICE_TV1_SUPPORT
);
2336 radeon_add_legacy_connector(dev
, 6,
2337 ATOM_DEVICE_TV1_SUPPORT
,
2338 DRM_MODE_CONNECTOR_SVIDEO
,
2340 CONNECTOR_OBJECT_ID_SVIDEO
,
2347 radeon_link_encoder_connector(dev
);
2352 void radeon_combios_get_power_modes(struct radeon_device
*rdev
)
2354 struct drm_device
*dev
= rdev
->ddev
;
2355 u16 offset
, misc
, misc2
= 0;
2356 u8 rev
, blocks
, tmp
;
2357 int state_index
= 0;
2359 rdev
->pm
.default_power_state
= NULL
;
2361 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
2362 offset
= combios_get_table_offset(dev
, COMBIOS_POWERPLAY_INFO_TABLE
);
2364 rev
= RBIOS8(offset
);
2365 blocks
= RBIOS8(offset
+ 0x2);
2366 /* power mode 0 tends to be the only valid one */
2367 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2368 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= RBIOS32(offset
+ 0x5 + 0x2);
2369 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= RBIOS32(offset
+ 0x5 + 0x6);
2370 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2371 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2373 /* skip overclock modes for now */
2374 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
>
2375 rdev
->clock
.default_mclk
+ RADEON_MODE_OVERCLOCK_MARGIN
) ||
2376 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
>
2377 rdev
->clock
.default_sclk
+ RADEON_MODE_OVERCLOCK_MARGIN
))
2379 rdev
->pm
.power_state
[state_index
].type
=
2380 POWER_STATE_TYPE_BATTERY
;
2381 misc
= RBIOS16(offset
+ 0x5 + 0x0);
2383 misc2
= RBIOS16(offset
+ 0x5 + 0xe);
2385 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_GPIO
;
2387 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2390 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2392 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.valid
= true;
2394 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.reg
=
2395 RBIOS16(offset
+ 0x5 + 0xb) * 4;
2396 tmp
= RBIOS8(offset
+ 0x5 + 0xd);
2397 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.mask
= (1 << tmp
);
2399 u8 entries
= RBIOS8(offset
+ 0x5 + 0xb);
2400 u16 voltage_table_offset
= RBIOS16(offset
+ 0x5 + 0xc);
2401 if (entries
&& voltage_table_offset
) {
2402 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.reg
=
2403 RBIOS16(voltage_table_offset
) * 4;
2404 tmp
= RBIOS8(voltage_table_offset
+ 0x2);
2405 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.mask
= (1 << tmp
);
2407 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.valid
= false;
2409 switch ((misc2
& 0x700) >> 8) {
2412 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 0;
2415 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 33;
2418 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 66;
2421 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 99;
2424 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 132;
2428 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2430 rdev
->pm
.power_state
[state_index
].non_clock_info
.pcie_lanes
=
2431 RBIOS8(offset
+ 0x5 + 0x10);
2434 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2437 /* XXX figure out some good default low power mode for desktop cards */
2441 /* add the default mode */
2442 rdev
->pm
.power_state
[state_index
].type
=
2443 POWER_STATE_TYPE_DEFAULT
;
2444 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2445 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= rdev
->clock
.default_mclk
;
2446 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= rdev
->clock
.default_sclk
;
2447 rdev
->pm
.power_state
[state_index
].default_clock_mode
= &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2448 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2449 if (rdev
->asic
->get_pcie_lanes
)
2450 rdev
->pm
.power_state
[state_index
].non_clock_info
.pcie_lanes
= radeon_get_pcie_lanes(rdev
);
2452 rdev
->pm
.power_state
[state_index
].non_clock_info
.pcie_lanes
= 16;
2453 rdev
->pm
.default_power_state
= &rdev
->pm
.power_state
[state_index
];
2454 rdev
->pm
.num_power_states
= state_index
+ 1;
2456 rdev
->pm
.current_power_state
= rdev
->pm
.default_power_state
;
2457 rdev
->pm
.current_clock_mode
=
2458 rdev
->pm
.default_power_state
->default_clock_mode
;
2461 void radeon_external_tmds_setup(struct drm_encoder
*encoder
)
2463 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2464 struct radeon_encoder_ext_tmds
*tmds
= radeon_encoder
->enc_priv
;
2469 switch (tmds
->dvo_chip
) {
2472 radeon_i2c_put_byte(tmds
->i2c_bus
,
2475 radeon_i2c_put_byte(tmds
->i2c_bus
,
2478 radeon_i2c_put_byte(tmds
->i2c_bus
,
2481 radeon_i2c_put_byte(tmds
->i2c_bus
,
2484 radeon_i2c_put_byte(tmds
->i2c_bus
,
2489 /* sil 1178 - untested */
2508 bool radeon_combios_external_tmds_setup(struct drm_encoder
*encoder
)
2510 struct drm_device
*dev
= encoder
->dev
;
2511 struct radeon_device
*rdev
= dev
->dev_private
;
2512 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2514 uint8_t blocks
, slave_addr
, rev
;
2516 uint32_t reg
, val
, and_mask
, or_mask
;
2517 struct radeon_encoder_ext_tmds
*tmds
= radeon_encoder
->enc_priv
;
2522 if (rdev
->flags
& RADEON_IS_IGP
) {
2523 offset
= combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_ON_TABLE
);
2524 rev
= RBIOS8(offset
);
2526 rev
= RBIOS8(offset
);
2528 blocks
= RBIOS8(offset
+ 3);
2530 while (blocks
> 0) {
2531 id
= RBIOS16(index
);
2535 reg
= (id
& 0x1fff) * 4;
2536 val
= RBIOS32(index
);
2541 reg
= (id
& 0x1fff) * 4;
2542 and_mask
= RBIOS32(index
);
2544 or_mask
= RBIOS32(index
);
2547 val
= (val
& and_mask
) | or_mask
;
2551 val
= RBIOS16(index
);
2556 val
= RBIOS16(index
);
2561 slave_addr
= id
& 0xff;
2562 slave_addr
>>= 1; /* 7 bit addressing */
2564 reg
= RBIOS8(index
);
2566 val
= RBIOS8(index
);
2568 radeon_i2c_put_byte(tmds
->i2c_bus
,
2573 DRM_ERROR("Unknown id %d\n", id
>> 13);
2582 offset
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
2584 index
= offset
+ 10;
2585 id
= RBIOS16(index
);
2586 while (id
!= 0xffff) {
2590 reg
= (id
& 0x1fff) * 4;
2591 val
= RBIOS32(index
);
2595 reg
= (id
& 0x1fff) * 4;
2596 and_mask
= RBIOS32(index
);
2598 or_mask
= RBIOS32(index
);
2601 val
= (val
& and_mask
) | or_mask
;
2605 val
= RBIOS16(index
);
2611 and_mask
= RBIOS32(index
);
2613 or_mask
= RBIOS32(index
);
2615 val
= RREG32_PLL(reg
);
2616 val
= (val
& and_mask
) | or_mask
;
2617 WREG32_PLL(reg
, val
);
2621 val
= RBIOS8(index
);
2623 radeon_i2c_put_byte(tmds
->i2c_bus
,
2628 DRM_ERROR("Unknown id %d\n", id
>> 13);
2631 id
= RBIOS16(index
);
2639 static void combios_parse_mmio_table(struct drm_device
*dev
, uint16_t offset
)
2641 struct radeon_device
*rdev
= dev
->dev_private
;
2644 while (RBIOS16(offset
)) {
2645 uint16_t cmd
= ((RBIOS16(offset
) & 0xe000) >> 13);
2646 uint32_t addr
= (RBIOS16(offset
) & 0x1fff);
2647 uint32_t val
, and_mask
, or_mask
;
2653 val
= RBIOS32(offset
);
2658 val
= RBIOS32(offset
);
2663 and_mask
= RBIOS32(offset
);
2665 or_mask
= RBIOS32(offset
);
2673 and_mask
= RBIOS32(offset
);
2675 or_mask
= RBIOS32(offset
);
2683 val
= RBIOS16(offset
);
2688 val
= RBIOS16(offset
);
2695 (RADEON_CLK_PWRMGT_CNTL
) &
2702 if ((RREG32(RADEON_MC_STATUS
) &
2718 static void combios_parse_pll_table(struct drm_device
*dev
, uint16_t offset
)
2720 struct radeon_device
*rdev
= dev
->dev_private
;
2723 while (RBIOS8(offset
)) {
2724 uint8_t cmd
= ((RBIOS8(offset
) & 0xc0) >> 6);
2725 uint8_t addr
= (RBIOS8(offset
) & 0x3f);
2726 uint32_t val
, shift
, tmp
;
2727 uint32_t and_mask
, or_mask
;
2732 val
= RBIOS32(offset
);
2734 WREG32_PLL(addr
, val
);
2737 shift
= RBIOS8(offset
) * 8;
2739 and_mask
= RBIOS8(offset
) << shift
;
2740 and_mask
|= ~(0xff << shift
);
2742 or_mask
= RBIOS8(offset
) << shift
;
2744 tmp
= RREG32_PLL(addr
);
2747 WREG32_PLL(addr
, tmp
);
2763 (RADEON_CLK_PWRMGT_CNTL
) &
2771 (RADEON_CLK_PWRMGT_CNTL
) &
2778 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL
);
2779 if (tmp
& RADEON_CG_NO1_DEBUG_0
) {
2781 uint32_t mclk_cntl
=
2784 mclk_cntl
&= 0xffff0000;
2785 /*mclk_cntl |= 0x00001111;*//* ??? */
2786 WREG32_PLL(RADEON_MCLK_CNTL
,
2791 (RADEON_CLK_PWRMGT_CNTL
,
2793 ~RADEON_CG_NO1_DEBUG_0
);
2808 static void combios_parse_ram_reset_table(struct drm_device
*dev
,
2811 struct radeon_device
*rdev
= dev
->dev_private
;
2815 uint8_t val
= RBIOS8(offset
);
2816 while (val
!= 0xff) {
2820 uint32_t channel_complete_mask
;
2822 if (ASIC_IS_R300(rdev
))
2823 channel_complete_mask
=
2824 R300_MEM_PWRUP_COMPLETE
;
2826 channel_complete_mask
=
2827 RADEON_MEM_PWRUP_COMPLETE
;
2830 if ((RREG32(RADEON_MEM_STR_CNTL
) &
2831 channel_complete_mask
) ==
2832 channel_complete_mask
)
2836 uint32_t or_mask
= RBIOS16(offset
);
2839 tmp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
2840 tmp
&= RADEON_SDRAM_MODE_MASK
;
2842 WREG32(RADEON_MEM_SDRAM_MODE_REG
, tmp
);
2844 or_mask
= val
<< 24;
2845 tmp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
2846 tmp
&= RADEON_B3MEM_RESET_MASK
;
2848 WREG32(RADEON_MEM_SDRAM_MODE_REG
, tmp
);
2850 val
= RBIOS8(offset
);
2855 static uint32_t combios_detect_ram(struct drm_device
*dev
, int ram
,
2856 int mem_addr_mapping
)
2858 struct radeon_device
*rdev
= dev
->dev_private
;
2863 mem_cntl
= RREG32(RADEON_MEM_CNTL
);
2864 if (mem_cntl
& RV100_HALF_MODE
)
2867 mem_cntl
&= ~(0xff << 8);
2868 mem_cntl
|= (mem_addr_mapping
& 0xff) << 8;
2869 WREG32(RADEON_MEM_CNTL
, mem_cntl
);
2870 RREG32(RADEON_MEM_CNTL
);
2874 /* something like this???? */
2876 addr
= ram
* 1024 * 1024;
2877 /* write to each page */
2878 WREG32(RADEON_MM_INDEX
, (addr
) | RADEON_MM_APER
);
2879 WREG32(RADEON_MM_DATA
, 0xdeadbeef);
2880 /* read back and verify */
2881 WREG32(RADEON_MM_INDEX
, (addr
) | RADEON_MM_APER
);
2882 if (RREG32(RADEON_MM_DATA
) != 0xdeadbeef)
2889 static void combios_write_ram_size(struct drm_device
*dev
)
2891 struct radeon_device
*rdev
= dev
->dev_private
;
2894 uint32_t mem_size
= 0;
2895 uint32_t mem_cntl
= 0;
2897 /* should do something smarter here I guess... */
2898 if (rdev
->flags
& RADEON_IS_IGP
)
2901 /* first check detected mem table */
2902 offset
= combios_get_table_offset(dev
, COMBIOS_DETECTED_MEM_TABLE
);
2904 rev
= RBIOS8(offset
);
2906 mem_cntl
= RBIOS32(offset
+ 1);
2907 mem_size
= RBIOS16(offset
+ 5);
2908 if (((rdev
->flags
& RADEON_FAMILY_MASK
) < CHIP_R200
) &&
2909 ((dev
->pdev
->device
!= 0x515e)
2910 && (dev
->pdev
->device
!= 0x5969)))
2911 WREG32(RADEON_MEM_CNTL
, mem_cntl
);
2917 combios_get_table_offset(dev
, COMBIOS_MEM_CONFIG_TABLE
);
2919 rev
= RBIOS8(offset
- 1);
2921 if (((rdev
->flags
& RADEON_FAMILY_MASK
) <
2923 && ((dev
->pdev
->device
!= 0x515e)
2924 && (dev
->pdev
->device
!= 0x5969))) {
2926 int mem_addr_mapping
= 0;
2928 while (RBIOS8(offset
)) {
2929 ram
= RBIOS8(offset
);
2932 if (mem_addr_mapping
!= 0x25)
2935 combios_detect_ram(dev
, ram
,
2942 mem_size
= RBIOS8(offset
);
2944 mem_size
= RBIOS8(offset
);
2945 mem_size
*= 2; /* convert to MB */
2950 mem_size
*= (1024 * 1024); /* convert to bytes */
2951 WREG32(RADEON_CONFIG_MEMSIZE
, mem_size
);
2954 void radeon_combios_dyn_clk_setup(struct drm_device
*dev
, int enable
)
2956 uint16_t dyn_clk_info
=
2957 combios_get_table_offset(dev
, COMBIOS_DYN_CLK_1_TABLE
);
2960 combios_parse_pll_table(dev
, dyn_clk_info
);
2963 void radeon_combios_asic_init(struct drm_device
*dev
)
2965 struct radeon_device
*rdev
= dev
->dev_private
;
2968 /* port hardcoded mac stuff from radeonfb */
2969 if (rdev
->bios
== NULL
)
2973 table
= combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_1_TABLE
);
2975 combios_parse_mmio_table(dev
, table
);
2978 table
= combios_get_table_offset(dev
, COMBIOS_PLL_INIT_TABLE
);
2980 combios_parse_pll_table(dev
, table
);
2983 table
= combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_2_TABLE
);
2985 combios_parse_mmio_table(dev
, table
);
2987 if (!(rdev
->flags
& RADEON_IS_IGP
)) {
2990 combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_4_TABLE
);
2992 combios_parse_mmio_table(dev
, table
);
2995 table
= combios_get_table_offset(dev
, COMBIOS_RAM_RESET_TABLE
);
2997 combios_parse_ram_reset_table(dev
, table
);
3001 combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_3_TABLE
);
3003 combios_parse_mmio_table(dev
, table
);
3005 /* write CONFIG_MEMSIZE */
3006 combios_write_ram_size(dev
);
3010 table
= combios_get_table_offset(dev
, COMBIOS_DYN_CLK_1_TABLE
);
3012 combios_parse_pll_table(dev
, table
);
3016 void radeon_combios_initialize_bios_scratch_regs(struct drm_device
*dev
)
3018 struct radeon_device
*rdev
= dev
->dev_private
;
3019 uint32_t bios_0_scratch
, bios_6_scratch
, bios_7_scratch
;
3021 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
3022 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3023 bios_7_scratch
= RREG32(RADEON_BIOS_7_SCRATCH
);
3025 /* let the bios control the backlight */
3026 bios_0_scratch
&= ~RADEON_DRIVER_BRIGHTNESS_EN
;
3028 /* tell the bios not to handle mode switching */
3029 bios_6_scratch
|= (RADEON_DISPLAY_SWITCHING_DIS
|
3030 RADEON_ACC_MODE_CHANGE
);
3032 /* tell the bios a driver is loaded */
3033 bios_7_scratch
|= RADEON_DRV_LOADED
;
3035 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
3036 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
3037 WREG32(RADEON_BIOS_7_SCRATCH
, bios_7_scratch
);
3040 void radeon_combios_output_lock(struct drm_encoder
*encoder
, bool lock
)
3042 struct drm_device
*dev
= encoder
->dev
;
3043 struct radeon_device
*rdev
= dev
->dev_private
;
3044 uint32_t bios_6_scratch
;
3046 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3049 bios_6_scratch
|= RADEON_DRIVER_CRITICAL
;
3051 bios_6_scratch
&= ~RADEON_DRIVER_CRITICAL
;
3053 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
3057 radeon_combios_connected_scratch_regs(struct drm_connector
*connector
,
3058 struct drm_encoder
*encoder
,
3061 struct drm_device
*dev
= connector
->dev
;
3062 struct radeon_device
*rdev
= dev
->dev_private
;
3063 struct radeon_connector
*radeon_connector
=
3064 to_radeon_connector(connector
);
3065 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3066 uint32_t bios_4_scratch
= RREG32(RADEON_BIOS_4_SCRATCH
);
3067 uint32_t bios_5_scratch
= RREG32(RADEON_BIOS_5_SCRATCH
);
3069 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
3070 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
3072 DRM_DEBUG("TV1 connected\n");
3074 bios_4_scratch
|= RADEON_TV1_ATTACHED_SVIDEO
;
3075 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3076 bios_5_scratch
|= RADEON_TV1_ON
;
3077 bios_5_scratch
|= RADEON_ACC_REQ_TV1
;
3079 DRM_DEBUG("TV1 disconnected\n");
3080 bios_4_scratch
&= ~RADEON_TV1_ATTACHED_MASK
;
3081 bios_5_scratch
&= ~RADEON_TV1_ON
;
3082 bios_5_scratch
&= ~RADEON_ACC_REQ_TV1
;
3085 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
3086 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
3088 DRM_DEBUG("LCD1 connected\n");
3089 bios_4_scratch
|= RADEON_LCD1_ATTACHED
;
3090 bios_5_scratch
|= RADEON_LCD1_ON
;
3091 bios_5_scratch
|= RADEON_ACC_REQ_LCD1
;
3093 DRM_DEBUG("LCD1 disconnected\n");
3094 bios_4_scratch
&= ~RADEON_LCD1_ATTACHED
;
3095 bios_5_scratch
&= ~RADEON_LCD1_ON
;
3096 bios_5_scratch
&= ~RADEON_ACC_REQ_LCD1
;
3099 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
3100 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
3102 DRM_DEBUG("CRT1 connected\n");
3103 bios_4_scratch
|= RADEON_CRT1_ATTACHED_COLOR
;
3104 bios_5_scratch
|= RADEON_CRT1_ON
;
3105 bios_5_scratch
|= RADEON_ACC_REQ_CRT1
;
3107 DRM_DEBUG("CRT1 disconnected\n");
3108 bios_4_scratch
&= ~RADEON_CRT1_ATTACHED_MASK
;
3109 bios_5_scratch
&= ~RADEON_CRT1_ON
;
3110 bios_5_scratch
&= ~RADEON_ACC_REQ_CRT1
;
3113 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
3114 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
3116 DRM_DEBUG("CRT2 connected\n");
3117 bios_4_scratch
|= RADEON_CRT2_ATTACHED_COLOR
;
3118 bios_5_scratch
|= RADEON_CRT2_ON
;
3119 bios_5_scratch
|= RADEON_ACC_REQ_CRT2
;
3121 DRM_DEBUG("CRT2 disconnected\n");
3122 bios_4_scratch
&= ~RADEON_CRT2_ATTACHED_MASK
;
3123 bios_5_scratch
&= ~RADEON_CRT2_ON
;
3124 bios_5_scratch
&= ~RADEON_ACC_REQ_CRT2
;
3127 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
3128 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
3130 DRM_DEBUG("DFP1 connected\n");
3131 bios_4_scratch
|= RADEON_DFP1_ATTACHED
;
3132 bios_5_scratch
|= RADEON_DFP1_ON
;
3133 bios_5_scratch
|= RADEON_ACC_REQ_DFP1
;
3135 DRM_DEBUG("DFP1 disconnected\n");
3136 bios_4_scratch
&= ~RADEON_DFP1_ATTACHED
;
3137 bios_5_scratch
&= ~RADEON_DFP1_ON
;
3138 bios_5_scratch
&= ~RADEON_ACC_REQ_DFP1
;
3141 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
3142 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
3144 DRM_DEBUG("DFP2 connected\n");
3145 bios_4_scratch
|= RADEON_DFP2_ATTACHED
;
3146 bios_5_scratch
|= RADEON_DFP2_ON
;
3147 bios_5_scratch
|= RADEON_ACC_REQ_DFP2
;
3149 DRM_DEBUG("DFP2 disconnected\n");
3150 bios_4_scratch
&= ~RADEON_DFP2_ATTACHED
;
3151 bios_5_scratch
&= ~RADEON_DFP2_ON
;
3152 bios_5_scratch
&= ~RADEON_ACC_REQ_DFP2
;
3155 WREG32(RADEON_BIOS_4_SCRATCH
, bios_4_scratch
);
3156 WREG32(RADEON_BIOS_5_SCRATCH
, bios_5_scratch
);
3160 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
3162 struct drm_device
*dev
= encoder
->dev
;
3163 struct radeon_device
*rdev
= dev
->dev_private
;
3164 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3165 uint32_t bios_5_scratch
= RREG32(RADEON_BIOS_5_SCRATCH
);
3167 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
3168 bios_5_scratch
&= ~RADEON_TV1_CRTC_MASK
;
3169 bios_5_scratch
|= (crtc
<< RADEON_TV1_CRTC_SHIFT
);
3171 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
3172 bios_5_scratch
&= ~RADEON_CRT1_CRTC_MASK
;
3173 bios_5_scratch
|= (crtc
<< RADEON_CRT1_CRTC_SHIFT
);
3175 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
3176 bios_5_scratch
&= ~RADEON_CRT2_CRTC_MASK
;
3177 bios_5_scratch
|= (crtc
<< RADEON_CRT2_CRTC_SHIFT
);
3179 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
3180 bios_5_scratch
&= ~RADEON_LCD1_CRTC_MASK
;
3181 bios_5_scratch
|= (crtc
<< RADEON_LCD1_CRTC_SHIFT
);
3183 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
3184 bios_5_scratch
&= ~RADEON_DFP1_CRTC_MASK
;
3185 bios_5_scratch
|= (crtc
<< RADEON_DFP1_CRTC_SHIFT
);
3187 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
3188 bios_5_scratch
&= ~RADEON_DFP2_CRTC_MASK
;
3189 bios_5_scratch
|= (crtc
<< RADEON_DFP2_CRTC_SHIFT
);
3191 WREG32(RADEON_BIOS_5_SCRATCH
, bios_5_scratch
);
3195 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
3197 struct drm_device
*dev
= encoder
->dev
;
3198 struct radeon_device
*rdev
= dev
->dev_private
;
3199 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3200 uint32_t bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3202 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
)) {
3204 bios_6_scratch
|= RADEON_TV_DPMS_ON
;
3206 bios_6_scratch
&= ~RADEON_TV_DPMS_ON
;
3208 if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
3210 bios_6_scratch
|= RADEON_CRT_DPMS_ON
;
3212 bios_6_scratch
&= ~RADEON_CRT_DPMS_ON
;
3214 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
3216 bios_6_scratch
|= RADEON_LCD_DPMS_ON
;
3218 bios_6_scratch
&= ~RADEON_LCD_DPMS_ON
;
3220 if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
3222 bios_6_scratch
|= RADEON_DFP_DPMS_ON
;
3224 bios_6_scratch
&= ~RADEON_DFP_DPMS_ON
;
3226 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);