2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include "radeon_drm.h"
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_id(struct drm_device
*dev
, uint32_t supported_device
,
44 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device
*dev
,
49 uint32_t connector_id
,
50 uint32_t supported_device
,
52 struct radeon_i2c_bus_rec
*i2c_bus
,
53 uint16_t connector_object_id
,
54 struct radeon_hpd
*hpd
);
56 /* from radeon_legacy_encoder.c */
58 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_id
,
59 uint32_t supported_device
);
61 /* old legacy ATI BIOS routines */
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset
{
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE
,
67 COMBIOS_BIOS_SUPPORT_TABLE
,
68 COMBIOS_DAC_PROGRAMMING_TABLE
,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE
,
70 COMBIOS_CRTC_INFO_TABLE
,
71 COMBIOS_PLL_INFO_TABLE
,
72 COMBIOS_TV_INFO_TABLE
,
73 COMBIOS_DFP_INFO_TABLE
,
74 COMBIOS_HW_CONFIG_INFO_TABLE
,
75 COMBIOS_MULTIMEDIA_INFO_TABLE
,
76 COMBIOS_TV_STD_PATCH_TABLE
,
77 COMBIOS_LCD_INFO_TABLE
,
78 COMBIOS_MOBILE_INFO_TABLE
,
79 COMBIOS_PLL_INIT_TABLE
,
80 COMBIOS_MEM_CONFIG_TABLE
,
81 COMBIOS_SAVE_MASK_TABLE
,
82 COMBIOS_HARDCODED_EDID_TABLE
,
83 COMBIOS_ASIC_INIT_2_TABLE
,
84 COMBIOS_CONNECTOR_INFO_TABLE
,
85 COMBIOS_DYN_CLK_1_TABLE
,
86 COMBIOS_RESERVED_MEM_TABLE
,
87 COMBIOS_EXT_TMDS_INFO_TABLE
,
88 COMBIOS_MEM_CLK_INFO_TABLE
,
89 COMBIOS_EXT_DAC_INFO_TABLE
,
90 COMBIOS_MISC_INFO_TABLE
,
91 COMBIOS_CRT_INFO_TABLE
,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE
,
94 COMBIOS_FAN_SPEED_INFO_TABLE
,
95 COMBIOS_OVERDRIVE_INFO_TABLE
,
96 COMBIOS_OEM_INFO_TABLE
,
97 COMBIOS_DYN_CLK_2_TABLE
,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE
,
99 COMBIOS_I2C_INFO_TABLE
,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE
, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE
, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE
, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE
, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE
, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE
, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE
, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE
, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE
, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE
, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE
, /* offset from tmds power */
114 enum radeon_combios_ddc
{
124 enum radeon_combios_connector
{
125 CONNECTOR_NONE_LEGACY
,
126 CONNECTOR_PROPRIETARY_LEGACY
,
127 CONNECTOR_CRT_LEGACY
,
128 CONNECTOR_DVI_I_LEGACY
,
129 CONNECTOR_DVI_D_LEGACY
,
130 CONNECTOR_CTV_LEGACY
,
131 CONNECTOR_STV_LEGACY
,
132 CONNECTOR_UNSUPPORTED_LEGACY
135 const int legacy_connector_convert
[] = {
136 DRM_MODE_CONNECTOR_Unknown
,
137 DRM_MODE_CONNECTOR_DVID
,
138 DRM_MODE_CONNECTOR_VGA
,
139 DRM_MODE_CONNECTOR_DVII
,
140 DRM_MODE_CONNECTOR_DVID
,
141 DRM_MODE_CONNECTOR_Composite
,
142 DRM_MODE_CONNECTOR_SVIDEO
,
143 DRM_MODE_CONNECTOR_Unknown
,
146 static uint16_t combios_get_table_offset(struct drm_device
*dev
,
147 enum radeon_combios_table_offset table
)
149 struct radeon_device
*rdev
= dev
->dev_private
;
151 uint16_t offset
= 0, check_offset
;
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE
:
159 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0xc);
161 offset
= check_offset
;
163 case COMBIOS_BIOS_SUPPORT_TABLE
:
164 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x14);
166 offset
= check_offset
;
168 case COMBIOS_DAC_PROGRAMMING_TABLE
:
169 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2a);
171 offset
= check_offset
;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE
:
174 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2c);
176 offset
= check_offset
;
178 case COMBIOS_CRTC_INFO_TABLE
:
179 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2e);
181 offset
= check_offset
;
183 case COMBIOS_PLL_INFO_TABLE
:
184 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x30);
186 offset
= check_offset
;
188 case COMBIOS_TV_INFO_TABLE
:
189 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x32);
191 offset
= check_offset
;
193 case COMBIOS_DFP_INFO_TABLE
:
194 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x34);
196 offset
= check_offset
;
198 case COMBIOS_HW_CONFIG_INFO_TABLE
:
199 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x36);
201 offset
= check_offset
;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE
:
204 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x38);
206 offset
= check_offset
;
208 case COMBIOS_TV_STD_PATCH_TABLE
:
209 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x3e);
211 offset
= check_offset
;
213 case COMBIOS_LCD_INFO_TABLE
:
214 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x40);
216 offset
= check_offset
;
218 case COMBIOS_MOBILE_INFO_TABLE
:
219 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x42);
221 offset
= check_offset
;
223 case COMBIOS_PLL_INIT_TABLE
:
224 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x46);
226 offset
= check_offset
;
228 case COMBIOS_MEM_CONFIG_TABLE
:
229 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x48);
231 offset
= check_offset
;
233 case COMBIOS_SAVE_MASK_TABLE
:
234 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4a);
236 offset
= check_offset
;
238 case COMBIOS_HARDCODED_EDID_TABLE
:
239 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4c);
241 offset
= check_offset
;
243 case COMBIOS_ASIC_INIT_2_TABLE
:
244 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4e);
246 offset
= check_offset
;
248 case COMBIOS_CONNECTOR_INFO_TABLE
:
249 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x50);
251 offset
= check_offset
;
253 case COMBIOS_DYN_CLK_1_TABLE
:
254 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x52);
256 offset
= check_offset
;
258 case COMBIOS_RESERVED_MEM_TABLE
:
259 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x54);
261 offset
= check_offset
;
263 case COMBIOS_EXT_TMDS_INFO_TABLE
:
264 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x58);
266 offset
= check_offset
;
268 case COMBIOS_MEM_CLK_INFO_TABLE
:
269 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5a);
271 offset
= check_offset
;
273 case COMBIOS_EXT_DAC_INFO_TABLE
:
274 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5c);
276 offset
= check_offset
;
278 case COMBIOS_MISC_INFO_TABLE
:
279 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5e);
281 offset
= check_offset
;
283 case COMBIOS_CRT_INFO_TABLE
:
284 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x60);
286 offset
= check_offset
;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
:
289 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x62);
291 offset
= check_offset
;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE
:
294 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x64);
296 offset
= check_offset
;
298 case COMBIOS_FAN_SPEED_INFO_TABLE
:
299 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x66);
301 offset
= check_offset
;
303 case COMBIOS_OVERDRIVE_INFO_TABLE
:
304 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x68);
306 offset
= check_offset
;
308 case COMBIOS_OEM_INFO_TABLE
:
309 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6a);
311 offset
= check_offset
;
313 case COMBIOS_DYN_CLK_2_TABLE
:
314 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6c);
316 offset
= check_offset
;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE
:
319 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6e);
321 offset
= check_offset
;
323 case COMBIOS_I2C_INFO_TABLE
:
324 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x70);
326 offset
= check_offset
;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE
: /* offset from misc info */
331 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
333 rev
= RBIOS8(check_offset
);
335 check_offset
= RBIOS16(check_offset
+ 0x3);
337 offset
= check_offset
;
341 case COMBIOS_ASIC_INIT_4_TABLE
: /* offset from misc info */
343 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
345 rev
= RBIOS8(check_offset
);
347 check_offset
= RBIOS16(check_offset
+ 0x5);
349 offset
= check_offset
;
353 case COMBIOS_DETECTED_MEM_TABLE
: /* offset from misc info */
355 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
357 rev
= RBIOS8(check_offset
);
359 check_offset
= RBIOS16(check_offset
+ 0x7);
361 offset
= check_offset
;
365 case COMBIOS_ASIC_INIT_5_TABLE
: /* offset from misc info */
367 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
369 rev
= RBIOS8(check_offset
);
371 check_offset
= RBIOS16(check_offset
+ 0x9);
373 offset
= check_offset
;
377 case COMBIOS_RAM_RESET_TABLE
: /* offset from mem config */
379 combios_get_table_offset(dev
, COMBIOS_MEM_CONFIG_TABLE
);
381 while (RBIOS8(check_offset
++));
384 offset
= check_offset
;
387 case COMBIOS_POWERPLAY_INFO_TABLE
: /* offset from mobile info */
389 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
391 check_offset
= RBIOS16(check_offset
+ 0x11);
393 offset
= check_offset
;
396 case COMBIOS_GPIO_INFO_TABLE
: /* offset from mobile info */
398 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
400 check_offset
= RBIOS16(check_offset
+ 0x13);
402 offset
= check_offset
;
405 case COMBIOS_LCD_DDC_INFO_TABLE
: /* offset from mobile info */
407 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
409 check_offset
= RBIOS16(check_offset
+ 0x15);
411 offset
= check_offset
;
414 case COMBIOS_TMDS_POWER_TABLE
: /* offset from mobile info */
416 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
418 check_offset
= RBIOS16(check_offset
+ 0x17);
420 offset
= check_offset
;
423 case COMBIOS_TMDS_POWER_ON_TABLE
: /* offset from tmds power */
425 combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_TABLE
);
427 check_offset
= RBIOS16(check_offset
+ 0x2);
429 offset
= check_offset
;
432 case COMBIOS_TMDS_POWER_OFF_TABLE
: /* offset from tmds power */
434 combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_TABLE
);
436 check_offset
= RBIOS16(check_offset
+ 0x4);
438 offset
= check_offset
;
449 bool radeon_combios_check_hardcoded_edid(struct radeon_device
*rdev
)
454 edid_info
= combios_get_table_offset(rdev
->ddev
, COMBIOS_HARDCODED_EDID_TABLE
);
458 raw
= rdev
->bios
+ edid_info
;
459 edid
= kmalloc(EDID_LENGTH
* (raw
[0x7e] + 1), GFP_KERNEL
);
463 memcpy((unsigned char *)edid
, raw
, EDID_LENGTH
* (raw
[0x7e] + 1));
465 if (!drm_edid_is_valid(edid
)) {
470 rdev
->mode_info
.bios_hardcoded_edid
= edid
;
475 radeon_combios_get_hardcoded_edid(struct radeon_device
*rdev
)
477 if (rdev
->mode_info
.bios_hardcoded_edid
)
478 return rdev
->mode_info
.bios_hardcoded_edid
;
482 static struct radeon_i2c_bus_rec
combios_setup_i2c_bus(struct radeon_device
*rdev
,
485 struct radeon_i2c_bus_rec i2c
;
487 if (ddc_line
== RADEON_GPIOPAD_MASK
) {
488 i2c
.mask_clk_reg
= RADEON_GPIOPAD_MASK
;
489 i2c
.mask_data_reg
= RADEON_GPIOPAD_MASK
;
490 i2c
.a_clk_reg
= RADEON_GPIOPAD_A
;
491 i2c
.a_data_reg
= RADEON_GPIOPAD_A
;
492 i2c
.en_clk_reg
= RADEON_GPIOPAD_EN
;
493 i2c
.en_data_reg
= RADEON_GPIOPAD_EN
;
494 i2c
.y_clk_reg
= RADEON_GPIOPAD_Y
;
495 i2c
.y_data_reg
= RADEON_GPIOPAD_Y
;
496 } else if (ddc_line
== RADEON_MDGPIO_MASK
) {
497 i2c
.mask_clk_reg
= RADEON_MDGPIO_MASK
;
498 i2c
.mask_data_reg
= RADEON_MDGPIO_MASK
;
499 i2c
.a_clk_reg
= RADEON_MDGPIO_A
;
500 i2c
.a_data_reg
= RADEON_MDGPIO_A
;
501 i2c
.en_clk_reg
= RADEON_MDGPIO_EN
;
502 i2c
.en_data_reg
= RADEON_MDGPIO_EN
;
503 i2c
.y_clk_reg
= RADEON_MDGPIO_Y
;
504 i2c
.y_data_reg
= RADEON_MDGPIO_Y
;
506 i2c
.mask_clk_mask
= RADEON_GPIO_EN_1
;
507 i2c
.mask_data_mask
= RADEON_GPIO_EN_0
;
508 i2c
.a_clk_mask
= RADEON_GPIO_A_1
;
509 i2c
.a_data_mask
= RADEON_GPIO_A_0
;
510 i2c
.en_clk_mask
= RADEON_GPIO_EN_1
;
511 i2c
.en_data_mask
= RADEON_GPIO_EN_0
;
512 i2c
.y_clk_mask
= RADEON_GPIO_Y_1
;
513 i2c
.y_data_mask
= RADEON_GPIO_Y_0
;
515 i2c
.mask_clk_reg
= ddc_line
;
516 i2c
.mask_data_reg
= ddc_line
;
517 i2c
.a_clk_reg
= ddc_line
;
518 i2c
.a_data_reg
= ddc_line
;
519 i2c
.en_clk_reg
= ddc_line
;
520 i2c
.en_data_reg
= ddc_line
;
521 i2c
.y_clk_reg
= ddc_line
;
522 i2c
.y_data_reg
= ddc_line
;
525 switch (rdev
->family
) {
533 case RADEON_GPIO_DVI_DDC
:
534 i2c
.hw_capable
= true;
537 i2c
.hw_capable
= false;
543 case RADEON_GPIO_DVI_DDC
:
544 case RADEON_GPIO_MONID
:
545 i2c
.hw_capable
= true;
548 i2c
.hw_capable
= false;
555 case RADEON_GPIO_VGA_DDC
:
556 case RADEON_GPIO_DVI_DDC
:
557 case RADEON_GPIO_CRT2_DDC
:
558 i2c
.hw_capable
= true;
561 i2c
.hw_capable
= false;
568 case RADEON_GPIO_VGA_DDC
:
569 case RADEON_GPIO_DVI_DDC
:
570 i2c
.hw_capable
= true;
573 i2c
.hw_capable
= false;
582 case RADEON_GPIO_VGA_DDC
:
583 case RADEON_GPIO_DVI_DDC
:
584 i2c
.hw_capable
= true;
586 case RADEON_GPIO_MONID
:
587 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
588 * reliably on some pre-r4xx hardware; not sure why.
590 i2c
.hw_capable
= false;
593 i2c
.hw_capable
= false;
598 i2c
.hw_capable
= false;
603 i2c
.hpd
= RADEON_HPD_NONE
;
613 bool radeon_combios_get_clock_info(struct drm_device
*dev
)
615 struct radeon_device
*rdev
= dev
->dev_private
;
617 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
618 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
619 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
620 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
624 pll_info
= combios_get_table_offset(dev
, COMBIOS_PLL_INFO_TABLE
);
626 rev
= RBIOS8(pll_info
);
629 p1pll
->reference_freq
= RBIOS16(pll_info
+ 0xe);
630 p1pll
->reference_div
= RBIOS16(pll_info
+ 0x10);
631 p1pll
->pll_out_min
= RBIOS32(pll_info
+ 0x12);
632 p1pll
->pll_out_max
= RBIOS32(pll_info
+ 0x16);
633 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
634 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
637 p1pll
->pll_in_min
= RBIOS32(pll_info
+ 0x36);
638 p1pll
->pll_in_max
= RBIOS32(pll_info
+ 0x3a);
640 p1pll
->pll_in_min
= 40;
641 p1pll
->pll_in_max
= 500;
646 spll
->reference_freq
= RBIOS16(pll_info
+ 0x1a);
647 spll
->reference_div
= RBIOS16(pll_info
+ 0x1c);
648 spll
->pll_out_min
= RBIOS32(pll_info
+ 0x1e);
649 spll
->pll_out_max
= RBIOS32(pll_info
+ 0x22);
652 spll
->pll_in_min
= RBIOS32(pll_info
+ 0x48);
653 spll
->pll_in_max
= RBIOS32(pll_info
+ 0x4c);
656 spll
->pll_in_min
= 40;
657 spll
->pll_in_max
= 500;
661 mpll
->reference_freq
= RBIOS16(pll_info
+ 0x26);
662 mpll
->reference_div
= RBIOS16(pll_info
+ 0x28);
663 mpll
->pll_out_min
= RBIOS32(pll_info
+ 0x2a);
664 mpll
->pll_out_max
= RBIOS32(pll_info
+ 0x2e);
667 mpll
->pll_in_min
= RBIOS32(pll_info
+ 0x5a);
668 mpll
->pll_in_max
= RBIOS32(pll_info
+ 0x5e);
671 mpll
->pll_in_min
= 40;
672 mpll
->pll_in_max
= 500;
675 /* default sclk/mclk */
676 sclk
= RBIOS16(pll_info
+ 0xa);
677 mclk
= RBIOS16(pll_info
+ 0x8);
683 rdev
->clock
.default_sclk
= sclk
;
684 rdev
->clock
.default_mclk
= mclk
;
691 bool radeon_combios_sideport_present(struct radeon_device
*rdev
)
693 struct drm_device
*dev
= rdev
->ddev
;
696 igp_info
= combios_get_table_offset(dev
, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
);
699 if (RBIOS16(igp_info
+ 0x4))
705 static const uint32_t default_primarydac_adj
[CHIP_LAST
] = {
706 0x00000808, /* r100 */
707 0x00000808, /* rv100 */
708 0x00000808, /* rs100 */
709 0x00000808, /* rv200 */
710 0x00000808, /* rs200 */
711 0x00000808, /* r200 */
712 0x00000808, /* rv250 */
713 0x00000000, /* rs300 */
714 0x00000808, /* rv280 */
715 0x00000808, /* r300 */
716 0x00000808, /* r350 */
717 0x00000808, /* rv350 */
718 0x00000808, /* rv380 */
719 0x00000808, /* r420 */
720 0x00000808, /* r423 */
721 0x00000808, /* rv410 */
722 0x00000000, /* rs400 */
723 0x00000000, /* rs480 */
726 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device
*rdev
,
727 struct radeon_encoder_primary_dac
*p_dac
)
729 p_dac
->ps2_pdac_adj
= default_primarydac_adj
[rdev
->family
];
733 struct radeon_encoder_primary_dac
*radeon_combios_get_primary_dac_info(struct
737 struct drm_device
*dev
= encoder
->base
.dev
;
738 struct radeon_device
*rdev
= dev
->dev_private
;
740 uint8_t rev
, bg
, dac
;
741 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
744 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
),
750 /* check CRT table */
751 dac_info
= combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
753 rev
= RBIOS8(dac_info
) & 0x3;
755 bg
= RBIOS8(dac_info
+ 0x2) & 0xf;
756 dac
= (RBIOS8(dac_info
+ 0x2) >> 4) & 0xf;
757 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
759 bg
= RBIOS8(dac_info
+ 0x2) & 0xf;
760 dac
= RBIOS8(dac_info
+ 0x3) & 0xf;
761 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
763 /* if the values are all zeros, use the table */
764 if (p_dac
->ps2_pdac_adj
)
768 if (!found
) /* fallback to defaults */
769 radeon_legacy_get_primary_dac_info_from_table(rdev
, p_dac
);
775 radeon_combios_get_tv_info(struct radeon_device
*rdev
)
777 struct drm_device
*dev
= rdev
->ddev
;
779 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
781 tv_info
= combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
783 if (RBIOS8(tv_info
+ 6) == 'T') {
784 switch (RBIOS8(tv_info
+ 7) & 0xf) {
786 tv_std
= TV_STD_NTSC
;
787 DRM_INFO("Default TV standard: NTSC\n");
791 DRM_INFO("Default TV standard: PAL\n");
794 tv_std
= TV_STD_PAL_M
;
795 DRM_INFO("Default TV standard: PAL-M\n");
798 tv_std
= TV_STD_PAL_60
;
799 DRM_INFO("Default TV standard: PAL-60\n");
802 tv_std
= TV_STD_NTSC_J
;
803 DRM_INFO("Default TV standard: NTSC-J\n");
806 tv_std
= TV_STD_SCART_PAL
;
807 DRM_INFO("Default TV standard: SCART-PAL\n");
810 tv_std
= TV_STD_NTSC
;
812 ("Unknown TV standard; defaulting to NTSC\n");
816 switch ((RBIOS8(tv_info
+ 9) >> 2) & 0x3) {
818 DRM_INFO("29.498928713 MHz TV ref clk\n");
821 DRM_INFO("28.636360000 MHz TV ref clk\n");
824 DRM_INFO("14.318180000 MHz TV ref clk\n");
827 DRM_INFO("27.000000000 MHz TV ref clk\n");
837 static const uint32_t default_tvdac_adj
[CHIP_LAST
] = {
838 0x00000000, /* r100 */
839 0x00280000, /* rv100 */
840 0x00000000, /* rs100 */
841 0x00880000, /* rv200 */
842 0x00000000, /* rs200 */
843 0x00000000, /* r200 */
844 0x00770000, /* rv250 */
845 0x00290000, /* rs300 */
846 0x00560000, /* rv280 */
847 0x00780000, /* r300 */
848 0x00770000, /* r350 */
849 0x00780000, /* rv350 */
850 0x00780000, /* rv380 */
851 0x01080000, /* r420 */
852 0x01080000, /* r423 */
853 0x01080000, /* rv410 */
854 0x00780000, /* rs400 */
855 0x00780000, /* rs480 */
858 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device
*rdev
,
859 struct radeon_encoder_tv_dac
*tv_dac
)
861 tv_dac
->ps2_tvdac_adj
= default_tvdac_adj
[rdev
->family
];
862 if ((rdev
->flags
& RADEON_IS_MOBILITY
) && (rdev
->family
== CHIP_RV250
))
863 tv_dac
->ps2_tvdac_adj
= 0x00880000;
864 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
865 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
869 struct radeon_encoder_tv_dac
*radeon_combios_get_tv_dac_info(struct
873 struct drm_device
*dev
= encoder
->base
.dev
;
874 struct radeon_device
*rdev
= dev
->dev_private
;
876 uint8_t rev
, bg
, dac
;
877 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
880 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
884 /* first check TV table */
885 dac_info
= combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
887 rev
= RBIOS8(dac_info
+ 0x3);
889 bg
= RBIOS8(dac_info
+ 0xc) & 0xf;
890 dac
= RBIOS8(dac_info
+ 0xd) & 0xf;
891 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
893 bg
= RBIOS8(dac_info
+ 0xe) & 0xf;
894 dac
= RBIOS8(dac_info
+ 0xf) & 0xf;
895 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
897 bg
= RBIOS8(dac_info
+ 0x10) & 0xf;
898 dac
= RBIOS8(dac_info
+ 0x11) & 0xf;
899 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
900 /* if the values are all zeros, use the table */
901 if (tv_dac
->ps2_tvdac_adj
)
903 } else if (rev
> 1) {
904 bg
= RBIOS8(dac_info
+ 0xc) & 0xf;
905 dac
= (RBIOS8(dac_info
+ 0xc) >> 4) & 0xf;
906 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
908 bg
= RBIOS8(dac_info
+ 0xd) & 0xf;
909 dac
= (RBIOS8(dac_info
+ 0xd) >> 4) & 0xf;
910 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
912 bg
= RBIOS8(dac_info
+ 0xe) & 0xf;
913 dac
= (RBIOS8(dac_info
+ 0xe) >> 4) & 0xf;
914 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
915 /* if the values are all zeros, use the table */
916 if (tv_dac
->ps2_tvdac_adj
)
919 tv_dac
->tv_std
= radeon_combios_get_tv_info(rdev
);
922 /* then check CRT table */
924 combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
926 rev
= RBIOS8(dac_info
) & 0x3;
928 bg
= RBIOS8(dac_info
+ 0x3) & 0xf;
929 dac
= (RBIOS8(dac_info
+ 0x3) >> 4) & 0xf;
930 tv_dac
->ps2_tvdac_adj
=
931 (bg
<< 16) | (dac
<< 20);
932 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
933 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
934 /* if the values are all zeros, use the table */
935 if (tv_dac
->ps2_tvdac_adj
)
938 bg
= RBIOS8(dac_info
+ 0x4) & 0xf;
939 dac
= RBIOS8(dac_info
+ 0x5) & 0xf;
940 tv_dac
->ps2_tvdac_adj
=
941 (bg
<< 16) | (dac
<< 20);
942 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
943 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
944 /* if the values are all zeros, use the table */
945 if (tv_dac
->ps2_tvdac_adj
)
949 DRM_INFO("No TV DAC info found in BIOS\n");
953 if (!found
) /* fallback to defaults */
954 radeon_legacy_get_tv_dac_info_from_table(rdev
, tv_dac
);
959 static struct radeon_encoder_lvds
*radeon_legacy_get_lvds_info_from_regs(struct
963 struct radeon_encoder_lvds
*lvds
= NULL
;
964 uint32_t fp_vert_stretch
, fp_horz_stretch
;
965 uint32_t ppll_div_sel
, ppll_val
;
966 uint32_t lvds_ss_gen_cntl
= RREG32(RADEON_LVDS_SS_GEN_CNTL
);
968 lvds
= kzalloc(sizeof(struct radeon_encoder_lvds
), GFP_KERNEL
);
973 fp_vert_stretch
= RREG32(RADEON_FP_VERT_STRETCH
);
974 fp_horz_stretch
= RREG32(RADEON_FP_HORZ_STRETCH
);
976 /* These should be fail-safe defaults, fingers crossed */
977 lvds
->panel_pwr_delay
= 200;
978 lvds
->panel_vcc_delay
= 2000;
980 lvds
->lvds_gen_cntl
= RREG32(RADEON_LVDS_GEN_CNTL
);
981 lvds
->panel_digon_delay
= (lvds_ss_gen_cntl
>> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT
) & 0xf;
982 lvds
->panel_blon_delay
= (lvds_ss_gen_cntl
>> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT
) & 0xf;
984 if (fp_vert_stretch
& RADEON_VERT_STRETCH_ENABLE
)
985 lvds
->native_mode
.vdisplay
=
986 ((fp_vert_stretch
& RADEON_VERT_PANEL_SIZE
) >>
987 RADEON_VERT_PANEL_SHIFT
) + 1;
989 lvds
->native_mode
.vdisplay
=
990 (RREG32(RADEON_CRTC_V_TOTAL_DISP
) >> 16) + 1;
992 if (fp_horz_stretch
& RADEON_HORZ_STRETCH_ENABLE
)
993 lvds
->native_mode
.hdisplay
=
994 (((fp_horz_stretch
& RADEON_HORZ_PANEL_SIZE
) >>
995 RADEON_HORZ_PANEL_SHIFT
) + 1) * 8;
997 lvds
->native_mode
.hdisplay
=
998 ((RREG32(RADEON_CRTC_H_TOTAL_DISP
) >> 16) + 1) * 8;
1000 if ((lvds
->native_mode
.hdisplay
< 640) ||
1001 (lvds
->native_mode
.vdisplay
< 480)) {
1002 lvds
->native_mode
.hdisplay
= 640;
1003 lvds
->native_mode
.vdisplay
= 480;
1006 ppll_div_sel
= RREG8(RADEON_CLOCK_CNTL_INDEX
+ 1) & 0x3;
1007 ppll_val
= RREG32_PLL(RADEON_PPLL_DIV_0
+ ppll_div_sel
);
1008 if ((ppll_val
& 0x000707ff) == 0x1bb)
1009 lvds
->use_bios_dividers
= false;
1011 lvds
->panel_ref_divider
=
1012 RREG32_PLL(RADEON_PPLL_REF_DIV
) & 0x3ff;
1013 lvds
->panel_post_divider
= (ppll_val
>> 16) & 0x7;
1014 lvds
->panel_fb_divider
= ppll_val
& 0x7ff;
1016 if ((lvds
->panel_ref_divider
!= 0) &&
1017 (lvds
->panel_fb_divider
> 3))
1018 lvds
->use_bios_dividers
= true;
1020 lvds
->panel_vcc_delay
= 200;
1022 DRM_INFO("Panel info derived from registers\n");
1023 DRM_INFO("Panel Size %dx%d\n", lvds
->native_mode
.hdisplay
,
1024 lvds
->native_mode
.vdisplay
);
1029 struct radeon_encoder_lvds
*radeon_combios_get_lvds_info(struct radeon_encoder
1032 struct drm_device
*dev
= encoder
->base
.dev
;
1033 struct radeon_device
*rdev
= dev
->dev_private
;
1035 uint32_t panel_setup
;
1038 struct radeon_encoder_lvds
*lvds
= NULL
;
1040 lcd_info
= combios_get_table_offset(dev
, COMBIOS_LCD_INFO_TABLE
);
1043 lvds
= kzalloc(sizeof(struct radeon_encoder_lvds
), GFP_KERNEL
);
1048 for (i
= 0; i
< 24; i
++)
1049 stmp
[i
] = RBIOS8(lcd_info
+ i
+ 1);
1052 DRM_INFO("Panel ID String: %s\n", stmp
);
1054 lvds
->native_mode
.hdisplay
= RBIOS16(lcd_info
+ 0x19);
1055 lvds
->native_mode
.vdisplay
= RBIOS16(lcd_info
+ 0x1b);
1057 DRM_INFO("Panel Size %dx%d\n", lvds
->native_mode
.hdisplay
,
1058 lvds
->native_mode
.vdisplay
);
1060 lvds
->panel_vcc_delay
= RBIOS16(lcd_info
+ 0x2c);
1061 lvds
->panel_vcc_delay
= min_t(u16
, lvds
->panel_vcc_delay
, 2000);
1063 lvds
->panel_pwr_delay
= RBIOS8(lcd_info
+ 0x24);
1064 lvds
->panel_digon_delay
= RBIOS16(lcd_info
+ 0x38) & 0xf;
1065 lvds
->panel_blon_delay
= (RBIOS16(lcd_info
+ 0x38) >> 4) & 0xf;
1067 lvds
->panel_ref_divider
= RBIOS16(lcd_info
+ 0x2e);
1068 lvds
->panel_post_divider
= RBIOS8(lcd_info
+ 0x30);
1069 lvds
->panel_fb_divider
= RBIOS16(lcd_info
+ 0x31);
1070 if ((lvds
->panel_ref_divider
!= 0) &&
1071 (lvds
->panel_fb_divider
> 3))
1072 lvds
->use_bios_dividers
= true;
1074 panel_setup
= RBIOS32(lcd_info
+ 0x39);
1075 lvds
->lvds_gen_cntl
= 0xff00;
1076 if (panel_setup
& 0x1)
1077 lvds
->lvds_gen_cntl
|= RADEON_LVDS_PANEL_FORMAT
;
1079 if ((panel_setup
>> 4) & 0x1)
1080 lvds
->lvds_gen_cntl
|= RADEON_LVDS_PANEL_TYPE
;
1082 switch ((panel_setup
>> 8) & 0x7) {
1084 lvds
->lvds_gen_cntl
|= RADEON_LVDS_NO_FM
;
1087 lvds
->lvds_gen_cntl
|= RADEON_LVDS_2_GREY
;
1090 lvds
->lvds_gen_cntl
|= RADEON_LVDS_4_GREY
;
1096 if ((panel_setup
>> 16) & 0x1)
1097 lvds
->lvds_gen_cntl
|= RADEON_LVDS_FP_POL_LOW
;
1099 if ((panel_setup
>> 17) & 0x1)
1100 lvds
->lvds_gen_cntl
|= RADEON_LVDS_LP_POL_LOW
;
1102 if ((panel_setup
>> 18) & 0x1)
1103 lvds
->lvds_gen_cntl
|= RADEON_LVDS_DTM_POL_LOW
;
1105 if ((panel_setup
>> 23) & 0x1)
1106 lvds
->lvds_gen_cntl
|= RADEON_LVDS_BL_CLK_SEL
;
1108 lvds
->lvds_gen_cntl
|= (panel_setup
& 0xf0000000);
1110 for (i
= 0; i
< 32; i
++) {
1111 tmp
= RBIOS16(lcd_info
+ 64 + i
* 2);
1115 if ((RBIOS16(tmp
) == lvds
->native_mode
.hdisplay
) &&
1116 (RBIOS16(tmp
+ 2) == lvds
->native_mode
.vdisplay
)) {
1117 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
1118 (RBIOS16(tmp
+ 17) - RBIOS16(tmp
+ 19)) * 8;
1119 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
1120 (RBIOS16(tmp
+ 21) - RBIOS16(tmp
+ 19) - 1) * 8;
1121 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
1122 (RBIOS8(tmp
+ 23) * 8);
1124 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
1125 (RBIOS16(tmp
+ 24) - RBIOS16(tmp
+ 26));
1126 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
1127 ((RBIOS16(tmp
+ 28) & 0x7ff) - RBIOS16(tmp
+ 26));
1128 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
1129 ((RBIOS16(tmp
+ 28) & 0xf800) >> 11);
1131 lvds
->native_mode
.clock
= RBIOS16(tmp
+ 9) * 10;
1132 lvds
->native_mode
.flags
= 0;
1133 /* set crtc values */
1134 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1139 DRM_INFO("No panel info found in BIOS\n");
1140 lvds
= radeon_legacy_get_lvds_info_from_regs(rdev
);
1144 encoder
->native_mode
= lvds
->native_mode
;
1148 static const struct radeon_tmds_pll default_tmds_pll
[CHIP_LAST
][4] = {
1149 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1150 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1151 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1152 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1153 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1154 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1155 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1156 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1157 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1158 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1159 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1160 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1161 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1162 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1163 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1164 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1165 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1166 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1169 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder
*encoder
,
1170 struct radeon_encoder_int_tmds
*tmds
)
1172 struct drm_device
*dev
= encoder
->base
.dev
;
1173 struct radeon_device
*rdev
= dev
->dev_private
;
1176 for (i
= 0; i
< 4; i
++) {
1177 tmds
->tmds_pll
[i
].value
=
1178 default_tmds_pll
[rdev
->family
][i
].value
;
1179 tmds
->tmds_pll
[i
].freq
= default_tmds_pll
[rdev
->family
][i
].freq
;
1185 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder
*encoder
,
1186 struct radeon_encoder_int_tmds
*tmds
)
1188 struct drm_device
*dev
= encoder
->base
.dev
;
1189 struct radeon_device
*rdev
= dev
->dev_private
;
1194 tmds_info
= combios_get_table_offset(dev
, COMBIOS_DFP_INFO_TABLE
);
1197 ver
= RBIOS8(tmds_info
);
1198 DRM_INFO("DFP table revision: %d\n", ver
);
1200 n
= RBIOS8(tmds_info
+ 5) + 1;
1203 for (i
= 0; i
< n
; i
++) {
1204 tmds
->tmds_pll
[i
].value
=
1205 RBIOS32(tmds_info
+ i
* 10 + 0x08);
1206 tmds
->tmds_pll
[i
].freq
=
1207 RBIOS16(tmds_info
+ i
* 10 + 0x10);
1208 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1209 tmds
->tmds_pll
[i
].freq
,
1210 tmds
->tmds_pll
[i
].value
);
1212 } else if (ver
== 4) {
1214 n
= RBIOS8(tmds_info
+ 5) + 1;
1217 for (i
= 0; i
< n
; i
++) {
1218 tmds
->tmds_pll
[i
].value
=
1219 RBIOS32(tmds_info
+ stride
+ 0x08);
1220 tmds
->tmds_pll
[i
].freq
=
1221 RBIOS16(tmds_info
+ stride
+ 0x10);
1226 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1227 tmds
->tmds_pll
[i
].freq
,
1228 tmds
->tmds_pll
[i
].value
);
1232 DRM_INFO("No TMDS info found in BIOS\n");
1238 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder
*encoder
,
1239 struct radeon_encoder_ext_tmds
*tmds
)
1241 struct drm_device
*dev
= encoder
->base
.dev
;
1242 struct radeon_device
*rdev
= dev
->dev_private
;
1243 struct radeon_i2c_bus_rec i2c_bus
;
1245 /* default for macs */
1246 i2c_bus
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_MONID
);
1247 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1249 /* XXX some macs have duallink chips */
1250 switch (rdev
->mode_info
.connector_table
) {
1251 case CT_POWERBOOK_EXTERNAL
:
1252 case CT_MINI_EXTERNAL
:
1254 tmds
->dvo_chip
= DVO_SIL164
;
1255 tmds
->slave_addr
= 0x70 >> 1; /* 7 bit addressing */
1262 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder
*encoder
,
1263 struct radeon_encoder_ext_tmds
*tmds
)
1265 struct drm_device
*dev
= encoder
->base
.dev
;
1266 struct radeon_device
*rdev
= dev
->dev_private
;
1268 uint8_t ver
, id
, blocks
, clk
, data
;
1270 enum radeon_combios_ddc gpio
;
1271 struct radeon_i2c_bus_rec i2c_bus
;
1273 tmds
->i2c_bus
= NULL
;
1274 if (rdev
->flags
& RADEON_IS_IGP
) {
1275 offset
= combios_get_table_offset(dev
, COMBIOS_I2C_INFO_TABLE
);
1277 ver
= RBIOS8(offset
);
1278 DRM_INFO("GPIO Table revision: %d\n", ver
);
1279 blocks
= RBIOS8(offset
+ 2);
1280 for (i
= 0; i
< blocks
; i
++) {
1281 id
= RBIOS8(offset
+ 3 + (i
* 5) + 0);
1283 clk
= RBIOS8(offset
+ 3 + (i
* 5) + 3);
1284 data
= RBIOS8(offset
+ 3 + (i
* 5) + 4);
1285 i2c_bus
.valid
= true;
1286 i2c_bus
.mask_clk_mask
= (1 << clk
);
1287 i2c_bus
.mask_data_mask
= (1 << data
);
1288 i2c_bus
.a_clk_mask
= (1 << clk
);
1289 i2c_bus
.a_data_mask
= (1 << data
);
1290 i2c_bus
.en_clk_mask
= (1 << clk
);
1291 i2c_bus
.en_data_mask
= (1 << data
);
1292 i2c_bus
.y_clk_mask
= (1 << clk
);
1293 i2c_bus
.y_data_mask
= (1 << data
);
1294 i2c_bus
.mask_clk_reg
= RADEON_GPIOPAD_MASK
;
1295 i2c_bus
.mask_data_reg
= RADEON_GPIOPAD_MASK
;
1296 i2c_bus
.a_clk_reg
= RADEON_GPIOPAD_A
;
1297 i2c_bus
.a_data_reg
= RADEON_GPIOPAD_A
;
1298 i2c_bus
.en_clk_reg
= RADEON_GPIOPAD_EN
;
1299 i2c_bus
.en_data_reg
= RADEON_GPIOPAD_EN
;
1300 i2c_bus
.y_clk_reg
= RADEON_GPIOPAD_Y
;
1301 i2c_bus
.y_data_reg
= RADEON_GPIOPAD_Y
;
1302 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1303 tmds
->dvo_chip
= DVO_SIL164
;
1304 tmds
->slave_addr
= 0x70 >> 1; /* 7 bit addressing */
1310 offset
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
1312 ver
= RBIOS8(offset
);
1313 DRM_INFO("External TMDS Table revision: %d\n", ver
);
1314 tmds
->slave_addr
= RBIOS8(offset
+ 4 + 2);
1315 tmds
->slave_addr
>>= 1; /* 7 bit addressing */
1316 gpio
= RBIOS8(offset
+ 4 + 3);
1319 i2c_bus
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_MONID
);
1320 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1323 i2c_bus
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1324 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1327 i2c_bus
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1328 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1331 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1332 if (rdev
->family
>= CHIP_R300
)
1333 i2c_bus
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_MONID
);
1335 i2c_bus
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_CRT2_DDC
);
1336 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1338 case DDC_LCD
: /* MM i2c */
1339 i2c_bus
.valid
= true;
1340 i2c_bus
.hw_capable
= true;
1341 i2c_bus
.mm_i2c
= true;
1342 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1345 DRM_ERROR("Unsupported gpio %d\n", gpio
);
1351 if (!tmds
->i2c_bus
) {
1352 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1359 bool radeon_get_legacy_connector_info_from_table(struct drm_device
*dev
)
1361 struct radeon_device
*rdev
= dev
->dev_private
;
1362 struct radeon_i2c_bus_rec ddc_i2c
;
1363 struct radeon_hpd hpd
;
1365 rdev
->mode_info
.connector_table
= radeon_connector_table
;
1366 if (rdev
->mode_info
.connector_table
== CT_NONE
) {
1367 #ifdef CONFIG_PPC_PMAC
1368 if (of_machine_is_compatible("PowerBook3,3")) {
1369 /* powerbook with VGA */
1370 rdev
->mode_info
.connector_table
= CT_POWERBOOK_VGA
;
1371 } else if (of_machine_is_compatible("PowerBook3,4") ||
1372 of_machine_is_compatible("PowerBook3,5")) {
1373 /* powerbook with internal tmds */
1374 rdev
->mode_info
.connector_table
= CT_POWERBOOK_INTERNAL
;
1375 } else if (of_machine_is_compatible("PowerBook5,1") ||
1376 of_machine_is_compatible("PowerBook5,2") ||
1377 of_machine_is_compatible("PowerBook5,3") ||
1378 of_machine_is_compatible("PowerBook5,4") ||
1379 of_machine_is_compatible("PowerBook5,5")) {
1380 /* powerbook with external single link tmds (sil164) */
1381 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1382 } else if (of_machine_is_compatible("PowerBook5,6")) {
1383 /* powerbook with external dual or single link tmds */
1384 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1385 } else if (of_machine_is_compatible("PowerBook5,7") ||
1386 of_machine_is_compatible("PowerBook5,8") ||
1387 of_machine_is_compatible("PowerBook5,9")) {
1388 /* PowerBook6,2 ? */
1389 /* powerbook with external dual link tmds (sil1178?) */
1390 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1391 } else if (of_machine_is_compatible("PowerBook4,1") ||
1392 of_machine_is_compatible("PowerBook4,2") ||
1393 of_machine_is_compatible("PowerBook4,3") ||
1394 of_machine_is_compatible("PowerBook6,3") ||
1395 of_machine_is_compatible("PowerBook6,5") ||
1396 of_machine_is_compatible("PowerBook6,7")) {
1398 rdev
->mode_info
.connector_table
= CT_IBOOK
;
1399 } else if (of_machine_is_compatible("PowerMac4,4")) {
1401 rdev
->mode_info
.connector_table
= CT_EMAC
;
1402 } else if (of_machine_is_compatible("PowerMac10,1")) {
1403 /* mini with internal tmds */
1404 rdev
->mode_info
.connector_table
= CT_MINI_INTERNAL
;
1405 } else if (of_machine_is_compatible("PowerMac10,2")) {
1406 /* mini with external tmds */
1407 rdev
->mode_info
.connector_table
= CT_MINI_EXTERNAL
;
1408 } else if (of_machine_is_compatible("PowerMac12,1")) {
1410 /* imac g5 isight */
1411 rdev
->mode_info
.connector_table
= CT_IMAC_G5_ISIGHT
;
1413 #endif /* CONFIG_PPC_PMAC */
1414 rdev
->mode_info
.connector_table
= CT_GENERIC
;
1417 switch (rdev
->mode_info
.connector_table
) {
1419 DRM_INFO("Connector Table: %d (generic)\n",
1420 rdev
->mode_info
.connector_table
);
1421 /* these are the most common settings */
1422 if (rdev
->flags
& RADEON_SINGLE_CRTC
) {
1423 /* VGA - primary dac */
1424 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1425 hpd
.hpd
= RADEON_HPD_NONE
;
1426 radeon_add_legacy_encoder(dev
,
1427 radeon_get_encoder_id(dev
,
1428 ATOM_DEVICE_CRT1_SUPPORT
,
1430 ATOM_DEVICE_CRT1_SUPPORT
);
1431 radeon_add_legacy_connector(dev
, 0,
1432 ATOM_DEVICE_CRT1_SUPPORT
,
1433 DRM_MODE_CONNECTOR_VGA
,
1435 CONNECTOR_OBJECT_ID_VGA
,
1437 } else if (rdev
->flags
& RADEON_IS_MOBILITY
) {
1439 ddc_i2c
= combios_setup_i2c_bus(rdev
, 0);
1440 hpd
.hpd
= RADEON_HPD_NONE
;
1441 radeon_add_legacy_encoder(dev
,
1442 radeon_get_encoder_id(dev
,
1443 ATOM_DEVICE_LCD1_SUPPORT
,
1445 ATOM_DEVICE_LCD1_SUPPORT
);
1446 radeon_add_legacy_connector(dev
, 0,
1447 ATOM_DEVICE_LCD1_SUPPORT
,
1448 DRM_MODE_CONNECTOR_LVDS
,
1450 CONNECTOR_OBJECT_ID_LVDS
,
1453 /* VGA - primary dac */
1454 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1455 hpd
.hpd
= RADEON_HPD_NONE
;
1456 radeon_add_legacy_encoder(dev
,
1457 radeon_get_encoder_id(dev
,
1458 ATOM_DEVICE_CRT1_SUPPORT
,
1460 ATOM_DEVICE_CRT1_SUPPORT
);
1461 radeon_add_legacy_connector(dev
, 1,
1462 ATOM_DEVICE_CRT1_SUPPORT
,
1463 DRM_MODE_CONNECTOR_VGA
,
1465 CONNECTOR_OBJECT_ID_VGA
,
1468 /* DVI-I - tv dac, int tmds */
1469 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1470 hpd
.hpd
= RADEON_HPD_1
;
1471 radeon_add_legacy_encoder(dev
,
1472 radeon_get_encoder_id(dev
,
1473 ATOM_DEVICE_DFP1_SUPPORT
,
1475 ATOM_DEVICE_DFP1_SUPPORT
);
1476 radeon_add_legacy_encoder(dev
,
1477 radeon_get_encoder_id(dev
,
1478 ATOM_DEVICE_CRT2_SUPPORT
,
1480 ATOM_DEVICE_CRT2_SUPPORT
);
1481 radeon_add_legacy_connector(dev
, 0,
1482 ATOM_DEVICE_DFP1_SUPPORT
|
1483 ATOM_DEVICE_CRT2_SUPPORT
,
1484 DRM_MODE_CONNECTOR_DVII
,
1486 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1489 /* VGA - primary dac */
1490 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1491 hpd
.hpd
= RADEON_HPD_NONE
;
1492 radeon_add_legacy_encoder(dev
,
1493 radeon_get_encoder_id(dev
,
1494 ATOM_DEVICE_CRT1_SUPPORT
,
1496 ATOM_DEVICE_CRT1_SUPPORT
);
1497 radeon_add_legacy_connector(dev
, 1,
1498 ATOM_DEVICE_CRT1_SUPPORT
,
1499 DRM_MODE_CONNECTOR_VGA
,
1501 CONNECTOR_OBJECT_ID_VGA
,
1505 if (rdev
->family
!= CHIP_R100
&& rdev
->family
!= CHIP_R200
) {
1507 ddc_i2c
.valid
= false;
1508 hpd
.hpd
= RADEON_HPD_NONE
;
1509 radeon_add_legacy_encoder(dev
,
1510 radeon_get_encoder_id(dev
,
1511 ATOM_DEVICE_TV1_SUPPORT
,
1513 ATOM_DEVICE_TV1_SUPPORT
);
1514 radeon_add_legacy_connector(dev
, 2,
1515 ATOM_DEVICE_TV1_SUPPORT
,
1516 DRM_MODE_CONNECTOR_SVIDEO
,
1518 CONNECTOR_OBJECT_ID_SVIDEO
,
1523 DRM_INFO("Connector Table: %d (ibook)\n",
1524 rdev
->mode_info
.connector_table
);
1526 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1527 hpd
.hpd
= RADEON_HPD_NONE
;
1528 radeon_add_legacy_encoder(dev
,
1529 radeon_get_encoder_id(dev
,
1530 ATOM_DEVICE_LCD1_SUPPORT
,
1532 ATOM_DEVICE_LCD1_SUPPORT
);
1533 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1534 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1535 CONNECTOR_OBJECT_ID_LVDS
,
1538 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1539 hpd
.hpd
= RADEON_HPD_NONE
;
1540 radeon_add_legacy_encoder(dev
,
1541 radeon_get_encoder_id(dev
,
1542 ATOM_DEVICE_CRT2_SUPPORT
,
1544 ATOM_DEVICE_CRT2_SUPPORT
);
1545 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1546 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1547 CONNECTOR_OBJECT_ID_VGA
,
1550 ddc_i2c
.valid
= false;
1551 hpd
.hpd
= RADEON_HPD_NONE
;
1552 radeon_add_legacy_encoder(dev
,
1553 radeon_get_encoder_id(dev
,
1554 ATOM_DEVICE_TV1_SUPPORT
,
1556 ATOM_DEVICE_TV1_SUPPORT
);
1557 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1558 DRM_MODE_CONNECTOR_SVIDEO
,
1560 CONNECTOR_OBJECT_ID_SVIDEO
,
1563 case CT_POWERBOOK_EXTERNAL
:
1564 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1565 rdev
->mode_info
.connector_table
);
1567 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1568 hpd
.hpd
= RADEON_HPD_NONE
;
1569 radeon_add_legacy_encoder(dev
,
1570 radeon_get_encoder_id(dev
,
1571 ATOM_DEVICE_LCD1_SUPPORT
,
1573 ATOM_DEVICE_LCD1_SUPPORT
);
1574 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1575 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1576 CONNECTOR_OBJECT_ID_LVDS
,
1578 /* DVI-I - primary dac, ext tmds */
1579 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1580 hpd
.hpd
= RADEON_HPD_2
; /* ??? */
1581 radeon_add_legacy_encoder(dev
,
1582 radeon_get_encoder_id(dev
,
1583 ATOM_DEVICE_DFP2_SUPPORT
,
1585 ATOM_DEVICE_DFP2_SUPPORT
);
1586 radeon_add_legacy_encoder(dev
,
1587 radeon_get_encoder_id(dev
,
1588 ATOM_DEVICE_CRT1_SUPPORT
,
1590 ATOM_DEVICE_CRT1_SUPPORT
);
1591 /* XXX some are SL */
1592 radeon_add_legacy_connector(dev
, 1,
1593 ATOM_DEVICE_DFP2_SUPPORT
|
1594 ATOM_DEVICE_CRT1_SUPPORT
,
1595 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1596 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
,
1599 ddc_i2c
.valid
= false;
1600 hpd
.hpd
= RADEON_HPD_NONE
;
1601 radeon_add_legacy_encoder(dev
,
1602 radeon_get_encoder_id(dev
,
1603 ATOM_DEVICE_TV1_SUPPORT
,
1605 ATOM_DEVICE_TV1_SUPPORT
);
1606 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1607 DRM_MODE_CONNECTOR_SVIDEO
,
1609 CONNECTOR_OBJECT_ID_SVIDEO
,
1612 case CT_POWERBOOK_INTERNAL
:
1613 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1614 rdev
->mode_info
.connector_table
);
1616 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1617 hpd
.hpd
= RADEON_HPD_NONE
;
1618 radeon_add_legacy_encoder(dev
,
1619 radeon_get_encoder_id(dev
,
1620 ATOM_DEVICE_LCD1_SUPPORT
,
1622 ATOM_DEVICE_LCD1_SUPPORT
);
1623 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1624 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1625 CONNECTOR_OBJECT_ID_LVDS
,
1627 /* DVI-I - primary dac, int tmds */
1628 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1629 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
1630 radeon_add_legacy_encoder(dev
,
1631 radeon_get_encoder_id(dev
,
1632 ATOM_DEVICE_DFP1_SUPPORT
,
1634 ATOM_DEVICE_DFP1_SUPPORT
);
1635 radeon_add_legacy_encoder(dev
,
1636 radeon_get_encoder_id(dev
,
1637 ATOM_DEVICE_CRT1_SUPPORT
,
1639 ATOM_DEVICE_CRT1_SUPPORT
);
1640 radeon_add_legacy_connector(dev
, 1,
1641 ATOM_DEVICE_DFP1_SUPPORT
|
1642 ATOM_DEVICE_CRT1_SUPPORT
,
1643 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1644 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1647 ddc_i2c
.valid
= false;
1648 hpd
.hpd
= RADEON_HPD_NONE
;
1649 radeon_add_legacy_encoder(dev
,
1650 radeon_get_encoder_id(dev
,
1651 ATOM_DEVICE_TV1_SUPPORT
,
1653 ATOM_DEVICE_TV1_SUPPORT
);
1654 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1655 DRM_MODE_CONNECTOR_SVIDEO
,
1657 CONNECTOR_OBJECT_ID_SVIDEO
,
1660 case CT_POWERBOOK_VGA
:
1661 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1662 rdev
->mode_info
.connector_table
);
1664 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1665 hpd
.hpd
= RADEON_HPD_NONE
;
1666 radeon_add_legacy_encoder(dev
,
1667 radeon_get_encoder_id(dev
,
1668 ATOM_DEVICE_LCD1_SUPPORT
,
1670 ATOM_DEVICE_LCD1_SUPPORT
);
1671 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1672 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1673 CONNECTOR_OBJECT_ID_LVDS
,
1675 /* VGA - primary dac */
1676 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1677 hpd
.hpd
= RADEON_HPD_NONE
;
1678 radeon_add_legacy_encoder(dev
,
1679 radeon_get_encoder_id(dev
,
1680 ATOM_DEVICE_CRT1_SUPPORT
,
1682 ATOM_DEVICE_CRT1_SUPPORT
);
1683 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT1_SUPPORT
,
1684 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1685 CONNECTOR_OBJECT_ID_VGA
,
1688 ddc_i2c
.valid
= false;
1689 hpd
.hpd
= RADEON_HPD_NONE
;
1690 radeon_add_legacy_encoder(dev
,
1691 radeon_get_encoder_id(dev
,
1692 ATOM_DEVICE_TV1_SUPPORT
,
1694 ATOM_DEVICE_TV1_SUPPORT
);
1695 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1696 DRM_MODE_CONNECTOR_SVIDEO
,
1698 CONNECTOR_OBJECT_ID_SVIDEO
,
1701 case CT_MINI_EXTERNAL
:
1702 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1703 rdev
->mode_info
.connector_table
);
1704 /* DVI-I - tv dac, ext tmds */
1705 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_CRT2_DDC
);
1706 hpd
.hpd
= RADEON_HPD_2
; /* ??? */
1707 radeon_add_legacy_encoder(dev
,
1708 radeon_get_encoder_id(dev
,
1709 ATOM_DEVICE_DFP2_SUPPORT
,
1711 ATOM_DEVICE_DFP2_SUPPORT
);
1712 radeon_add_legacy_encoder(dev
,
1713 radeon_get_encoder_id(dev
,
1714 ATOM_DEVICE_CRT2_SUPPORT
,
1716 ATOM_DEVICE_CRT2_SUPPORT
);
1717 /* XXX are any DL? */
1718 radeon_add_legacy_connector(dev
, 0,
1719 ATOM_DEVICE_DFP2_SUPPORT
|
1720 ATOM_DEVICE_CRT2_SUPPORT
,
1721 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1722 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1725 ddc_i2c
.valid
= false;
1726 hpd
.hpd
= RADEON_HPD_NONE
;
1727 radeon_add_legacy_encoder(dev
,
1728 radeon_get_encoder_id(dev
,
1729 ATOM_DEVICE_TV1_SUPPORT
,
1731 ATOM_DEVICE_TV1_SUPPORT
);
1732 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_TV1_SUPPORT
,
1733 DRM_MODE_CONNECTOR_SVIDEO
,
1735 CONNECTOR_OBJECT_ID_SVIDEO
,
1738 case CT_MINI_INTERNAL
:
1739 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1740 rdev
->mode_info
.connector_table
);
1741 /* DVI-I - tv dac, int tmds */
1742 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_CRT2_DDC
);
1743 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
1744 radeon_add_legacy_encoder(dev
,
1745 radeon_get_encoder_id(dev
,
1746 ATOM_DEVICE_DFP1_SUPPORT
,
1748 ATOM_DEVICE_DFP1_SUPPORT
);
1749 radeon_add_legacy_encoder(dev
,
1750 radeon_get_encoder_id(dev
,
1751 ATOM_DEVICE_CRT2_SUPPORT
,
1753 ATOM_DEVICE_CRT2_SUPPORT
);
1754 radeon_add_legacy_connector(dev
, 0,
1755 ATOM_DEVICE_DFP1_SUPPORT
|
1756 ATOM_DEVICE_CRT2_SUPPORT
,
1757 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1758 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1761 ddc_i2c
.valid
= false;
1762 hpd
.hpd
= RADEON_HPD_NONE
;
1763 radeon_add_legacy_encoder(dev
,
1764 radeon_get_encoder_id(dev
,
1765 ATOM_DEVICE_TV1_SUPPORT
,
1767 ATOM_DEVICE_TV1_SUPPORT
);
1768 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_TV1_SUPPORT
,
1769 DRM_MODE_CONNECTOR_SVIDEO
,
1771 CONNECTOR_OBJECT_ID_SVIDEO
,
1774 case CT_IMAC_G5_ISIGHT
:
1775 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1776 rdev
->mode_info
.connector_table
);
1777 /* DVI-D - int tmds */
1778 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_MONID
);
1779 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
1780 radeon_add_legacy_encoder(dev
,
1781 radeon_get_encoder_id(dev
,
1782 ATOM_DEVICE_DFP1_SUPPORT
,
1784 ATOM_DEVICE_DFP1_SUPPORT
);
1785 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_DFP1_SUPPORT
,
1786 DRM_MODE_CONNECTOR_DVID
, &ddc_i2c
,
1787 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
,
1790 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1791 hpd
.hpd
= RADEON_HPD_NONE
;
1792 radeon_add_legacy_encoder(dev
,
1793 radeon_get_encoder_id(dev
,
1794 ATOM_DEVICE_CRT2_SUPPORT
,
1796 ATOM_DEVICE_CRT2_SUPPORT
);
1797 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1798 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1799 CONNECTOR_OBJECT_ID_VGA
,
1802 ddc_i2c
.valid
= false;
1803 hpd
.hpd
= RADEON_HPD_NONE
;
1804 radeon_add_legacy_encoder(dev
,
1805 radeon_get_encoder_id(dev
,
1806 ATOM_DEVICE_TV1_SUPPORT
,
1808 ATOM_DEVICE_TV1_SUPPORT
);
1809 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1810 DRM_MODE_CONNECTOR_SVIDEO
,
1812 CONNECTOR_OBJECT_ID_SVIDEO
,
1816 DRM_INFO("Connector Table: %d (emac)\n",
1817 rdev
->mode_info
.connector_table
);
1818 /* VGA - primary dac */
1819 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
1820 hpd
.hpd
= RADEON_HPD_NONE
;
1821 radeon_add_legacy_encoder(dev
,
1822 radeon_get_encoder_id(dev
,
1823 ATOM_DEVICE_CRT1_SUPPORT
,
1825 ATOM_DEVICE_CRT1_SUPPORT
);
1826 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_CRT1_SUPPORT
,
1827 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1828 CONNECTOR_OBJECT_ID_VGA
,
1831 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_CRT2_DDC
);
1832 hpd
.hpd
= RADEON_HPD_NONE
;
1833 radeon_add_legacy_encoder(dev
,
1834 radeon_get_encoder_id(dev
,
1835 ATOM_DEVICE_CRT2_SUPPORT
,
1837 ATOM_DEVICE_CRT2_SUPPORT
);
1838 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1839 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1840 CONNECTOR_OBJECT_ID_VGA
,
1843 ddc_i2c
.valid
= false;
1844 hpd
.hpd
= RADEON_HPD_NONE
;
1845 radeon_add_legacy_encoder(dev
,
1846 radeon_get_encoder_id(dev
,
1847 ATOM_DEVICE_TV1_SUPPORT
,
1849 ATOM_DEVICE_TV1_SUPPORT
);
1850 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1851 DRM_MODE_CONNECTOR_SVIDEO
,
1853 CONNECTOR_OBJECT_ID_SVIDEO
,
1857 DRM_INFO("Connector table: %d (invalid)\n",
1858 rdev
->mode_info
.connector_table
);
1862 radeon_link_encoder_connector(dev
);
1867 static bool radeon_apply_legacy_quirks(struct drm_device
*dev
,
1869 enum radeon_combios_connector
1871 struct radeon_i2c_bus_rec
*ddc_i2c
,
1872 struct radeon_hpd
*hpd
)
1874 struct radeon_device
*rdev
= dev
->dev_private
;
1876 /* XPRESS DDC quirks */
1877 if ((rdev
->family
== CHIP_RS400
||
1878 rdev
->family
== CHIP_RS480
) &&
1879 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_CRT2_DDC
)
1880 *ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_MONID
);
1881 else if ((rdev
->family
== CHIP_RS400
||
1882 rdev
->family
== CHIP_RS480
) &&
1883 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_MONID
) {
1884 *ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIOPAD_MASK
);
1885 ddc_i2c
->mask_clk_mask
= (0x20 << 8);
1886 ddc_i2c
->mask_data_mask
= 0x80;
1887 ddc_i2c
->a_clk_mask
= (0x20 << 8);
1888 ddc_i2c
->a_data_mask
= 0x80;
1889 ddc_i2c
->en_clk_mask
= (0x20 << 8);
1890 ddc_i2c
->en_data_mask
= 0x80;
1891 ddc_i2c
->y_clk_mask
= (0x20 << 8);
1892 ddc_i2c
->y_data_mask
= 0x80;
1895 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1896 if ((rdev
->family
>= CHIP_R300
) &&
1897 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_CRT2_DDC
)
1898 *ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
1900 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1901 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1902 if (dev
->pdev
->device
== 0x515e &&
1903 dev
->pdev
->subsystem_vendor
== 0x1014) {
1904 if (*legacy_connector
== CONNECTOR_CRT_LEGACY
&&
1905 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_CRT2_DDC
)
1909 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1910 if (dev
->pdev
->device
== 0x5159 &&
1911 dev
->pdev
->subsystem_vendor
== 0x1002 &&
1912 dev
->pdev
->subsystem_device
== 0x013a) {
1913 if (*legacy_connector
== CONNECTOR_DVI_I_LEGACY
)
1914 *legacy_connector
= CONNECTOR_CRT_LEGACY
;
1918 /* X300 card with extra non-existent DVI port */
1919 if (dev
->pdev
->device
== 0x5B60 &&
1920 dev
->pdev
->subsystem_vendor
== 0x17af &&
1921 dev
->pdev
->subsystem_device
== 0x201e && bios_index
== 2) {
1922 if (*legacy_connector
== CONNECTOR_DVI_I_LEGACY
)
1929 static bool radeon_apply_legacy_tv_quirks(struct drm_device
*dev
)
1931 /* Acer 5102 has non-existent TV port */
1932 if (dev
->pdev
->device
== 0x5975 &&
1933 dev
->pdev
->subsystem_vendor
== 0x1025 &&
1934 dev
->pdev
->subsystem_device
== 0x009f)
1937 /* HP dc5750 has non-existent TV port */
1938 if (dev
->pdev
->device
== 0x5974 &&
1939 dev
->pdev
->subsystem_vendor
== 0x103c &&
1940 dev
->pdev
->subsystem_device
== 0x280a)
1943 /* MSI S270 has non-existent TV port */
1944 if (dev
->pdev
->device
== 0x5955 &&
1945 dev
->pdev
->subsystem_vendor
== 0x1462 &&
1946 dev
->pdev
->subsystem_device
== 0x0131)
1952 static uint16_t combios_check_dl_dvi(struct drm_device
*dev
, int is_dvi_d
)
1954 struct radeon_device
*rdev
= dev
->dev_private
;
1955 uint32_t ext_tmds_info
;
1957 if (rdev
->flags
& RADEON_IS_IGP
) {
1959 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
1961 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
1963 ext_tmds_info
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
1964 if (ext_tmds_info
) {
1965 uint8_t rev
= RBIOS8(ext_tmds_info
);
1966 uint8_t flags
= RBIOS8(ext_tmds_info
+ 4 + 5);
1969 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
1971 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
1975 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
1977 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
1982 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
1984 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
1987 bool radeon_get_legacy_connector_info_from_bios(struct drm_device
*dev
)
1989 struct radeon_device
*rdev
= dev
->dev_private
;
1990 uint32_t conn_info
, entry
, devices
;
1991 uint16_t tmp
, connector_object_id
;
1992 enum radeon_combios_ddc ddc_type
;
1993 enum radeon_combios_connector connector
;
1995 struct radeon_i2c_bus_rec ddc_i2c
;
1996 struct radeon_hpd hpd
;
1998 conn_info
= combios_get_table_offset(dev
, COMBIOS_CONNECTOR_INFO_TABLE
);
2000 for (i
= 0; i
< 4; i
++) {
2001 entry
= conn_info
+ 2 + i
* 2;
2003 if (!RBIOS16(entry
))
2006 tmp
= RBIOS16(entry
);
2008 connector
= (tmp
>> 12) & 0xf;
2010 ddc_type
= (tmp
>> 8) & 0xf;
2014 combios_setup_i2c_bus(rdev
, RADEON_GPIO_MONID
);
2018 combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
2022 combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
2026 combios_setup_i2c_bus(rdev
, RADEON_GPIO_CRT2_DDC
);
2032 switch (connector
) {
2033 case CONNECTOR_PROPRIETARY_LEGACY
:
2034 case CONNECTOR_DVI_I_LEGACY
:
2035 case CONNECTOR_DVI_D_LEGACY
:
2036 if ((tmp
>> 4) & 0x1)
2037 hpd
.hpd
= RADEON_HPD_2
;
2039 hpd
.hpd
= RADEON_HPD_1
;
2042 hpd
.hpd
= RADEON_HPD_NONE
;
2046 if (!radeon_apply_legacy_quirks(dev
, i
, &connector
,
2050 switch (connector
) {
2051 case CONNECTOR_PROPRIETARY_LEGACY
:
2052 if ((tmp
>> 4) & 0x1)
2053 devices
= ATOM_DEVICE_DFP2_SUPPORT
;
2055 devices
= ATOM_DEVICE_DFP1_SUPPORT
;
2056 radeon_add_legacy_encoder(dev
,
2057 radeon_get_encoder_id
2060 radeon_add_legacy_connector(dev
, i
, devices
,
2061 legacy_connector_convert
2064 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
,
2067 case CONNECTOR_CRT_LEGACY
:
2069 devices
= ATOM_DEVICE_CRT2_SUPPORT
;
2070 radeon_add_legacy_encoder(dev
,
2071 radeon_get_encoder_id
2073 ATOM_DEVICE_CRT2_SUPPORT
,
2075 ATOM_DEVICE_CRT2_SUPPORT
);
2077 devices
= ATOM_DEVICE_CRT1_SUPPORT
;
2078 radeon_add_legacy_encoder(dev
,
2079 radeon_get_encoder_id
2081 ATOM_DEVICE_CRT1_SUPPORT
,
2083 ATOM_DEVICE_CRT1_SUPPORT
);
2085 radeon_add_legacy_connector(dev
,
2088 legacy_connector_convert
2091 CONNECTOR_OBJECT_ID_VGA
,
2094 case CONNECTOR_DVI_I_LEGACY
:
2097 devices
|= ATOM_DEVICE_CRT2_SUPPORT
;
2098 radeon_add_legacy_encoder(dev
,
2099 radeon_get_encoder_id
2101 ATOM_DEVICE_CRT2_SUPPORT
,
2103 ATOM_DEVICE_CRT2_SUPPORT
);
2105 devices
|= ATOM_DEVICE_CRT1_SUPPORT
;
2106 radeon_add_legacy_encoder(dev
,
2107 radeon_get_encoder_id
2109 ATOM_DEVICE_CRT1_SUPPORT
,
2111 ATOM_DEVICE_CRT1_SUPPORT
);
2113 if ((tmp
>> 4) & 0x1) {
2114 devices
|= ATOM_DEVICE_DFP2_SUPPORT
;
2115 radeon_add_legacy_encoder(dev
,
2116 radeon_get_encoder_id
2118 ATOM_DEVICE_DFP2_SUPPORT
,
2120 ATOM_DEVICE_DFP2_SUPPORT
);
2121 connector_object_id
= combios_check_dl_dvi(dev
, 0);
2123 devices
|= ATOM_DEVICE_DFP1_SUPPORT
;
2124 radeon_add_legacy_encoder(dev
,
2125 radeon_get_encoder_id
2127 ATOM_DEVICE_DFP1_SUPPORT
,
2129 ATOM_DEVICE_DFP1_SUPPORT
);
2130 connector_object_id
= CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
2132 radeon_add_legacy_connector(dev
,
2135 legacy_connector_convert
2138 connector_object_id
,
2141 case CONNECTOR_DVI_D_LEGACY
:
2142 if ((tmp
>> 4) & 0x1) {
2143 devices
= ATOM_DEVICE_DFP2_SUPPORT
;
2144 connector_object_id
= combios_check_dl_dvi(dev
, 1);
2146 devices
= ATOM_DEVICE_DFP1_SUPPORT
;
2147 connector_object_id
= CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
2149 radeon_add_legacy_encoder(dev
,
2150 radeon_get_encoder_id
2153 radeon_add_legacy_connector(dev
, i
, devices
,
2154 legacy_connector_convert
2157 connector_object_id
,
2160 case CONNECTOR_CTV_LEGACY
:
2161 case CONNECTOR_STV_LEGACY
:
2162 radeon_add_legacy_encoder(dev
,
2163 radeon_get_encoder_id
2165 ATOM_DEVICE_TV1_SUPPORT
,
2167 ATOM_DEVICE_TV1_SUPPORT
);
2168 radeon_add_legacy_connector(dev
, i
,
2169 ATOM_DEVICE_TV1_SUPPORT
,
2170 legacy_connector_convert
2173 CONNECTOR_OBJECT_ID_SVIDEO
,
2177 DRM_ERROR("Unknown connector type: %d\n",
2184 uint16_t tmds_info
=
2185 combios_get_table_offset(dev
, COMBIOS_DFP_INFO_TABLE
);
2187 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2189 radeon_add_legacy_encoder(dev
,
2190 radeon_get_encoder_id(dev
,
2191 ATOM_DEVICE_CRT1_SUPPORT
,
2193 ATOM_DEVICE_CRT1_SUPPORT
);
2194 radeon_add_legacy_encoder(dev
,
2195 radeon_get_encoder_id(dev
,
2196 ATOM_DEVICE_DFP1_SUPPORT
,
2198 ATOM_DEVICE_DFP1_SUPPORT
);
2200 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_DVI_DDC
);
2201 hpd
.hpd
= RADEON_HPD_1
;
2202 radeon_add_legacy_connector(dev
,
2204 ATOM_DEVICE_CRT1_SUPPORT
|
2205 ATOM_DEVICE_DFP1_SUPPORT
,
2206 DRM_MODE_CONNECTOR_DVII
,
2208 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
2212 combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
2213 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2215 radeon_add_legacy_encoder(dev
,
2216 radeon_get_encoder_id(dev
,
2217 ATOM_DEVICE_CRT1_SUPPORT
,
2219 ATOM_DEVICE_CRT1_SUPPORT
);
2220 ddc_i2c
= combios_setup_i2c_bus(rdev
, RADEON_GPIO_VGA_DDC
);
2221 hpd
.hpd
= RADEON_HPD_NONE
;
2222 radeon_add_legacy_connector(dev
,
2224 ATOM_DEVICE_CRT1_SUPPORT
,
2225 DRM_MODE_CONNECTOR_VGA
,
2227 CONNECTOR_OBJECT_ID_VGA
,
2230 DRM_DEBUG("No connector info found\n");
2236 if (rdev
->flags
& RADEON_IS_MOBILITY
|| rdev
->flags
& RADEON_IS_IGP
) {
2238 combios_get_table_offset(dev
, COMBIOS_LCD_INFO_TABLE
);
2240 uint16_t lcd_ddc_info
=
2241 combios_get_table_offset(dev
,
2242 COMBIOS_LCD_DDC_INFO_TABLE
);
2244 radeon_add_legacy_encoder(dev
,
2245 radeon_get_encoder_id(dev
,
2246 ATOM_DEVICE_LCD1_SUPPORT
,
2248 ATOM_DEVICE_LCD1_SUPPORT
);
2251 ddc_type
= RBIOS8(lcd_ddc_info
+ 2);
2255 combios_setup_i2c_bus
2256 (rdev
, RADEON_GPIO_MONID
);
2260 combios_setup_i2c_bus
2261 (rdev
, RADEON_GPIO_DVI_DDC
);
2265 combios_setup_i2c_bus
2266 (rdev
, RADEON_GPIO_VGA_DDC
);
2270 combios_setup_i2c_bus
2271 (rdev
, RADEON_GPIO_CRT2_DDC
);
2275 combios_setup_i2c_bus
2276 (rdev
, RADEON_GPIOPAD_MASK
);
2277 ddc_i2c
.mask_clk_mask
=
2278 RBIOS32(lcd_ddc_info
+ 3);
2279 ddc_i2c
.mask_data_mask
=
2280 RBIOS32(lcd_ddc_info
+ 7);
2281 ddc_i2c
.a_clk_mask
=
2282 RBIOS32(lcd_ddc_info
+ 3);
2283 ddc_i2c
.a_data_mask
=
2284 RBIOS32(lcd_ddc_info
+ 7);
2285 ddc_i2c
.en_clk_mask
=
2286 RBIOS32(lcd_ddc_info
+ 3);
2287 ddc_i2c
.en_data_mask
=
2288 RBIOS32(lcd_ddc_info
+ 7);
2289 ddc_i2c
.y_clk_mask
=
2290 RBIOS32(lcd_ddc_info
+ 3);
2291 ddc_i2c
.y_data_mask
=
2292 RBIOS32(lcd_ddc_info
+ 7);
2296 combios_setup_i2c_bus
2297 (rdev
, RADEON_MDGPIO_MASK
);
2298 ddc_i2c
.mask_clk_mask
=
2299 RBIOS32(lcd_ddc_info
+ 3);
2300 ddc_i2c
.mask_data_mask
=
2301 RBIOS32(lcd_ddc_info
+ 7);
2302 ddc_i2c
.a_clk_mask
=
2303 RBIOS32(lcd_ddc_info
+ 3);
2304 ddc_i2c
.a_data_mask
=
2305 RBIOS32(lcd_ddc_info
+ 7);
2306 ddc_i2c
.en_clk_mask
=
2307 RBIOS32(lcd_ddc_info
+ 3);
2308 ddc_i2c
.en_data_mask
=
2309 RBIOS32(lcd_ddc_info
+ 7);
2310 ddc_i2c
.y_clk_mask
=
2311 RBIOS32(lcd_ddc_info
+ 3);
2312 ddc_i2c
.y_data_mask
=
2313 RBIOS32(lcd_ddc_info
+ 7);
2316 ddc_i2c
.valid
= false;
2319 DRM_DEBUG("LCD DDC Info Table found!\n");
2321 ddc_i2c
.valid
= false;
2323 hpd
.hpd
= RADEON_HPD_NONE
;
2324 radeon_add_legacy_connector(dev
,
2326 ATOM_DEVICE_LCD1_SUPPORT
,
2327 DRM_MODE_CONNECTOR_LVDS
,
2329 CONNECTOR_OBJECT_ID_LVDS
,
2334 /* check TV table */
2335 if (rdev
->family
!= CHIP_R100
&& rdev
->family
!= CHIP_R200
) {
2337 combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
2339 if (RBIOS8(tv_info
+ 6) == 'T') {
2340 if (radeon_apply_legacy_tv_quirks(dev
)) {
2341 hpd
.hpd
= RADEON_HPD_NONE
;
2342 radeon_add_legacy_encoder(dev
,
2343 radeon_get_encoder_id
2345 ATOM_DEVICE_TV1_SUPPORT
,
2347 ATOM_DEVICE_TV1_SUPPORT
);
2348 radeon_add_legacy_connector(dev
, 6,
2349 ATOM_DEVICE_TV1_SUPPORT
,
2350 DRM_MODE_CONNECTOR_SVIDEO
,
2352 CONNECTOR_OBJECT_ID_SVIDEO
,
2359 radeon_link_encoder_connector(dev
);
2364 void radeon_combios_get_power_modes(struct radeon_device
*rdev
)
2366 struct drm_device
*dev
= rdev
->ddev
;
2367 u16 offset
, misc
, misc2
= 0;
2368 u8 rev
, blocks
, tmp
;
2369 int state_index
= 0;
2371 rdev
->pm
.default_power_state_index
= -1;
2373 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
2374 offset
= combios_get_table_offset(dev
, COMBIOS_POWERPLAY_INFO_TABLE
);
2376 rev
= RBIOS8(offset
);
2377 blocks
= RBIOS8(offset
+ 0x2);
2378 /* power mode 0 tends to be the only valid one */
2379 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2380 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= RBIOS32(offset
+ 0x5 + 0x2);
2381 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= RBIOS32(offset
+ 0x5 + 0x6);
2382 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2383 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2385 rdev
->pm
.power_state
[state_index
].type
=
2386 POWER_STATE_TYPE_BATTERY
;
2387 misc
= RBIOS16(offset
+ 0x5 + 0x0);
2389 misc2
= RBIOS16(offset
+ 0x5 + 0xe);
2390 rdev
->pm
.power_state
[state_index
].misc
= misc
;
2391 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
2393 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_GPIO
;
2395 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2398 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2400 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.valid
= true;
2402 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.reg
=
2403 RBIOS16(offset
+ 0x5 + 0xb) * 4;
2404 tmp
= RBIOS8(offset
+ 0x5 + 0xd);
2405 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.mask
= (1 << tmp
);
2407 u8 entries
= RBIOS8(offset
+ 0x5 + 0xb);
2408 u16 voltage_table_offset
= RBIOS16(offset
+ 0x5 + 0xc);
2409 if (entries
&& voltage_table_offset
) {
2410 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.reg
=
2411 RBIOS16(voltage_table_offset
) * 4;
2412 tmp
= RBIOS8(voltage_table_offset
+ 0x2);
2413 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.mask
= (1 << tmp
);
2415 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.valid
= false;
2417 switch ((misc2
& 0x700) >> 8) {
2420 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 0;
2423 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 33;
2426 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 66;
2429 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 99;
2432 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 132;
2436 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2438 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2439 RBIOS8(offset
+ 0x5 + 0x10);
2440 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2443 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2446 /* XXX figure out some good default low power mode for desktop cards */
2450 /* add the default mode */
2451 rdev
->pm
.power_state
[state_index
].type
=
2452 POWER_STATE_TYPE_DEFAULT
;
2453 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2454 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= rdev
->clock
.default_mclk
;
2455 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= rdev
->clock
.default_sclk
;
2456 rdev
->pm
.power_state
[state_index
].default_clock_mode
= &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2457 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2458 rdev
->pm
.power_state
[state_index
].pcie_lanes
= 16;
2459 rdev
->pm
.power_state
[state_index
].flags
= 0;
2460 rdev
->pm
.default_power_state_index
= state_index
;
2461 rdev
->pm
.num_power_states
= state_index
+ 1;
2463 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
2464 rdev
->pm
.current_clock_mode_index
= 0;
2467 void radeon_external_tmds_setup(struct drm_encoder
*encoder
)
2469 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2470 struct radeon_encoder_ext_tmds
*tmds
= radeon_encoder
->enc_priv
;
2475 switch (tmds
->dvo_chip
) {
2478 radeon_i2c_put_byte(tmds
->i2c_bus
,
2481 radeon_i2c_put_byte(tmds
->i2c_bus
,
2484 radeon_i2c_put_byte(tmds
->i2c_bus
,
2487 radeon_i2c_put_byte(tmds
->i2c_bus
,
2490 radeon_i2c_put_byte(tmds
->i2c_bus
,
2495 /* sil 1178 - untested */
2514 bool radeon_combios_external_tmds_setup(struct drm_encoder
*encoder
)
2516 struct drm_device
*dev
= encoder
->dev
;
2517 struct radeon_device
*rdev
= dev
->dev_private
;
2518 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2520 uint8_t blocks
, slave_addr
, rev
;
2522 uint32_t reg
, val
, and_mask
, or_mask
;
2523 struct radeon_encoder_ext_tmds
*tmds
= radeon_encoder
->enc_priv
;
2528 if (rdev
->flags
& RADEON_IS_IGP
) {
2529 offset
= combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_ON_TABLE
);
2530 rev
= RBIOS8(offset
);
2532 rev
= RBIOS8(offset
);
2534 blocks
= RBIOS8(offset
+ 3);
2536 while (blocks
> 0) {
2537 id
= RBIOS16(index
);
2541 reg
= (id
& 0x1fff) * 4;
2542 val
= RBIOS32(index
);
2547 reg
= (id
& 0x1fff) * 4;
2548 and_mask
= RBIOS32(index
);
2550 or_mask
= RBIOS32(index
);
2553 val
= (val
& and_mask
) | or_mask
;
2557 val
= RBIOS16(index
);
2562 val
= RBIOS16(index
);
2567 slave_addr
= id
& 0xff;
2568 slave_addr
>>= 1; /* 7 bit addressing */
2570 reg
= RBIOS8(index
);
2572 val
= RBIOS8(index
);
2574 radeon_i2c_put_byte(tmds
->i2c_bus
,
2579 DRM_ERROR("Unknown id %d\n", id
>> 13);
2588 offset
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
2590 index
= offset
+ 10;
2591 id
= RBIOS16(index
);
2592 while (id
!= 0xffff) {
2596 reg
= (id
& 0x1fff) * 4;
2597 val
= RBIOS32(index
);
2601 reg
= (id
& 0x1fff) * 4;
2602 and_mask
= RBIOS32(index
);
2604 or_mask
= RBIOS32(index
);
2607 val
= (val
& and_mask
) | or_mask
;
2611 val
= RBIOS16(index
);
2617 and_mask
= RBIOS32(index
);
2619 or_mask
= RBIOS32(index
);
2621 val
= RREG32_PLL(reg
);
2622 val
= (val
& and_mask
) | or_mask
;
2623 WREG32_PLL(reg
, val
);
2627 val
= RBIOS8(index
);
2629 radeon_i2c_put_byte(tmds
->i2c_bus
,
2634 DRM_ERROR("Unknown id %d\n", id
>> 13);
2637 id
= RBIOS16(index
);
2645 static void combios_parse_mmio_table(struct drm_device
*dev
, uint16_t offset
)
2647 struct radeon_device
*rdev
= dev
->dev_private
;
2650 while (RBIOS16(offset
)) {
2651 uint16_t cmd
= ((RBIOS16(offset
) & 0xe000) >> 13);
2652 uint32_t addr
= (RBIOS16(offset
) & 0x1fff);
2653 uint32_t val
, and_mask
, or_mask
;
2659 val
= RBIOS32(offset
);
2664 val
= RBIOS32(offset
);
2669 and_mask
= RBIOS32(offset
);
2671 or_mask
= RBIOS32(offset
);
2679 and_mask
= RBIOS32(offset
);
2681 or_mask
= RBIOS32(offset
);
2689 val
= RBIOS16(offset
);
2694 val
= RBIOS16(offset
);
2701 (RADEON_CLK_PWRMGT_CNTL
) &
2708 if ((RREG32(RADEON_MC_STATUS
) &
2724 static void combios_parse_pll_table(struct drm_device
*dev
, uint16_t offset
)
2726 struct radeon_device
*rdev
= dev
->dev_private
;
2729 while (RBIOS8(offset
)) {
2730 uint8_t cmd
= ((RBIOS8(offset
) & 0xc0) >> 6);
2731 uint8_t addr
= (RBIOS8(offset
) & 0x3f);
2732 uint32_t val
, shift
, tmp
;
2733 uint32_t and_mask
, or_mask
;
2738 val
= RBIOS32(offset
);
2740 WREG32_PLL(addr
, val
);
2743 shift
= RBIOS8(offset
) * 8;
2745 and_mask
= RBIOS8(offset
) << shift
;
2746 and_mask
|= ~(0xff << shift
);
2748 or_mask
= RBIOS8(offset
) << shift
;
2750 tmp
= RREG32_PLL(addr
);
2753 WREG32_PLL(addr
, tmp
);
2769 (RADEON_CLK_PWRMGT_CNTL
) &
2777 (RADEON_CLK_PWRMGT_CNTL
) &
2784 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL
);
2785 if (tmp
& RADEON_CG_NO1_DEBUG_0
) {
2787 uint32_t mclk_cntl
=
2790 mclk_cntl
&= 0xffff0000;
2791 /*mclk_cntl |= 0x00001111;*//* ??? */
2792 WREG32_PLL(RADEON_MCLK_CNTL
,
2797 (RADEON_CLK_PWRMGT_CNTL
,
2799 ~RADEON_CG_NO1_DEBUG_0
);
2814 static void combios_parse_ram_reset_table(struct drm_device
*dev
,
2817 struct radeon_device
*rdev
= dev
->dev_private
;
2821 uint8_t val
= RBIOS8(offset
);
2822 while (val
!= 0xff) {
2826 uint32_t channel_complete_mask
;
2828 if (ASIC_IS_R300(rdev
))
2829 channel_complete_mask
=
2830 R300_MEM_PWRUP_COMPLETE
;
2832 channel_complete_mask
=
2833 RADEON_MEM_PWRUP_COMPLETE
;
2836 if ((RREG32(RADEON_MEM_STR_CNTL
) &
2837 channel_complete_mask
) ==
2838 channel_complete_mask
)
2842 uint32_t or_mask
= RBIOS16(offset
);
2845 tmp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
2846 tmp
&= RADEON_SDRAM_MODE_MASK
;
2848 WREG32(RADEON_MEM_SDRAM_MODE_REG
, tmp
);
2850 or_mask
= val
<< 24;
2851 tmp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
2852 tmp
&= RADEON_B3MEM_RESET_MASK
;
2854 WREG32(RADEON_MEM_SDRAM_MODE_REG
, tmp
);
2856 val
= RBIOS8(offset
);
2861 static uint32_t combios_detect_ram(struct drm_device
*dev
, int ram
,
2862 int mem_addr_mapping
)
2864 struct radeon_device
*rdev
= dev
->dev_private
;
2869 mem_cntl
= RREG32(RADEON_MEM_CNTL
);
2870 if (mem_cntl
& RV100_HALF_MODE
)
2873 mem_cntl
&= ~(0xff << 8);
2874 mem_cntl
|= (mem_addr_mapping
& 0xff) << 8;
2875 WREG32(RADEON_MEM_CNTL
, mem_cntl
);
2876 RREG32(RADEON_MEM_CNTL
);
2880 /* something like this???? */
2882 addr
= ram
* 1024 * 1024;
2883 /* write to each page */
2884 WREG32(RADEON_MM_INDEX
, (addr
) | RADEON_MM_APER
);
2885 WREG32(RADEON_MM_DATA
, 0xdeadbeef);
2886 /* read back and verify */
2887 WREG32(RADEON_MM_INDEX
, (addr
) | RADEON_MM_APER
);
2888 if (RREG32(RADEON_MM_DATA
) != 0xdeadbeef)
2895 static void combios_write_ram_size(struct drm_device
*dev
)
2897 struct radeon_device
*rdev
= dev
->dev_private
;
2900 uint32_t mem_size
= 0;
2901 uint32_t mem_cntl
= 0;
2903 /* should do something smarter here I guess... */
2904 if (rdev
->flags
& RADEON_IS_IGP
)
2907 /* first check detected mem table */
2908 offset
= combios_get_table_offset(dev
, COMBIOS_DETECTED_MEM_TABLE
);
2910 rev
= RBIOS8(offset
);
2912 mem_cntl
= RBIOS32(offset
+ 1);
2913 mem_size
= RBIOS16(offset
+ 5);
2914 if (((rdev
->flags
& RADEON_FAMILY_MASK
) < CHIP_R200
) &&
2915 ((dev
->pdev
->device
!= 0x515e)
2916 && (dev
->pdev
->device
!= 0x5969)))
2917 WREG32(RADEON_MEM_CNTL
, mem_cntl
);
2923 combios_get_table_offset(dev
, COMBIOS_MEM_CONFIG_TABLE
);
2925 rev
= RBIOS8(offset
- 1);
2927 if (((rdev
->flags
& RADEON_FAMILY_MASK
) <
2929 && ((dev
->pdev
->device
!= 0x515e)
2930 && (dev
->pdev
->device
!= 0x5969))) {
2932 int mem_addr_mapping
= 0;
2934 while (RBIOS8(offset
)) {
2935 ram
= RBIOS8(offset
);
2938 if (mem_addr_mapping
!= 0x25)
2941 combios_detect_ram(dev
, ram
,
2948 mem_size
= RBIOS8(offset
);
2950 mem_size
= RBIOS8(offset
);
2951 mem_size
*= 2; /* convert to MB */
2956 mem_size
*= (1024 * 1024); /* convert to bytes */
2957 WREG32(RADEON_CONFIG_MEMSIZE
, mem_size
);
2960 void radeon_combios_dyn_clk_setup(struct drm_device
*dev
, int enable
)
2962 uint16_t dyn_clk_info
=
2963 combios_get_table_offset(dev
, COMBIOS_DYN_CLK_1_TABLE
);
2966 combios_parse_pll_table(dev
, dyn_clk_info
);
2969 void radeon_combios_asic_init(struct drm_device
*dev
)
2971 struct radeon_device
*rdev
= dev
->dev_private
;
2974 /* port hardcoded mac stuff from radeonfb */
2975 if (rdev
->bios
== NULL
)
2979 table
= combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_1_TABLE
);
2981 combios_parse_mmio_table(dev
, table
);
2984 table
= combios_get_table_offset(dev
, COMBIOS_PLL_INIT_TABLE
);
2986 combios_parse_pll_table(dev
, table
);
2989 table
= combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_2_TABLE
);
2991 combios_parse_mmio_table(dev
, table
);
2993 if (!(rdev
->flags
& RADEON_IS_IGP
)) {
2996 combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_4_TABLE
);
2998 combios_parse_mmio_table(dev
, table
);
3001 table
= combios_get_table_offset(dev
, COMBIOS_RAM_RESET_TABLE
);
3003 combios_parse_ram_reset_table(dev
, table
);
3007 combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_3_TABLE
);
3009 combios_parse_mmio_table(dev
, table
);
3011 /* write CONFIG_MEMSIZE */
3012 combios_write_ram_size(dev
);
3016 table
= combios_get_table_offset(dev
, COMBIOS_DYN_CLK_1_TABLE
);
3018 combios_parse_pll_table(dev
, table
);
3022 void radeon_combios_initialize_bios_scratch_regs(struct drm_device
*dev
)
3024 struct radeon_device
*rdev
= dev
->dev_private
;
3025 uint32_t bios_0_scratch
, bios_6_scratch
, bios_7_scratch
;
3027 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
3028 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3029 bios_7_scratch
= RREG32(RADEON_BIOS_7_SCRATCH
);
3031 /* let the bios control the backlight */
3032 bios_0_scratch
&= ~RADEON_DRIVER_BRIGHTNESS_EN
;
3034 /* tell the bios not to handle mode switching */
3035 bios_6_scratch
|= (RADEON_DISPLAY_SWITCHING_DIS
|
3036 RADEON_ACC_MODE_CHANGE
);
3038 /* tell the bios a driver is loaded */
3039 bios_7_scratch
|= RADEON_DRV_LOADED
;
3041 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
3042 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
3043 WREG32(RADEON_BIOS_7_SCRATCH
, bios_7_scratch
);
3046 void radeon_combios_output_lock(struct drm_encoder
*encoder
, bool lock
)
3048 struct drm_device
*dev
= encoder
->dev
;
3049 struct radeon_device
*rdev
= dev
->dev_private
;
3050 uint32_t bios_6_scratch
;
3052 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3055 bios_6_scratch
|= RADEON_DRIVER_CRITICAL
;
3057 bios_6_scratch
&= ~RADEON_DRIVER_CRITICAL
;
3059 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
3063 radeon_combios_connected_scratch_regs(struct drm_connector
*connector
,
3064 struct drm_encoder
*encoder
,
3067 struct drm_device
*dev
= connector
->dev
;
3068 struct radeon_device
*rdev
= dev
->dev_private
;
3069 struct radeon_connector
*radeon_connector
=
3070 to_radeon_connector(connector
);
3071 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3072 uint32_t bios_4_scratch
= RREG32(RADEON_BIOS_4_SCRATCH
);
3073 uint32_t bios_5_scratch
= RREG32(RADEON_BIOS_5_SCRATCH
);
3075 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
3076 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
3078 DRM_DEBUG("TV1 connected\n");
3080 bios_4_scratch
|= RADEON_TV1_ATTACHED_SVIDEO
;
3081 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3082 bios_5_scratch
|= RADEON_TV1_ON
;
3083 bios_5_scratch
|= RADEON_ACC_REQ_TV1
;
3085 DRM_DEBUG("TV1 disconnected\n");
3086 bios_4_scratch
&= ~RADEON_TV1_ATTACHED_MASK
;
3087 bios_5_scratch
&= ~RADEON_TV1_ON
;
3088 bios_5_scratch
&= ~RADEON_ACC_REQ_TV1
;
3091 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
3092 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
3094 DRM_DEBUG("LCD1 connected\n");
3095 bios_4_scratch
|= RADEON_LCD1_ATTACHED
;
3096 bios_5_scratch
|= RADEON_LCD1_ON
;
3097 bios_5_scratch
|= RADEON_ACC_REQ_LCD1
;
3099 DRM_DEBUG("LCD1 disconnected\n");
3100 bios_4_scratch
&= ~RADEON_LCD1_ATTACHED
;
3101 bios_5_scratch
&= ~RADEON_LCD1_ON
;
3102 bios_5_scratch
&= ~RADEON_ACC_REQ_LCD1
;
3105 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
3106 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
3108 DRM_DEBUG("CRT1 connected\n");
3109 bios_4_scratch
|= RADEON_CRT1_ATTACHED_COLOR
;
3110 bios_5_scratch
|= RADEON_CRT1_ON
;
3111 bios_5_scratch
|= RADEON_ACC_REQ_CRT1
;
3113 DRM_DEBUG("CRT1 disconnected\n");
3114 bios_4_scratch
&= ~RADEON_CRT1_ATTACHED_MASK
;
3115 bios_5_scratch
&= ~RADEON_CRT1_ON
;
3116 bios_5_scratch
&= ~RADEON_ACC_REQ_CRT1
;
3119 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
3120 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
3122 DRM_DEBUG("CRT2 connected\n");
3123 bios_4_scratch
|= RADEON_CRT2_ATTACHED_COLOR
;
3124 bios_5_scratch
|= RADEON_CRT2_ON
;
3125 bios_5_scratch
|= RADEON_ACC_REQ_CRT2
;
3127 DRM_DEBUG("CRT2 disconnected\n");
3128 bios_4_scratch
&= ~RADEON_CRT2_ATTACHED_MASK
;
3129 bios_5_scratch
&= ~RADEON_CRT2_ON
;
3130 bios_5_scratch
&= ~RADEON_ACC_REQ_CRT2
;
3133 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
3134 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
3136 DRM_DEBUG("DFP1 connected\n");
3137 bios_4_scratch
|= RADEON_DFP1_ATTACHED
;
3138 bios_5_scratch
|= RADEON_DFP1_ON
;
3139 bios_5_scratch
|= RADEON_ACC_REQ_DFP1
;
3141 DRM_DEBUG("DFP1 disconnected\n");
3142 bios_4_scratch
&= ~RADEON_DFP1_ATTACHED
;
3143 bios_5_scratch
&= ~RADEON_DFP1_ON
;
3144 bios_5_scratch
&= ~RADEON_ACC_REQ_DFP1
;
3147 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
3148 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
3150 DRM_DEBUG("DFP2 connected\n");
3151 bios_4_scratch
|= RADEON_DFP2_ATTACHED
;
3152 bios_5_scratch
|= RADEON_DFP2_ON
;
3153 bios_5_scratch
|= RADEON_ACC_REQ_DFP2
;
3155 DRM_DEBUG("DFP2 disconnected\n");
3156 bios_4_scratch
&= ~RADEON_DFP2_ATTACHED
;
3157 bios_5_scratch
&= ~RADEON_DFP2_ON
;
3158 bios_5_scratch
&= ~RADEON_ACC_REQ_DFP2
;
3161 WREG32(RADEON_BIOS_4_SCRATCH
, bios_4_scratch
);
3162 WREG32(RADEON_BIOS_5_SCRATCH
, bios_5_scratch
);
3166 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
3168 struct drm_device
*dev
= encoder
->dev
;
3169 struct radeon_device
*rdev
= dev
->dev_private
;
3170 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3171 uint32_t bios_5_scratch
= RREG32(RADEON_BIOS_5_SCRATCH
);
3173 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
3174 bios_5_scratch
&= ~RADEON_TV1_CRTC_MASK
;
3175 bios_5_scratch
|= (crtc
<< RADEON_TV1_CRTC_SHIFT
);
3177 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
3178 bios_5_scratch
&= ~RADEON_CRT1_CRTC_MASK
;
3179 bios_5_scratch
|= (crtc
<< RADEON_CRT1_CRTC_SHIFT
);
3181 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
3182 bios_5_scratch
&= ~RADEON_CRT2_CRTC_MASK
;
3183 bios_5_scratch
|= (crtc
<< RADEON_CRT2_CRTC_SHIFT
);
3185 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
3186 bios_5_scratch
&= ~RADEON_LCD1_CRTC_MASK
;
3187 bios_5_scratch
|= (crtc
<< RADEON_LCD1_CRTC_SHIFT
);
3189 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
3190 bios_5_scratch
&= ~RADEON_DFP1_CRTC_MASK
;
3191 bios_5_scratch
|= (crtc
<< RADEON_DFP1_CRTC_SHIFT
);
3193 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
3194 bios_5_scratch
&= ~RADEON_DFP2_CRTC_MASK
;
3195 bios_5_scratch
|= (crtc
<< RADEON_DFP2_CRTC_SHIFT
);
3197 WREG32(RADEON_BIOS_5_SCRATCH
, bios_5_scratch
);
3201 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
3203 struct drm_device
*dev
= encoder
->dev
;
3204 struct radeon_device
*rdev
= dev
->dev_private
;
3205 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3206 uint32_t bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3208 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
)) {
3210 bios_6_scratch
|= RADEON_TV_DPMS_ON
;
3212 bios_6_scratch
&= ~RADEON_TV_DPMS_ON
;
3214 if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
3216 bios_6_scratch
|= RADEON_CRT_DPMS_ON
;
3218 bios_6_scratch
&= ~RADEON_CRT_DPMS_ON
;
3220 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
3222 bios_6_scratch
|= RADEON_LCD_DPMS_ON
;
3224 bios_6_scratch
&= ~RADEON_LCD_DPMS_ON
;
3226 if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
3228 bios_6_scratch
|= RADEON_DFP_DPMS_ON
;
3230 bios_6_scratch
&= ~RADEON_DFP_DPMS_ON
;
3232 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);