2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include "radeon_drm.h"
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_id(struct drm_device
*dev
, uint32_t supported_device
,
44 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device
*dev
,
49 uint32_t connector_id
,
50 uint32_t supported_device
,
52 struct radeon_i2c_bus_rec
*i2c_bus
,
53 uint16_t connector_object_id
);
55 /* from radeon_legacy_encoder.c */
57 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_id
,
58 uint32_t supported_device
);
60 /* old legacy ATI BIOS routines */
62 /* COMBIOS table offsets */
63 enum radeon_combios_table_offset
{
64 /* absolute offset tables */
65 COMBIOS_ASIC_INIT_1_TABLE
,
66 COMBIOS_BIOS_SUPPORT_TABLE
,
67 COMBIOS_DAC_PROGRAMMING_TABLE
,
68 COMBIOS_MAX_COLOR_DEPTH_TABLE
,
69 COMBIOS_CRTC_INFO_TABLE
,
70 COMBIOS_PLL_INFO_TABLE
,
71 COMBIOS_TV_INFO_TABLE
,
72 COMBIOS_DFP_INFO_TABLE
,
73 COMBIOS_HW_CONFIG_INFO_TABLE
,
74 COMBIOS_MULTIMEDIA_INFO_TABLE
,
75 COMBIOS_TV_STD_PATCH_TABLE
,
76 COMBIOS_LCD_INFO_TABLE
,
77 COMBIOS_MOBILE_INFO_TABLE
,
78 COMBIOS_PLL_INIT_TABLE
,
79 COMBIOS_MEM_CONFIG_TABLE
,
80 COMBIOS_SAVE_MASK_TABLE
,
81 COMBIOS_HARDCODED_EDID_TABLE
,
82 COMBIOS_ASIC_INIT_2_TABLE
,
83 COMBIOS_CONNECTOR_INFO_TABLE
,
84 COMBIOS_DYN_CLK_1_TABLE
,
85 COMBIOS_RESERVED_MEM_TABLE
,
86 COMBIOS_EXT_TMDS_INFO_TABLE
,
87 COMBIOS_MEM_CLK_INFO_TABLE
,
88 COMBIOS_EXT_DAC_INFO_TABLE
,
89 COMBIOS_MISC_INFO_TABLE
,
90 COMBIOS_CRT_INFO_TABLE
,
91 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
,
92 COMBIOS_COMPONENT_VIDEO_INFO_TABLE
,
93 COMBIOS_FAN_SPEED_INFO_TABLE
,
94 COMBIOS_OVERDRIVE_INFO_TABLE
,
95 COMBIOS_OEM_INFO_TABLE
,
96 COMBIOS_DYN_CLK_2_TABLE
,
97 COMBIOS_POWER_CONNECTOR_INFO_TABLE
,
98 COMBIOS_I2C_INFO_TABLE
,
99 /* relative offset tables */
100 COMBIOS_ASIC_INIT_3_TABLE
, /* offset from misc info */
101 COMBIOS_ASIC_INIT_4_TABLE
, /* offset from misc info */
102 COMBIOS_DETECTED_MEM_TABLE
, /* offset from misc info */
103 COMBIOS_ASIC_INIT_5_TABLE
, /* offset from misc info */
104 COMBIOS_RAM_RESET_TABLE
, /* offset from mem config */
105 COMBIOS_POWERPLAY_INFO_TABLE
, /* offset from mobile info */
106 COMBIOS_GPIO_INFO_TABLE
, /* offset from mobile info */
107 COMBIOS_LCD_DDC_INFO_TABLE
, /* offset from mobile info */
108 COMBIOS_TMDS_POWER_TABLE
, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_ON_TABLE
, /* offset from tmds power */
110 COMBIOS_TMDS_POWER_OFF_TABLE
, /* offset from tmds power */
113 enum radeon_combios_ddc
{
123 enum radeon_combios_connector
{
124 CONNECTOR_NONE_LEGACY
,
125 CONNECTOR_PROPRIETARY_LEGACY
,
126 CONNECTOR_CRT_LEGACY
,
127 CONNECTOR_DVI_I_LEGACY
,
128 CONNECTOR_DVI_D_LEGACY
,
129 CONNECTOR_CTV_LEGACY
,
130 CONNECTOR_STV_LEGACY
,
131 CONNECTOR_UNSUPPORTED_LEGACY
134 const int legacy_connector_convert
[] = {
135 DRM_MODE_CONNECTOR_Unknown
,
136 DRM_MODE_CONNECTOR_DVID
,
137 DRM_MODE_CONNECTOR_VGA
,
138 DRM_MODE_CONNECTOR_DVII
,
139 DRM_MODE_CONNECTOR_DVID
,
140 DRM_MODE_CONNECTOR_Composite
,
141 DRM_MODE_CONNECTOR_SVIDEO
,
142 DRM_MODE_CONNECTOR_Unknown
,
145 static uint16_t combios_get_table_offset(struct drm_device
*dev
,
146 enum radeon_combios_table_offset table
)
148 struct radeon_device
*rdev
= dev
->dev_private
;
150 uint16_t offset
= 0, check_offset
;
153 /* absolute offset tables */
154 case COMBIOS_ASIC_INIT_1_TABLE
:
155 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0xc);
157 offset
= check_offset
;
159 case COMBIOS_BIOS_SUPPORT_TABLE
:
160 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x14);
162 offset
= check_offset
;
164 case COMBIOS_DAC_PROGRAMMING_TABLE
:
165 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2a);
167 offset
= check_offset
;
169 case COMBIOS_MAX_COLOR_DEPTH_TABLE
:
170 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2c);
172 offset
= check_offset
;
174 case COMBIOS_CRTC_INFO_TABLE
:
175 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2e);
177 offset
= check_offset
;
179 case COMBIOS_PLL_INFO_TABLE
:
180 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x30);
182 offset
= check_offset
;
184 case COMBIOS_TV_INFO_TABLE
:
185 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x32);
187 offset
= check_offset
;
189 case COMBIOS_DFP_INFO_TABLE
:
190 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x34);
192 offset
= check_offset
;
194 case COMBIOS_HW_CONFIG_INFO_TABLE
:
195 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x36);
197 offset
= check_offset
;
199 case COMBIOS_MULTIMEDIA_INFO_TABLE
:
200 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x38);
202 offset
= check_offset
;
204 case COMBIOS_TV_STD_PATCH_TABLE
:
205 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x3e);
207 offset
= check_offset
;
209 case COMBIOS_LCD_INFO_TABLE
:
210 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x40);
212 offset
= check_offset
;
214 case COMBIOS_MOBILE_INFO_TABLE
:
215 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x42);
217 offset
= check_offset
;
219 case COMBIOS_PLL_INIT_TABLE
:
220 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x46);
222 offset
= check_offset
;
224 case COMBIOS_MEM_CONFIG_TABLE
:
225 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x48);
227 offset
= check_offset
;
229 case COMBIOS_SAVE_MASK_TABLE
:
230 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4a);
232 offset
= check_offset
;
234 case COMBIOS_HARDCODED_EDID_TABLE
:
235 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4c);
237 offset
= check_offset
;
239 case COMBIOS_ASIC_INIT_2_TABLE
:
240 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4e);
242 offset
= check_offset
;
244 case COMBIOS_CONNECTOR_INFO_TABLE
:
245 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x50);
247 offset
= check_offset
;
249 case COMBIOS_DYN_CLK_1_TABLE
:
250 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x52);
252 offset
= check_offset
;
254 case COMBIOS_RESERVED_MEM_TABLE
:
255 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x54);
257 offset
= check_offset
;
259 case COMBIOS_EXT_TMDS_INFO_TABLE
:
260 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x58);
262 offset
= check_offset
;
264 case COMBIOS_MEM_CLK_INFO_TABLE
:
265 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5a);
267 offset
= check_offset
;
269 case COMBIOS_EXT_DAC_INFO_TABLE
:
270 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5c);
272 offset
= check_offset
;
274 case COMBIOS_MISC_INFO_TABLE
:
275 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5e);
277 offset
= check_offset
;
279 case COMBIOS_CRT_INFO_TABLE
:
280 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x60);
282 offset
= check_offset
;
284 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
:
285 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x62);
287 offset
= check_offset
;
289 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE
:
290 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x64);
292 offset
= check_offset
;
294 case COMBIOS_FAN_SPEED_INFO_TABLE
:
295 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x66);
297 offset
= check_offset
;
299 case COMBIOS_OVERDRIVE_INFO_TABLE
:
300 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x68);
302 offset
= check_offset
;
304 case COMBIOS_OEM_INFO_TABLE
:
305 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6a);
307 offset
= check_offset
;
309 case COMBIOS_DYN_CLK_2_TABLE
:
310 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6c);
312 offset
= check_offset
;
314 case COMBIOS_POWER_CONNECTOR_INFO_TABLE
:
315 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6e);
317 offset
= check_offset
;
319 case COMBIOS_I2C_INFO_TABLE
:
320 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x70);
322 offset
= check_offset
;
324 /* relative offset tables */
325 case COMBIOS_ASIC_INIT_3_TABLE
: /* offset from misc info */
327 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
329 rev
= RBIOS8(check_offset
);
331 check_offset
= RBIOS16(check_offset
+ 0x3);
333 offset
= check_offset
;
337 case COMBIOS_ASIC_INIT_4_TABLE
: /* offset from misc info */
339 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
341 rev
= RBIOS8(check_offset
);
343 check_offset
= RBIOS16(check_offset
+ 0x5);
345 offset
= check_offset
;
349 case COMBIOS_DETECTED_MEM_TABLE
: /* offset from misc info */
351 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
353 rev
= RBIOS8(check_offset
);
355 check_offset
= RBIOS16(check_offset
+ 0x7);
357 offset
= check_offset
;
361 case COMBIOS_ASIC_INIT_5_TABLE
: /* offset from misc info */
363 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
365 rev
= RBIOS8(check_offset
);
367 check_offset
= RBIOS16(check_offset
+ 0x9);
369 offset
= check_offset
;
373 case COMBIOS_RAM_RESET_TABLE
: /* offset from mem config */
375 combios_get_table_offset(dev
, COMBIOS_MEM_CONFIG_TABLE
);
377 while (RBIOS8(check_offset
++));
380 offset
= check_offset
;
383 case COMBIOS_POWERPLAY_INFO_TABLE
: /* offset from mobile info */
385 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
387 check_offset
= RBIOS16(check_offset
+ 0x11);
389 offset
= check_offset
;
392 case COMBIOS_GPIO_INFO_TABLE
: /* offset from mobile info */
394 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
396 check_offset
= RBIOS16(check_offset
+ 0x13);
398 offset
= check_offset
;
401 case COMBIOS_LCD_DDC_INFO_TABLE
: /* offset from mobile info */
403 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
405 check_offset
= RBIOS16(check_offset
+ 0x15);
407 offset
= check_offset
;
410 case COMBIOS_TMDS_POWER_TABLE
: /* offset from mobile info */
412 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
414 check_offset
= RBIOS16(check_offset
+ 0x17);
416 offset
= check_offset
;
419 case COMBIOS_TMDS_POWER_ON_TABLE
: /* offset from tmds power */
421 combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_TABLE
);
423 check_offset
= RBIOS16(check_offset
+ 0x2);
425 offset
= check_offset
;
428 case COMBIOS_TMDS_POWER_OFF_TABLE
: /* offset from tmds power */
430 combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_TABLE
);
432 check_offset
= RBIOS16(check_offset
+ 0x4);
434 offset
= check_offset
;
445 struct radeon_i2c_bus_rec
combios_setup_i2c_bus(int ddc_line
)
447 struct radeon_i2c_bus_rec i2c
;
449 i2c
.mask_clk_mask
= RADEON_GPIO_EN_1
;
450 i2c
.mask_data_mask
= RADEON_GPIO_EN_0
;
451 i2c
.a_clk_mask
= RADEON_GPIO_A_1
;
452 i2c
.a_data_mask
= RADEON_GPIO_A_0
;
453 i2c
.en_clk_mask
= RADEON_GPIO_EN_1
;
454 i2c
.en_data_mask
= RADEON_GPIO_EN_0
;
455 i2c
.y_clk_mask
= RADEON_GPIO_Y_1
;
456 i2c
.y_data_mask
= RADEON_GPIO_Y_0
;
457 if ((ddc_line
== RADEON_LCD_GPIO_MASK
) ||
458 (ddc_line
== RADEON_MDGPIO_EN_REG
)) {
459 i2c
.mask_clk_reg
= ddc_line
;
460 i2c
.mask_data_reg
= ddc_line
;
461 i2c
.a_clk_reg
= ddc_line
;
462 i2c
.a_data_reg
= ddc_line
;
463 i2c
.en_clk_reg
= ddc_line
;
464 i2c
.en_data_reg
= ddc_line
;
465 i2c
.y_clk_reg
= ddc_line
+ 4;
466 i2c
.y_data_reg
= ddc_line
+ 4;
468 i2c
.mask_clk_reg
= ddc_line
;
469 i2c
.mask_data_reg
= ddc_line
;
470 i2c
.a_clk_reg
= ddc_line
;
471 i2c
.a_data_reg
= ddc_line
;
472 i2c
.en_clk_reg
= ddc_line
;
473 i2c
.en_data_reg
= ddc_line
;
474 i2c
.y_clk_reg
= ddc_line
;
475 i2c
.y_data_reg
= ddc_line
;
486 bool radeon_combios_get_clock_info(struct drm_device
*dev
)
488 struct radeon_device
*rdev
= dev
->dev_private
;
490 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
491 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
492 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
493 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
497 if (rdev
->bios
== NULL
)
500 pll_info
= combios_get_table_offset(dev
, COMBIOS_PLL_INFO_TABLE
);
502 rev
= RBIOS8(pll_info
);
505 p1pll
->reference_freq
= RBIOS16(pll_info
+ 0xe);
506 p1pll
->reference_div
= RBIOS16(pll_info
+ 0x10);
507 p1pll
->pll_out_min
= RBIOS32(pll_info
+ 0x12);
508 p1pll
->pll_out_max
= RBIOS32(pll_info
+ 0x16);
511 p1pll
->pll_in_min
= RBIOS32(pll_info
+ 0x36);
512 p1pll
->pll_in_max
= RBIOS32(pll_info
+ 0x3a);
514 p1pll
->pll_in_min
= 40;
515 p1pll
->pll_in_max
= 500;
520 spll
->reference_freq
= RBIOS16(pll_info
+ 0x1a);
521 spll
->reference_div
= RBIOS16(pll_info
+ 0x1c);
522 spll
->pll_out_min
= RBIOS32(pll_info
+ 0x1e);
523 spll
->pll_out_max
= RBIOS32(pll_info
+ 0x22);
526 spll
->pll_in_min
= RBIOS32(pll_info
+ 0x48);
527 spll
->pll_in_max
= RBIOS32(pll_info
+ 0x4c);
530 spll
->pll_in_min
= 40;
531 spll
->pll_in_max
= 500;
535 mpll
->reference_freq
= RBIOS16(pll_info
+ 0x26);
536 mpll
->reference_div
= RBIOS16(pll_info
+ 0x28);
537 mpll
->pll_out_min
= RBIOS32(pll_info
+ 0x2a);
538 mpll
->pll_out_max
= RBIOS32(pll_info
+ 0x2e);
541 mpll
->pll_in_min
= RBIOS32(pll_info
+ 0x5a);
542 mpll
->pll_in_max
= RBIOS32(pll_info
+ 0x5e);
545 mpll
->pll_in_min
= 40;
546 mpll
->pll_in_max
= 500;
549 /* default sclk/mclk */
550 sclk
= RBIOS16(pll_info
+ 0xa);
551 mclk
= RBIOS16(pll_info
+ 0x8);
557 rdev
->clock
.default_sclk
= sclk
;
558 rdev
->clock
.default_mclk
= mclk
;
565 struct radeon_encoder_primary_dac
*radeon_combios_get_primary_dac_info(struct
569 struct drm_device
*dev
= encoder
->base
.dev
;
570 struct radeon_device
*rdev
= dev
->dev_private
;
572 uint8_t rev
, bg
, dac
;
573 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
575 if (rdev
->bios
== NULL
)
578 /* check CRT table */
579 dac_info
= combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
582 kzalloc(sizeof(struct radeon_encoder_primary_dac
),
588 rev
= RBIOS8(dac_info
) & 0x3;
590 bg
= RBIOS8(dac_info
+ 0x2) & 0xf;
591 dac
= (RBIOS8(dac_info
+ 0x2) >> 4) & 0xf;
592 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
594 bg
= RBIOS8(dac_info
+ 0x2) & 0xf;
595 dac
= RBIOS8(dac_info
+ 0x3) & 0xf;
596 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
604 static enum radeon_tv_std
605 radeon_combios_get_tv_info(struct radeon_encoder
*encoder
)
607 struct drm_device
*dev
= encoder
->base
.dev
;
608 struct radeon_device
*rdev
= dev
->dev_private
;
610 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
612 tv_info
= combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
614 if (RBIOS8(tv_info
+ 6) == 'T') {
615 switch (RBIOS8(tv_info
+ 7) & 0xf) {
617 tv_std
= TV_STD_NTSC
;
618 DRM_INFO("Default TV standard: NTSC\n");
622 DRM_INFO("Default TV standard: PAL\n");
625 tv_std
= TV_STD_PAL_M
;
626 DRM_INFO("Default TV standard: PAL-M\n");
629 tv_std
= TV_STD_PAL_60
;
630 DRM_INFO("Default TV standard: PAL-60\n");
633 tv_std
= TV_STD_NTSC_J
;
634 DRM_INFO("Default TV standard: NTSC-J\n");
637 tv_std
= TV_STD_SCART_PAL
;
638 DRM_INFO("Default TV standard: SCART-PAL\n");
641 tv_std
= TV_STD_NTSC
;
643 ("Unknown TV standard; defaulting to NTSC\n");
647 switch ((RBIOS8(tv_info
+ 9) >> 2) & 0x3) {
649 DRM_INFO("29.498928713 MHz TV ref clk\n");
652 DRM_INFO("28.636360000 MHz TV ref clk\n");
655 DRM_INFO("14.318180000 MHz TV ref clk\n");
658 DRM_INFO("27.000000000 MHz TV ref clk\n");
668 static const uint32_t default_tvdac_adj
[CHIP_LAST
] = {
669 0x00000000, /* r100 */
670 0x00280000, /* rv100 */
671 0x00000000, /* rs100 */
672 0x00880000, /* rv200 */
673 0x00000000, /* rs200 */
674 0x00000000, /* r200 */
675 0x00770000, /* rv250 */
676 0x00290000, /* rs300 */
677 0x00560000, /* rv280 */
678 0x00780000, /* r300 */
679 0x00770000, /* r350 */
680 0x00780000, /* rv350 */
681 0x00780000, /* rv380 */
682 0x01080000, /* r420 */
683 0x01080000, /* r423 */
684 0x01080000, /* rv410 */
685 0x00780000, /* rs400 */
686 0x00780000, /* rs480 */
689 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device
*rdev
,
690 struct radeon_encoder_tv_dac
*tv_dac
)
692 tv_dac
->ps2_tvdac_adj
= default_tvdac_adj
[rdev
->family
];
693 if ((rdev
->flags
& RADEON_IS_MOBILITY
) && (rdev
->family
== CHIP_RV250
))
694 tv_dac
->ps2_tvdac_adj
= 0x00880000;
695 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
696 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
700 struct radeon_encoder_tv_dac
*radeon_combios_get_tv_dac_info(struct
704 struct drm_device
*dev
= encoder
->base
.dev
;
705 struct radeon_device
*rdev
= dev
->dev_private
;
707 uint8_t rev
, bg
, dac
;
708 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
711 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
715 if (rdev
->bios
== NULL
)
718 /* first check TV table */
719 dac_info
= combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
721 rev
= RBIOS8(dac_info
+ 0x3);
723 bg
= RBIOS8(dac_info
+ 0xc) & 0xf;
724 dac
= RBIOS8(dac_info
+ 0xd) & 0xf;
725 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
727 bg
= RBIOS8(dac_info
+ 0xe) & 0xf;
728 dac
= RBIOS8(dac_info
+ 0xf) & 0xf;
729 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
731 bg
= RBIOS8(dac_info
+ 0x10) & 0xf;
732 dac
= RBIOS8(dac_info
+ 0x11) & 0xf;
733 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
735 } else if (rev
> 1) {
736 bg
= RBIOS8(dac_info
+ 0xc) & 0xf;
737 dac
= (RBIOS8(dac_info
+ 0xc) >> 4) & 0xf;
738 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
740 bg
= RBIOS8(dac_info
+ 0xd) & 0xf;
741 dac
= (RBIOS8(dac_info
+ 0xd) >> 4) & 0xf;
742 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
744 bg
= RBIOS8(dac_info
+ 0xe) & 0xf;
745 dac
= (RBIOS8(dac_info
+ 0xe) >> 4) & 0xf;
746 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
749 tv_dac
->tv_std
= radeon_combios_get_tv_info(encoder
);
752 /* then check CRT table */
754 combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
756 rev
= RBIOS8(dac_info
) & 0x3;
758 bg
= RBIOS8(dac_info
+ 0x3) & 0xf;
759 dac
= (RBIOS8(dac_info
+ 0x3) >> 4) & 0xf;
760 tv_dac
->ps2_tvdac_adj
=
761 (bg
<< 16) | (dac
<< 20);
762 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
763 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
766 bg
= RBIOS8(dac_info
+ 0x4) & 0xf;
767 dac
= RBIOS8(dac_info
+ 0x5) & 0xf;
768 tv_dac
->ps2_tvdac_adj
=
769 (bg
<< 16) | (dac
<< 20);
770 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
771 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
775 DRM_INFO("No TV DAC info found in BIOS\n");
780 if (!found
) /* fallback to defaults */
781 radeon_legacy_get_tv_dac_info_from_table(rdev
, tv_dac
);
786 static struct radeon_encoder_lvds
*radeon_legacy_get_lvds_info_from_regs(struct
790 struct radeon_encoder_lvds
*lvds
= NULL
;
791 uint32_t fp_vert_stretch
, fp_horz_stretch
;
792 uint32_t ppll_div_sel
, ppll_val
;
793 uint32_t lvds_ss_gen_cntl
= RREG32(RADEON_LVDS_SS_GEN_CNTL
);
795 lvds
= kzalloc(sizeof(struct radeon_encoder_lvds
), GFP_KERNEL
);
800 fp_vert_stretch
= RREG32(RADEON_FP_VERT_STRETCH
);
801 fp_horz_stretch
= RREG32(RADEON_FP_HORZ_STRETCH
);
803 /* These should be fail-safe defaults, fingers crossed */
804 lvds
->panel_pwr_delay
= 200;
805 lvds
->panel_vcc_delay
= 2000;
807 lvds
->lvds_gen_cntl
= RREG32(RADEON_LVDS_GEN_CNTL
);
808 lvds
->panel_digon_delay
= (lvds_ss_gen_cntl
>> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT
) & 0xf;
809 lvds
->panel_blon_delay
= (lvds_ss_gen_cntl
>> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT
) & 0xf;
811 if (fp_vert_stretch
& RADEON_VERT_STRETCH_ENABLE
)
812 lvds
->native_mode
.vdisplay
=
813 ((fp_vert_stretch
& RADEON_VERT_PANEL_SIZE
) >>
814 RADEON_VERT_PANEL_SHIFT
) + 1;
816 lvds
->native_mode
.vdisplay
=
817 (RREG32(RADEON_CRTC_V_TOTAL_DISP
) >> 16) + 1;
819 if (fp_horz_stretch
& RADEON_HORZ_STRETCH_ENABLE
)
820 lvds
->native_mode
.hdisplay
=
821 (((fp_horz_stretch
& RADEON_HORZ_PANEL_SIZE
) >>
822 RADEON_HORZ_PANEL_SHIFT
) + 1) * 8;
824 lvds
->native_mode
.hdisplay
=
825 ((RREG32(RADEON_CRTC_H_TOTAL_DISP
) >> 16) + 1) * 8;
827 if ((lvds
->native_mode
.hdisplay
< 640) ||
828 (lvds
->native_mode
.vdisplay
< 480)) {
829 lvds
->native_mode
.hdisplay
= 640;
830 lvds
->native_mode
.vdisplay
= 480;
833 ppll_div_sel
= RREG8(RADEON_CLOCK_CNTL_INDEX
+ 1) & 0x3;
834 ppll_val
= RREG32_PLL(RADEON_PPLL_DIV_0
+ ppll_div_sel
);
835 if ((ppll_val
& 0x000707ff) == 0x1bb)
836 lvds
->use_bios_dividers
= false;
838 lvds
->panel_ref_divider
=
839 RREG32_PLL(RADEON_PPLL_REF_DIV
) & 0x3ff;
840 lvds
->panel_post_divider
= (ppll_val
>> 16) & 0x7;
841 lvds
->panel_fb_divider
= ppll_val
& 0x7ff;
843 if ((lvds
->panel_ref_divider
!= 0) &&
844 (lvds
->panel_fb_divider
> 3))
845 lvds
->use_bios_dividers
= true;
847 lvds
->panel_vcc_delay
= 200;
849 DRM_INFO("Panel info derived from registers\n");
850 DRM_INFO("Panel Size %dx%d\n", lvds
->native_mode
.hdisplay
,
851 lvds
->native_mode
.vdisplay
);
856 struct radeon_encoder_lvds
*radeon_combios_get_lvds_info(struct radeon_encoder
859 struct drm_device
*dev
= encoder
->base
.dev
;
860 struct radeon_device
*rdev
= dev
->dev_private
;
862 uint32_t panel_setup
;
865 struct radeon_encoder_lvds
*lvds
= NULL
;
867 if (rdev
->bios
== NULL
) {
868 lvds
= radeon_legacy_get_lvds_info_from_regs(rdev
);
872 lcd_info
= combios_get_table_offset(dev
, COMBIOS_LCD_INFO_TABLE
);
875 lvds
= kzalloc(sizeof(struct radeon_encoder_lvds
), GFP_KERNEL
);
880 for (i
= 0; i
< 24; i
++)
881 stmp
[i
] = RBIOS8(lcd_info
+ i
+ 1);
884 DRM_INFO("Panel ID String: %s\n", stmp
);
886 lvds
->native_mode
.hdisplay
= RBIOS16(lcd_info
+ 0x19);
887 lvds
->native_mode
.vdisplay
= RBIOS16(lcd_info
+ 0x1b);
889 DRM_INFO("Panel Size %dx%d\n", lvds
->native_mode
.hdisplay
,
890 lvds
->native_mode
.vdisplay
);
892 lvds
->panel_vcc_delay
= RBIOS16(lcd_info
+ 0x2c);
893 if (lvds
->panel_vcc_delay
> 2000 || lvds
->panel_vcc_delay
< 0)
894 lvds
->panel_vcc_delay
= 2000;
896 lvds
->panel_pwr_delay
= RBIOS8(lcd_info
+ 0x24);
897 lvds
->panel_digon_delay
= RBIOS16(lcd_info
+ 0x38) & 0xf;
898 lvds
->panel_blon_delay
= (RBIOS16(lcd_info
+ 0x38) >> 4) & 0xf;
900 lvds
->panel_ref_divider
= RBIOS16(lcd_info
+ 0x2e);
901 lvds
->panel_post_divider
= RBIOS8(lcd_info
+ 0x30);
902 lvds
->panel_fb_divider
= RBIOS16(lcd_info
+ 0x31);
903 if ((lvds
->panel_ref_divider
!= 0) &&
904 (lvds
->panel_fb_divider
> 3))
905 lvds
->use_bios_dividers
= true;
907 panel_setup
= RBIOS32(lcd_info
+ 0x39);
908 lvds
->lvds_gen_cntl
= 0xff00;
909 if (panel_setup
& 0x1)
910 lvds
->lvds_gen_cntl
|= RADEON_LVDS_PANEL_FORMAT
;
912 if ((panel_setup
>> 4) & 0x1)
913 lvds
->lvds_gen_cntl
|= RADEON_LVDS_PANEL_TYPE
;
915 switch ((panel_setup
>> 8) & 0x7) {
917 lvds
->lvds_gen_cntl
|= RADEON_LVDS_NO_FM
;
920 lvds
->lvds_gen_cntl
|= RADEON_LVDS_2_GREY
;
923 lvds
->lvds_gen_cntl
|= RADEON_LVDS_4_GREY
;
929 if ((panel_setup
>> 16) & 0x1)
930 lvds
->lvds_gen_cntl
|= RADEON_LVDS_FP_POL_LOW
;
932 if ((panel_setup
>> 17) & 0x1)
933 lvds
->lvds_gen_cntl
|= RADEON_LVDS_LP_POL_LOW
;
935 if ((panel_setup
>> 18) & 0x1)
936 lvds
->lvds_gen_cntl
|= RADEON_LVDS_DTM_POL_LOW
;
938 if ((panel_setup
>> 23) & 0x1)
939 lvds
->lvds_gen_cntl
|= RADEON_LVDS_BL_CLK_SEL
;
941 lvds
->lvds_gen_cntl
|= (panel_setup
& 0xf0000000);
943 for (i
= 0; i
< 32; i
++) {
944 tmp
= RBIOS16(lcd_info
+ 64 + i
* 2);
948 if ((RBIOS16(tmp
) == lvds
->native_mode
.hdisplay
) &&
950 lvds
->native_mode
.vdisplay
)) {
951 lvds
->native_mode
.htotal
= RBIOS16(tmp
+ 17) * 8;
952 lvds
->native_mode
.hsync_start
= RBIOS16(tmp
+ 21) * 8;
953 lvds
->native_mode
.hsync_end
= (RBIOS8(tmp
+ 23) +
954 RBIOS16(tmp
+ 21)) * 8;
956 lvds
->native_mode
.vtotal
= RBIOS16(tmp
+ 24);
957 lvds
->native_mode
.vsync_start
= RBIOS16(tmp
+ 28) & 0x7ff;
958 lvds
->native_mode
.vsync_end
=
959 ((RBIOS16(tmp
+ 28) & 0xf800) >> 11) +
960 (RBIOS16(tmp
+ 28) & 0x7ff);
962 lvds
->native_mode
.clock
= RBIOS16(tmp
+ 9) * 10;
963 lvds
->native_mode
.flags
= 0;
964 /* set crtc values */
965 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
970 DRM_INFO("No panel info found in BIOS\n");
971 lvds
= radeon_legacy_get_lvds_info_from_regs(rdev
);
975 encoder
->native_mode
= lvds
->native_mode
;
979 static const struct radeon_tmds_pll default_tmds_pll
[CHIP_LAST
][4] = {
980 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
981 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
982 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
983 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
984 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
985 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
986 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
987 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
988 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
989 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
990 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
991 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
992 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
993 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
994 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
995 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
996 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
997 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1000 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder
*encoder
,
1001 struct radeon_encoder_int_tmds
*tmds
)
1003 struct drm_device
*dev
= encoder
->base
.dev
;
1004 struct radeon_device
*rdev
= dev
->dev_private
;
1007 for (i
= 0; i
< 4; i
++) {
1008 tmds
->tmds_pll
[i
].value
=
1009 default_tmds_pll
[rdev
->family
][i
].value
;
1010 tmds
->tmds_pll
[i
].freq
= default_tmds_pll
[rdev
->family
][i
].freq
;
1016 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder
*encoder
,
1017 struct radeon_encoder_int_tmds
*tmds
)
1019 struct drm_device
*dev
= encoder
->base
.dev
;
1020 struct radeon_device
*rdev
= dev
->dev_private
;
1025 if (rdev
->bios
== NULL
)
1028 tmds_info
= combios_get_table_offset(dev
, COMBIOS_DFP_INFO_TABLE
);
1031 ver
= RBIOS8(tmds_info
);
1032 DRM_INFO("DFP table revision: %d\n", ver
);
1034 n
= RBIOS8(tmds_info
+ 5) + 1;
1037 for (i
= 0; i
< n
; i
++) {
1038 tmds
->tmds_pll
[i
].value
=
1039 RBIOS32(tmds_info
+ i
* 10 + 0x08);
1040 tmds
->tmds_pll
[i
].freq
=
1041 RBIOS16(tmds_info
+ i
* 10 + 0x10);
1042 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1043 tmds
->tmds_pll
[i
].freq
,
1044 tmds
->tmds_pll
[i
].value
);
1046 } else if (ver
== 4) {
1048 n
= RBIOS8(tmds_info
+ 5) + 1;
1051 for (i
= 0; i
< n
; i
++) {
1052 tmds
->tmds_pll
[i
].value
=
1053 RBIOS32(tmds_info
+ stride
+ 0x08);
1054 tmds
->tmds_pll
[i
].freq
=
1055 RBIOS16(tmds_info
+ stride
+ 0x10);
1060 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1061 tmds
->tmds_pll
[i
].freq
,
1062 tmds
->tmds_pll
[i
].value
);
1066 DRM_INFO("No TMDS info found in BIOS\n");
1072 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder
*encoder
,
1073 struct radeon_encoder_ext_tmds
*tmds
)
1075 struct drm_device
*dev
= encoder
->base
.dev
;
1076 struct radeon_device
*rdev
= dev
->dev_private
;
1077 struct radeon_i2c_bus_rec i2c_bus
;
1079 /* default for macs */
1080 i2c_bus
= combios_setup_i2c_bus(RADEON_GPIO_MONID
);
1081 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1083 /* XXX some macs have duallink chips */
1084 switch (rdev
->mode_info
.connector_table
) {
1085 case CT_POWERBOOK_EXTERNAL
:
1086 case CT_MINI_EXTERNAL
:
1088 tmds
->dvo_chip
= DVO_SIL164
;
1089 tmds
->slave_addr
= 0x70 >> 1; /* 7 bit addressing */
1096 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder
*encoder
,
1097 struct radeon_encoder_ext_tmds
*tmds
)
1099 struct drm_device
*dev
= encoder
->base
.dev
;
1100 struct radeon_device
*rdev
= dev
->dev_private
;
1102 uint8_t ver
, id
, blocks
, clk
, data
;
1104 enum radeon_combios_ddc gpio
;
1105 struct radeon_i2c_bus_rec i2c_bus
;
1107 if (rdev
->bios
== NULL
)
1110 tmds
->i2c_bus
= NULL
;
1111 if (rdev
->flags
& RADEON_IS_IGP
) {
1112 offset
= combios_get_table_offset(dev
, COMBIOS_I2C_INFO_TABLE
);
1114 ver
= RBIOS8(offset
);
1115 DRM_INFO("GPIO Table revision: %d\n", ver
);
1116 blocks
= RBIOS8(offset
+ 2);
1117 for (i
= 0; i
< blocks
; i
++) {
1118 id
= RBIOS8(offset
+ 3 + (i
* 5) + 0);
1120 clk
= RBIOS8(offset
+ 3 + (i
* 5) + 3);
1121 data
= RBIOS8(offset
+ 3 + (i
* 5) + 4);
1122 i2c_bus
.valid
= true;
1123 i2c_bus
.mask_clk_mask
= (1 << clk
);
1124 i2c_bus
.mask_data_mask
= (1 << data
);
1125 i2c_bus
.a_clk_mask
= (1 << clk
);
1126 i2c_bus
.a_data_mask
= (1 << data
);
1127 i2c_bus
.en_clk_mask
= (1 << clk
);
1128 i2c_bus
.en_data_mask
= (1 << data
);
1129 i2c_bus
.y_clk_mask
= (1 << clk
);
1130 i2c_bus
.y_data_mask
= (1 << data
);
1131 i2c_bus
.mask_clk_reg
= RADEON_GPIOPAD_MASK
;
1132 i2c_bus
.mask_data_reg
= RADEON_GPIOPAD_MASK
;
1133 i2c_bus
.a_clk_reg
= RADEON_GPIOPAD_A
;
1134 i2c_bus
.a_data_reg
= RADEON_GPIOPAD_A
;
1135 i2c_bus
.en_clk_reg
= RADEON_GPIOPAD_EN
;
1136 i2c_bus
.en_data_reg
= RADEON_GPIOPAD_EN
;
1137 i2c_bus
.y_clk_reg
= RADEON_GPIOPAD_Y
;
1138 i2c_bus
.y_data_reg
= RADEON_GPIOPAD_Y
;
1139 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1140 tmds
->dvo_chip
= DVO_SIL164
;
1141 tmds
->slave_addr
= 0x70 >> 1; /* 7 bit addressing */
1147 offset
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
1149 ver
= RBIOS8(offset
);
1150 DRM_INFO("External TMDS Table revision: %d\n", ver
);
1151 tmds
->slave_addr
= RBIOS8(offset
+ 4 + 2);
1152 tmds
->slave_addr
>>= 1; /* 7 bit addressing */
1153 gpio
= RBIOS8(offset
+ 4 + 3);
1156 i2c_bus
= combios_setup_i2c_bus(RADEON_GPIO_MONID
);
1157 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1160 i2c_bus
= combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC
);
1161 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1164 i2c_bus
= combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC
);
1165 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1168 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1169 if (rdev
->family
>= CHIP_R300
)
1170 i2c_bus
= combios_setup_i2c_bus(RADEON_GPIO_MONID
);
1172 i2c_bus
= combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC
);
1173 tmds
->i2c_bus
= radeon_i2c_create(dev
, &i2c_bus
, "DVO");
1175 case DDC_LCD
: /* MM i2c */
1176 DRM_ERROR("MM i2c requires hw i2c engine\n");
1179 DRM_ERROR("Unsupported gpio %d\n", gpio
);
1185 if (!tmds
->i2c_bus
) {
1186 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1193 bool radeon_get_legacy_connector_info_from_table(struct drm_device
*dev
)
1195 struct radeon_device
*rdev
= dev
->dev_private
;
1196 struct radeon_i2c_bus_rec ddc_i2c
;
1198 rdev
->mode_info
.connector_table
= radeon_connector_table
;
1199 if (rdev
->mode_info
.connector_table
== CT_NONE
) {
1200 #ifdef CONFIG_PPC_PMAC
1201 if (machine_is_compatible("PowerBook3,3")) {
1202 /* powerbook with VGA */
1203 rdev
->mode_info
.connector_table
= CT_POWERBOOK_VGA
;
1204 } else if (machine_is_compatible("PowerBook3,4") ||
1205 machine_is_compatible("PowerBook3,5")) {
1206 /* powerbook with internal tmds */
1207 rdev
->mode_info
.connector_table
= CT_POWERBOOK_INTERNAL
;
1208 } else if (machine_is_compatible("PowerBook5,1") ||
1209 machine_is_compatible("PowerBook5,2") ||
1210 machine_is_compatible("PowerBook5,3") ||
1211 machine_is_compatible("PowerBook5,4") ||
1212 machine_is_compatible("PowerBook5,5")) {
1213 /* powerbook with external single link tmds (sil164) */
1214 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1215 } else if (machine_is_compatible("PowerBook5,6")) {
1216 /* powerbook with external dual or single link tmds */
1217 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1218 } else if (machine_is_compatible("PowerBook5,7") ||
1219 machine_is_compatible("PowerBook5,8") ||
1220 machine_is_compatible("PowerBook5,9")) {
1221 /* PowerBook6,2 ? */
1222 /* powerbook with external dual link tmds (sil1178?) */
1223 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1224 } else if (machine_is_compatible("PowerBook4,1") ||
1225 machine_is_compatible("PowerBook4,2") ||
1226 machine_is_compatible("PowerBook4,3") ||
1227 machine_is_compatible("PowerBook6,3") ||
1228 machine_is_compatible("PowerBook6,5") ||
1229 machine_is_compatible("PowerBook6,7")) {
1231 rdev
->mode_info
.connector_table
= CT_IBOOK
;
1232 } else if (machine_is_compatible("PowerMac4,4")) {
1234 rdev
->mode_info
.connector_table
= CT_EMAC
;
1235 } else if (machine_is_compatible("PowerMac10,1")) {
1236 /* mini with internal tmds */
1237 rdev
->mode_info
.connector_table
= CT_MINI_INTERNAL
;
1238 } else if (machine_is_compatible("PowerMac10,2")) {
1239 /* mini with external tmds */
1240 rdev
->mode_info
.connector_table
= CT_MINI_EXTERNAL
;
1241 } else if (machine_is_compatible("PowerMac12,1")) {
1243 /* imac g5 isight */
1244 rdev
->mode_info
.connector_table
= CT_IMAC_G5_ISIGHT
;
1246 #endif /* CONFIG_PPC_PMAC */
1247 rdev
->mode_info
.connector_table
= CT_GENERIC
;
1250 switch (rdev
->mode_info
.connector_table
) {
1252 DRM_INFO("Connector Table: %d (generic)\n",
1253 rdev
->mode_info
.connector_table
);
1254 /* these are the most common settings */
1255 if (rdev
->flags
& RADEON_SINGLE_CRTC
) {
1256 /* VGA - primary dac */
1257 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC
);
1258 radeon_add_legacy_encoder(dev
,
1259 radeon_get_encoder_id(dev
,
1260 ATOM_DEVICE_CRT1_SUPPORT
,
1262 ATOM_DEVICE_CRT1_SUPPORT
);
1263 radeon_add_legacy_connector(dev
, 0,
1264 ATOM_DEVICE_CRT1_SUPPORT
,
1265 DRM_MODE_CONNECTOR_VGA
,
1267 CONNECTOR_OBJECT_ID_VGA
);
1268 } else if (rdev
->flags
& RADEON_IS_MOBILITY
) {
1270 ddc_i2c
= combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK
);
1271 radeon_add_legacy_encoder(dev
,
1272 radeon_get_encoder_id(dev
,
1273 ATOM_DEVICE_LCD1_SUPPORT
,
1275 ATOM_DEVICE_LCD1_SUPPORT
);
1276 radeon_add_legacy_connector(dev
, 0,
1277 ATOM_DEVICE_LCD1_SUPPORT
,
1278 DRM_MODE_CONNECTOR_LVDS
,
1280 CONNECTOR_OBJECT_ID_LVDS
);
1282 /* VGA - primary dac */
1283 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC
);
1284 radeon_add_legacy_encoder(dev
,
1285 radeon_get_encoder_id(dev
,
1286 ATOM_DEVICE_CRT1_SUPPORT
,
1288 ATOM_DEVICE_CRT1_SUPPORT
);
1289 radeon_add_legacy_connector(dev
, 1,
1290 ATOM_DEVICE_CRT1_SUPPORT
,
1291 DRM_MODE_CONNECTOR_VGA
,
1293 CONNECTOR_OBJECT_ID_VGA
);
1295 /* DVI-I - tv dac, int tmds */
1296 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC
);
1297 radeon_add_legacy_encoder(dev
,
1298 radeon_get_encoder_id(dev
,
1299 ATOM_DEVICE_DFP1_SUPPORT
,
1301 ATOM_DEVICE_DFP1_SUPPORT
);
1302 radeon_add_legacy_encoder(dev
,
1303 radeon_get_encoder_id(dev
,
1304 ATOM_DEVICE_CRT2_SUPPORT
,
1306 ATOM_DEVICE_CRT2_SUPPORT
);
1307 radeon_add_legacy_connector(dev
, 0,
1308 ATOM_DEVICE_DFP1_SUPPORT
|
1309 ATOM_DEVICE_CRT2_SUPPORT
,
1310 DRM_MODE_CONNECTOR_DVII
,
1312 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
);
1314 /* VGA - primary dac */
1315 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC
);
1316 radeon_add_legacy_encoder(dev
,
1317 radeon_get_encoder_id(dev
,
1318 ATOM_DEVICE_CRT1_SUPPORT
,
1320 ATOM_DEVICE_CRT1_SUPPORT
);
1321 radeon_add_legacy_connector(dev
, 1,
1322 ATOM_DEVICE_CRT1_SUPPORT
,
1323 DRM_MODE_CONNECTOR_VGA
,
1325 CONNECTOR_OBJECT_ID_VGA
);
1328 if (rdev
->family
!= CHIP_R100
&& rdev
->family
!= CHIP_R200
) {
1330 radeon_add_legacy_encoder(dev
,
1331 radeon_get_encoder_id(dev
,
1332 ATOM_DEVICE_TV1_SUPPORT
,
1334 ATOM_DEVICE_TV1_SUPPORT
);
1335 radeon_add_legacy_connector(dev
, 2,
1336 ATOM_DEVICE_TV1_SUPPORT
,
1337 DRM_MODE_CONNECTOR_SVIDEO
,
1339 CONNECTOR_OBJECT_ID_SVIDEO
);
1343 DRM_INFO("Connector Table: %d (ibook)\n",
1344 rdev
->mode_info
.connector_table
);
1346 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC
);
1347 radeon_add_legacy_encoder(dev
,
1348 radeon_get_encoder_id(dev
,
1349 ATOM_DEVICE_LCD1_SUPPORT
,
1351 ATOM_DEVICE_LCD1_SUPPORT
);
1352 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1353 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1354 CONNECTOR_OBJECT_ID_LVDS
);
1356 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC
);
1357 radeon_add_legacy_encoder(dev
,
1358 radeon_get_encoder_id(dev
,
1359 ATOM_DEVICE_CRT2_SUPPORT
,
1361 ATOM_DEVICE_CRT2_SUPPORT
);
1362 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1363 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1364 CONNECTOR_OBJECT_ID_VGA
);
1366 radeon_add_legacy_encoder(dev
,
1367 radeon_get_encoder_id(dev
,
1368 ATOM_DEVICE_TV1_SUPPORT
,
1370 ATOM_DEVICE_TV1_SUPPORT
);
1371 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1372 DRM_MODE_CONNECTOR_SVIDEO
,
1374 CONNECTOR_OBJECT_ID_SVIDEO
);
1376 case CT_POWERBOOK_EXTERNAL
:
1377 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1378 rdev
->mode_info
.connector_table
);
1380 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC
);
1381 radeon_add_legacy_encoder(dev
,
1382 radeon_get_encoder_id(dev
,
1383 ATOM_DEVICE_LCD1_SUPPORT
,
1385 ATOM_DEVICE_LCD1_SUPPORT
);
1386 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1387 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1388 CONNECTOR_OBJECT_ID_LVDS
);
1389 /* DVI-I - primary dac, ext tmds */
1390 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC
);
1391 radeon_add_legacy_encoder(dev
,
1392 radeon_get_encoder_id(dev
,
1393 ATOM_DEVICE_DFP2_SUPPORT
,
1395 ATOM_DEVICE_DFP2_SUPPORT
);
1396 radeon_add_legacy_encoder(dev
,
1397 radeon_get_encoder_id(dev
,
1398 ATOM_DEVICE_CRT1_SUPPORT
,
1400 ATOM_DEVICE_CRT1_SUPPORT
);
1401 /* XXX some are SL */
1402 radeon_add_legacy_connector(dev
, 1,
1403 ATOM_DEVICE_DFP2_SUPPORT
|
1404 ATOM_DEVICE_CRT1_SUPPORT
,
1405 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1406 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
);
1408 radeon_add_legacy_encoder(dev
,
1409 radeon_get_encoder_id(dev
,
1410 ATOM_DEVICE_TV1_SUPPORT
,
1412 ATOM_DEVICE_TV1_SUPPORT
);
1413 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1414 DRM_MODE_CONNECTOR_SVIDEO
,
1416 CONNECTOR_OBJECT_ID_SVIDEO
);
1418 case CT_POWERBOOK_INTERNAL
:
1419 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1420 rdev
->mode_info
.connector_table
);
1422 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC
);
1423 radeon_add_legacy_encoder(dev
,
1424 radeon_get_encoder_id(dev
,
1425 ATOM_DEVICE_LCD1_SUPPORT
,
1427 ATOM_DEVICE_LCD1_SUPPORT
);
1428 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1429 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1430 CONNECTOR_OBJECT_ID_LVDS
);
1431 /* DVI-I - primary dac, int tmds */
1432 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC
);
1433 radeon_add_legacy_encoder(dev
,
1434 radeon_get_encoder_id(dev
,
1435 ATOM_DEVICE_DFP1_SUPPORT
,
1437 ATOM_DEVICE_DFP1_SUPPORT
);
1438 radeon_add_legacy_encoder(dev
,
1439 radeon_get_encoder_id(dev
,
1440 ATOM_DEVICE_CRT1_SUPPORT
,
1442 ATOM_DEVICE_CRT1_SUPPORT
);
1443 radeon_add_legacy_connector(dev
, 1,
1444 ATOM_DEVICE_DFP1_SUPPORT
|
1445 ATOM_DEVICE_CRT1_SUPPORT
,
1446 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1447 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
);
1449 radeon_add_legacy_encoder(dev
,
1450 radeon_get_encoder_id(dev
,
1451 ATOM_DEVICE_TV1_SUPPORT
,
1453 ATOM_DEVICE_TV1_SUPPORT
);
1454 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1455 DRM_MODE_CONNECTOR_SVIDEO
,
1457 CONNECTOR_OBJECT_ID_SVIDEO
);
1459 case CT_POWERBOOK_VGA
:
1460 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1461 rdev
->mode_info
.connector_table
);
1463 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC
);
1464 radeon_add_legacy_encoder(dev
,
1465 radeon_get_encoder_id(dev
,
1466 ATOM_DEVICE_LCD1_SUPPORT
,
1468 ATOM_DEVICE_LCD1_SUPPORT
);
1469 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1470 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1471 CONNECTOR_OBJECT_ID_LVDS
);
1472 /* VGA - primary dac */
1473 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC
);
1474 radeon_add_legacy_encoder(dev
,
1475 radeon_get_encoder_id(dev
,
1476 ATOM_DEVICE_CRT1_SUPPORT
,
1478 ATOM_DEVICE_CRT1_SUPPORT
);
1479 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT1_SUPPORT
,
1480 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1481 CONNECTOR_OBJECT_ID_VGA
);
1483 radeon_add_legacy_encoder(dev
,
1484 radeon_get_encoder_id(dev
,
1485 ATOM_DEVICE_TV1_SUPPORT
,
1487 ATOM_DEVICE_TV1_SUPPORT
);
1488 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1489 DRM_MODE_CONNECTOR_SVIDEO
,
1491 CONNECTOR_OBJECT_ID_SVIDEO
);
1493 case CT_MINI_EXTERNAL
:
1494 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1495 rdev
->mode_info
.connector_table
);
1496 /* DVI-I - tv dac, ext tmds */
1497 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC
);
1498 radeon_add_legacy_encoder(dev
,
1499 radeon_get_encoder_id(dev
,
1500 ATOM_DEVICE_DFP2_SUPPORT
,
1502 ATOM_DEVICE_DFP2_SUPPORT
);
1503 radeon_add_legacy_encoder(dev
,
1504 radeon_get_encoder_id(dev
,
1505 ATOM_DEVICE_CRT2_SUPPORT
,
1507 ATOM_DEVICE_CRT2_SUPPORT
);
1508 /* XXX are any DL? */
1509 radeon_add_legacy_connector(dev
, 0,
1510 ATOM_DEVICE_DFP2_SUPPORT
|
1511 ATOM_DEVICE_CRT2_SUPPORT
,
1512 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1513 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
);
1515 radeon_add_legacy_encoder(dev
,
1516 radeon_get_encoder_id(dev
,
1517 ATOM_DEVICE_TV1_SUPPORT
,
1519 ATOM_DEVICE_TV1_SUPPORT
);
1520 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_TV1_SUPPORT
,
1521 DRM_MODE_CONNECTOR_SVIDEO
,
1523 CONNECTOR_OBJECT_ID_SVIDEO
);
1525 case CT_MINI_INTERNAL
:
1526 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1527 rdev
->mode_info
.connector_table
);
1528 /* DVI-I - tv dac, int tmds */
1529 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC
);
1530 radeon_add_legacy_encoder(dev
,
1531 radeon_get_encoder_id(dev
,
1532 ATOM_DEVICE_DFP1_SUPPORT
,
1534 ATOM_DEVICE_DFP1_SUPPORT
);
1535 radeon_add_legacy_encoder(dev
,
1536 radeon_get_encoder_id(dev
,
1537 ATOM_DEVICE_CRT2_SUPPORT
,
1539 ATOM_DEVICE_CRT2_SUPPORT
);
1540 radeon_add_legacy_connector(dev
, 0,
1541 ATOM_DEVICE_DFP1_SUPPORT
|
1542 ATOM_DEVICE_CRT2_SUPPORT
,
1543 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1544 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
);
1546 radeon_add_legacy_encoder(dev
,
1547 radeon_get_encoder_id(dev
,
1548 ATOM_DEVICE_TV1_SUPPORT
,
1550 ATOM_DEVICE_TV1_SUPPORT
);
1551 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_TV1_SUPPORT
,
1552 DRM_MODE_CONNECTOR_SVIDEO
,
1554 CONNECTOR_OBJECT_ID_SVIDEO
);
1556 case CT_IMAC_G5_ISIGHT
:
1557 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1558 rdev
->mode_info
.connector_table
);
1559 /* DVI-D - int tmds */
1560 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_MONID
);
1561 radeon_add_legacy_encoder(dev
,
1562 radeon_get_encoder_id(dev
,
1563 ATOM_DEVICE_DFP1_SUPPORT
,
1565 ATOM_DEVICE_DFP1_SUPPORT
);
1566 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_DFP1_SUPPORT
,
1567 DRM_MODE_CONNECTOR_DVID
, &ddc_i2c
,
1568 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
);
1570 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC
);
1571 radeon_add_legacy_encoder(dev
,
1572 radeon_get_encoder_id(dev
,
1573 ATOM_DEVICE_CRT2_SUPPORT
,
1575 ATOM_DEVICE_CRT2_SUPPORT
);
1576 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1577 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1578 CONNECTOR_OBJECT_ID_VGA
);
1580 radeon_add_legacy_encoder(dev
,
1581 radeon_get_encoder_id(dev
,
1582 ATOM_DEVICE_TV1_SUPPORT
,
1584 ATOM_DEVICE_TV1_SUPPORT
);
1585 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1586 DRM_MODE_CONNECTOR_SVIDEO
,
1588 CONNECTOR_OBJECT_ID_SVIDEO
);
1591 DRM_INFO("Connector Table: %d (emac)\n",
1592 rdev
->mode_info
.connector_table
);
1593 /* VGA - primary dac */
1594 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC
);
1595 radeon_add_legacy_encoder(dev
,
1596 radeon_get_encoder_id(dev
,
1597 ATOM_DEVICE_CRT1_SUPPORT
,
1599 ATOM_DEVICE_CRT1_SUPPORT
);
1600 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_CRT1_SUPPORT
,
1601 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1602 CONNECTOR_OBJECT_ID_VGA
);
1604 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC
);
1605 radeon_add_legacy_encoder(dev
,
1606 radeon_get_encoder_id(dev
,
1607 ATOM_DEVICE_CRT2_SUPPORT
,
1609 ATOM_DEVICE_CRT2_SUPPORT
);
1610 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1611 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1612 CONNECTOR_OBJECT_ID_VGA
);
1614 radeon_add_legacy_encoder(dev
,
1615 radeon_get_encoder_id(dev
,
1616 ATOM_DEVICE_TV1_SUPPORT
,
1618 ATOM_DEVICE_TV1_SUPPORT
);
1619 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1620 DRM_MODE_CONNECTOR_SVIDEO
,
1622 CONNECTOR_OBJECT_ID_SVIDEO
);
1625 DRM_INFO("Connector table: %d (invalid)\n",
1626 rdev
->mode_info
.connector_table
);
1630 radeon_link_encoder_connector(dev
);
1635 static bool radeon_apply_legacy_quirks(struct drm_device
*dev
,
1637 enum radeon_combios_connector
1639 struct radeon_i2c_bus_rec
*ddc_i2c
)
1641 struct radeon_device
*rdev
= dev
->dev_private
;
1643 /* XPRESS DDC quirks */
1644 if ((rdev
->family
== CHIP_RS400
||
1645 rdev
->family
== CHIP_RS480
) &&
1646 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_CRT2_DDC
)
1647 *ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_MONID
);
1648 else if ((rdev
->family
== CHIP_RS400
||
1649 rdev
->family
== CHIP_RS480
) &&
1650 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_MONID
) {
1651 ddc_i2c
->valid
= true;
1652 ddc_i2c
->mask_clk_mask
= (0x20 << 8);
1653 ddc_i2c
->mask_data_mask
= 0x80;
1654 ddc_i2c
->a_clk_mask
= (0x20 << 8);
1655 ddc_i2c
->a_data_mask
= 0x80;
1656 ddc_i2c
->en_clk_mask
= (0x20 << 8);
1657 ddc_i2c
->en_data_mask
= 0x80;
1658 ddc_i2c
->y_clk_mask
= (0x20 << 8);
1659 ddc_i2c
->y_data_mask
= 0x80;
1660 ddc_i2c
->mask_clk_reg
= RADEON_GPIOPAD_MASK
;
1661 ddc_i2c
->mask_data_reg
= RADEON_GPIOPAD_MASK
;
1662 ddc_i2c
->a_clk_reg
= RADEON_GPIOPAD_A
;
1663 ddc_i2c
->a_data_reg
= RADEON_GPIOPAD_A
;
1664 ddc_i2c
->en_clk_reg
= RADEON_GPIOPAD_EN
;
1665 ddc_i2c
->en_data_reg
= RADEON_GPIOPAD_EN
;
1666 ddc_i2c
->y_clk_reg
= RADEON_GPIOPAD_Y
;
1667 ddc_i2c
->y_data_reg
= RADEON_GPIOPAD_Y
;
1670 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1671 if ((rdev
->family
>= CHIP_R300
) &&
1672 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_CRT2_DDC
)
1673 *ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC
);
1675 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1676 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1677 if (dev
->pdev
->device
== 0x515e &&
1678 dev
->pdev
->subsystem_vendor
== 0x1014) {
1679 if (*legacy_connector
== CONNECTOR_CRT_LEGACY
&&
1680 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_CRT2_DDC
)
1684 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1685 if (dev
->pdev
->device
== 0x5159 &&
1686 dev
->pdev
->subsystem_vendor
== 0x1002 &&
1687 dev
->pdev
->subsystem_device
== 0x013a) {
1688 if (*legacy_connector
== CONNECTOR_DVI_I_LEGACY
)
1689 *legacy_connector
= CONNECTOR_CRT_LEGACY
;
1693 /* X300 card with extra non-existent DVI port */
1694 if (dev
->pdev
->device
== 0x5B60 &&
1695 dev
->pdev
->subsystem_vendor
== 0x17af &&
1696 dev
->pdev
->subsystem_device
== 0x201e && bios_index
== 2) {
1697 if (*legacy_connector
== CONNECTOR_DVI_I_LEGACY
)
1704 static bool radeon_apply_legacy_tv_quirks(struct drm_device
*dev
)
1706 /* Acer 5102 has non-existent TV port */
1707 if (dev
->pdev
->device
== 0x5975 &&
1708 dev
->pdev
->subsystem_vendor
== 0x1025 &&
1709 dev
->pdev
->subsystem_device
== 0x009f)
1712 /* HP dc5750 has non-existent TV port */
1713 if (dev
->pdev
->device
== 0x5974 &&
1714 dev
->pdev
->subsystem_vendor
== 0x103c &&
1715 dev
->pdev
->subsystem_device
== 0x280a)
1721 static uint16_t combios_check_dl_dvi(struct drm_device
*dev
, int is_dvi_d
)
1723 struct radeon_device
*rdev
= dev
->dev_private
;
1724 uint32_t ext_tmds_info
;
1726 if (rdev
->flags
& RADEON_IS_IGP
) {
1728 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
1730 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
1732 ext_tmds_info
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
1733 if (ext_tmds_info
) {
1734 uint8_t rev
= RBIOS8(ext_tmds_info
);
1735 uint8_t flags
= RBIOS8(ext_tmds_info
+ 4 + 5);
1738 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
1740 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
1744 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
1746 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
1751 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
1753 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
1756 bool radeon_get_legacy_connector_info_from_bios(struct drm_device
*dev
)
1758 struct radeon_device
*rdev
= dev
->dev_private
;
1759 uint32_t conn_info
, entry
, devices
;
1760 uint16_t tmp
, connector_object_id
;
1761 enum radeon_combios_ddc ddc_type
;
1762 enum radeon_combios_connector connector
;
1764 struct radeon_i2c_bus_rec ddc_i2c
;
1766 if (rdev
->bios
== NULL
)
1769 conn_info
= combios_get_table_offset(dev
, COMBIOS_CONNECTOR_INFO_TABLE
);
1771 for (i
= 0; i
< 4; i
++) {
1772 entry
= conn_info
+ 2 + i
* 2;
1774 if (!RBIOS16(entry
))
1777 tmp
= RBIOS16(entry
);
1779 connector
= (tmp
>> 12) & 0xf;
1781 ddc_type
= (tmp
>> 8) & 0xf;
1785 combios_setup_i2c_bus(RADEON_GPIO_MONID
);
1789 combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC
);
1793 combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC
);
1797 combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC
);
1803 if (!radeon_apply_legacy_quirks(dev
, i
, &connector
,
1807 switch (connector
) {
1808 case CONNECTOR_PROPRIETARY_LEGACY
:
1809 if ((tmp
>> 4) & 0x1)
1810 devices
= ATOM_DEVICE_DFP2_SUPPORT
;
1812 devices
= ATOM_DEVICE_DFP1_SUPPORT
;
1813 radeon_add_legacy_encoder(dev
,
1814 radeon_get_encoder_id
1817 radeon_add_legacy_connector(dev
, i
, devices
,
1818 legacy_connector_convert
1821 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
);
1823 case CONNECTOR_CRT_LEGACY
:
1825 devices
= ATOM_DEVICE_CRT2_SUPPORT
;
1826 radeon_add_legacy_encoder(dev
,
1827 radeon_get_encoder_id
1829 ATOM_DEVICE_CRT2_SUPPORT
,
1831 ATOM_DEVICE_CRT2_SUPPORT
);
1833 devices
= ATOM_DEVICE_CRT1_SUPPORT
;
1834 radeon_add_legacy_encoder(dev
,
1835 radeon_get_encoder_id
1837 ATOM_DEVICE_CRT1_SUPPORT
,
1839 ATOM_DEVICE_CRT1_SUPPORT
);
1841 radeon_add_legacy_connector(dev
,
1844 legacy_connector_convert
1847 CONNECTOR_OBJECT_ID_VGA
);
1849 case CONNECTOR_DVI_I_LEGACY
:
1852 devices
|= ATOM_DEVICE_CRT2_SUPPORT
;
1853 radeon_add_legacy_encoder(dev
,
1854 radeon_get_encoder_id
1856 ATOM_DEVICE_CRT2_SUPPORT
,
1858 ATOM_DEVICE_CRT2_SUPPORT
);
1860 devices
|= ATOM_DEVICE_CRT1_SUPPORT
;
1861 radeon_add_legacy_encoder(dev
,
1862 radeon_get_encoder_id
1864 ATOM_DEVICE_CRT1_SUPPORT
,
1866 ATOM_DEVICE_CRT1_SUPPORT
);
1868 if ((tmp
>> 4) & 0x1) {
1869 devices
|= ATOM_DEVICE_DFP2_SUPPORT
;
1870 radeon_add_legacy_encoder(dev
,
1871 radeon_get_encoder_id
1873 ATOM_DEVICE_DFP2_SUPPORT
,
1875 ATOM_DEVICE_DFP2_SUPPORT
);
1876 connector_object_id
= combios_check_dl_dvi(dev
, 0);
1878 devices
|= ATOM_DEVICE_DFP1_SUPPORT
;
1879 radeon_add_legacy_encoder(dev
,
1880 radeon_get_encoder_id
1882 ATOM_DEVICE_DFP1_SUPPORT
,
1884 ATOM_DEVICE_DFP1_SUPPORT
);
1885 connector_object_id
= CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
1887 radeon_add_legacy_connector(dev
,
1890 legacy_connector_convert
1893 connector_object_id
);
1895 case CONNECTOR_DVI_D_LEGACY
:
1896 if ((tmp
>> 4) & 0x1) {
1897 devices
= ATOM_DEVICE_DFP2_SUPPORT
;
1898 connector_object_id
= combios_check_dl_dvi(dev
, 1);
1900 devices
= ATOM_DEVICE_DFP1_SUPPORT
;
1901 connector_object_id
= CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
1903 radeon_add_legacy_encoder(dev
,
1904 radeon_get_encoder_id
1907 radeon_add_legacy_connector(dev
, i
, devices
,
1908 legacy_connector_convert
1911 connector_object_id
);
1913 case CONNECTOR_CTV_LEGACY
:
1914 case CONNECTOR_STV_LEGACY
:
1915 radeon_add_legacy_encoder(dev
,
1916 radeon_get_encoder_id
1918 ATOM_DEVICE_TV1_SUPPORT
,
1920 ATOM_DEVICE_TV1_SUPPORT
);
1921 radeon_add_legacy_connector(dev
, i
,
1922 ATOM_DEVICE_TV1_SUPPORT
,
1923 legacy_connector_convert
1926 CONNECTOR_OBJECT_ID_SVIDEO
);
1929 DRM_ERROR("Unknown connector type: %d\n",
1936 uint16_t tmds_info
=
1937 combios_get_table_offset(dev
, COMBIOS_DFP_INFO_TABLE
);
1939 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
1941 radeon_add_legacy_encoder(dev
,
1942 radeon_get_encoder_id(dev
,
1943 ATOM_DEVICE_CRT1_SUPPORT
,
1945 ATOM_DEVICE_CRT1_SUPPORT
);
1946 radeon_add_legacy_encoder(dev
,
1947 radeon_get_encoder_id(dev
,
1948 ATOM_DEVICE_DFP1_SUPPORT
,
1950 ATOM_DEVICE_DFP1_SUPPORT
);
1952 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC
);
1953 radeon_add_legacy_connector(dev
,
1955 ATOM_DEVICE_CRT1_SUPPORT
|
1956 ATOM_DEVICE_DFP1_SUPPORT
,
1957 DRM_MODE_CONNECTOR_DVII
,
1959 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
);
1962 combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
1963 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
1965 radeon_add_legacy_encoder(dev
,
1966 radeon_get_encoder_id(dev
,
1967 ATOM_DEVICE_CRT1_SUPPORT
,
1969 ATOM_DEVICE_CRT1_SUPPORT
);
1970 ddc_i2c
= combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC
);
1971 radeon_add_legacy_connector(dev
,
1973 ATOM_DEVICE_CRT1_SUPPORT
,
1974 DRM_MODE_CONNECTOR_VGA
,
1976 CONNECTOR_OBJECT_ID_VGA
);
1978 DRM_DEBUG("No connector info found\n");
1984 if (rdev
->flags
& RADEON_IS_MOBILITY
|| rdev
->flags
& RADEON_IS_IGP
) {
1986 combios_get_table_offset(dev
, COMBIOS_LCD_INFO_TABLE
);
1988 uint16_t lcd_ddc_info
=
1989 combios_get_table_offset(dev
,
1990 COMBIOS_LCD_DDC_INFO_TABLE
);
1992 radeon_add_legacy_encoder(dev
,
1993 radeon_get_encoder_id(dev
,
1994 ATOM_DEVICE_LCD1_SUPPORT
,
1996 ATOM_DEVICE_LCD1_SUPPORT
);
1999 ddc_type
= RBIOS8(lcd_ddc_info
+ 2);
2003 combios_setup_i2c_bus
2004 (RADEON_GPIO_MONID
);
2008 combios_setup_i2c_bus
2009 (RADEON_GPIO_DVI_DDC
);
2013 combios_setup_i2c_bus
2014 (RADEON_GPIO_VGA_DDC
);
2018 combios_setup_i2c_bus
2019 (RADEON_GPIO_CRT2_DDC
);
2023 combios_setup_i2c_bus
2024 (RADEON_LCD_GPIO_MASK
);
2025 ddc_i2c
.mask_clk_mask
=
2026 RBIOS32(lcd_ddc_info
+ 3);
2027 ddc_i2c
.mask_data_mask
=
2028 RBIOS32(lcd_ddc_info
+ 7);
2029 ddc_i2c
.a_clk_mask
=
2030 RBIOS32(lcd_ddc_info
+ 3);
2031 ddc_i2c
.a_data_mask
=
2032 RBIOS32(lcd_ddc_info
+ 7);
2033 ddc_i2c
.en_clk_mask
=
2034 RBIOS32(lcd_ddc_info
+ 3);
2035 ddc_i2c
.en_data_mask
=
2036 RBIOS32(lcd_ddc_info
+ 7);
2037 ddc_i2c
.y_clk_mask
=
2038 RBIOS32(lcd_ddc_info
+ 3);
2039 ddc_i2c
.y_data_mask
=
2040 RBIOS32(lcd_ddc_info
+ 7);
2044 combios_setup_i2c_bus
2045 (RADEON_MDGPIO_EN_REG
);
2046 ddc_i2c
.mask_clk_mask
=
2047 RBIOS32(lcd_ddc_info
+ 3);
2048 ddc_i2c
.mask_data_mask
=
2049 RBIOS32(lcd_ddc_info
+ 7);
2050 ddc_i2c
.a_clk_mask
=
2051 RBIOS32(lcd_ddc_info
+ 3);
2052 ddc_i2c
.a_data_mask
=
2053 RBIOS32(lcd_ddc_info
+ 7);
2054 ddc_i2c
.en_clk_mask
=
2055 RBIOS32(lcd_ddc_info
+ 3);
2056 ddc_i2c
.en_data_mask
=
2057 RBIOS32(lcd_ddc_info
+ 7);
2058 ddc_i2c
.y_clk_mask
=
2059 RBIOS32(lcd_ddc_info
+ 3);
2060 ddc_i2c
.y_data_mask
=
2061 RBIOS32(lcd_ddc_info
+ 7);
2064 ddc_i2c
.valid
= false;
2067 DRM_DEBUG("LCD DDC Info Table found!\n");
2069 ddc_i2c
.valid
= false;
2071 radeon_add_legacy_connector(dev
,
2073 ATOM_DEVICE_LCD1_SUPPORT
,
2074 DRM_MODE_CONNECTOR_LVDS
,
2076 CONNECTOR_OBJECT_ID_LVDS
);
2080 /* check TV table */
2081 if (rdev
->family
!= CHIP_R100
&& rdev
->family
!= CHIP_R200
) {
2083 combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
2085 if (RBIOS8(tv_info
+ 6) == 'T') {
2086 if (radeon_apply_legacy_tv_quirks(dev
)) {
2087 radeon_add_legacy_encoder(dev
,
2088 radeon_get_encoder_id
2090 ATOM_DEVICE_TV1_SUPPORT
,
2092 ATOM_DEVICE_TV1_SUPPORT
);
2093 radeon_add_legacy_connector(dev
, 6,
2094 ATOM_DEVICE_TV1_SUPPORT
,
2095 DRM_MODE_CONNECTOR_SVIDEO
,
2097 CONNECTOR_OBJECT_ID_SVIDEO
);
2103 radeon_link_encoder_connector(dev
);
2108 void radeon_external_tmds_setup(struct drm_encoder
*encoder
)
2110 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2111 struct radeon_encoder_ext_tmds
*tmds
= radeon_encoder
->enc_priv
;
2116 switch (tmds
->dvo_chip
) {
2119 radeon_i2c_do_lock(tmds
->i2c_bus
, 1);
2120 radeon_i2c_sw_put_byte(tmds
->i2c_bus
,
2123 radeon_i2c_sw_put_byte(tmds
->i2c_bus
,
2126 radeon_i2c_sw_put_byte(tmds
->i2c_bus
,
2129 radeon_i2c_sw_put_byte(tmds
->i2c_bus
,
2132 radeon_i2c_sw_put_byte(tmds
->i2c_bus
,
2135 radeon_i2c_do_lock(tmds
->i2c_bus
, 0);
2138 /* sil 1178 - untested */
2157 bool radeon_combios_external_tmds_setup(struct drm_encoder
*encoder
)
2159 struct drm_device
*dev
= encoder
->dev
;
2160 struct radeon_device
*rdev
= dev
->dev_private
;
2161 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2163 uint8_t blocks
, slave_addr
, rev
;
2165 uint32_t reg
, val
, and_mask
, or_mask
;
2166 struct radeon_encoder_ext_tmds
*tmds
= radeon_encoder
->enc_priv
;
2168 if (rdev
->bios
== NULL
)
2174 if (rdev
->flags
& RADEON_IS_IGP
) {
2175 offset
= combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_ON_TABLE
);
2176 rev
= RBIOS8(offset
);
2178 rev
= RBIOS8(offset
);
2180 blocks
= RBIOS8(offset
+ 3);
2182 while (blocks
> 0) {
2183 id
= RBIOS16(index
);
2187 reg
= (id
& 0x1fff) * 4;
2188 val
= RBIOS32(index
);
2193 reg
= (id
& 0x1fff) * 4;
2194 and_mask
= RBIOS32(index
);
2196 or_mask
= RBIOS32(index
);
2199 val
= (val
& and_mask
) | or_mask
;
2203 val
= RBIOS16(index
);
2208 val
= RBIOS16(index
);
2213 slave_addr
= id
& 0xff;
2214 slave_addr
>>= 1; /* 7 bit addressing */
2216 reg
= RBIOS8(index
);
2218 val
= RBIOS8(index
);
2220 radeon_i2c_do_lock(tmds
->i2c_bus
, 1);
2221 radeon_i2c_sw_put_byte(tmds
->i2c_bus
,
2224 radeon_i2c_do_lock(tmds
->i2c_bus
, 0);
2227 DRM_ERROR("Unknown id %d\n", id
>> 13);
2236 offset
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
2238 index
= offset
+ 10;
2239 id
= RBIOS16(index
);
2240 while (id
!= 0xffff) {
2244 reg
= (id
& 0x1fff) * 4;
2245 val
= RBIOS32(index
);
2249 reg
= (id
& 0x1fff) * 4;
2250 and_mask
= RBIOS32(index
);
2252 or_mask
= RBIOS32(index
);
2255 val
= (val
& and_mask
) | or_mask
;
2259 val
= RBIOS16(index
);
2265 and_mask
= RBIOS32(index
);
2267 or_mask
= RBIOS32(index
);
2269 val
= RREG32_PLL(reg
);
2270 val
= (val
& and_mask
) | or_mask
;
2271 WREG32_PLL(reg
, val
);
2275 val
= RBIOS8(index
);
2277 radeon_i2c_do_lock(tmds
->i2c_bus
, 1);
2278 radeon_i2c_sw_put_byte(tmds
->i2c_bus
,
2281 radeon_i2c_do_lock(tmds
->i2c_bus
, 0);
2284 DRM_ERROR("Unknown id %d\n", id
>> 13);
2287 id
= RBIOS16(index
);
2295 static void combios_parse_mmio_table(struct drm_device
*dev
, uint16_t offset
)
2297 struct radeon_device
*rdev
= dev
->dev_private
;
2300 while (RBIOS16(offset
)) {
2301 uint16_t cmd
= ((RBIOS16(offset
) & 0xe000) >> 13);
2302 uint32_t addr
= (RBIOS16(offset
) & 0x1fff);
2303 uint32_t val
, and_mask
, or_mask
;
2309 val
= RBIOS32(offset
);
2314 val
= RBIOS32(offset
);
2319 and_mask
= RBIOS32(offset
);
2321 or_mask
= RBIOS32(offset
);
2329 and_mask
= RBIOS32(offset
);
2331 or_mask
= RBIOS32(offset
);
2339 val
= RBIOS16(offset
);
2344 val
= RBIOS16(offset
);
2351 (RADEON_CLK_PWRMGT_CNTL
) &
2358 if ((RREG32(RADEON_MC_STATUS
) &
2374 static void combios_parse_pll_table(struct drm_device
*dev
, uint16_t offset
)
2376 struct radeon_device
*rdev
= dev
->dev_private
;
2379 while (RBIOS8(offset
)) {
2380 uint8_t cmd
= ((RBIOS8(offset
) & 0xc0) >> 6);
2381 uint8_t addr
= (RBIOS8(offset
) & 0x3f);
2382 uint32_t val
, shift
, tmp
;
2383 uint32_t and_mask
, or_mask
;
2388 val
= RBIOS32(offset
);
2390 WREG32_PLL(addr
, val
);
2393 shift
= RBIOS8(offset
) * 8;
2395 and_mask
= RBIOS8(offset
) << shift
;
2396 and_mask
|= ~(0xff << shift
);
2398 or_mask
= RBIOS8(offset
) << shift
;
2400 tmp
= RREG32_PLL(addr
);
2403 WREG32_PLL(addr
, tmp
);
2419 (RADEON_CLK_PWRMGT_CNTL
) &
2427 (RADEON_CLK_PWRMGT_CNTL
) &
2434 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL
);
2435 if (tmp
& RADEON_CG_NO1_DEBUG_0
) {
2437 uint32_t mclk_cntl
=
2440 mclk_cntl
&= 0xffff0000;
2441 /*mclk_cntl |= 0x00001111;*//* ??? */
2442 WREG32_PLL(RADEON_MCLK_CNTL
,
2447 (RADEON_CLK_PWRMGT_CNTL
,
2449 ~RADEON_CG_NO1_DEBUG_0
);
2464 static void combios_parse_ram_reset_table(struct drm_device
*dev
,
2467 struct radeon_device
*rdev
= dev
->dev_private
;
2471 uint8_t val
= RBIOS8(offset
);
2472 while (val
!= 0xff) {
2476 uint32_t channel_complete_mask
;
2478 if (ASIC_IS_R300(rdev
))
2479 channel_complete_mask
=
2480 R300_MEM_PWRUP_COMPLETE
;
2482 channel_complete_mask
=
2483 RADEON_MEM_PWRUP_COMPLETE
;
2486 if ((RREG32(RADEON_MEM_STR_CNTL
) &
2487 channel_complete_mask
) ==
2488 channel_complete_mask
)
2492 uint32_t or_mask
= RBIOS16(offset
);
2495 tmp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
2496 tmp
&= RADEON_SDRAM_MODE_MASK
;
2498 WREG32(RADEON_MEM_SDRAM_MODE_REG
, tmp
);
2500 or_mask
= val
<< 24;
2501 tmp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
2502 tmp
&= RADEON_B3MEM_RESET_MASK
;
2504 WREG32(RADEON_MEM_SDRAM_MODE_REG
, tmp
);
2506 val
= RBIOS8(offset
);
2511 static uint32_t combios_detect_ram(struct drm_device
*dev
, int ram
,
2512 int mem_addr_mapping
)
2514 struct radeon_device
*rdev
= dev
->dev_private
;
2519 mem_cntl
= RREG32(RADEON_MEM_CNTL
);
2520 if (mem_cntl
& RV100_HALF_MODE
)
2523 mem_cntl
&= ~(0xff << 8);
2524 mem_cntl
|= (mem_addr_mapping
& 0xff) << 8;
2525 WREG32(RADEON_MEM_CNTL
, mem_cntl
);
2526 RREG32(RADEON_MEM_CNTL
);
2530 /* something like this???? */
2532 addr
= ram
* 1024 * 1024;
2533 /* write to each page */
2534 WREG32(RADEON_MM_INDEX
, (addr
) | RADEON_MM_APER
);
2535 WREG32(RADEON_MM_DATA
, 0xdeadbeef);
2536 /* read back and verify */
2537 WREG32(RADEON_MM_INDEX
, (addr
) | RADEON_MM_APER
);
2538 if (RREG32(RADEON_MM_DATA
) != 0xdeadbeef)
2545 static void combios_write_ram_size(struct drm_device
*dev
)
2547 struct radeon_device
*rdev
= dev
->dev_private
;
2550 uint32_t mem_size
= 0;
2551 uint32_t mem_cntl
= 0;
2553 /* should do something smarter here I guess... */
2554 if (rdev
->flags
& RADEON_IS_IGP
)
2557 /* first check detected mem table */
2558 offset
= combios_get_table_offset(dev
, COMBIOS_DETECTED_MEM_TABLE
);
2560 rev
= RBIOS8(offset
);
2562 mem_cntl
= RBIOS32(offset
+ 1);
2563 mem_size
= RBIOS16(offset
+ 5);
2564 if (((rdev
->flags
& RADEON_FAMILY_MASK
) < CHIP_R200
) &&
2565 ((dev
->pdev
->device
!= 0x515e)
2566 && (dev
->pdev
->device
!= 0x5969)))
2567 WREG32(RADEON_MEM_CNTL
, mem_cntl
);
2573 combios_get_table_offset(dev
, COMBIOS_MEM_CONFIG_TABLE
);
2575 rev
= RBIOS8(offset
- 1);
2577 if (((rdev
->flags
& RADEON_FAMILY_MASK
) <
2579 && ((dev
->pdev
->device
!= 0x515e)
2580 && (dev
->pdev
->device
!= 0x5969))) {
2582 int mem_addr_mapping
= 0;
2584 while (RBIOS8(offset
)) {
2585 ram
= RBIOS8(offset
);
2588 if (mem_addr_mapping
!= 0x25)
2591 combios_detect_ram(dev
, ram
,
2598 mem_size
= RBIOS8(offset
);
2600 mem_size
= RBIOS8(offset
);
2601 mem_size
*= 2; /* convert to MB */
2606 mem_size
*= (1024 * 1024); /* convert to bytes */
2607 WREG32(RADEON_CONFIG_MEMSIZE
, mem_size
);
2610 void radeon_combios_dyn_clk_setup(struct drm_device
*dev
, int enable
)
2612 uint16_t dyn_clk_info
=
2613 combios_get_table_offset(dev
, COMBIOS_DYN_CLK_1_TABLE
);
2616 combios_parse_pll_table(dev
, dyn_clk_info
);
2619 void radeon_combios_asic_init(struct drm_device
*dev
)
2621 struct radeon_device
*rdev
= dev
->dev_private
;
2624 /* port hardcoded mac stuff from radeonfb */
2625 if (rdev
->bios
== NULL
)
2629 table
= combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_1_TABLE
);
2631 combios_parse_mmio_table(dev
, table
);
2634 table
= combios_get_table_offset(dev
, COMBIOS_PLL_INIT_TABLE
);
2636 combios_parse_pll_table(dev
, table
);
2639 table
= combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_2_TABLE
);
2641 combios_parse_mmio_table(dev
, table
);
2643 if (!(rdev
->flags
& RADEON_IS_IGP
)) {
2646 combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_4_TABLE
);
2648 combios_parse_mmio_table(dev
, table
);
2651 table
= combios_get_table_offset(dev
, COMBIOS_RAM_RESET_TABLE
);
2653 combios_parse_ram_reset_table(dev
, table
);
2657 combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_3_TABLE
);
2659 combios_parse_mmio_table(dev
, table
);
2661 /* write CONFIG_MEMSIZE */
2662 combios_write_ram_size(dev
);
2666 table
= combios_get_table_offset(dev
, COMBIOS_DYN_CLK_1_TABLE
);
2668 combios_parse_pll_table(dev
, table
);
2672 void radeon_combios_initialize_bios_scratch_regs(struct drm_device
*dev
)
2674 struct radeon_device
*rdev
= dev
->dev_private
;
2675 uint32_t bios_0_scratch
, bios_6_scratch
, bios_7_scratch
;
2677 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
2678 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2679 bios_7_scratch
= RREG32(RADEON_BIOS_7_SCRATCH
);
2681 /* let the bios control the backlight */
2682 bios_0_scratch
&= ~RADEON_DRIVER_BRIGHTNESS_EN
;
2684 /* tell the bios not to handle mode switching */
2685 bios_6_scratch
|= (RADEON_DISPLAY_SWITCHING_DIS
|
2686 RADEON_ACC_MODE_CHANGE
);
2688 /* tell the bios a driver is loaded */
2689 bios_7_scratch
|= RADEON_DRV_LOADED
;
2691 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
2692 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2693 WREG32(RADEON_BIOS_7_SCRATCH
, bios_7_scratch
);
2696 void radeon_combios_output_lock(struct drm_encoder
*encoder
, bool lock
)
2698 struct drm_device
*dev
= encoder
->dev
;
2699 struct radeon_device
*rdev
= dev
->dev_private
;
2700 uint32_t bios_6_scratch
;
2702 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2705 bios_6_scratch
|= RADEON_DRIVER_CRITICAL
;
2707 bios_6_scratch
&= ~RADEON_DRIVER_CRITICAL
;
2709 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2713 radeon_combios_connected_scratch_regs(struct drm_connector
*connector
,
2714 struct drm_encoder
*encoder
,
2717 struct drm_device
*dev
= connector
->dev
;
2718 struct radeon_device
*rdev
= dev
->dev_private
;
2719 struct radeon_connector
*radeon_connector
=
2720 to_radeon_connector(connector
);
2721 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2722 uint32_t bios_4_scratch
= RREG32(RADEON_BIOS_4_SCRATCH
);
2723 uint32_t bios_5_scratch
= RREG32(RADEON_BIOS_5_SCRATCH
);
2725 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
2726 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
2728 DRM_DEBUG("TV1 connected\n");
2730 bios_4_scratch
|= RADEON_TV1_ATTACHED_SVIDEO
;
2731 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2732 bios_5_scratch
|= RADEON_TV1_ON
;
2733 bios_5_scratch
|= RADEON_ACC_REQ_TV1
;
2735 DRM_DEBUG("TV1 disconnected\n");
2736 bios_4_scratch
&= ~RADEON_TV1_ATTACHED_MASK
;
2737 bios_5_scratch
&= ~RADEON_TV1_ON
;
2738 bios_5_scratch
&= ~RADEON_ACC_REQ_TV1
;
2741 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
2742 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
2744 DRM_DEBUG("LCD1 connected\n");
2745 bios_4_scratch
|= RADEON_LCD1_ATTACHED
;
2746 bios_5_scratch
|= RADEON_LCD1_ON
;
2747 bios_5_scratch
|= RADEON_ACC_REQ_LCD1
;
2749 DRM_DEBUG("LCD1 disconnected\n");
2750 bios_4_scratch
&= ~RADEON_LCD1_ATTACHED
;
2751 bios_5_scratch
&= ~RADEON_LCD1_ON
;
2752 bios_5_scratch
&= ~RADEON_ACC_REQ_LCD1
;
2755 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
2756 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
2758 DRM_DEBUG("CRT1 connected\n");
2759 bios_4_scratch
|= RADEON_CRT1_ATTACHED_COLOR
;
2760 bios_5_scratch
|= RADEON_CRT1_ON
;
2761 bios_5_scratch
|= RADEON_ACC_REQ_CRT1
;
2763 DRM_DEBUG("CRT1 disconnected\n");
2764 bios_4_scratch
&= ~RADEON_CRT1_ATTACHED_MASK
;
2765 bios_5_scratch
&= ~RADEON_CRT1_ON
;
2766 bios_5_scratch
&= ~RADEON_ACC_REQ_CRT1
;
2769 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
2770 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
2772 DRM_DEBUG("CRT2 connected\n");
2773 bios_4_scratch
|= RADEON_CRT2_ATTACHED_COLOR
;
2774 bios_5_scratch
|= RADEON_CRT2_ON
;
2775 bios_5_scratch
|= RADEON_ACC_REQ_CRT2
;
2777 DRM_DEBUG("CRT2 disconnected\n");
2778 bios_4_scratch
&= ~RADEON_CRT2_ATTACHED_MASK
;
2779 bios_5_scratch
&= ~RADEON_CRT2_ON
;
2780 bios_5_scratch
&= ~RADEON_ACC_REQ_CRT2
;
2783 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
2784 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
2786 DRM_DEBUG("DFP1 connected\n");
2787 bios_4_scratch
|= RADEON_DFP1_ATTACHED
;
2788 bios_5_scratch
|= RADEON_DFP1_ON
;
2789 bios_5_scratch
|= RADEON_ACC_REQ_DFP1
;
2791 DRM_DEBUG("DFP1 disconnected\n");
2792 bios_4_scratch
&= ~RADEON_DFP1_ATTACHED
;
2793 bios_5_scratch
&= ~RADEON_DFP1_ON
;
2794 bios_5_scratch
&= ~RADEON_ACC_REQ_DFP1
;
2797 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
2798 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
2800 DRM_DEBUG("DFP2 connected\n");
2801 bios_4_scratch
|= RADEON_DFP2_ATTACHED
;
2802 bios_5_scratch
|= RADEON_DFP2_ON
;
2803 bios_5_scratch
|= RADEON_ACC_REQ_DFP2
;
2805 DRM_DEBUG("DFP2 disconnected\n");
2806 bios_4_scratch
&= ~RADEON_DFP2_ATTACHED
;
2807 bios_5_scratch
&= ~RADEON_DFP2_ON
;
2808 bios_5_scratch
&= ~RADEON_ACC_REQ_DFP2
;
2811 WREG32(RADEON_BIOS_4_SCRATCH
, bios_4_scratch
);
2812 WREG32(RADEON_BIOS_5_SCRATCH
, bios_5_scratch
);
2816 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
2818 struct drm_device
*dev
= encoder
->dev
;
2819 struct radeon_device
*rdev
= dev
->dev_private
;
2820 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2821 uint32_t bios_5_scratch
= RREG32(RADEON_BIOS_5_SCRATCH
);
2823 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2824 bios_5_scratch
&= ~RADEON_TV1_CRTC_MASK
;
2825 bios_5_scratch
|= (crtc
<< RADEON_TV1_CRTC_SHIFT
);
2827 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2828 bios_5_scratch
&= ~RADEON_CRT1_CRTC_MASK
;
2829 bios_5_scratch
|= (crtc
<< RADEON_CRT1_CRTC_SHIFT
);
2831 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2832 bios_5_scratch
&= ~RADEON_CRT2_CRTC_MASK
;
2833 bios_5_scratch
|= (crtc
<< RADEON_CRT2_CRTC_SHIFT
);
2835 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
2836 bios_5_scratch
&= ~RADEON_LCD1_CRTC_MASK
;
2837 bios_5_scratch
|= (crtc
<< RADEON_LCD1_CRTC_SHIFT
);
2839 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
2840 bios_5_scratch
&= ~RADEON_DFP1_CRTC_MASK
;
2841 bios_5_scratch
|= (crtc
<< RADEON_DFP1_CRTC_SHIFT
);
2843 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
2844 bios_5_scratch
&= ~RADEON_DFP2_CRTC_MASK
;
2845 bios_5_scratch
|= (crtc
<< RADEON_DFP2_CRTC_SHIFT
);
2847 WREG32(RADEON_BIOS_5_SCRATCH
, bios_5_scratch
);
2851 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
2853 struct drm_device
*dev
= encoder
->dev
;
2854 struct radeon_device
*rdev
= dev
->dev_private
;
2855 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2856 uint32_t bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2858 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
)) {
2860 bios_6_scratch
|= RADEON_TV_DPMS_ON
;
2862 bios_6_scratch
&= ~RADEON_TV_DPMS_ON
;
2864 if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
2866 bios_6_scratch
|= RADEON_CRT_DPMS_ON
;
2868 bios_6_scratch
&= ~RADEON_CRT_DPMS_ON
;
2870 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
2872 bios_6_scratch
|= RADEON_LCD_DPMS_ON
;
2874 bios_6_scratch
&= ~RADEON_LCD_DPMS_ON
;
2876 if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
2878 bios_6_scratch
|= RADEON_DFP_DPMS_ON
;
2880 bios_6_scratch
&= ~RADEON_DFP_DPMS_ON
;
2882 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);