2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include "radeon_drm.h"
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_enum(struct drm_device
*dev
, uint32_t supported_device
,
44 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device
*dev
,
49 uint32_t connector_id
,
50 uint32_t supported_device
,
52 struct radeon_i2c_bus_rec
*i2c_bus
,
53 uint16_t connector_object_id
,
54 struct radeon_hpd
*hpd
);
56 /* from radeon_legacy_encoder.c */
58 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
59 uint32_t supported_device
);
61 /* old legacy ATI BIOS routines */
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset
{
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE
,
67 COMBIOS_BIOS_SUPPORT_TABLE
,
68 COMBIOS_DAC_PROGRAMMING_TABLE
,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE
,
70 COMBIOS_CRTC_INFO_TABLE
,
71 COMBIOS_PLL_INFO_TABLE
,
72 COMBIOS_TV_INFO_TABLE
,
73 COMBIOS_DFP_INFO_TABLE
,
74 COMBIOS_HW_CONFIG_INFO_TABLE
,
75 COMBIOS_MULTIMEDIA_INFO_TABLE
,
76 COMBIOS_TV_STD_PATCH_TABLE
,
77 COMBIOS_LCD_INFO_TABLE
,
78 COMBIOS_MOBILE_INFO_TABLE
,
79 COMBIOS_PLL_INIT_TABLE
,
80 COMBIOS_MEM_CONFIG_TABLE
,
81 COMBIOS_SAVE_MASK_TABLE
,
82 COMBIOS_HARDCODED_EDID_TABLE
,
83 COMBIOS_ASIC_INIT_2_TABLE
,
84 COMBIOS_CONNECTOR_INFO_TABLE
,
85 COMBIOS_DYN_CLK_1_TABLE
,
86 COMBIOS_RESERVED_MEM_TABLE
,
87 COMBIOS_EXT_TMDS_INFO_TABLE
,
88 COMBIOS_MEM_CLK_INFO_TABLE
,
89 COMBIOS_EXT_DAC_INFO_TABLE
,
90 COMBIOS_MISC_INFO_TABLE
,
91 COMBIOS_CRT_INFO_TABLE
,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE
,
94 COMBIOS_FAN_SPEED_INFO_TABLE
,
95 COMBIOS_OVERDRIVE_INFO_TABLE
,
96 COMBIOS_OEM_INFO_TABLE
,
97 COMBIOS_DYN_CLK_2_TABLE
,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE
,
99 COMBIOS_I2C_INFO_TABLE
,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE
, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE
, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE
, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE
, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE
, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE
, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE
, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE
, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE
, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE
, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE
, /* offset from tmds power */
114 enum radeon_combios_ddc
{
124 enum radeon_combios_connector
{
125 CONNECTOR_NONE_LEGACY
,
126 CONNECTOR_PROPRIETARY_LEGACY
,
127 CONNECTOR_CRT_LEGACY
,
128 CONNECTOR_DVI_I_LEGACY
,
129 CONNECTOR_DVI_D_LEGACY
,
130 CONNECTOR_CTV_LEGACY
,
131 CONNECTOR_STV_LEGACY
,
132 CONNECTOR_UNSUPPORTED_LEGACY
135 const int legacy_connector_convert
[] = {
136 DRM_MODE_CONNECTOR_Unknown
,
137 DRM_MODE_CONNECTOR_DVID
,
138 DRM_MODE_CONNECTOR_VGA
,
139 DRM_MODE_CONNECTOR_DVII
,
140 DRM_MODE_CONNECTOR_DVID
,
141 DRM_MODE_CONNECTOR_Composite
,
142 DRM_MODE_CONNECTOR_SVIDEO
,
143 DRM_MODE_CONNECTOR_Unknown
,
146 static uint16_t combios_get_table_offset(struct drm_device
*dev
,
147 enum radeon_combios_table_offset table
)
149 struct radeon_device
*rdev
= dev
->dev_private
;
151 uint16_t offset
= 0, check_offset
;
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE
:
159 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0xc);
161 offset
= check_offset
;
163 case COMBIOS_BIOS_SUPPORT_TABLE
:
164 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x14);
166 offset
= check_offset
;
168 case COMBIOS_DAC_PROGRAMMING_TABLE
:
169 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2a);
171 offset
= check_offset
;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE
:
174 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2c);
176 offset
= check_offset
;
178 case COMBIOS_CRTC_INFO_TABLE
:
179 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2e);
181 offset
= check_offset
;
183 case COMBIOS_PLL_INFO_TABLE
:
184 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x30);
186 offset
= check_offset
;
188 case COMBIOS_TV_INFO_TABLE
:
189 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x32);
191 offset
= check_offset
;
193 case COMBIOS_DFP_INFO_TABLE
:
194 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x34);
196 offset
= check_offset
;
198 case COMBIOS_HW_CONFIG_INFO_TABLE
:
199 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x36);
201 offset
= check_offset
;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE
:
204 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x38);
206 offset
= check_offset
;
208 case COMBIOS_TV_STD_PATCH_TABLE
:
209 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x3e);
211 offset
= check_offset
;
213 case COMBIOS_LCD_INFO_TABLE
:
214 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x40);
216 offset
= check_offset
;
218 case COMBIOS_MOBILE_INFO_TABLE
:
219 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x42);
221 offset
= check_offset
;
223 case COMBIOS_PLL_INIT_TABLE
:
224 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x46);
226 offset
= check_offset
;
228 case COMBIOS_MEM_CONFIG_TABLE
:
229 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x48);
231 offset
= check_offset
;
233 case COMBIOS_SAVE_MASK_TABLE
:
234 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4a);
236 offset
= check_offset
;
238 case COMBIOS_HARDCODED_EDID_TABLE
:
239 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4c);
241 offset
= check_offset
;
243 case COMBIOS_ASIC_INIT_2_TABLE
:
244 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4e);
246 offset
= check_offset
;
248 case COMBIOS_CONNECTOR_INFO_TABLE
:
249 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x50);
251 offset
= check_offset
;
253 case COMBIOS_DYN_CLK_1_TABLE
:
254 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x52);
256 offset
= check_offset
;
258 case COMBIOS_RESERVED_MEM_TABLE
:
259 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x54);
261 offset
= check_offset
;
263 case COMBIOS_EXT_TMDS_INFO_TABLE
:
264 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x58);
266 offset
= check_offset
;
268 case COMBIOS_MEM_CLK_INFO_TABLE
:
269 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5a);
271 offset
= check_offset
;
273 case COMBIOS_EXT_DAC_INFO_TABLE
:
274 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5c);
276 offset
= check_offset
;
278 case COMBIOS_MISC_INFO_TABLE
:
279 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5e);
281 offset
= check_offset
;
283 case COMBIOS_CRT_INFO_TABLE
:
284 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x60);
286 offset
= check_offset
;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
:
289 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x62);
291 offset
= check_offset
;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE
:
294 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x64);
296 offset
= check_offset
;
298 case COMBIOS_FAN_SPEED_INFO_TABLE
:
299 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x66);
301 offset
= check_offset
;
303 case COMBIOS_OVERDRIVE_INFO_TABLE
:
304 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x68);
306 offset
= check_offset
;
308 case COMBIOS_OEM_INFO_TABLE
:
309 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6a);
311 offset
= check_offset
;
313 case COMBIOS_DYN_CLK_2_TABLE
:
314 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6c);
316 offset
= check_offset
;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE
:
319 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6e);
321 offset
= check_offset
;
323 case COMBIOS_I2C_INFO_TABLE
:
324 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x70);
326 offset
= check_offset
;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE
: /* offset from misc info */
331 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
333 rev
= RBIOS8(check_offset
);
335 check_offset
= RBIOS16(check_offset
+ 0x3);
337 offset
= check_offset
;
341 case COMBIOS_ASIC_INIT_4_TABLE
: /* offset from misc info */
343 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
345 rev
= RBIOS8(check_offset
);
347 check_offset
= RBIOS16(check_offset
+ 0x5);
349 offset
= check_offset
;
353 case COMBIOS_DETECTED_MEM_TABLE
: /* offset from misc info */
355 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
357 rev
= RBIOS8(check_offset
);
359 check_offset
= RBIOS16(check_offset
+ 0x7);
361 offset
= check_offset
;
365 case COMBIOS_ASIC_INIT_5_TABLE
: /* offset from misc info */
367 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
369 rev
= RBIOS8(check_offset
);
371 check_offset
= RBIOS16(check_offset
+ 0x9);
373 offset
= check_offset
;
377 case COMBIOS_RAM_RESET_TABLE
: /* offset from mem config */
379 combios_get_table_offset(dev
, COMBIOS_MEM_CONFIG_TABLE
);
381 while (RBIOS8(check_offset
++));
384 offset
= check_offset
;
387 case COMBIOS_POWERPLAY_INFO_TABLE
: /* offset from mobile info */
389 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
391 check_offset
= RBIOS16(check_offset
+ 0x11);
393 offset
= check_offset
;
396 case COMBIOS_GPIO_INFO_TABLE
: /* offset from mobile info */
398 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
400 check_offset
= RBIOS16(check_offset
+ 0x13);
402 offset
= check_offset
;
405 case COMBIOS_LCD_DDC_INFO_TABLE
: /* offset from mobile info */
407 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
409 check_offset
= RBIOS16(check_offset
+ 0x15);
411 offset
= check_offset
;
414 case COMBIOS_TMDS_POWER_TABLE
: /* offset from mobile info */
416 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
418 check_offset
= RBIOS16(check_offset
+ 0x17);
420 offset
= check_offset
;
423 case COMBIOS_TMDS_POWER_ON_TABLE
: /* offset from tmds power */
425 combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_TABLE
);
427 check_offset
= RBIOS16(check_offset
+ 0x2);
429 offset
= check_offset
;
432 case COMBIOS_TMDS_POWER_OFF_TABLE
: /* offset from tmds power */
434 combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_TABLE
);
436 check_offset
= RBIOS16(check_offset
+ 0x4);
438 offset
= check_offset
;
449 bool radeon_combios_check_hardcoded_edid(struct radeon_device
*rdev
)
454 edid_info
= combios_get_table_offset(rdev
->ddev
, COMBIOS_HARDCODED_EDID_TABLE
);
458 raw
= rdev
->bios
+ edid_info
;
459 edid
= kmalloc(EDID_LENGTH
* (raw
[0x7e] + 1), GFP_KERNEL
);
463 memcpy((unsigned char *)edid
, raw
, EDID_LENGTH
* (raw
[0x7e] + 1));
465 if (!drm_edid_is_valid(edid
)) {
470 rdev
->mode_info
.bios_hardcoded_edid
= edid
;
475 radeon_combios_get_hardcoded_edid(struct radeon_device
*rdev
)
477 if (rdev
->mode_info
.bios_hardcoded_edid
)
478 return rdev
->mode_info
.bios_hardcoded_edid
;
482 static struct radeon_i2c_bus_rec
combios_setup_i2c_bus(struct radeon_device
*rdev
,
483 enum radeon_combios_ddc ddc
,
487 struct radeon_i2c_bus_rec i2c
;
491 * DDC_NONE_DETECTED = none
492 * DDC_DVI = RADEON_GPIO_DVI_DDC
493 * DDC_VGA = RADEON_GPIO_VGA_DDC
494 * DDC_LCD = RADEON_GPIOPAD_MASK
495 * DDC_GPIO = RADEON_MDGPIO_MASK
497 * DDC_MONID = RADEON_GPIO_MONID
498 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
500 * DDC_MONID = RADEON_GPIO_MONID
501 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
503 * DDC_MONID = RADEON_GPIOPAD_MASK
504 * DDC_CRT2 = RADEON_GPIO_MONID
507 case DDC_NONE_DETECTED
:
512 ddc_line
= RADEON_GPIO_DVI_DDC
;
515 ddc_line
= RADEON_GPIO_VGA_DDC
;
518 ddc_line
= RADEON_GPIOPAD_MASK
;
521 ddc_line
= RADEON_MDGPIO_MASK
;
524 if (rdev
->family
== CHIP_RS300
||
525 rdev
->family
== CHIP_RS400
||
526 rdev
->family
== CHIP_RS480
)
527 ddc_line
= RADEON_GPIOPAD_MASK
;
529 ddc_line
= RADEON_GPIO_MONID
;
532 if (rdev
->family
== CHIP_RS300
||
533 rdev
->family
== CHIP_RS400
||
534 rdev
->family
== CHIP_RS480
)
535 ddc_line
= RADEON_GPIO_MONID
;
536 else if (rdev
->family
>= CHIP_R300
) {
537 ddc_line
= RADEON_GPIO_DVI_DDC
;
540 ddc_line
= RADEON_GPIO_CRT2_DDC
;
544 if (ddc_line
== RADEON_GPIOPAD_MASK
) {
545 i2c
.mask_clk_reg
= RADEON_GPIOPAD_MASK
;
546 i2c
.mask_data_reg
= RADEON_GPIOPAD_MASK
;
547 i2c
.a_clk_reg
= RADEON_GPIOPAD_A
;
548 i2c
.a_data_reg
= RADEON_GPIOPAD_A
;
549 i2c
.en_clk_reg
= RADEON_GPIOPAD_EN
;
550 i2c
.en_data_reg
= RADEON_GPIOPAD_EN
;
551 i2c
.y_clk_reg
= RADEON_GPIOPAD_Y
;
552 i2c
.y_data_reg
= RADEON_GPIOPAD_Y
;
553 } else if (ddc_line
== RADEON_MDGPIO_MASK
) {
554 i2c
.mask_clk_reg
= RADEON_MDGPIO_MASK
;
555 i2c
.mask_data_reg
= RADEON_MDGPIO_MASK
;
556 i2c
.a_clk_reg
= RADEON_MDGPIO_A
;
557 i2c
.a_data_reg
= RADEON_MDGPIO_A
;
558 i2c
.en_clk_reg
= RADEON_MDGPIO_EN
;
559 i2c
.en_data_reg
= RADEON_MDGPIO_EN
;
560 i2c
.y_clk_reg
= RADEON_MDGPIO_Y
;
561 i2c
.y_data_reg
= RADEON_MDGPIO_Y
;
563 i2c
.mask_clk_reg
= ddc_line
;
564 i2c
.mask_data_reg
= ddc_line
;
565 i2c
.a_clk_reg
= ddc_line
;
566 i2c
.a_data_reg
= ddc_line
;
567 i2c
.en_clk_reg
= ddc_line
;
568 i2c
.en_data_reg
= ddc_line
;
569 i2c
.y_clk_reg
= ddc_line
;
570 i2c
.y_data_reg
= ddc_line
;
573 if (clk_mask
&& data_mask
) {
574 i2c
.mask_clk_mask
= clk_mask
;
575 i2c
.mask_data_mask
= data_mask
;
576 i2c
.a_clk_mask
= clk_mask
;
577 i2c
.a_data_mask
= data_mask
;
578 i2c
.en_clk_mask
= clk_mask
;
579 i2c
.en_data_mask
= data_mask
;
580 i2c
.y_clk_mask
= clk_mask
;
581 i2c
.y_data_mask
= data_mask
;
583 i2c
.mask_clk_mask
= RADEON_GPIO_EN_1
;
584 i2c
.mask_data_mask
= RADEON_GPIO_EN_0
;
585 i2c
.a_clk_mask
= RADEON_GPIO_A_1
;
586 i2c
.a_data_mask
= RADEON_GPIO_A_0
;
587 i2c
.en_clk_mask
= RADEON_GPIO_EN_1
;
588 i2c
.en_data_mask
= RADEON_GPIO_EN_0
;
589 i2c
.y_clk_mask
= RADEON_GPIO_Y_1
;
590 i2c
.y_data_mask
= RADEON_GPIO_Y_0
;
593 switch (rdev
->family
) {
601 case RADEON_GPIO_DVI_DDC
:
602 i2c
.hw_capable
= true;
605 i2c
.hw_capable
= false;
611 case RADEON_GPIO_DVI_DDC
:
612 case RADEON_GPIO_MONID
:
613 i2c
.hw_capable
= true;
616 i2c
.hw_capable
= false;
623 case RADEON_GPIO_VGA_DDC
:
624 case RADEON_GPIO_DVI_DDC
:
625 case RADEON_GPIO_CRT2_DDC
:
626 i2c
.hw_capable
= true;
629 i2c
.hw_capable
= false;
636 case RADEON_GPIO_VGA_DDC
:
637 case RADEON_GPIO_DVI_DDC
:
638 i2c
.hw_capable
= true;
641 i2c
.hw_capable
= false;
650 case RADEON_GPIO_VGA_DDC
:
651 case RADEON_GPIO_DVI_DDC
:
652 i2c
.hw_capable
= true;
654 case RADEON_GPIO_MONID
:
655 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
656 * reliably on some pre-r4xx hardware; not sure why.
658 i2c
.hw_capable
= false;
661 i2c
.hw_capable
= false;
666 i2c
.hw_capable
= false;
672 i2c
.hpd
= RADEON_HPD_NONE
;
682 void radeon_combios_i2c_init(struct radeon_device
*rdev
)
684 struct drm_device
*dev
= rdev
->ddev
;
685 struct radeon_i2c_bus_rec i2c
;
688 i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
689 rdev
->i2c_bus
[0] = radeon_i2c_create(dev
, &i2c
, "DVI_DDC");
691 i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
692 rdev
->i2c_bus
[1] = radeon_i2c_create(dev
, &i2c
, "VGA_DDC");
695 i2c
.hw_capable
= true;
698 rdev
->i2c_bus
[2] = radeon_i2c_create(dev
, &i2c
, "MM_I2C");
700 if (rdev
->family
== CHIP_RS300
||
701 rdev
->family
== CHIP_RS400
||
702 rdev
->family
== CHIP_RS480
) {
704 u8 id
, blocks
, clk
, data
;
707 i2c
= combios_setup_i2c_bus(rdev
, DDC_CRT2
, 0, 0);
708 rdev
->i2c_bus
[3] = radeon_i2c_create(dev
, &i2c
, "MONID");
710 offset
= combios_get_table_offset(dev
, COMBIOS_I2C_INFO_TABLE
);
712 blocks
= RBIOS8(offset
+ 2);
713 for (i
= 0; i
< blocks
; i
++) {
714 id
= RBIOS8(offset
+ 3 + (i
* 5) + 0);
716 clk
= RBIOS8(offset
+ 3 + (i
* 5) + 3);
717 data
= RBIOS8(offset
+ 3 + (i
* 5) + 4);
718 i2c
= combios_setup_i2c_bus(rdev
, DDC_MONID
,
720 rdev
->i2c_bus
[4] = radeon_i2c_create(dev
, &i2c
, "GPIOPAD_MASK");
726 } else if (rdev
->family
>= CHIP_R300
) {
727 i2c
= combios_setup_i2c_bus(rdev
, DDC_MONID
, 0, 0);
728 rdev
->i2c_bus
[3] = radeon_i2c_create(dev
, &i2c
, "MONID");
730 i2c
= combios_setup_i2c_bus(rdev
, DDC_MONID
, 0, 0);
731 rdev
->i2c_bus
[3] = radeon_i2c_create(dev
, &i2c
, "MONID");
733 i2c
= combios_setup_i2c_bus(rdev
, DDC_CRT2
, 0, 0);
734 rdev
->i2c_bus
[4] = radeon_i2c_create(dev
, &i2c
, "CRT2_DDC");
738 bool radeon_combios_get_clock_info(struct drm_device
*dev
)
740 struct radeon_device
*rdev
= dev
->dev_private
;
742 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
743 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
744 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
745 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
749 pll_info
= combios_get_table_offset(dev
, COMBIOS_PLL_INFO_TABLE
);
751 rev
= RBIOS8(pll_info
);
754 p1pll
->reference_freq
= RBIOS16(pll_info
+ 0xe);
755 p1pll
->reference_div
= RBIOS16(pll_info
+ 0x10);
756 p1pll
->pll_out_min
= RBIOS32(pll_info
+ 0x12);
757 p1pll
->pll_out_max
= RBIOS32(pll_info
+ 0x16);
758 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
759 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
762 p1pll
->pll_in_min
= RBIOS32(pll_info
+ 0x36);
763 p1pll
->pll_in_max
= RBIOS32(pll_info
+ 0x3a);
765 p1pll
->pll_in_min
= 40;
766 p1pll
->pll_in_max
= 500;
771 spll
->reference_freq
= RBIOS16(pll_info
+ 0x1a);
772 spll
->reference_div
= RBIOS16(pll_info
+ 0x1c);
773 spll
->pll_out_min
= RBIOS32(pll_info
+ 0x1e);
774 spll
->pll_out_max
= RBIOS32(pll_info
+ 0x22);
777 spll
->pll_in_min
= RBIOS32(pll_info
+ 0x48);
778 spll
->pll_in_max
= RBIOS32(pll_info
+ 0x4c);
781 spll
->pll_in_min
= 40;
782 spll
->pll_in_max
= 500;
786 mpll
->reference_freq
= RBIOS16(pll_info
+ 0x26);
787 mpll
->reference_div
= RBIOS16(pll_info
+ 0x28);
788 mpll
->pll_out_min
= RBIOS32(pll_info
+ 0x2a);
789 mpll
->pll_out_max
= RBIOS32(pll_info
+ 0x2e);
792 mpll
->pll_in_min
= RBIOS32(pll_info
+ 0x5a);
793 mpll
->pll_in_max
= RBIOS32(pll_info
+ 0x5e);
796 mpll
->pll_in_min
= 40;
797 mpll
->pll_in_max
= 500;
800 /* default sclk/mclk */
801 sclk
= RBIOS16(pll_info
+ 0xa);
802 mclk
= RBIOS16(pll_info
+ 0x8);
808 rdev
->clock
.default_sclk
= sclk
;
809 rdev
->clock
.default_mclk
= mclk
;
816 bool radeon_combios_sideport_present(struct radeon_device
*rdev
)
818 struct drm_device
*dev
= rdev
->ddev
;
821 /* sideport is AMD only */
822 if (rdev
->family
== CHIP_RS400
)
825 igp_info
= combios_get_table_offset(dev
, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
);
828 if (RBIOS16(igp_info
+ 0x4))
834 static const uint32_t default_primarydac_adj
[CHIP_LAST
] = {
835 0x00000808, /* r100 */
836 0x00000808, /* rv100 */
837 0x00000808, /* rs100 */
838 0x00000808, /* rv200 */
839 0x00000808, /* rs200 */
840 0x00000808, /* r200 */
841 0x00000808, /* rv250 */
842 0x00000000, /* rs300 */
843 0x00000808, /* rv280 */
844 0x00000808, /* r300 */
845 0x00000808, /* r350 */
846 0x00000808, /* rv350 */
847 0x00000808, /* rv380 */
848 0x00000808, /* r420 */
849 0x00000808, /* r423 */
850 0x00000808, /* rv410 */
851 0x00000000, /* rs400 */
852 0x00000000, /* rs480 */
855 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device
*rdev
,
856 struct radeon_encoder_primary_dac
*p_dac
)
858 p_dac
->ps2_pdac_adj
= default_primarydac_adj
[rdev
->family
];
862 struct radeon_encoder_primary_dac
*radeon_combios_get_primary_dac_info(struct
866 struct drm_device
*dev
= encoder
->base
.dev
;
867 struct radeon_device
*rdev
= dev
->dev_private
;
869 uint8_t rev
, bg
, dac
;
870 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
873 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
),
879 /* check CRT table */
880 dac_info
= combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
882 rev
= RBIOS8(dac_info
) & 0x3;
884 bg
= RBIOS8(dac_info
+ 0x2) & 0xf;
885 dac
= (RBIOS8(dac_info
+ 0x2) >> 4) & 0xf;
886 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
888 bg
= RBIOS8(dac_info
+ 0x2) & 0xf;
889 dac
= RBIOS8(dac_info
+ 0x3) & 0xf;
890 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
892 /* if the values are all zeros, use the table */
893 if (p_dac
->ps2_pdac_adj
)
897 if (!found
) /* fallback to defaults */
898 radeon_legacy_get_primary_dac_info_from_table(rdev
, p_dac
);
904 radeon_combios_get_tv_info(struct radeon_device
*rdev
)
906 struct drm_device
*dev
= rdev
->ddev
;
908 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
910 tv_info
= combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
912 if (RBIOS8(tv_info
+ 6) == 'T') {
913 switch (RBIOS8(tv_info
+ 7) & 0xf) {
915 tv_std
= TV_STD_NTSC
;
916 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
920 DRM_DEBUG_KMS("Default TV standard: PAL\n");
923 tv_std
= TV_STD_PAL_M
;
924 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
927 tv_std
= TV_STD_PAL_60
;
928 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
931 tv_std
= TV_STD_NTSC_J
;
932 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
935 tv_std
= TV_STD_SCART_PAL
;
936 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
939 tv_std
= TV_STD_NTSC
;
941 ("Unknown TV standard; defaulting to NTSC\n");
945 switch ((RBIOS8(tv_info
+ 9) >> 2) & 0x3) {
947 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
950 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
953 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
956 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
966 static const uint32_t default_tvdac_adj
[CHIP_LAST
] = {
967 0x00000000, /* r100 */
968 0x00280000, /* rv100 */
969 0x00000000, /* rs100 */
970 0x00880000, /* rv200 */
971 0x00000000, /* rs200 */
972 0x00000000, /* r200 */
973 0x00770000, /* rv250 */
974 0x00290000, /* rs300 */
975 0x00560000, /* rv280 */
976 0x00780000, /* r300 */
977 0x00770000, /* r350 */
978 0x00780000, /* rv350 */
979 0x00780000, /* rv380 */
980 0x01080000, /* r420 */
981 0x01080000, /* r423 */
982 0x01080000, /* rv410 */
983 0x00780000, /* rs400 */
984 0x00780000, /* rs480 */
987 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device
*rdev
,
988 struct radeon_encoder_tv_dac
*tv_dac
)
990 tv_dac
->ps2_tvdac_adj
= default_tvdac_adj
[rdev
->family
];
991 if ((rdev
->flags
& RADEON_IS_MOBILITY
) && (rdev
->family
== CHIP_RV250
))
992 tv_dac
->ps2_tvdac_adj
= 0x00880000;
993 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
994 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
998 struct radeon_encoder_tv_dac
*radeon_combios_get_tv_dac_info(struct
1002 struct drm_device
*dev
= encoder
->base
.dev
;
1003 struct radeon_device
*rdev
= dev
->dev_private
;
1005 uint8_t rev
, bg
, dac
;
1006 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1009 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1013 /* first check TV table */
1014 dac_info
= combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
1016 rev
= RBIOS8(dac_info
+ 0x3);
1018 bg
= RBIOS8(dac_info
+ 0xc) & 0xf;
1019 dac
= RBIOS8(dac_info
+ 0xd) & 0xf;
1020 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1022 bg
= RBIOS8(dac_info
+ 0xe) & 0xf;
1023 dac
= RBIOS8(dac_info
+ 0xf) & 0xf;
1024 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1026 bg
= RBIOS8(dac_info
+ 0x10) & 0xf;
1027 dac
= RBIOS8(dac_info
+ 0x11) & 0xf;
1028 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1029 /* if the values are all zeros, use the table */
1030 if (tv_dac
->ps2_tvdac_adj
)
1032 } else if (rev
> 1) {
1033 bg
= RBIOS8(dac_info
+ 0xc) & 0xf;
1034 dac
= (RBIOS8(dac_info
+ 0xc) >> 4) & 0xf;
1035 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1037 bg
= RBIOS8(dac_info
+ 0xd) & 0xf;
1038 dac
= (RBIOS8(dac_info
+ 0xd) >> 4) & 0xf;
1039 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1041 bg
= RBIOS8(dac_info
+ 0xe) & 0xf;
1042 dac
= (RBIOS8(dac_info
+ 0xe) >> 4) & 0xf;
1043 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1044 /* if the values are all zeros, use the table */
1045 if (tv_dac
->ps2_tvdac_adj
)
1048 tv_dac
->tv_std
= radeon_combios_get_tv_info(rdev
);
1051 /* then check CRT table */
1053 combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
1055 rev
= RBIOS8(dac_info
) & 0x3;
1057 bg
= RBIOS8(dac_info
+ 0x3) & 0xf;
1058 dac
= (RBIOS8(dac_info
+ 0x3) >> 4) & 0xf;
1059 tv_dac
->ps2_tvdac_adj
=
1060 (bg
<< 16) | (dac
<< 20);
1061 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
1062 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
1063 /* if the values are all zeros, use the table */
1064 if (tv_dac
->ps2_tvdac_adj
)
1067 bg
= RBIOS8(dac_info
+ 0x4) & 0xf;
1068 dac
= RBIOS8(dac_info
+ 0x5) & 0xf;
1069 tv_dac
->ps2_tvdac_adj
=
1070 (bg
<< 16) | (dac
<< 20);
1071 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
1072 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
1073 /* if the values are all zeros, use the table */
1074 if (tv_dac
->ps2_tvdac_adj
)
1078 DRM_INFO("No TV DAC info found in BIOS\n");
1082 if (!found
) /* fallback to defaults */
1083 radeon_legacy_get_tv_dac_info_from_table(rdev
, tv_dac
);
1088 static struct radeon_encoder_lvds
*radeon_legacy_get_lvds_info_from_regs(struct
1092 struct radeon_encoder_lvds
*lvds
= NULL
;
1093 uint32_t fp_vert_stretch
, fp_horz_stretch
;
1094 uint32_t ppll_div_sel
, ppll_val
;
1095 uint32_t lvds_ss_gen_cntl
= RREG32(RADEON_LVDS_SS_GEN_CNTL
);
1097 lvds
= kzalloc(sizeof(struct radeon_encoder_lvds
), GFP_KERNEL
);
1102 fp_vert_stretch
= RREG32(RADEON_FP_VERT_STRETCH
);
1103 fp_horz_stretch
= RREG32(RADEON_FP_HORZ_STRETCH
);
1105 /* These should be fail-safe defaults, fingers crossed */
1106 lvds
->panel_pwr_delay
= 200;
1107 lvds
->panel_vcc_delay
= 2000;
1109 lvds
->lvds_gen_cntl
= RREG32(RADEON_LVDS_GEN_CNTL
);
1110 lvds
->panel_digon_delay
= (lvds_ss_gen_cntl
>> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT
) & 0xf;
1111 lvds
->panel_blon_delay
= (lvds_ss_gen_cntl
>> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT
) & 0xf;
1113 if (fp_vert_stretch
& RADEON_VERT_STRETCH_ENABLE
)
1114 lvds
->native_mode
.vdisplay
=
1115 ((fp_vert_stretch
& RADEON_VERT_PANEL_SIZE
) >>
1116 RADEON_VERT_PANEL_SHIFT
) + 1;
1118 lvds
->native_mode
.vdisplay
=
1119 (RREG32(RADEON_CRTC_V_TOTAL_DISP
) >> 16) + 1;
1121 if (fp_horz_stretch
& RADEON_HORZ_STRETCH_ENABLE
)
1122 lvds
->native_mode
.hdisplay
=
1123 (((fp_horz_stretch
& RADEON_HORZ_PANEL_SIZE
) >>
1124 RADEON_HORZ_PANEL_SHIFT
) + 1) * 8;
1126 lvds
->native_mode
.hdisplay
=
1127 ((RREG32(RADEON_CRTC_H_TOTAL_DISP
) >> 16) + 1) * 8;
1129 if ((lvds
->native_mode
.hdisplay
< 640) ||
1130 (lvds
->native_mode
.vdisplay
< 480)) {
1131 lvds
->native_mode
.hdisplay
= 640;
1132 lvds
->native_mode
.vdisplay
= 480;
1135 ppll_div_sel
= RREG8(RADEON_CLOCK_CNTL_INDEX
+ 1) & 0x3;
1136 ppll_val
= RREG32_PLL(RADEON_PPLL_DIV_0
+ ppll_div_sel
);
1137 if ((ppll_val
& 0x000707ff) == 0x1bb)
1138 lvds
->use_bios_dividers
= false;
1140 lvds
->panel_ref_divider
=
1141 RREG32_PLL(RADEON_PPLL_REF_DIV
) & 0x3ff;
1142 lvds
->panel_post_divider
= (ppll_val
>> 16) & 0x7;
1143 lvds
->panel_fb_divider
= ppll_val
& 0x7ff;
1145 if ((lvds
->panel_ref_divider
!= 0) &&
1146 (lvds
->panel_fb_divider
> 3))
1147 lvds
->use_bios_dividers
= true;
1149 lvds
->panel_vcc_delay
= 200;
1151 DRM_INFO("Panel info derived from registers\n");
1152 DRM_INFO("Panel Size %dx%d\n", lvds
->native_mode
.hdisplay
,
1153 lvds
->native_mode
.vdisplay
);
1158 struct radeon_encoder_lvds
*radeon_combios_get_lvds_info(struct radeon_encoder
1161 struct drm_device
*dev
= encoder
->base
.dev
;
1162 struct radeon_device
*rdev
= dev
->dev_private
;
1164 uint32_t panel_setup
;
1167 struct radeon_encoder_lvds
*lvds
= NULL
;
1169 lcd_info
= combios_get_table_offset(dev
, COMBIOS_LCD_INFO_TABLE
);
1172 lvds
= kzalloc(sizeof(struct radeon_encoder_lvds
), GFP_KERNEL
);
1177 for (i
= 0; i
< 24; i
++)
1178 stmp
[i
] = RBIOS8(lcd_info
+ i
+ 1);
1181 DRM_INFO("Panel ID String: %s\n", stmp
);
1183 lvds
->native_mode
.hdisplay
= RBIOS16(lcd_info
+ 0x19);
1184 lvds
->native_mode
.vdisplay
= RBIOS16(lcd_info
+ 0x1b);
1186 DRM_INFO("Panel Size %dx%d\n", lvds
->native_mode
.hdisplay
,
1187 lvds
->native_mode
.vdisplay
);
1189 lvds
->panel_vcc_delay
= RBIOS16(lcd_info
+ 0x2c);
1190 lvds
->panel_vcc_delay
= min_t(u16
, lvds
->panel_vcc_delay
, 2000);
1192 lvds
->panel_pwr_delay
= RBIOS8(lcd_info
+ 0x24);
1193 lvds
->panel_digon_delay
= RBIOS16(lcd_info
+ 0x38) & 0xf;
1194 lvds
->panel_blon_delay
= (RBIOS16(lcd_info
+ 0x38) >> 4) & 0xf;
1196 lvds
->panel_ref_divider
= RBIOS16(lcd_info
+ 0x2e);
1197 lvds
->panel_post_divider
= RBIOS8(lcd_info
+ 0x30);
1198 lvds
->panel_fb_divider
= RBIOS16(lcd_info
+ 0x31);
1199 if ((lvds
->panel_ref_divider
!= 0) &&
1200 (lvds
->panel_fb_divider
> 3))
1201 lvds
->use_bios_dividers
= true;
1203 panel_setup
= RBIOS32(lcd_info
+ 0x39);
1204 lvds
->lvds_gen_cntl
= 0xff00;
1205 if (panel_setup
& 0x1)
1206 lvds
->lvds_gen_cntl
|= RADEON_LVDS_PANEL_FORMAT
;
1208 if ((panel_setup
>> 4) & 0x1)
1209 lvds
->lvds_gen_cntl
|= RADEON_LVDS_PANEL_TYPE
;
1211 switch ((panel_setup
>> 8) & 0x7) {
1213 lvds
->lvds_gen_cntl
|= RADEON_LVDS_NO_FM
;
1216 lvds
->lvds_gen_cntl
|= RADEON_LVDS_2_GREY
;
1219 lvds
->lvds_gen_cntl
|= RADEON_LVDS_4_GREY
;
1225 if ((panel_setup
>> 16) & 0x1)
1226 lvds
->lvds_gen_cntl
|= RADEON_LVDS_FP_POL_LOW
;
1228 if ((panel_setup
>> 17) & 0x1)
1229 lvds
->lvds_gen_cntl
|= RADEON_LVDS_LP_POL_LOW
;
1231 if ((panel_setup
>> 18) & 0x1)
1232 lvds
->lvds_gen_cntl
|= RADEON_LVDS_DTM_POL_LOW
;
1234 if ((panel_setup
>> 23) & 0x1)
1235 lvds
->lvds_gen_cntl
|= RADEON_LVDS_BL_CLK_SEL
;
1237 lvds
->lvds_gen_cntl
|= (panel_setup
& 0xf0000000);
1239 for (i
= 0; i
< 32; i
++) {
1240 tmp
= RBIOS16(lcd_info
+ 64 + i
* 2);
1244 if ((RBIOS16(tmp
) == lvds
->native_mode
.hdisplay
) &&
1245 (RBIOS16(tmp
+ 2) == lvds
->native_mode
.vdisplay
)) {
1246 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
1247 (RBIOS16(tmp
+ 17) - RBIOS16(tmp
+ 19)) * 8;
1248 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
1249 (RBIOS16(tmp
+ 21) - RBIOS16(tmp
+ 19) - 1) * 8;
1250 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
1251 (RBIOS8(tmp
+ 23) * 8);
1253 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
1254 (RBIOS16(tmp
+ 24) - RBIOS16(tmp
+ 26));
1255 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
1256 ((RBIOS16(tmp
+ 28) & 0x7ff) - RBIOS16(tmp
+ 26));
1257 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
1258 ((RBIOS16(tmp
+ 28) & 0xf800) >> 11);
1260 lvds
->native_mode
.clock
= RBIOS16(tmp
+ 9) * 10;
1261 lvds
->native_mode
.flags
= 0;
1262 /* set crtc values */
1263 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1268 DRM_INFO("No panel info found in BIOS\n");
1269 lvds
= radeon_legacy_get_lvds_info_from_regs(rdev
);
1273 encoder
->native_mode
= lvds
->native_mode
;
1277 static const struct radeon_tmds_pll default_tmds_pll
[CHIP_LAST
][4] = {
1278 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1279 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1280 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1281 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1282 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1283 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1284 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1285 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1286 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1287 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1288 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1289 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1290 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1291 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1292 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1293 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1294 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1295 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1298 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder
*encoder
,
1299 struct radeon_encoder_int_tmds
*tmds
)
1301 struct drm_device
*dev
= encoder
->base
.dev
;
1302 struct radeon_device
*rdev
= dev
->dev_private
;
1305 for (i
= 0; i
< 4; i
++) {
1306 tmds
->tmds_pll
[i
].value
=
1307 default_tmds_pll
[rdev
->family
][i
].value
;
1308 tmds
->tmds_pll
[i
].freq
= default_tmds_pll
[rdev
->family
][i
].freq
;
1314 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder
*encoder
,
1315 struct radeon_encoder_int_tmds
*tmds
)
1317 struct drm_device
*dev
= encoder
->base
.dev
;
1318 struct radeon_device
*rdev
= dev
->dev_private
;
1323 tmds_info
= combios_get_table_offset(dev
, COMBIOS_DFP_INFO_TABLE
);
1326 ver
= RBIOS8(tmds_info
);
1327 DRM_DEBUG_KMS("DFP table revision: %d\n", ver
);
1329 n
= RBIOS8(tmds_info
+ 5) + 1;
1332 for (i
= 0; i
< n
; i
++) {
1333 tmds
->tmds_pll
[i
].value
=
1334 RBIOS32(tmds_info
+ i
* 10 + 0x08);
1335 tmds
->tmds_pll
[i
].freq
=
1336 RBIOS16(tmds_info
+ i
* 10 + 0x10);
1337 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1338 tmds
->tmds_pll
[i
].freq
,
1339 tmds
->tmds_pll
[i
].value
);
1341 } else if (ver
== 4) {
1343 n
= RBIOS8(tmds_info
+ 5) + 1;
1346 for (i
= 0; i
< n
; i
++) {
1347 tmds
->tmds_pll
[i
].value
=
1348 RBIOS32(tmds_info
+ stride
+ 0x08);
1349 tmds
->tmds_pll
[i
].freq
=
1350 RBIOS16(tmds_info
+ stride
+ 0x10);
1355 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1356 tmds
->tmds_pll
[i
].freq
,
1357 tmds
->tmds_pll
[i
].value
);
1361 DRM_INFO("No TMDS info found in BIOS\n");
1367 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder
*encoder
,
1368 struct radeon_encoder_ext_tmds
*tmds
)
1370 struct drm_device
*dev
= encoder
->base
.dev
;
1371 struct radeon_device
*rdev
= dev
->dev_private
;
1372 struct radeon_i2c_bus_rec i2c_bus
;
1374 /* default for macs */
1375 i2c_bus
= combios_setup_i2c_bus(rdev
, DDC_MONID
, 0, 0);
1376 tmds
->i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
1378 /* XXX some macs have duallink chips */
1379 switch (rdev
->mode_info
.connector_table
) {
1380 case CT_POWERBOOK_EXTERNAL
:
1381 case CT_MINI_EXTERNAL
:
1383 tmds
->dvo_chip
= DVO_SIL164
;
1384 tmds
->slave_addr
= 0x70 >> 1; /* 7 bit addressing */
1391 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder
*encoder
,
1392 struct radeon_encoder_ext_tmds
*tmds
)
1394 struct drm_device
*dev
= encoder
->base
.dev
;
1395 struct radeon_device
*rdev
= dev
->dev_private
;
1398 enum radeon_combios_ddc gpio
;
1399 struct radeon_i2c_bus_rec i2c_bus
;
1401 tmds
->i2c_bus
= NULL
;
1402 if (rdev
->flags
& RADEON_IS_IGP
) {
1403 i2c_bus
= combios_setup_i2c_bus(rdev
, DDC_MONID
, 0, 0);
1404 tmds
->i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
1405 tmds
->dvo_chip
= DVO_SIL164
;
1406 tmds
->slave_addr
= 0x70 >> 1; /* 7 bit addressing */
1408 offset
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
1410 ver
= RBIOS8(offset
);
1411 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver
);
1412 tmds
->slave_addr
= RBIOS8(offset
+ 4 + 2);
1413 tmds
->slave_addr
>>= 1; /* 7 bit addressing */
1414 gpio
= RBIOS8(offset
+ 4 + 3);
1415 if (gpio
== DDC_LCD
) {
1417 i2c_bus
.valid
= true;
1418 i2c_bus
.hw_capable
= true;
1419 i2c_bus
.mm_i2c
= true;
1420 i2c_bus
.i2c_id
= 0xa0;
1422 i2c_bus
= combios_setup_i2c_bus(rdev
, gpio
, 0, 0);
1423 tmds
->i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
1427 if (!tmds
->i2c_bus
) {
1428 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1435 bool radeon_get_legacy_connector_info_from_table(struct drm_device
*dev
)
1437 struct radeon_device
*rdev
= dev
->dev_private
;
1438 struct radeon_i2c_bus_rec ddc_i2c
;
1439 struct radeon_hpd hpd
;
1441 rdev
->mode_info
.connector_table
= radeon_connector_table
;
1442 if (rdev
->mode_info
.connector_table
== CT_NONE
) {
1443 #ifdef CONFIG_PPC_PMAC
1444 if (of_machine_is_compatible("PowerBook3,3")) {
1445 /* powerbook with VGA */
1446 rdev
->mode_info
.connector_table
= CT_POWERBOOK_VGA
;
1447 } else if (of_machine_is_compatible("PowerBook3,4") ||
1448 of_machine_is_compatible("PowerBook3,5")) {
1449 /* powerbook with internal tmds */
1450 rdev
->mode_info
.connector_table
= CT_POWERBOOK_INTERNAL
;
1451 } else if (of_machine_is_compatible("PowerBook5,1") ||
1452 of_machine_is_compatible("PowerBook5,2") ||
1453 of_machine_is_compatible("PowerBook5,3") ||
1454 of_machine_is_compatible("PowerBook5,4") ||
1455 of_machine_is_compatible("PowerBook5,5")) {
1456 /* powerbook with external single link tmds (sil164) */
1457 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1458 } else if (of_machine_is_compatible("PowerBook5,6")) {
1459 /* powerbook with external dual or single link tmds */
1460 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1461 } else if (of_machine_is_compatible("PowerBook5,7") ||
1462 of_machine_is_compatible("PowerBook5,8") ||
1463 of_machine_is_compatible("PowerBook5,9")) {
1464 /* PowerBook6,2 ? */
1465 /* powerbook with external dual link tmds (sil1178?) */
1466 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1467 } else if (of_machine_is_compatible("PowerBook4,1") ||
1468 of_machine_is_compatible("PowerBook4,2") ||
1469 of_machine_is_compatible("PowerBook4,3") ||
1470 of_machine_is_compatible("PowerBook6,3") ||
1471 of_machine_is_compatible("PowerBook6,5") ||
1472 of_machine_is_compatible("PowerBook6,7")) {
1474 rdev
->mode_info
.connector_table
= CT_IBOOK
;
1475 } else if (of_machine_is_compatible("PowerMac4,4")) {
1477 rdev
->mode_info
.connector_table
= CT_EMAC
;
1478 } else if (of_machine_is_compatible("PowerMac10,1")) {
1479 /* mini with internal tmds */
1480 rdev
->mode_info
.connector_table
= CT_MINI_INTERNAL
;
1481 } else if (of_machine_is_compatible("PowerMac10,2")) {
1482 /* mini with external tmds */
1483 rdev
->mode_info
.connector_table
= CT_MINI_EXTERNAL
;
1484 } else if (of_machine_is_compatible("PowerMac12,1")) {
1486 /* imac g5 isight */
1487 rdev
->mode_info
.connector_table
= CT_IMAC_G5_ISIGHT
;
1488 } else if ((rdev
->pdev
->device
== 0x4a48) &&
1489 (rdev
->pdev
->subsystem_vendor
== 0x1002) &&
1490 (rdev
->pdev
->subsystem_device
== 0x4a48)) {
1492 rdev
->mode_info
.connector_table
= CT_MAC_X800
;
1494 #endif /* CONFIG_PPC_PMAC */
1496 if (ASIC_IS_RN50(rdev
))
1497 rdev
->mode_info
.connector_table
= CT_RN50_POWER
;
1500 rdev
->mode_info
.connector_table
= CT_GENERIC
;
1503 switch (rdev
->mode_info
.connector_table
) {
1505 DRM_INFO("Connector Table: %d (generic)\n",
1506 rdev
->mode_info
.connector_table
);
1507 /* these are the most common settings */
1508 if (rdev
->flags
& RADEON_SINGLE_CRTC
) {
1509 /* VGA - primary dac */
1510 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1511 hpd
.hpd
= RADEON_HPD_NONE
;
1512 radeon_add_legacy_encoder(dev
,
1513 radeon_get_encoder_enum(dev
,
1514 ATOM_DEVICE_CRT1_SUPPORT
,
1516 ATOM_DEVICE_CRT1_SUPPORT
);
1517 radeon_add_legacy_connector(dev
, 0,
1518 ATOM_DEVICE_CRT1_SUPPORT
,
1519 DRM_MODE_CONNECTOR_VGA
,
1521 CONNECTOR_OBJECT_ID_VGA
,
1523 } else if (rdev
->flags
& RADEON_IS_MOBILITY
) {
1525 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_NONE_DETECTED
, 0, 0);
1526 hpd
.hpd
= RADEON_HPD_NONE
;
1527 radeon_add_legacy_encoder(dev
,
1528 radeon_get_encoder_enum(dev
,
1529 ATOM_DEVICE_LCD1_SUPPORT
,
1531 ATOM_DEVICE_LCD1_SUPPORT
);
1532 radeon_add_legacy_connector(dev
, 0,
1533 ATOM_DEVICE_LCD1_SUPPORT
,
1534 DRM_MODE_CONNECTOR_LVDS
,
1536 CONNECTOR_OBJECT_ID_LVDS
,
1539 /* VGA - primary dac */
1540 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1541 hpd
.hpd
= RADEON_HPD_NONE
;
1542 radeon_add_legacy_encoder(dev
,
1543 radeon_get_encoder_enum(dev
,
1544 ATOM_DEVICE_CRT1_SUPPORT
,
1546 ATOM_DEVICE_CRT1_SUPPORT
);
1547 radeon_add_legacy_connector(dev
, 1,
1548 ATOM_DEVICE_CRT1_SUPPORT
,
1549 DRM_MODE_CONNECTOR_VGA
,
1551 CONNECTOR_OBJECT_ID_VGA
,
1554 /* DVI-I - tv dac, int tmds */
1555 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
1556 hpd
.hpd
= RADEON_HPD_1
;
1557 radeon_add_legacy_encoder(dev
,
1558 radeon_get_encoder_enum(dev
,
1559 ATOM_DEVICE_DFP1_SUPPORT
,
1561 ATOM_DEVICE_DFP1_SUPPORT
);
1562 radeon_add_legacy_encoder(dev
,
1563 radeon_get_encoder_enum(dev
,
1564 ATOM_DEVICE_CRT2_SUPPORT
,
1566 ATOM_DEVICE_CRT2_SUPPORT
);
1567 radeon_add_legacy_connector(dev
, 0,
1568 ATOM_DEVICE_DFP1_SUPPORT
|
1569 ATOM_DEVICE_CRT2_SUPPORT
,
1570 DRM_MODE_CONNECTOR_DVII
,
1572 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1575 /* VGA - primary dac */
1576 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1577 hpd
.hpd
= RADEON_HPD_NONE
;
1578 radeon_add_legacy_encoder(dev
,
1579 radeon_get_encoder_enum(dev
,
1580 ATOM_DEVICE_CRT1_SUPPORT
,
1582 ATOM_DEVICE_CRT1_SUPPORT
);
1583 radeon_add_legacy_connector(dev
, 1,
1584 ATOM_DEVICE_CRT1_SUPPORT
,
1585 DRM_MODE_CONNECTOR_VGA
,
1587 CONNECTOR_OBJECT_ID_VGA
,
1591 if (rdev
->family
!= CHIP_R100
&& rdev
->family
!= CHIP_R200
) {
1593 ddc_i2c
.valid
= false;
1594 hpd
.hpd
= RADEON_HPD_NONE
;
1595 radeon_add_legacy_encoder(dev
,
1596 radeon_get_encoder_enum(dev
,
1597 ATOM_DEVICE_TV1_SUPPORT
,
1599 ATOM_DEVICE_TV1_SUPPORT
);
1600 radeon_add_legacy_connector(dev
, 2,
1601 ATOM_DEVICE_TV1_SUPPORT
,
1602 DRM_MODE_CONNECTOR_SVIDEO
,
1604 CONNECTOR_OBJECT_ID_SVIDEO
,
1609 DRM_INFO("Connector Table: %d (ibook)\n",
1610 rdev
->mode_info
.connector_table
);
1612 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
1613 hpd
.hpd
= RADEON_HPD_NONE
;
1614 radeon_add_legacy_encoder(dev
,
1615 radeon_get_encoder_enum(dev
,
1616 ATOM_DEVICE_LCD1_SUPPORT
,
1618 ATOM_DEVICE_LCD1_SUPPORT
);
1619 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1620 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1621 CONNECTOR_OBJECT_ID_LVDS
,
1624 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1625 hpd
.hpd
= RADEON_HPD_NONE
;
1626 radeon_add_legacy_encoder(dev
,
1627 radeon_get_encoder_enum(dev
,
1628 ATOM_DEVICE_CRT2_SUPPORT
,
1630 ATOM_DEVICE_CRT2_SUPPORT
);
1631 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1632 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1633 CONNECTOR_OBJECT_ID_VGA
,
1636 ddc_i2c
.valid
= false;
1637 hpd
.hpd
= RADEON_HPD_NONE
;
1638 radeon_add_legacy_encoder(dev
,
1639 radeon_get_encoder_enum(dev
,
1640 ATOM_DEVICE_TV1_SUPPORT
,
1642 ATOM_DEVICE_TV1_SUPPORT
);
1643 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1644 DRM_MODE_CONNECTOR_SVIDEO
,
1646 CONNECTOR_OBJECT_ID_SVIDEO
,
1649 case CT_POWERBOOK_EXTERNAL
:
1650 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1651 rdev
->mode_info
.connector_table
);
1653 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
1654 hpd
.hpd
= RADEON_HPD_NONE
;
1655 radeon_add_legacy_encoder(dev
,
1656 radeon_get_encoder_enum(dev
,
1657 ATOM_DEVICE_LCD1_SUPPORT
,
1659 ATOM_DEVICE_LCD1_SUPPORT
);
1660 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1661 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1662 CONNECTOR_OBJECT_ID_LVDS
,
1664 /* DVI-I - primary dac, ext tmds */
1665 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1666 hpd
.hpd
= RADEON_HPD_2
; /* ??? */
1667 radeon_add_legacy_encoder(dev
,
1668 radeon_get_encoder_enum(dev
,
1669 ATOM_DEVICE_DFP2_SUPPORT
,
1671 ATOM_DEVICE_DFP2_SUPPORT
);
1672 radeon_add_legacy_encoder(dev
,
1673 radeon_get_encoder_enum(dev
,
1674 ATOM_DEVICE_CRT1_SUPPORT
,
1676 ATOM_DEVICE_CRT1_SUPPORT
);
1677 /* XXX some are SL */
1678 radeon_add_legacy_connector(dev
, 1,
1679 ATOM_DEVICE_DFP2_SUPPORT
|
1680 ATOM_DEVICE_CRT1_SUPPORT
,
1681 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1682 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
,
1685 ddc_i2c
.valid
= false;
1686 hpd
.hpd
= RADEON_HPD_NONE
;
1687 radeon_add_legacy_encoder(dev
,
1688 radeon_get_encoder_enum(dev
,
1689 ATOM_DEVICE_TV1_SUPPORT
,
1691 ATOM_DEVICE_TV1_SUPPORT
);
1692 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1693 DRM_MODE_CONNECTOR_SVIDEO
,
1695 CONNECTOR_OBJECT_ID_SVIDEO
,
1698 case CT_POWERBOOK_INTERNAL
:
1699 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1700 rdev
->mode_info
.connector_table
);
1702 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
1703 hpd
.hpd
= RADEON_HPD_NONE
;
1704 radeon_add_legacy_encoder(dev
,
1705 radeon_get_encoder_enum(dev
,
1706 ATOM_DEVICE_LCD1_SUPPORT
,
1708 ATOM_DEVICE_LCD1_SUPPORT
);
1709 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1710 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1711 CONNECTOR_OBJECT_ID_LVDS
,
1713 /* DVI-I - primary dac, int tmds */
1714 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1715 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
1716 radeon_add_legacy_encoder(dev
,
1717 radeon_get_encoder_enum(dev
,
1718 ATOM_DEVICE_DFP1_SUPPORT
,
1720 ATOM_DEVICE_DFP1_SUPPORT
);
1721 radeon_add_legacy_encoder(dev
,
1722 radeon_get_encoder_enum(dev
,
1723 ATOM_DEVICE_CRT1_SUPPORT
,
1725 ATOM_DEVICE_CRT1_SUPPORT
);
1726 radeon_add_legacy_connector(dev
, 1,
1727 ATOM_DEVICE_DFP1_SUPPORT
|
1728 ATOM_DEVICE_CRT1_SUPPORT
,
1729 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1730 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1733 ddc_i2c
.valid
= false;
1734 hpd
.hpd
= RADEON_HPD_NONE
;
1735 radeon_add_legacy_encoder(dev
,
1736 radeon_get_encoder_enum(dev
,
1737 ATOM_DEVICE_TV1_SUPPORT
,
1739 ATOM_DEVICE_TV1_SUPPORT
);
1740 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1741 DRM_MODE_CONNECTOR_SVIDEO
,
1743 CONNECTOR_OBJECT_ID_SVIDEO
,
1746 case CT_POWERBOOK_VGA
:
1747 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1748 rdev
->mode_info
.connector_table
);
1750 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
1751 hpd
.hpd
= RADEON_HPD_NONE
;
1752 radeon_add_legacy_encoder(dev
,
1753 radeon_get_encoder_enum(dev
,
1754 ATOM_DEVICE_LCD1_SUPPORT
,
1756 ATOM_DEVICE_LCD1_SUPPORT
);
1757 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1758 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1759 CONNECTOR_OBJECT_ID_LVDS
,
1761 /* VGA - primary dac */
1762 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1763 hpd
.hpd
= RADEON_HPD_NONE
;
1764 radeon_add_legacy_encoder(dev
,
1765 radeon_get_encoder_enum(dev
,
1766 ATOM_DEVICE_CRT1_SUPPORT
,
1768 ATOM_DEVICE_CRT1_SUPPORT
);
1769 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT1_SUPPORT
,
1770 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1771 CONNECTOR_OBJECT_ID_VGA
,
1774 ddc_i2c
.valid
= false;
1775 hpd
.hpd
= RADEON_HPD_NONE
;
1776 radeon_add_legacy_encoder(dev
,
1777 radeon_get_encoder_enum(dev
,
1778 ATOM_DEVICE_TV1_SUPPORT
,
1780 ATOM_DEVICE_TV1_SUPPORT
);
1781 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1782 DRM_MODE_CONNECTOR_SVIDEO
,
1784 CONNECTOR_OBJECT_ID_SVIDEO
,
1787 case CT_MINI_EXTERNAL
:
1788 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1789 rdev
->mode_info
.connector_table
);
1790 /* DVI-I - tv dac, ext tmds */
1791 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_CRT2
, 0, 0);
1792 hpd
.hpd
= RADEON_HPD_2
; /* ??? */
1793 radeon_add_legacy_encoder(dev
,
1794 radeon_get_encoder_enum(dev
,
1795 ATOM_DEVICE_DFP2_SUPPORT
,
1797 ATOM_DEVICE_DFP2_SUPPORT
);
1798 radeon_add_legacy_encoder(dev
,
1799 radeon_get_encoder_enum(dev
,
1800 ATOM_DEVICE_CRT2_SUPPORT
,
1802 ATOM_DEVICE_CRT2_SUPPORT
);
1803 /* XXX are any DL? */
1804 radeon_add_legacy_connector(dev
, 0,
1805 ATOM_DEVICE_DFP2_SUPPORT
|
1806 ATOM_DEVICE_CRT2_SUPPORT
,
1807 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1808 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1811 ddc_i2c
.valid
= false;
1812 hpd
.hpd
= RADEON_HPD_NONE
;
1813 radeon_add_legacy_encoder(dev
,
1814 radeon_get_encoder_enum(dev
,
1815 ATOM_DEVICE_TV1_SUPPORT
,
1817 ATOM_DEVICE_TV1_SUPPORT
);
1818 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_TV1_SUPPORT
,
1819 DRM_MODE_CONNECTOR_SVIDEO
,
1821 CONNECTOR_OBJECT_ID_SVIDEO
,
1824 case CT_MINI_INTERNAL
:
1825 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1826 rdev
->mode_info
.connector_table
);
1827 /* DVI-I - tv dac, int tmds */
1828 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_CRT2
, 0, 0);
1829 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
1830 radeon_add_legacy_encoder(dev
,
1831 radeon_get_encoder_enum(dev
,
1832 ATOM_DEVICE_DFP1_SUPPORT
,
1834 ATOM_DEVICE_DFP1_SUPPORT
);
1835 radeon_add_legacy_encoder(dev
,
1836 radeon_get_encoder_enum(dev
,
1837 ATOM_DEVICE_CRT2_SUPPORT
,
1839 ATOM_DEVICE_CRT2_SUPPORT
);
1840 radeon_add_legacy_connector(dev
, 0,
1841 ATOM_DEVICE_DFP1_SUPPORT
|
1842 ATOM_DEVICE_CRT2_SUPPORT
,
1843 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1844 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1847 ddc_i2c
.valid
= false;
1848 hpd
.hpd
= RADEON_HPD_NONE
;
1849 radeon_add_legacy_encoder(dev
,
1850 radeon_get_encoder_enum(dev
,
1851 ATOM_DEVICE_TV1_SUPPORT
,
1853 ATOM_DEVICE_TV1_SUPPORT
);
1854 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_TV1_SUPPORT
,
1855 DRM_MODE_CONNECTOR_SVIDEO
,
1857 CONNECTOR_OBJECT_ID_SVIDEO
,
1860 case CT_IMAC_G5_ISIGHT
:
1861 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1862 rdev
->mode_info
.connector_table
);
1863 /* DVI-D - int tmds */
1864 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_MONID
, 0, 0);
1865 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
1866 radeon_add_legacy_encoder(dev
,
1867 radeon_get_encoder_enum(dev
,
1868 ATOM_DEVICE_DFP1_SUPPORT
,
1870 ATOM_DEVICE_DFP1_SUPPORT
);
1871 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_DFP1_SUPPORT
,
1872 DRM_MODE_CONNECTOR_DVID
, &ddc_i2c
,
1873 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
,
1876 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
1877 hpd
.hpd
= RADEON_HPD_NONE
;
1878 radeon_add_legacy_encoder(dev
,
1879 radeon_get_encoder_enum(dev
,
1880 ATOM_DEVICE_CRT2_SUPPORT
,
1882 ATOM_DEVICE_CRT2_SUPPORT
);
1883 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1884 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1885 CONNECTOR_OBJECT_ID_VGA
,
1888 ddc_i2c
.valid
= false;
1889 hpd
.hpd
= RADEON_HPD_NONE
;
1890 radeon_add_legacy_encoder(dev
,
1891 radeon_get_encoder_enum(dev
,
1892 ATOM_DEVICE_TV1_SUPPORT
,
1894 ATOM_DEVICE_TV1_SUPPORT
);
1895 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1896 DRM_MODE_CONNECTOR_SVIDEO
,
1898 CONNECTOR_OBJECT_ID_SVIDEO
,
1902 DRM_INFO("Connector Table: %d (emac)\n",
1903 rdev
->mode_info
.connector_table
);
1904 /* VGA - primary dac */
1905 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1906 hpd
.hpd
= RADEON_HPD_NONE
;
1907 radeon_add_legacy_encoder(dev
,
1908 radeon_get_encoder_enum(dev
,
1909 ATOM_DEVICE_CRT1_SUPPORT
,
1911 ATOM_DEVICE_CRT1_SUPPORT
);
1912 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_CRT1_SUPPORT
,
1913 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1914 CONNECTOR_OBJECT_ID_VGA
,
1917 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_CRT2
, 0, 0);
1918 hpd
.hpd
= RADEON_HPD_NONE
;
1919 radeon_add_legacy_encoder(dev
,
1920 radeon_get_encoder_enum(dev
,
1921 ATOM_DEVICE_CRT2_SUPPORT
,
1923 ATOM_DEVICE_CRT2_SUPPORT
);
1924 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1925 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1926 CONNECTOR_OBJECT_ID_VGA
,
1929 ddc_i2c
.valid
= false;
1930 hpd
.hpd
= RADEON_HPD_NONE
;
1931 radeon_add_legacy_encoder(dev
,
1932 radeon_get_encoder_enum(dev
,
1933 ATOM_DEVICE_TV1_SUPPORT
,
1935 ATOM_DEVICE_TV1_SUPPORT
);
1936 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1937 DRM_MODE_CONNECTOR_SVIDEO
,
1939 CONNECTOR_OBJECT_ID_SVIDEO
,
1943 DRM_INFO("Connector Table: %d (rn50-power)\n",
1944 rdev
->mode_info
.connector_table
);
1945 /* VGA - primary dac */
1946 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1947 hpd
.hpd
= RADEON_HPD_NONE
;
1948 radeon_add_legacy_encoder(dev
,
1949 radeon_get_encoder_enum(dev
,
1950 ATOM_DEVICE_CRT1_SUPPORT
,
1952 ATOM_DEVICE_CRT1_SUPPORT
);
1953 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_CRT1_SUPPORT
,
1954 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1955 CONNECTOR_OBJECT_ID_VGA
,
1957 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_CRT2
, 0, 0);
1958 hpd
.hpd
= RADEON_HPD_NONE
;
1959 radeon_add_legacy_encoder(dev
,
1960 radeon_get_encoder_enum(dev
,
1961 ATOM_DEVICE_CRT2_SUPPORT
,
1963 ATOM_DEVICE_CRT2_SUPPORT
);
1964 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1965 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1966 CONNECTOR_OBJECT_ID_VGA
,
1970 DRM_INFO("Connector Table: %d (mac x800)\n",
1971 rdev
->mode_info
.connector_table
);
1972 /* DVI - primary dac, internal tmds */
1973 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
1974 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
1975 radeon_add_legacy_encoder(dev
,
1976 radeon_get_encoder_enum(dev
,
1977 ATOM_DEVICE_DFP1_SUPPORT
,
1979 ATOM_DEVICE_DFP1_SUPPORT
);
1980 radeon_add_legacy_encoder(dev
,
1981 radeon_get_encoder_enum(dev
,
1982 ATOM_DEVICE_CRT1_SUPPORT
,
1984 ATOM_DEVICE_CRT1_SUPPORT
);
1985 radeon_add_legacy_connector(dev
, 0,
1986 ATOM_DEVICE_DFP1_SUPPORT
|
1987 ATOM_DEVICE_CRT1_SUPPORT
,
1988 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1989 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1991 /* DVI - tv dac, dvo */
1992 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_MONID
, 0, 0);
1993 hpd
.hpd
= RADEON_HPD_2
; /* ??? */
1994 radeon_add_legacy_encoder(dev
,
1995 radeon_get_encoder_enum(dev
,
1996 ATOM_DEVICE_DFP2_SUPPORT
,
1998 ATOM_DEVICE_DFP2_SUPPORT
);
1999 radeon_add_legacy_encoder(dev
,
2000 radeon_get_encoder_enum(dev
,
2001 ATOM_DEVICE_CRT2_SUPPORT
,
2003 ATOM_DEVICE_CRT2_SUPPORT
);
2004 radeon_add_legacy_connector(dev
, 1,
2005 ATOM_DEVICE_DFP2_SUPPORT
|
2006 ATOM_DEVICE_CRT2_SUPPORT
,
2007 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
2008 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
,
2012 DRM_INFO("Connector table: %d (invalid)\n",
2013 rdev
->mode_info
.connector_table
);
2017 radeon_link_encoder_connector(dev
);
2022 static bool radeon_apply_legacy_quirks(struct drm_device
*dev
,
2024 enum radeon_combios_connector
2026 struct radeon_i2c_bus_rec
*ddc_i2c
,
2027 struct radeon_hpd
*hpd
)
2030 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2031 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2032 if (dev
->pdev
->device
== 0x515e &&
2033 dev
->pdev
->subsystem_vendor
== 0x1014) {
2034 if (*legacy_connector
== CONNECTOR_CRT_LEGACY
&&
2035 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_CRT2_DDC
)
2039 /* X300 card with extra non-existent DVI port */
2040 if (dev
->pdev
->device
== 0x5B60 &&
2041 dev
->pdev
->subsystem_vendor
== 0x17af &&
2042 dev
->pdev
->subsystem_device
== 0x201e && bios_index
== 2) {
2043 if (*legacy_connector
== CONNECTOR_DVI_I_LEGACY
)
2050 static bool radeon_apply_legacy_tv_quirks(struct drm_device
*dev
)
2052 /* Acer 5102 has non-existent TV port */
2053 if (dev
->pdev
->device
== 0x5975 &&
2054 dev
->pdev
->subsystem_vendor
== 0x1025 &&
2055 dev
->pdev
->subsystem_device
== 0x009f)
2058 /* HP dc5750 has non-existent TV port */
2059 if (dev
->pdev
->device
== 0x5974 &&
2060 dev
->pdev
->subsystem_vendor
== 0x103c &&
2061 dev
->pdev
->subsystem_device
== 0x280a)
2064 /* MSI S270 has non-existent TV port */
2065 if (dev
->pdev
->device
== 0x5955 &&
2066 dev
->pdev
->subsystem_vendor
== 0x1462 &&
2067 dev
->pdev
->subsystem_device
== 0x0131)
2073 static uint16_t combios_check_dl_dvi(struct drm_device
*dev
, int is_dvi_d
)
2075 struct radeon_device
*rdev
= dev
->dev_private
;
2076 uint32_t ext_tmds_info
;
2078 if (rdev
->flags
& RADEON_IS_IGP
) {
2080 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
2082 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
2084 ext_tmds_info
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
2085 if (ext_tmds_info
) {
2086 uint8_t rev
= RBIOS8(ext_tmds_info
);
2087 uint8_t flags
= RBIOS8(ext_tmds_info
+ 4 + 5);
2090 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
2092 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
2096 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
2098 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
2103 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
2105 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
2108 bool radeon_get_legacy_connector_info_from_bios(struct drm_device
*dev
)
2110 struct radeon_device
*rdev
= dev
->dev_private
;
2111 uint32_t conn_info
, entry
, devices
;
2112 uint16_t tmp
, connector_object_id
;
2113 enum radeon_combios_ddc ddc_type
;
2114 enum radeon_combios_connector connector
;
2116 struct radeon_i2c_bus_rec ddc_i2c
;
2117 struct radeon_hpd hpd
;
2119 conn_info
= combios_get_table_offset(dev
, COMBIOS_CONNECTOR_INFO_TABLE
);
2121 for (i
= 0; i
< 4; i
++) {
2122 entry
= conn_info
+ 2 + i
* 2;
2124 if (!RBIOS16(entry
))
2127 tmp
= RBIOS16(entry
);
2129 connector
= (tmp
>> 12) & 0xf;
2131 ddc_type
= (tmp
>> 8) & 0xf;
2132 ddc_i2c
= combios_setup_i2c_bus(rdev
, ddc_type
, 0, 0);
2134 switch (connector
) {
2135 case CONNECTOR_PROPRIETARY_LEGACY
:
2136 case CONNECTOR_DVI_I_LEGACY
:
2137 case CONNECTOR_DVI_D_LEGACY
:
2138 if ((tmp
>> 4) & 0x1)
2139 hpd
.hpd
= RADEON_HPD_2
;
2141 hpd
.hpd
= RADEON_HPD_1
;
2144 hpd
.hpd
= RADEON_HPD_NONE
;
2148 if (!radeon_apply_legacy_quirks(dev
, i
, &connector
,
2152 switch (connector
) {
2153 case CONNECTOR_PROPRIETARY_LEGACY
:
2154 if ((tmp
>> 4) & 0x1)
2155 devices
= ATOM_DEVICE_DFP2_SUPPORT
;
2157 devices
= ATOM_DEVICE_DFP1_SUPPORT
;
2158 radeon_add_legacy_encoder(dev
,
2159 radeon_get_encoder_enum
2162 radeon_add_legacy_connector(dev
, i
, devices
,
2163 legacy_connector_convert
2166 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
,
2169 case CONNECTOR_CRT_LEGACY
:
2171 devices
= ATOM_DEVICE_CRT2_SUPPORT
;
2172 radeon_add_legacy_encoder(dev
,
2173 radeon_get_encoder_enum
2175 ATOM_DEVICE_CRT2_SUPPORT
,
2177 ATOM_DEVICE_CRT2_SUPPORT
);
2179 devices
= ATOM_DEVICE_CRT1_SUPPORT
;
2180 radeon_add_legacy_encoder(dev
,
2181 radeon_get_encoder_enum
2183 ATOM_DEVICE_CRT1_SUPPORT
,
2185 ATOM_DEVICE_CRT1_SUPPORT
);
2187 radeon_add_legacy_connector(dev
,
2190 legacy_connector_convert
2193 CONNECTOR_OBJECT_ID_VGA
,
2196 case CONNECTOR_DVI_I_LEGACY
:
2199 devices
|= ATOM_DEVICE_CRT2_SUPPORT
;
2200 radeon_add_legacy_encoder(dev
,
2201 radeon_get_encoder_enum
2203 ATOM_DEVICE_CRT2_SUPPORT
,
2205 ATOM_DEVICE_CRT2_SUPPORT
);
2207 devices
|= ATOM_DEVICE_CRT1_SUPPORT
;
2208 radeon_add_legacy_encoder(dev
,
2209 radeon_get_encoder_enum
2211 ATOM_DEVICE_CRT1_SUPPORT
,
2213 ATOM_DEVICE_CRT1_SUPPORT
);
2215 if ((tmp
>> 4) & 0x1) {
2216 devices
|= ATOM_DEVICE_DFP2_SUPPORT
;
2217 radeon_add_legacy_encoder(dev
,
2218 radeon_get_encoder_enum
2220 ATOM_DEVICE_DFP2_SUPPORT
,
2222 ATOM_DEVICE_DFP2_SUPPORT
);
2223 connector_object_id
= combios_check_dl_dvi(dev
, 0);
2225 devices
|= ATOM_DEVICE_DFP1_SUPPORT
;
2226 radeon_add_legacy_encoder(dev
,
2227 radeon_get_encoder_enum
2229 ATOM_DEVICE_DFP1_SUPPORT
,
2231 ATOM_DEVICE_DFP1_SUPPORT
);
2232 connector_object_id
= CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
2234 radeon_add_legacy_connector(dev
,
2237 legacy_connector_convert
2240 connector_object_id
,
2243 case CONNECTOR_DVI_D_LEGACY
:
2244 if ((tmp
>> 4) & 0x1) {
2245 devices
= ATOM_DEVICE_DFP2_SUPPORT
;
2246 connector_object_id
= combios_check_dl_dvi(dev
, 1);
2248 devices
= ATOM_DEVICE_DFP1_SUPPORT
;
2249 connector_object_id
= CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
2251 radeon_add_legacy_encoder(dev
,
2252 radeon_get_encoder_enum
2255 radeon_add_legacy_connector(dev
, i
, devices
,
2256 legacy_connector_convert
2259 connector_object_id
,
2262 case CONNECTOR_CTV_LEGACY
:
2263 case CONNECTOR_STV_LEGACY
:
2264 radeon_add_legacy_encoder(dev
,
2265 radeon_get_encoder_enum
2267 ATOM_DEVICE_TV1_SUPPORT
,
2269 ATOM_DEVICE_TV1_SUPPORT
);
2270 radeon_add_legacy_connector(dev
, i
,
2271 ATOM_DEVICE_TV1_SUPPORT
,
2272 legacy_connector_convert
2275 CONNECTOR_OBJECT_ID_SVIDEO
,
2279 DRM_ERROR("Unknown connector type: %d\n",
2286 uint16_t tmds_info
=
2287 combios_get_table_offset(dev
, COMBIOS_DFP_INFO_TABLE
);
2289 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2291 radeon_add_legacy_encoder(dev
,
2292 radeon_get_encoder_enum(dev
,
2293 ATOM_DEVICE_CRT1_SUPPORT
,
2295 ATOM_DEVICE_CRT1_SUPPORT
);
2296 radeon_add_legacy_encoder(dev
,
2297 radeon_get_encoder_enum(dev
,
2298 ATOM_DEVICE_DFP1_SUPPORT
,
2300 ATOM_DEVICE_DFP1_SUPPORT
);
2302 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
2303 hpd
.hpd
= RADEON_HPD_1
;
2304 radeon_add_legacy_connector(dev
,
2306 ATOM_DEVICE_CRT1_SUPPORT
|
2307 ATOM_DEVICE_DFP1_SUPPORT
,
2308 DRM_MODE_CONNECTOR_DVII
,
2310 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
2314 combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
2315 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2317 radeon_add_legacy_encoder(dev
,
2318 radeon_get_encoder_enum(dev
,
2319 ATOM_DEVICE_CRT1_SUPPORT
,
2321 ATOM_DEVICE_CRT1_SUPPORT
);
2322 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
2323 hpd
.hpd
= RADEON_HPD_NONE
;
2324 radeon_add_legacy_connector(dev
,
2326 ATOM_DEVICE_CRT1_SUPPORT
,
2327 DRM_MODE_CONNECTOR_VGA
,
2329 CONNECTOR_OBJECT_ID_VGA
,
2332 DRM_DEBUG_KMS("No connector info found\n");
2338 if (rdev
->flags
& RADEON_IS_MOBILITY
|| rdev
->flags
& RADEON_IS_IGP
) {
2340 combios_get_table_offset(dev
, COMBIOS_LCD_INFO_TABLE
);
2342 uint16_t lcd_ddc_info
=
2343 combios_get_table_offset(dev
,
2344 COMBIOS_LCD_DDC_INFO_TABLE
);
2346 radeon_add_legacy_encoder(dev
,
2347 radeon_get_encoder_enum(dev
,
2348 ATOM_DEVICE_LCD1_SUPPORT
,
2350 ATOM_DEVICE_LCD1_SUPPORT
);
2353 ddc_type
= RBIOS8(lcd_ddc_info
+ 2);
2357 combios_setup_i2c_bus(rdev
,
2359 RBIOS32(lcd_ddc_info
+ 3),
2360 RBIOS32(lcd_ddc_info
+ 7));
2361 radeon_i2c_add(rdev
, &ddc_i2c
, "LCD");
2365 combios_setup_i2c_bus(rdev
,
2367 RBIOS32(lcd_ddc_info
+ 3),
2368 RBIOS32(lcd_ddc_info
+ 7));
2369 radeon_i2c_add(rdev
, &ddc_i2c
, "LCD");
2373 combios_setup_i2c_bus(rdev
, ddc_type
, 0, 0);
2376 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2378 ddc_i2c
.valid
= false;
2380 hpd
.hpd
= RADEON_HPD_NONE
;
2381 radeon_add_legacy_connector(dev
,
2383 ATOM_DEVICE_LCD1_SUPPORT
,
2384 DRM_MODE_CONNECTOR_LVDS
,
2386 CONNECTOR_OBJECT_ID_LVDS
,
2391 /* check TV table */
2392 if (rdev
->family
!= CHIP_R100
&& rdev
->family
!= CHIP_R200
) {
2394 combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
2396 if (RBIOS8(tv_info
+ 6) == 'T') {
2397 if (radeon_apply_legacy_tv_quirks(dev
)) {
2398 hpd
.hpd
= RADEON_HPD_NONE
;
2399 ddc_i2c
.valid
= false;
2400 radeon_add_legacy_encoder(dev
,
2401 radeon_get_encoder_enum
2403 ATOM_DEVICE_TV1_SUPPORT
,
2405 ATOM_DEVICE_TV1_SUPPORT
);
2406 radeon_add_legacy_connector(dev
, 6,
2407 ATOM_DEVICE_TV1_SUPPORT
,
2408 DRM_MODE_CONNECTOR_SVIDEO
,
2410 CONNECTOR_OBJECT_ID_SVIDEO
,
2417 radeon_link_encoder_connector(dev
);
2422 void radeon_combios_get_power_modes(struct radeon_device
*rdev
)
2424 struct drm_device
*dev
= rdev
->ddev
;
2425 u16 offset
, misc
, misc2
= 0;
2426 u8 rev
, blocks
, tmp
;
2427 int state_index
= 0;
2429 rdev
->pm
.default_power_state_index
= -1;
2431 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
2432 offset
= combios_get_table_offset(dev
, COMBIOS_POWERPLAY_INFO_TABLE
);
2434 rev
= RBIOS8(offset
);
2435 blocks
= RBIOS8(offset
+ 0x2);
2436 /* power mode 0 tends to be the only valid one */
2437 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2438 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= RBIOS32(offset
+ 0x5 + 0x2);
2439 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= RBIOS32(offset
+ 0x5 + 0x6);
2440 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2441 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2443 rdev
->pm
.power_state
[state_index
].type
=
2444 POWER_STATE_TYPE_BATTERY
;
2445 misc
= RBIOS16(offset
+ 0x5 + 0x0);
2447 misc2
= RBIOS16(offset
+ 0x5 + 0xe);
2448 rdev
->pm
.power_state
[state_index
].misc
= misc
;
2449 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
2451 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_GPIO
;
2453 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2456 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2458 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.valid
= true;
2460 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.reg
=
2461 RBIOS16(offset
+ 0x5 + 0xb) * 4;
2462 tmp
= RBIOS8(offset
+ 0x5 + 0xd);
2463 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.mask
= (1 << tmp
);
2465 u8 entries
= RBIOS8(offset
+ 0x5 + 0xb);
2466 u16 voltage_table_offset
= RBIOS16(offset
+ 0x5 + 0xc);
2467 if (entries
&& voltage_table_offset
) {
2468 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.reg
=
2469 RBIOS16(voltage_table_offset
) * 4;
2470 tmp
= RBIOS8(voltage_table_offset
+ 0x2);
2471 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.mask
= (1 << tmp
);
2473 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.valid
= false;
2475 switch ((misc2
& 0x700) >> 8) {
2478 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 0;
2481 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 33;
2484 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 66;
2487 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 99;
2490 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 132;
2494 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2496 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2497 RBIOS8(offset
+ 0x5 + 0x10);
2498 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2501 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2504 /* XXX figure out some good default low power mode for desktop cards */
2508 /* add the default mode */
2509 rdev
->pm
.power_state
[state_index
].type
=
2510 POWER_STATE_TYPE_DEFAULT
;
2511 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2512 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= rdev
->clock
.default_mclk
;
2513 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= rdev
->clock
.default_sclk
;
2514 rdev
->pm
.power_state
[state_index
].default_clock_mode
= &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2515 if ((state_index
> 0) &&
2516 (rdev
->pm
.power_state
[0].clock_info
[0].voltage
.type
== VOLTAGE_GPIO
))
2517 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
=
2518 rdev
->pm
.power_state
[0].clock_info
[0].voltage
;
2520 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2521 rdev
->pm
.power_state
[state_index
].pcie_lanes
= 16;
2522 rdev
->pm
.power_state
[state_index
].flags
= 0;
2523 rdev
->pm
.default_power_state_index
= state_index
;
2524 rdev
->pm
.num_power_states
= state_index
+ 1;
2526 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
2527 rdev
->pm
.current_clock_mode_index
= 0;
2530 void radeon_external_tmds_setup(struct drm_encoder
*encoder
)
2532 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2533 struct radeon_encoder_ext_tmds
*tmds
= radeon_encoder
->enc_priv
;
2538 switch (tmds
->dvo_chip
) {
2541 radeon_i2c_put_byte(tmds
->i2c_bus
,
2544 radeon_i2c_put_byte(tmds
->i2c_bus
,
2547 radeon_i2c_put_byte(tmds
->i2c_bus
,
2550 radeon_i2c_put_byte(tmds
->i2c_bus
,
2553 radeon_i2c_put_byte(tmds
->i2c_bus
,
2558 /* sil 1178 - untested */
2577 bool radeon_combios_external_tmds_setup(struct drm_encoder
*encoder
)
2579 struct drm_device
*dev
= encoder
->dev
;
2580 struct radeon_device
*rdev
= dev
->dev_private
;
2581 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2583 uint8_t blocks
, slave_addr
, rev
;
2585 uint32_t reg
, val
, and_mask
, or_mask
;
2586 struct radeon_encoder_ext_tmds
*tmds
= radeon_encoder
->enc_priv
;
2591 if (rdev
->flags
& RADEON_IS_IGP
) {
2592 offset
= combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_ON_TABLE
);
2593 rev
= RBIOS8(offset
);
2595 rev
= RBIOS8(offset
);
2597 blocks
= RBIOS8(offset
+ 3);
2599 while (blocks
> 0) {
2600 id
= RBIOS16(index
);
2604 reg
= (id
& 0x1fff) * 4;
2605 val
= RBIOS32(index
);
2610 reg
= (id
& 0x1fff) * 4;
2611 and_mask
= RBIOS32(index
);
2613 or_mask
= RBIOS32(index
);
2616 val
= (val
& and_mask
) | or_mask
;
2620 val
= RBIOS16(index
);
2625 val
= RBIOS16(index
);
2630 slave_addr
= id
& 0xff;
2631 slave_addr
>>= 1; /* 7 bit addressing */
2633 reg
= RBIOS8(index
);
2635 val
= RBIOS8(index
);
2637 radeon_i2c_put_byte(tmds
->i2c_bus
,
2642 DRM_ERROR("Unknown id %d\n", id
>> 13);
2651 offset
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
2653 index
= offset
+ 10;
2654 id
= RBIOS16(index
);
2655 while (id
!= 0xffff) {
2659 reg
= (id
& 0x1fff) * 4;
2660 val
= RBIOS32(index
);
2664 reg
= (id
& 0x1fff) * 4;
2665 and_mask
= RBIOS32(index
);
2667 or_mask
= RBIOS32(index
);
2670 val
= (val
& and_mask
) | or_mask
;
2674 val
= RBIOS16(index
);
2680 and_mask
= RBIOS32(index
);
2682 or_mask
= RBIOS32(index
);
2684 val
= RREG32_PLL(reg
);
2685 val
= (val
& and_mask
) | or_mask
;
2686 WREG32_PLL(reg
, val
);
2690 val
= RBIOS8(index
);
2692 radeon_i2c_put_byte(tmds
->i2c_bus
,
2697 DRM_ERROR("Unknown id %d\n", id
>> 13);
2700 id
= RBIOS16(index
);
2708 static void combios_parse_mmio_table(struct drm_device
*dev
, uint16_t offset
)
2710 struct radeon_device
*rdev
= dev
->dev_private
;
2713 while (RBIOS16(offset
)) {
2714 uint16_t cmd
= ((RBIOS16(offset
) & 0xe000) >> 13);
2715 uint32_t addr
= (RBIOS16(offset
) & 0x1fff);
2716 uint32_t val
, and_mask
, or_mask
;
2722 val
= RBIOS32(offset
);
2727 val
= RBIOS32(offset
);
2732 and_mask
= RBIOS32(offset
);
2734 or_mask
= RBIOS32(offset
);
2742 and_mask
= RBIOS32(offset
);
2744 or_mask
= RBIOS32(offset
);
2752 val
= RBIOS16(offset
);
2757 val
= RBIOS16(offset
);
2764 (RADEON_CLK_PWRMGT_CNTL
) &
2771 if ((RREG32(RADEON_MC_STATUS
) &
2787 static void combios_parse_pll_table(struct drm_device
*dev
, uint16_t offset
)
2789 struct radeon_device
*rdev
= dev
->dev_private
;
2792 while (RBIOS8(offset
)) {
2793 uint8_t cmd
= ((RBIOS8(offset
) & 0xc0) >> 6);
2794 uint8_t addr
= (RBIOS8(offset
) & 0x3f);
2795 uint32_t val
, shift
, tmp
;
2796 uint32_t and_mask
, or_mask
;
2801 val
= RBIOS32(offset
);
2803 WREG32_PLL(addr
, val
);
2806 shift
= RBIOS8(offset
) * 8;
2808 and_mask
= RBIOS8(offset
) << shift
;
2809 and_mask
|= ~(0xff << shift
);
2811 or_mask
= RBIOS8(offset
) << shift
;
2813 tmp
= RREG32_PLL(addr
);
2816 WREG32_PLL(addr
, tmp
);
2832 (RADEON_CLK_PWRMGT_CNTL
) &
2840 (RADEON_CLK_PWRMGT_CNTL
) &
2847 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL
);
2848 if (tmp
& RADEON_CG_NO1_DEBUG_0
) {
2850 uint32_t mclk_cntl
=
2853 mclk_cntl
&= 0xffff0000;
2854 /*mclk_cntl |= 0x00001111;*//* ??? */
2855 WREG32_PLL(RADEON_MCLK_CNTL
,
2860 (RADEON_CLK_PWRMGT_CNTL
,
2862 ~RADEON_CG_NO1_DEBUG_0
);
2877 static void combios_parse_ram_reset_table(struct drm_device
*dev
,
2880 struct radeon_device
*rdev
= dev
->dev_private
;
2884 uint8_t val
= RBIOS8(offset
);
2885 while (val
!= 0xff) {
2889 uint32_t channel_complete_mask
;
2891 if (ASIC_IS_R300(rdev
))
2892 channel_complete_mask
=
2893 R300_MEM_PWRUP_COMPLETE
;
2895 channel_complete_mask
=
2896 RADEON_MEM_PWRUP_COMPLETE
;
2899 if ((RREG32(RADEON_MEM_STR_CNTL
) &
2900 channel_complete_mask
) ==
2901 channel_complete_mask
)
2905 uint32_t or_mask
= RBIOS16(offset
);
2908 tmp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
2909 tmp
&= RADEON_SDRAM_MODE_MASK
;
2911 WREG32(RADEON_MEM_SDRAM_MODE_REG
, tmp
);
2913 or_mask
= val
<< 24;
2914 tmp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
2915 tmp
&= RADEON_B3MEM_RESET_MASK
;
2917 WREG32(RADEON_MEM_SDRAM_MODE_REG
, tmp
);
2919 val
= RBIOS8(offset
);
2924 static uint32_t combios_detect_ram(struct drm_device
*dev
, int ram
,
2925 int mem_addr_mapping
)
2927 struct radeon_device
*rdev
= dev
->dev_private
;
2932 mem_cntl
= RREG32(RADEON_MEM_CNTL
);
2933 if (mem_cntl
& RV100_HALF_MODE
)
2936 mem_cntl
&= ~(0xff << 8);
2937 mem_cntl
|= (mem_addr_mapping
& 0xff) << 8;
2938 WREG32(RADEON_MEM_CNTL
, mem_cntl
);
2939 RREG32(RADEON_MEM_CNTL
);
2943 /* something like this???? */
2945 addr
= ram
* 1024 * 1024;
2946 /* write to each page */
2947 WREG32(RADEON_MM_INDEX
, (addr
) | RADEON_MM_APER
);
2948 WREG32(RADEON_MM_DATA
, 0xdeadbeef);
2949 /* read back and verify */
2950 WREG32(RADEON_MM_INDEX
, (addr
) | RADEON_MM_APER
);
2951 if (RREG32(RADEON_MM_DATA
) != 0xdeadbeef)
2958 static void combios_write_ram_size(struct drm_device
*dev
)
2960 struct radeon_device
*rdev
= dev
->dev_private
;
2963 uint32_t mem_size
= 0;
2964 uint32_t mem_cntl
= 0;
2966 /* should do something smarter here I guess... */
2967 if (rdev
->flags
& RADEON_IS_IGP
)
2970 /* first check detected mem table */
2971 offset
= combios_get_table_offset(dev
, COMBIOS_DETECTED_MEM_TABLE
);
2973 rev
= RBIOS8(offset
);
2975 mem_cntl
= RBIOS32(offset
+ 1);
2976 mem_size
= RBIOS16(offset
+ 5);
2977 if ((rdev
->family
< CHIP_R200
) &&
2978 !ASIC_IS_RN50(rdev
))
2979 WREG32(RADEON_MEM_CNTL
, mem_cntl
);
2985 combios_get_table_offset(dev
, COMBIOS_MEM_CONFIG_TABLE
);
2987 rev
= RBIOS8(offset
- 1);
2989 if ((rdev
->family
< CHIP_R200
)
2990 && !ASIC_IS_RN50(rdev
)) {
2992 int mem_addr_mapping
= 0;
2994 while (RBIOS8(offset
)) {
2995 ram
= RBIOS8(offset
);
2998 if (mem_addr_mapping
!= 0x25)
3001 combios_detect_ram(dev
, ram
,
3008 mem_size
= RBIOS8(offset
);
3010 mem_size
= RBIOS8(offset
);
3011 mem_size
*= 2; /* convert to MB */
3016 mem_size
*= (1024 * 1024); /* convert to bytes */
3017 WREG32(RADEON_CONFIG_MEMSIZE
, mem_size
);
3020 void radeon_combios_dyn_clk_setup(struct drm_device
*dev
, int enable
)
3022 uint16_t dyn_clk_info
=
3023 combios_get_table_offset(dev
, COMBIOS_DYN_CLK_1_TABLE
);
3026 combios_parse_pll_table(dev
, dyn_clk_info
);
3029 void radeon_combios_asic_init(struct drm_device
*dev
)
3031 struct radeon_device
*rdev
= dev
->dev_private
;
3034 /* port hardcoded mac stuff from radeonfb */
3035 if (rdev
->bios
== NULL
)
3039 table
= combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_1_TABLE
);
3041 combios_parse_mmio_table(dev
, table
);
3044 table
= combios_get_table_offset(dev
, COMBIOS_PLL_INIT_TABLE
);
3046 combios_parse_pll_table(dev
, table
);
3049 table
= combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_2_TABLE
);
3051 combios_parse_mmio_table(dev
, table
);
3053 if (!(rdev
->flags
& RADEON_IS_IGP
)) {
3056 combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_4_TABLE
);
3058 combios_parse_mmio_table(dev
, table
);
3061 table
= combios_get_table_offset(dev
, COMBIOS_RAM_RESET_TABLE
);
3063 combios_parse_ram_reset_table(dev
, table
);
3067 combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_3_TABLE
);
3069 combios_parse_mmio_table(dev
, table
);
3071 /* write CONFIG_MEMSIZE */
3072 combios_write_ram_size(dev
);
3075 /* quirk for rs4xx HP nx6125 laptop to make it resume
3076 * - it hangs on resume inside the dynclk 1 table.
3078 if (rdev
->family
== CHIP_RS480
&&
3079 rdev
->pdev
->subsystem_vendor
== 0x103c &&
3080 rdev
->pdev
->subsystem_device
== 0x308b)
3083 /* quirk for rs4xx HP dv5000 laptop to make it resume
3084 * - it hangs on resume inside the dynclk 1 table.
3086 if (rdev
->family
== CHIP_RS480
&&
3087 rdev
->pdev
->subsystem_vendor
== 0x103c &&
3088 rdev
->pdev
->subsystem_device
== 0x30a4)
3092 table
= combios_get_table_offset(dev
, COMBIOS_DYN_CLK_1_TABLE
);
3094 combios_parse_pll_table(dev
, table
);
3098 void radeon_combios_initialize_bios_scratch_regs(struct drm_device
*dev
)
3100 struct radeon_device
*rdev
= dev
->dev_private
;
3101 uint32_t bios_0_scratch
, bios_6_scratch
, bios_7_scratch
;
3103 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
3104 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3105 bios_7_scratch
= RREG32(RADEON_BIOS_7_SCRATCH
);
3107 /* let the bios control the backlight */
3108 bios_0_scratch
&= ~RADEON_DRIVER_BRIGHTNESS_EN
;
3110 /* tell the bios not to handle mode switching */
3111 bios_6_scratch
|= (RADEON_DISPLAY_SWITCHING_DIS
|
3112 RADEON_ACC_MODE_CHANGE
);
3114 /* tell the bios a driver is loaded */
3115 bios_7_scratch
|= RADEON_DRV_LOADED
;
3117 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
3118 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
3119 WREG32(RADEON_BIOS_7_SCRATCH
, bios_7_scratch
);
3122 void radeon_combios_output_lock(struct drm_encoder
*encoder
, bool lock
)
3124 struct drm_device
*dev
= encoder
->dev
;
3125 struct radeon_device
*rdev
= dev
->dev_private
;
3126 uint32_t bios_6_scratch
;
3128 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3131 bios_6_scratch
|= RADEON_DRIVER_CRITICAL
;
3133 bios_6_scratch
&= ~RADEON_DRIVER_CRITICAL
;
3135 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
3139 radeon_combios_connected_scratch_regs(struct drm_connector
*connector
,
3140 struct drm_encoder
*encoder
,
3143 struct drm_device
*dev
= connector
->dev
;
3144 struct radeon_device
*rdev
= dev
->dev_private
;
3145 struct radeon_connector
*radeon_connector
=
3146 to_radeon_connector(connector
);
3147 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3148 uint32_t bios_4_scratch
= RREG32(RADEON_BIOS_4_SCRATCH
);
3149 uint32_t bios_5_scratch
= RREG32(RADEON_BIOS_5_SCRATCH
);
3151 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
3152 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
3154 DRM_DEBUG_KMS("TV1 connected\n");
3156 bios_4_scratch
|= RADEON_TV1_ATTACHED_SVIDEO
;
3157 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3158 bios_5_scratch
|= RADEON_TV1_ON
;
3159 bios_5_scratch
|= RADEON_ACC_REQ_TV1
;
3161 DRM_DEBUG_KMS("TV1 disconnected\n");
3162 bios_4_scratch
&= ~RADEON_TV1_ATTACHED_MASK
;
3163 bios_5_scratch
&= ~RADEON_TV1_ON
;
3164 bios_5_scratch
&= ~RADEON_ACC_REQ_TV1
;
3167 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
3168 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
3170 DRM_DEBUG_KMS("LCD1 connected\n");
3171 bios_4_scratch
|= RADEON_LCD1_ATTACHED
;
3172 bios_5_scratch
|= RADEON_LCD1_ON
;
3173 bios_5_scratch
|= RADEON_ACC_REQ_LCD1
;
3175 DRM_DEBUG_KMS("LCD1 disconnected\n");
3176 bios_4_scratch
&= ~RADEON_LCD1_ATTACHED
;
3177 bios_5_scratch
&= ~RADEON_LCD1_ON
;
3178 bios_5_scratch
&= ~RADEON_ACC_REQ_LCD1
;
3181 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
3182 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
3184 DRM_DEBUG_KMS("CRT1 connected\n");
3185 bios_4_scratch
|= RADEON_CRT1_ATTACHED_COLOR
;
3186 bios_5_scratch
|= RADEON_CRT1_ON
;
3187 bios_5_scratch
|= RADEON_ACC_REQ_CRT1
;
3189 DRM_DEBUG_KMS("CRT1 disconnected\n");
3190 bios_4_scratch
&= ~RADEON_CRT1_ATTACHED_MASK
;
3191 bios_5_scratch
&= ~RADEON_CRT1_ON
;
3192 bios_5_scratch
&= ~RADEON_ACC_REQ_CRT1
;
3195 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
3196 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
3198 DRM_DEBUG_KMS("CRT2 connected\n");
3199 bios_4_scratch
|= RADEON_CRT2_ATTACHED_COLOR
;
3200 bios_5_scratch
|= RADEON_CRT2_ON
;
3201 bios_5_scratch
|= RADEON_ACC_REQ_CRT2
;
3203 DRM_DEBUG_KMS("CRT2 disconnected\n");
3204 bios_4_scratch
&= ~RADEON_CRT2_ATTACHED_MASK
;
3205 bios_5_scratch
&= ~RADEON_CRT2_ON
;
3206 bios_5_scratch
&= ~RADEON_ACC_REQ_CRT2
;
3209 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
3210 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
3212 DRM_DEBUG_KMS("DFP1 connected\n");
3213 bios_4_scratch
|= RADEON_DFP1_ATTACHED
;
3214 bios_5_scratch
|= RADEON_DFP1_ON
;
3215 bios_5_scratch
|= RADEON_ACC_REQ_DFP1
;
3217 DRM_DEBUG_KMS("DFP1 disconnected\n");
3218 bios_4_scratch
&= ~RADEON_DFP1_ATTACHED
;
3219 bios_5_scratch
&= ~RADEON_DFP1_ON
;
3220 bios_5_scratch
&= ~RADEON_ACC_REQ_DFP1
;
3223 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
3224 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
3226 DRM_DEBUG_KMS("DFP2 connected\n");
3227 bios_4_scratch
|= RADEON_DFP2_ATTACHED
;
3228 bios_5_scratch
|= RADEON_DFP2_ON
;
3229 bios_5_scratch
|= RADEON_ACC_REQ_DFP2
;
3231 DRM_DEBUG_KMS("DFP2 disconnected\n");
3232 bios_4_scratch
&= ~RADEON_DFP2_ATTACHED
;
3233 bios_5_scratch
&= ~RADEON_DFP2_ON
;
3234 bios_5_scratch
&= ~RADEON_ACC_REQ_DFP2
;
3237 WREG32(RADEON_BIOS_4_SCRATCH
, bios_4_scratch
);
3238 WREG32(RADEON_BIOS_5_SCRATCH
, bios_5_scratch
);
3242 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
3244 struct drm_device
*dev
= encoder
->dev
;
3245 struct radeon_device
*rdev
= dev
->dev_private
;
3246 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3247 uint32_t bios_5_scratch
= RREG32(RADEON_BIOS_5_SCRATCH
);
3249 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
3250 bios_5_scratch
&= ~RADEON_TV1_CRTC_MASK
;
3251 bios_5_scratch
|= (crtc
<< RADEON_TV1_CRTC_SHIFT
);
3253 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
3254 bios_5_scratch
&= ~RADEON_CRT1_CRTC_MASK
;
3255 bios_5_scratch
|= (crtc
<< RADEON_CRT1_CRTC_SHIFT
);
3257 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
3258 bios_5_scratch
&= ~RADEON_CRT2_CRTC_MASK
;
3259 bios_5_scratch
|= (crtc
<< RADEON_CRT2_CRTC_SHIFT
);
3261 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
3262 bios_5_scratch
&= ~RADEON_LCD1_CRTC_MASK
;
3263 bios_5_scratch
|= (crtc
<< RADEON_LCD1_CRTC_SHIFT
);
3265 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
3266 bios_5_scratch
&= ~RADEON_DFP1_CRTC_MASK
;
3267 bios_5_scratch
|= (crtc
<< RADEON_DFP1_CRTC_SHIFT
);
3269 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
3270 bios_5_scratch
&= ~RADEON_DFP2_CRTC_MASK
;
3271 bios_5_scratch
|= (crtc
<< RADEON_DFP2_CRTC_SHIFT
);
3273 WREG32(RADEON_BIOS_5_SCRATCH
, bios_5_scratch
);
3277 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
3279 struct drm_device
*dev
= encoder
->dev
;
3280 struct radeon_device
*rdev
= dev
->dev_private
;
3281 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3282 uint32_t bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3284 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
)) {
3286 bios_6_scratch
|= RADEON_TV_DPMS_ON
;
3288 bios_6_scratch
&= ~RADEON_TV_DPMS_ON
;
3290 if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
3292 bios_6_scratch
|= RADEON_CRT_DPMS_ON
;
3294 bios_6_scratch
&= ~RADEON_CRT_DPMS_ON
;
3296 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
3298 bios_6_scratch
|= RADEON_LCD_DPMS_ON
;
3300 bios_6_scratch
&= ~RADEON_LCD_DPMS_ON
;
3302 if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
3304 bios_6_scratch
|= RADEON_DFP_DPMS_ON
;
3306 bios_6_scratch
&= ~RADEON_DFP_DPMS_ON
;
3308 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);