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Merge branch 'for-linus' of git://git390.marist.edu/pub/scm/linux-2.6
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_combios.c
1 /*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27 #include "drmP.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
39
40 /* from radeon_encoder.c */
41 extern uint32_t
42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46 /* from radeon_connector.c */
47 extern void
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
55
56 /* from radeon_legacy_encoder.c */
57 extern void
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
59 uint32_t supported_device);
60
61 /* old legacy ATI BIOS routines */
62
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112 };
113
114 enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122 };
123
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133 };
134
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144 };
145
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148 {
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
153 if (!rdev->bios)
154 return 0;
155
156 switch (table) {
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
160 if (check_offset)
161 offset = check_offset;
162 break;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
165 if (check_offset)
166 offset = check_offset;
167 break;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
170 if (check_offset)
171 offset = check_offset;
172 break;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
175 if (check_offset)
176 offset = check_offset;
177 break;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
180 if (check_offset)
181 offset = check_offset;
182 break;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
185 if (check_offset)
186 offset = check_offset;
187 break;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
190 if (check_offset)
191 offset = check_offset;
192 break;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
195 if (check_offset)
196 offset = check_offset;
197 break;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
200 if (check_offset)
201 offset = check_offset;
202 break;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
205 if (check_offset)
206 offset = check_offset;
207 break;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
210 if (check_offset)
211 offset = check_offset;
212 break;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
215 if (check_offset)
216 offset = check_offset;
217 break;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
220 if (check_offset)
221 offset = check_offset;
222 break;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
225 if (check_offset)
226 offset = check_offset;
227 break;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
230 if (check_offset)
231 offset = check_offset;
232 break;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
235 if (check_offset)
236 offset = check_offset;
237 break;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
240 if (check_offset)
241 offset = check_offset;
242 break;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
245 if (check_offset)
246 offset = check_offset;
247 break;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
250 if (check_offset)
251 offset = check_offset;
252 break;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
255 if (check_offset)
256 offset = check_offset;
257 break;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
260 if (check_offset)
261 offset = check_offset;
262 break;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
265 if (check_offset)
266 offset = check_offset;
267 break;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
270 if (check_offset)
271 offset = check_offset;
272 break;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
275 if (check_offset)
276 offset = check_offset;
277 break;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
280 if (check_offset)
281 offset = check_offset;
282 break;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
285 if (check_offset)
286 offset = check_offset;
287 break;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
290 if (check_offset)
291 offset = check_offset;
292 break;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
295 if (check_offset)
296 offset = check_offset;
297 break;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
300 if (check_offset)
301 offset = check_offset;
302 break;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
305 if (check_offset)
306 offset = check_offset;
307 break;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
310 if (check_offset)
311 offset = check_offset;
312 break;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
315 if (check_offset)
316 offset = check_offset;
317 break;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
320 if (check_offset)
321 offset = check_offset;
322 break;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
325 if (check_offset)
326 offset = check_offset;
327 break;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
330 check_offset =
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
332 if (check_offset) {
333 rev = RBIOS8(check_offset);
334 if (rev > 0) {
335 check_offset = RBIOS16(check_offset + 0x3);
336 if (check_offset)
337 offset = check_offset;
338 }
339 }
340 break;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
342 check_offset =
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
344 if (check_offset) {
345 rev = RBIOS8(check_offset);
346 if (rev > 0) {
347 check_offset = RBIOS16(check_offset + 0x5);
348 if (check_offset)
349 offset = check_offset;
350 }
351 }
352 break;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
354 check_offset =
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
356 if (check_offset) {
357 rev = RBIOS8(check_offset);
358 if (rev > 0) {
359 check_offset = RBIOS16(check_offset + 0x7);
360 if (check_offset)
361 offset = check_offset;
362 }
363 }
364 break;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
366 check_offset =
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
368 if (check_offset) {
369 rev = RBIOS8(check_offset);
370 if (rev == 2) {
371 check_offset = RBIOS16(check_offset + 0x9);
372 if (check_offset)
373 offset = check_offset;
374 }
375 }
376 break;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
378 check_offset =
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
380 if (check_offset) {
381 while (RBIOS8(check_offset++));
382 check_offset += 2;
383 if (check_offset)
384 offset = check_offset;
385 }
386 break;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
388 check_offset =
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
390 if (check_offset) {
391 check_offset = RBIOS16(check_offset + 0x11);
392 if (check_offset)
393 offset = check_offset;
394 }
395 break;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
397 check_offset =
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
399 if (check_offset) {
400 check_offset = RBIOS16(check_offset + 0x13);
401 if (check_offset)
402 offset = check_offset;
403 }
404 break;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
406 check_offset =
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
408 if (check_offset) {
409 check_offset = RBIOS16(check_offset + 0x15);
410 if (check_offset)
411 offset = check_offset;
412 }
413 break;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
415 check_offset =
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
417 if (check_offset) {
418 check_offset = RBIOS16(check_offset + 0x17);
419 if (check_offset)
420 offset = check_offset;
421 }
422 break;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
424 check_offset =
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
426 if (check_offset) {
427 check_offset = RBIOS16(check_offset + 0x2);
428 if (check_offset)
429 offset = check_offset;
430 }
431 break;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
433 check_offset =
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
435 if (check_offset) {
436 check_offset = RBIOS16(check_offset + 0x4);
437 if (check_offset)
438 offset = check_offset;
439 }
440 break;
441 default:
442 break;
443 }
444
445 return offset;
446
447 }
448
449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
450 {
451 int edid_info;
452 struct edid *edid;
453 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
454 if (!edid_info)
455 return false;
456
457 edid = kmalloc(EDID_LENGTH * (DRM_MAX_EDID_EXT_NUM + 1),
458 GFP_KERNEL);
459 if (edid == NULL)
460 return false;
461
462 memcpy((unsigned char *)edid,
463 (unsigned char *)(rdev->bios + edid_info), EDID_LENGTH);
464
465 if (!drm_edid_is_valid(edid)) {
466 kfree(edid);
467 return false;
468 }
469
470 rdev->mode_info.bios_hardcoded_edid = edid;
471 return true;
472 }
473
474 struct edid *
475 radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
476 {
477 if (rdev->mode_info.bios_hardcoded_edid)
478 return rdev->mode_info.bios_hardcoded_edid;
479 return NULL;
480 }
481
482 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
483 int ddc_line)
484 {
485 struct radeon_i2c_bus_rec i2c;
486
487 if (ddc_line == RADEON_GPIOPAD_MASK) {
488 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
489 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
490 i2c.a_clk_reg = RADEON_GPIOPAD_A;
491 i2c.a_data_reg = RADEON_GPIOPAD_A;
492 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
493 i2c.en_data_reg = RADEON_GPIOPAD_EN;
494 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
495 i2c.y_data_reg = RADEON_GPIOPAD_Y;
496 } else if (ddc_line == RADEON_MDGPIO_MASK) {
497 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
498 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
499 i2c.a_clk_reg = RADEON_MDGPIO_A;
500 i2c.a_data_reg = RADEON_MDGPIO_A;
501 i2c.en_clk_reg = RADEON_MDGPIO_EN;
502 i2c.en_data_reg = RADEON_MDGPIO_EN;
503 i2c.y_clk_reg = RADEON_MDGPIO_Y;
504 i2c.y_data_reg = RADEON_MDGPIO_Y;
505 } else {
506 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
507 i2c.mask_data_mask = RADEON_GPIO_EN_0;
508 i2c.a_clk_mask = RADEON_GPIO_A_1;
509 i2c.a_data_mask = RADEON_GPIO_A_0;
510 i2c.en_clk_mask = RADEON_GPIO_EN_1;
511 i2c.en_data_mask = RADEON_GPIO_EN_0;
512 i2c.y_clk_mask = RADEON_GPIO_Y_1;
513 i2c.y_data_mask = RADEON_GPIO_Y_0;
514
515 i2c.mask_clk_reg = ddc_line;
516 i2c.mask_data_reg = ddc_line;
517 i2c.a_clk_reg = ddc_line;
518 i2c.a_data_reg = ddc_line;
519 i2c.en_clk_reg = ddc_line;
520 i2c.en_data_reg = ddc_line;
521 i2c.y_clk_reg = ddc_line;
522 i2c.y_data_reg = ddc_line;
523 }
524
525 switch (rdev->family) {
526 case CHIP_R100:
527 case CHIP_RV100:
528 case CHIP_RS100:
529 case CHIP_RV200:
530 case CHIP_RS200:
531 case CHIP_RS300:
532 switch (ddc_line) {
533 case RADEON_GPIO_DVI_DDC:
534 i2c.hw_capable = true;
535 break;
536 default:
537 i2c.hw_capable = false;
538 break;
539 }
540 break;
541 case CHIP_R200:
542 switch (ddc_line) {
543 case RADEON_GPIO_DVI_DDC:
544 case RADEON_GPIO_MONID:
545 i2c.hw_capable = true;
546 break;
547 default:
548 i2c.hw_capable = false;
549 break;
550 }
551 break;
552 case CHIP_RV250:
553 case CHIP_RV280:
554 switch (ddc_line) {
555 case RADEON_GPIO_VGA_DDC:
556 case RADEON_GPIO_DVI_DDC:
557 case RADEON_GPIO_CRT2_DDC:
558 i2c.hw_capable = true;
559 break;
560 default:
561 i2c.hw_capable = false;
562 break;
563 }
564 break;
565 case CHIP_R300:
566 case CHIP_R350:
567 switch (ddc_line) {
568 case RADEON_GPIO_VGA_DDC:
569 case RADEON_GPIO_DVI_DDC:
570 i2c.hw_capable = true;
571 break;
572 default:
573 i2c.hw_capable = false;
574 break;
575 }
576 break;
577 case CHIP_RV350:
578 case CHIP_RV380:
579 case CHIP_RS400:
580 case CHIP_RS480:
581 switch (ddc_line) {
582 case RADEON_GPIO_VGA_DDC:
583 case RADEON_GPIO_DVI_DDC:
584 i2c.hw_capable = true;
585 break;
586 case RADEON_GPIO_MONID:
587 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
588 * reliably on some pre-r4xx hardware; not sure why.
589 */
590 i2c.hw_capable = false;
591 break;
592 default:
593 i2c.hw_capable = false;
594 break;
595 }
596 break;
597 default:
598 i2c.hw_capable = false;
599 break;
600 }
601 i2c.mm_i2c = false;
602 i2c.i2c_id = 0;
603 i2c.hpd_id = 0;
604
605 if (ddc_line)
606 i2c.valid = true;
607 else
608 i2c.valid = false;
609
610 return i2c;
611 }
612
613 bool radeon_combios_get_clock_info(struct drm_device *dev)
614 {
615 struct radeon_device *rdev = dev->dev_private;
616 uint16_t pll_info;
617 struct radeon_pll *p1pll = &rdev->clock.p1pll;
618 struct radeon_pll *p2pll = &rdev->clock.p2pll;
619 struct radeon_pll *spll = &rdev->clock.spll;
620 struct radeon_pll *mpll = &rdev->clock.mpll;
621 int8_t rev;
622 uint16_t sclk, mclk;
623
624 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
625 if (pll_info) {
626 rev = RBIOS8(pll_info);
627
628 /* pixel clocks */
629 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
630 p1pll->reference_div = RBIOS16(pll_info + 0x10);
631 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
632 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
633 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
634 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
635
636 if (rev > 9) {
637 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
638 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
639 } else {
640 p1pll->pll_in_min = 40;
641 p1pll->pll_in_max = 500;
642 }
643 *p2pll = *p1pll;
644
645 /* system clock */
646 spll->reference_freq = RBIOS16(pll_info + 0x1a);
647 spll->reference_div = RBIOS16(pll_info + 0x1c);
648 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
649 spll->pll_out_max = RBIOS32(pll_info + 0x22);
650
651 if (rev > 10) {
652 spll->pll_in_min = RBIOS32(pll_info + 0x48);
653 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
654 } else {
655 /* ??? */
656 spll->pll_in_min = 40;
657 spll->pll_in_max = 500;
658 }
659
660 /* memory clock */
661 mpll->reference_freq = RBIOS16(pll_info + 0x26);
662 mpll->reference_div = RBIOS16(pll_info + 0x28);
663 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
664 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
665
666 if (rev > 10) {
667 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
668 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
669 } else {
670 /* ??? */
671 mpll->pll_in_min = 40;
672 mpll->pll_in_max = 500;
673 }
674
675 /* default sclk/mclk */
676 sclk = RBIOS16(pll_info + 0xa);
677 mclk = RBIOS16(pll_info + 0x8);
678 if (sclk == 0)
679 sclk = 200 * 100;
680 if (mclk == 0)
681 mclk = 200 * 100;
682
683 rdev->clock.default_sclk = sclk;
684 rdev->clock.default_mclk = mclk;
685
686 return true;
687 }
688 return false;
689 }
690
691 bool radeon_combios_sideport_present(struct radeon_device *rdev)
692 {
693 struct drm_device *dev = rdev->ddev;
694 u16 igp_info;
695
696 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
697
698 if (igp_info) {
699 if (RBIOS16(igp_info + 0x4))
700 return true;
701 }
702 return false;
703 }
704
705 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
706 0x00000808, /* r100 */
707 0x00000808, /* rv100 */
708 0x00000808, /* rs100 */
709 0x00000808, /* rv200 */
710 0x00000808, /* rs200 */
711 0x00000808, /* r200 */
712 0x00000808, /* rv250 */
713 0x00000000, /* rs300 */
714 0x00000808, /* rv280 */
715 0x00000808, /* r300 */
716 0x00000808, /* r350 */
717 0x00000808, /* rv350 */
718 0x00000808, /* rv380 */
719 0x00000808, /* r420 */
720 0x00000808, /* r423 */
721 0x00000808, /* rv410 */
722 0x00000000, /* rs400 */
723 0x00000000, /* rs480 */
724 };
725
726 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
727 struct radeon_encoder_primary_dac *p_dac)
728 {
729 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
730 return;
731 }
732
733 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
734 radeon_encoder
735 *encoder)
736 {
737 struct drm_device *dev = encoder->base.dev;
738 struct radeon_device *rdev = dev->dev_private;
739 uint16_t dac_info;
740 uint8_t rev, bg, dac;
741 struct radeon_encoder_primary_dac *p_dac = NULL;
742 int found = 0;
743
744 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
745 GFP_KERNEL);
746
747 if (!p_dac)
748 return NULL;
749
750 /* check CRT table */
751 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
752 if (dac_info) {
753 rev = RBIOS8(dac_info) & 0x3;
754 if (rev < 2) {
755 bg = RBIOS8(dac_info + 0x2) & 0xf;
756 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
757 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
758 } else {
759 bg = RBIOS8(dac_info + 0x2) & 0xf;
760 dac = RBIOS8(dac_info + 0x3) & 0xf;
761 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
762 }
763 /* if the values are all zeros, use the table */
764 if (p_dac->ps2_pdac_adj)
765 found = 1;
766 }
767
768 if (!found) /* fallback to defaults */
769 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
770
771 return p_dac;
772 }
773
774 enum radeon_tv_std
775 radeon_combios_get_tv_info(struct radeon_device *rdev)
776 {
777 struct drm_device *dev = rdev->ddev;
778 uint16_t tv_info;
779 enum radeon_tv_std tv_std = TV_STD_NTSC;
780
781 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
782 if (tv_info) {
783 if (RBIOS8(tv_info + 6) == 'T') {
784 switch (RBIOS8(tv_info + 7) & 0xf) {
785 case 1:
786 tv_std = TV_STD_NTSC;
787 DRM_INFO("Default TV standard: NTSC\n");
788 break;
789 case 2:
790 tv_std = TV_STD_PAL;
791 DRM_INFO("Default TV standard: PAL\n");
792 break;
793 case 3:
794 tv_std = TV_STD_PAL_M;
795 DRM_INFO("Default TV standard: PAL-M\n");
796 break;
797 case 4:
798 tv_std = TV_STD_PAL_60;
799 DRM_INFO("Default TV standard: PAL-60\n");
800 break;
801 case 5:
802 tv_std = TV_STD_NTSC_J;
803 DRM_INFO("Default TV standard: NTSC-J\n");
804 break;
805 case 6:
806 tv_std = TV_STD_SCART_PAL;
807 DRM_INFO("Default TV standard: SCART-PAL\n");
808 break;
809 default:
810 tv_std = TV_STD_NTSC;
811 DRM_INFO
812 ("Unknown TV standard; defaulting to NTSC\n");
813 break;
814 }
815
816 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
817 case 0:
818 DRM_INFO("29.498928713 MHz TV ref clk\n");
819 break;
820 case 1:
821 DRM_INFO("28.636360000 MHz TV ref clk\n");
822 break;
823 case 2:
824 DRM_INFO("14.318180000 MHz TV ref clk\n");
825 break;
826 case 3:
827 DRM_INFO("27.000000000 MHz TV ref clk\n");
828 break;
829 default:
830 break;
831 }
832 }
833 }
834 return tv_std;
835 }
836
837 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
838 0x00000000, /* r100 */
839 0x00280000, /* rv100 */
840 0x00000000, /* rs100 */
841 0x00880000, /* rv200 */
842 0x00000000, /* rs200 */
843 0x00000000, /* r200 */
844 0x00770000, /* rv250 */
845 0x00290000, /* rs300 */
846 0x00560000, /* rv280 */
847 0x00780000, /* r300 */
848 0x00770000, /* r350 */
849 0x00780000, /* rv350 */
850 0x00780000, /* rv380 */
851 0x01080000, /* r420 */
852 0x01080000, /* r423 */
853 0x01080000, /* rv410 */
854 0x00780000, /* rs400 */
855 0x00780000, /* rs480 */
856 };
857
858 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
859 struct radeon_encoder_tv_dac *tv_dac)
860 {
861 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
862 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
863 tv_dac->ps2_tvdac_adj = 0x00880000;
864 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
865 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
866 return;
867 }
868
869 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
870 radeon_encoder
871 *encoder)
872 {
873 struct drm_device *dev = encoder->base.dev;
874 struct radeon_device *rdev = dev->dev_private;
875 uint16_t dac_info;
876 uint8_t rev, bg, dac;
877 struct radeon_encoder_tv_dac *tv_dac = NULL;
878 int found = 0;
879
880 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
881 if (!tv_dac)
882 return NULL;
883
884 /* first check TV table */
885 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
886 if (dac_info) {
887 rev = RBIOS8(dac_info + 0x3);
888 if (rev > 4) {
889 bg = RBIOS8(dac_info + 0xc) & 0xf;
890 dac = RBIOS8(dac_info + 0xd) & 0xf;
891 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
892
893 bg = RBIOS8(dac_info + 0xe) & 0xf;
894 dac = RBIOS8(dac_info + 0xf) & 0xf;
895 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
896
897 bg = RBIOS8(dac_info + 0x10) & 0xf;
898 dac = RBIOS8(dac_info + 0x11) & 0xf;
899 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
900 /* if the values are all zeros, use the table */
901 if (tv_dac->ps2_tvdac_adj)
902 found = 1;
903 } else if (rev > 1) {
904 bg = RBIOS8(dac_info + 0xc) & 0xf;
905 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
906 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
907
908 bg = RBIOS8(dac_info + 0xd) & 0xf;
909 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
910 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
911
912 bg = RBIOS8(dac_info + 0xe) & 0xf;
913 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
914 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
915 /* if the values are all zeros, use the table */
916 if (tv_dac->ps2_tvdac_adj)
917 found = 1;
918 }
919 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
920 }
921 if (!found) {
922 /* then check CRT table */
923 dac_info =
924 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
925 if (dac_info) {
926 rev = RBIOS8(dac_info) & 0x3;
927 if (rev < 2) {
928 bg = RBIOS8(dac_info + 0x3) & 0xf;
929 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
930 tv_dac->ps2_tvdac_adj =
931 (bg << 16) | (dac << 20);
932 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
933 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
934 /* if the values are all zeros, use the table */
935 if (tv_dac->ps2_tvdac_adj)
936 found = 1;
937 } else {
938 bg = RBIOS8(dac_info + 0x4) & 0xf;
939 dac = RBIOS8(dac_info + 0x5) & 0xf;
940 tv_dac->ps2_tvdac_adj =
941 (bg << 16) | (dac << 20);
942 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
943 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
944 /* if the values are all zeros, use the table */
945 if (tv_dac->ps2_tvdac_adj)
946 found = 1;
947 }
948 } else {
949 DRM_INFO("No TV DAC info found in BIOS\n");
950 }
951 }
952
953 if (!found) /* fallback to defaults */
954 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
955
956 return tv_dac;
957 }
958
959 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
960 radeon_device
961 *rdev)
962 {
963 struct radeon_encoder_lvds *lvds = NULL;
964 uint32_t fp_vert_stretch, fp_horz_stretch;
965 uint32_t ppll_div_sel, ppll_val;
966 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
967
968 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
969
970 if (!lvds)
971 return NULL;
972
973 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
974 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
975
976 /* These should be fail-safe defaults, fingers crossed */
977 lvds->panel_pwr_delay = 200;
978 lvds->panel_vcc_delay = 2000;
979
980 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
981 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
982 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
983
984 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
985 lvds->native_mode.vdisplay =
986 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
987 RADEON_VERT_PANEL_SHIFT) + 1;
988 else
989 lvds->native_mode.vdisplay =
990 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
991
992 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
993 lvds->native_mode.hdisplay =
994 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
995 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
996 else
997 lvds->native_mode.hdisplay =
998 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
999
1000 if ((lvds->native_mode.hdisplay < 640) ||
1001 (lvds->native_mode.vdisplay < 480)) {
1002 lvds->native_mode.hdisplay = 640;
1003 lvds->native_mode.vdisplay = 480;
1004 }
1005
1006 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1007 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1008 if ((ppll_val & 0x000707ff) == 0x1bb)
1009 lvds->use_bios_dividers = false;
1010 else {
1011 lvds->panel_ref_divider =
1012 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1013 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1014 lvds->panel_fb_divider = ppll_val & 0x7ff;
1015
1016 if ((lvds->panel_ref_divider != 0) &&
1017 (lvds->panel_fb_divider > 3))
1018 lvds->use_bios_dividers = true;
1019 }
1020 lvds->panel_vcc_delay = 200;
1021
1022 DRM_INFO("Panel info derived from registers\n");
1023 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1024 lvds->native_mode.vdisplay);
1025
1026 return lvds;
1027 }
1028
1029 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1030 *encoder)
1031 {
1032 struct drm_device *dev = encoder->base.dev;
1033 struct radeon_device *rdev = dev->dev_private;
1034 uint16_t lcd_info;
1035 uint32_t panel_setup;
1036 char stmp[30];
1037 int tmp, i;
1038 struct radeon_encoder_lvds *lvds = NULL;
1039
1040 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1041
1042 if (lcd_info) {
1043 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1044
1045 if (!lvds)
1046 return NULL;
1047
1048 for (i = 0; i < 24; i++)
1049 stmp[i] = RBIOS8(lcd_info + i + 1);
1050 stmp[24] = 0;
1051
1052 DRM_INFO("Panel ID String: %s\n", stmp);
1053
1054 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1055 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1056
1057 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1058 lvds->native_mode.vdisplay);
1059
1060 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1061 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1062
1063 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1064 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1065 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1066
1067 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1068 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1069 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1070 if ((lvds->panel_ref_divider != 0) &&
1071 (lvds->panel_fb_divider > 3))
1072 lvds->use_bios_dividers = true;
1073
1074 panel_setup = RBIOS32(lcd_info + 0x39);
1075 lvds->lvds_gen_cntl = 0xff00;
1076 if (panel_setup & 0x1)
1077 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1078
1079 if ((panel_setup >> 4) & 0x1)
1080 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1081
1082 switch ((panel_setup >> 8) & 0x7) {
1083 case 0:
1084 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1085 break;
1086 case 1:
1087 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1088 break;
1089 case 2:
1090 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1091 break;
1092 default:
1093 break;
1094 }
1095
1096 if ((panel_setup >> 16) & 0x1)
1097 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1098
1099 if ((panel_setup >> 17) & 0x1)
1100 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1101
1102 if ((panel_setup >> 18) & 0x1)
1103 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1104
1105 if ((panel_setup >> 23) & 0x1)
1106 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1107
1108 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1109
1110 for (i = 0; i < 32; i++) {
1111 tmp = RBIOS16(lcd_info + 64 + i * 2);
1112 if (tmp == 0)
1113 break;
1114
1115 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1116 (RBIOS16(tmp + 2) ==
1117 lvds->native_mode.vdisplay)) {
1118 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
1119 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
1120 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
1121 RBIOS16(tmp + 21)) * 8;
1122
1123 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
1124 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
1125 lvds->native_mode.vsync_end =
1126 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
1127 (RBIOS16(tmp + 28) & 0x7ff);
1128
1129 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1130 lvds->native_mode.flags = 0;
1131 /* set crtc values */
1132 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1133
1134 }
1135 }
1136 } else {
1137 DRM_INFO("No panel info found in BIOS\n");
1138 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1139 }
1140
1141 if (lvds)
1142 encoder->native_mode = lvds->native_mode;
1143 return lvds;
1144 }
1145
1146 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1147 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1148 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1149 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1150 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1151 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1152 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1153 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1154 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1155 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1156 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1157 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1158 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1159 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1160 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1161 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1162 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1163 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1164 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1165 };
1166
1167 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1168 struct radeon_encoder_int_tmds *tmds)
1169 {
1170 struct drm_device *dev = encoder->base.dev;
1171 struct radeon_device *rdev = dev->dev_private;
1172 int i;
1173
1174 for (i = 0; i < 4; i++) {
1175 tmds->tmds_pll[i].value =
1176 default_tmds_pll[rdev->family][i].value;
1177 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1178 }
1179
1180 return true;
1181 }
1182
1183 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1184 struct radeon_encoder_int_tmds *tmds)
1185 {
1186 struct drm_device *dev = encoder->base.dev;
1187 struct radeon_device *rdev = dev->dev_private;
1188 uint16_t tmds_info;
1189 int i, n;
1190 uint8_t ver;
1191
1192 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1193
1194 if (tmds_info) {
1195 ver = RBIOS8(tmds_info);
1196 DRM_INFO("DFP table revision: %d\n", ver);
1197 if (ver == 3) {
1198 n = RBIOS8(tmds_info + 5) + 1;
1199 if (n > 4)
1200 n = 4;
1201 for (i = 0; i < n; i++) {
1202 tmds->tmds_pll[i].value =
1203 RBIOS32(tmds_info + i * 10 + 0x08);
1204 tmds->tmds_pll[i].freq =
1205 RBIOS16(tmds_info + i * 10 + 0x10);
1206 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1207 tmds->tmds_pll[i].freq,
1208 tmds->tmds_pll[i].value);
1209 }
1210 } else if (ver == 4) {
1211 int stride = 0;
1212 n = RBIOS8(tmds_info + 5) + 1;
1213 if (n > 4)
1214 n = 4;
1215 for (i = 0; i < n; i++) {
1216 tmds->tmds_pll[i].value =
1217 RBIOS32(tmds_info + stride + 0x08);
1218 tmds->tmds_pll[i].freq =
1219 RBIOS16(tmds_info + stride + 0x10);
1220 if (i == 0)
1221 stride += 10;
1222 else
1223 stride += 6;
1224 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1225 tmds->tmds_pll[i].freq,
1226 tmds->tmds_pll[i].value);
1227 }
1228 }
1229 } else {
1230 DRM_INFO("No TMDS info found in BIOS\n");
1231 return false;
1232 }
1233 return true;
1234 }
1235
1236 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1237 struct radeon_encoder_ext_tmds *tmds)
1238 {
1239 struct drm_device *dev = encoder->base.dev;
1240 struct radeon_device *rdev = dev->dev_private;
1241 struct radeon_i2c_bus_rec i2c_bus;
1242
1243 /* default for macs */
1244 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1245 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1246
1247 /* XXX some macs have duallink chips */
1248 switch (rdev->mode_info.connector_table) {
1249 case CT_POWERBOOK_EXTERNAL:
1250 case CT_MINI_EXTERNAL:
1251 default:
1252 tmds->dvo_chip = DVO_SIL164;
1253 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1254 break;
1255 }
1256
1257 return true;
1258 }
1259
1260 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1261 struct radeon_encoder_ext_tmds *tmds)
1262 {
1263 struct drm_device *dev = encoder->base.dev;
1264 struct radeon_device *rdev = dev->dev_private;
1265 uint16_t offset;
1266 uint8_t ver, id, blocks, clk, data;
1267 int i;
1268 enum radeon_combios_ddc gpio;
1269 struct radeon_i2c_bus_rec i2c_bus;
1270
1271 tmds->i2c_bus = NULL;
1272 if (rdev->flags & RADEON_IS_IGP) {
1273 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1274 if (offset) {
1275 ver = RBIOS8(offset);
1276 DRM_INFO("GPIO Table revision: %d\n", ver);
1277 blocks = RBIOS8(offset + 2);
1278 for (i = 0; i < blocks; i++) {
1279 id = RBIOS8(offset + 3 + (i * 5) + 0);
1280 if (id == 136) {
1281 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1282 data = RBIOS8(offset + 3 + (i * 5) + 4);
1283 i2c_bus.valid = true;
1284 i2c_bus.mask_clk_mask = (1 << clk);
1285 i2c_bus.mask_data_mask = (1 << data);
1286 i2c_bus.a_clk_mask = (1 << clk);
1287 i2c_bus.a_data_mask = (1 << data);
1288 i2c_bus.en_clk_mask = (1 << clk);
1289 i2c_bus.en_data_mask = (1 << data);
1290 i2c_bus.y_clk_mask = (1 << clk);
1291 i2c_bus.y_data_mask = (1 << data);
1292 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1293 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1294 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1295 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1296 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1297 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1298 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1299 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1300 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1301 tmds->dvo_chip = DVO_SIL164;
1302 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1303 break;
1304 }
1305 }
1306 }
1307 } else {
1308 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1309 if (offset) {
1310 ver = RBIOS8(offset);
1311 DRM_INFO("External TMDS Table revision: %d\n", ver);
1312 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1313 tmds->slave_addr >>= 1; /* 7 bit addressing */
1314 gpio = RBIOS8(offset + 4 + 3);
1315 switch (gpio) {
1316 case DDC_MONID:
1317 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1318 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1319 break;
1320 case DDC_DVI:
1321 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1322 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1323 break;
1324 case DDC_VGA:
1325 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1326 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1327 break;
1328 case DDC_CRT2:
1329 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1330 if (rdev->family >= CHIP_R300)
1331 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1332 else
1333 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1334 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1335 break;
1336 case DDC_LCD: /* MM i2c */
1337 i2c_bus.valid = true;
1338 i2c_bus.hw_capable = true;
1339 i2c_bus.mm_i2c = true;
1340 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1341 break;
1342 default:
1343 DRM_ERROR("Unsupported gpio %d\n", gpio);
1344 break;
1345 }
1346 }
1347 }
1348
1349 if (!tmds->i2c_bus) {
1350 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1351 return false;
1352 }
1353
1354 return true;
1355 }
1356
1357 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1358 {
1359 struct radeon_device *rdev = dev->dev_private;
1360 struct radeon_i2c_bus_rec ddc_i2c;
1361 struct radeon_hpd hpd;
1362
1363 rdev->mode_info.connector_table = radeon_connector_table;
1364 if (rdev->mode_info.connector_table == CT_NONE) {
1365 #ifdef CONFIG_PPC_PMAC
1366 if (of_machine_is_compatible("PowerBook3,3")) {
1367 /* powerbook with VGA */
1368 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1369 } else if (of_machine_is_compatible("PowerBook3,4") ||
1370 of_machine_is_compatible("PowerBook3,5")) {
1371 /* powerbook with internal tmds */
1372 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1373 } else if (of_machine_is_compatible("PowerBook5,1") ||
1374 of_machine_is_compatible("PowerBook5,2") ||
1375 of_machine_is_compatible("PowerBook5,3") ||
1376 of_machine_is_compatible("PowerBook5,4") ||
1377 of_machine_is_compatible("PowerBook5,5")) {
1378 /* powerbook with external single link tmds (sil164) */
1379 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1380 } else if (of_machine_is_compatible("PowerBook5,6")) {
1381 /* powerbook with external dual or single link tmds */
1382 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1383 } else if (of_machine_is_compatible("PowerBook5,7") ||
1384 of_machine_is_compatible("PowerBook5,8") ||
1385 of_machine_is_compatible("PowerBook5,9")) {
1386 /* PowerBook6,2 ? */
1387 /* powerbook with external dual link tmds (sil1178?) */
1388 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1389 } else if (of_machine_is_compatible("PowerBook4,1") ||
1390 of_machine_is_compatible("PowerBook4,2") ||
1391 of_machine_is_compatible("PowerBook4,3") ||
1392 of_machine_is_compatible("PowerBook6,3") ||
1393 of_machine_is_compatible("PowerBook6,5") ||
1394 of_machine_is_compatible("PowerBook6,7")) {
1395 /* ibook */
1396 rdev->mode_info.connector_table = CT_IBOOK;
1397 } else if (of_machine_is_compatible("PowerMac4,4")) {
1398 /* emac */
1399 rdev->mode_info.connector_table = CT_EMAC;
1400 } else if (of_machine_is_compatible("PowerMac10,1")) {
1401 /* mini with internal tmds */
1402 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1403 } else if (of_machine_is_compatible("PowerMac10,2")) {
1404 /* mini with external tmds */
1405 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1406 } else if (of_machine_is_compatible("PowerMac12,1")) {
1407 /* PowerMac8,1 ? */
1408 /* imac g5 isight */
1409 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1410 } else
1411 #endif /* CONFIG_PPC_PMAC */
1412 rdev->mode_info.connector_table = CT_GENERIC;
1413 }
1414
1415 switch (rdev->mode_info.connector_table) {
1416 case CT_GENERIC:
1417 DRM_INFO("Connector Table: %d (generic)\n",
1418 rdev->mode_info.connector_table);
1419 /* these are the most common settings */
1420 if (rdev->flags & RADEON_SINGLE_CRTC) {
1421 /* VGA - primary dac */
1422 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1423 hpd.hpd = RADEON_HPD_NONE;
1424 radeon_add_legacy_encoder(dev,
1425 radeon_get_encoder_id(dev,
1426 ATOM_DEVICE_CRT1_SUPPORT,
1427 1),
1428 ATOM_DEVICE_CRT1_SUPPORT);
1429 radeon_add_legacy_connector(dev, 0,
1430 ATOM_DEVICE_CRT1_SUPPORT,
1431 DRM_MODE_CONNECTOR_VGA,
1432 &ddc_i2c,
1433 CONNECTOR_OBJECT_ID_VGA,
1434 &hpd);
1435 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1436 /* LVDS */
1437 ddc_i2c = combios_setup_i2c_bus(rdev, 0);
1438 hpd.hpd = RADEON_HPD_NONE;
1439 radeon_add_legacy_encoder(dev,
1440 radeon_get_encoder_id(dev,
1441 ATOM_DEVICE_LCD1_SUPPORT,
1442 0),
1443 ATOM_DEVICE_LCD1_SUPPORT);
1444 radeon_add_legacy_connector(dev, 0,
1445 ATOM_DEVICE_LCD1_SUPPORT,
1446 DRM_MODE_CONNECTOR_LVDS,
1447 &ddc_i2c,
1448 CONNECTOR_OBJECT_ID_LVDS,
1449 &hpd);
1450
1451 /* VGA - primary dac */
1452 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1453 hpd.hpd = RADEON_HPD_NONE;
1454 radeon_add_legacy_encoder(dev,
1455 radeon_get_encoder_id(dev,
1456 ATOM_DEVICE_CRT1_SUPPORT,
1457 1),
1458 ATOM_DEVICE_CRT1_SUPPORT);
1459 radeon_add_legacy_connector(dev, 1,
1460 ATOM_DEVICE_CRT1_SUPPORT,
1461 DRM_MODE_CONNECTOR_VGA,
1462 &ddc_i2c,
1463 CONNECTOR_OBJECT_ID_VGA,
1464 &hpd);
1465 } else {
1466 /* DVI-I - tv dac, int tmds */
1467 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1468 hpd.hpd = RADEON_HPD_1;
1469 radeon_add_legacy_encoder(dev,
1470 radeon_get_encoder_id(dev,
1471 ATOM_DEVICE_DFP1_SUPPORT,
1472 0),
1473 ATOM_DEVICE_DFP1_SUPPORT);
1474 radeon_add_legacy_encoder(dev,
1475 radeon_get_encoder_id(dev,
1476 ATOM_DEVICE_CRT2_SUPPORT,
1477 2),
1478 ATOM_DEVICE_CRT2_SUPPORT);
1479 radeon_add_legacy_connector(dev, 0,
1480 ATOM_DEVICE_DFP1_SUPPORT |
1481 ATOM_DEVICE_CRT2_SUPPORT,
1482 DRM_MODE_CONNECTOR_DVII,
1483 &ddc_i2c,
1484 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1485 &hpd);
1486
1487 /* VGA - primary dac */
1488 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1489 hpd.hpd = RADEON_HPD_NONE;
1490 radeon_add_legacy_encoder(dev,
1491 radeon_get_encoder_id(dev,
1492 ATOM_DEVICE_CRT1_SUPPORT,
1493 1),
1494 ATOM_DEVICE_CRT1_SUPPORT);
1495 radeon_add_legacy_connector(dev, 1,
1496 ATOM_DEVICE_CRT1_SUPPORT,
1497 DRM_MODE_CONNECTOR_VGA,
1498 &ddc_i2c,
1499 CONNECTOR_OBJECT_ID_VGA,
1500 &hpd);
1501 }
1502
1503 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1504 /* TV - tv dac */
1505 ddc_i2c.valid = false;
1506 hpd.hpd = RADEON_HPD_NONE;
1507 radeon_add_legacy_encoder(dev,
1508 radeon_get_encoder_id(dev,
1509 ATOM_DEVICE_TV1_SUPPORT,
1510 2),
1511 ATOM_DEVICE_TV1_SUPPORT);
1512 radeon_add_legacy_connector(dev, 2,
1513 ATOM_DEVICE_TV1_SUPPORT,
1514 DRM_MODE_CONNECTOR_SVIDEO,
1515 &ddc_i2c,
1516 CONNECTOR_OBJECT_ID_SVIDEO,
1517 &hpd);
1518 }
1519 break;
1520 case CT_IBOOK:
1521 DRM_INFO("Connector Table: %d (ibook)\n",
1522 rdev->mode_info.connector_table);
1523 /* LVDS */
1524 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1525 hpd.hpd = RADEON_HPD_NONE;
1526 radeon_add_legacy_encoder(dev,
1527 radeon_get_encoder_id(dev,
1528 ATOM_DEVICE_LCD1_SUPPORT,
1529 0),
1530 ATOM_DEVICE_LCD1_SUPPORT);
1531 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1532 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1533 CONNECTOR_OBJECT_ID_LVDS,
1534 &hpd);
1535 /* VGA - TV DAC */
1536 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1537 hpd.hpd = RADEON_HPD_NONE;
1538 radeon_add_legacy_encoder(dev,
1539 radeon_get_encoder_id(dev,
1540 ATOM_DEVICE_CRT2_SUPPORT,
1541 2),
1542 ATOM_DEVICE_CRT2_SUPPORT);
1543 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1544 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1545 CONNECTOR_OBJECT_ID_VGA,
1546 &hpd);
1547 /* TV - TV DAC */
1548 ddc_i2c.valid = false;
1549 hpd.hpd = RADEON_HPD_NONE;
1550 radeon_add_legacy_encoder(dev,
1551 radeon_get_encoder_id(dev,
1552 ATOM_DEVICE_TV1_SUPPORT,
1553 2),
1554 ATOM_DEVICE_TV1_SUPPORT);
1555 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1556 DRM_MODE_CONNECTOR_SVIDEO,
1557 &ddc_i2c,
1558 CONNECTOR_OBJECT_ID_SVIDEO,
1559 &hpd);
1560 break;
1561 case CT_POWERBOOK_EXTERNAL:
1562 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1563 rdev->mode_info.connector_table);
1564 /* LVDS */
1565 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1566 hpd.hpd = RADEON_HPD_NONE;
1567 radeon_add_legacy_encoder(dev,
1568 radeon_get_encoder_id(dev,
1569 ATOM_DEVICE_LCD1_SUPPORT,
1570 0),
1571 ATOM_DEVICE_LCD1_SUPPORT);
1572 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1573 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1574 CONNECTOR_OBJECT_ID_LVDS,
1575 &hpd);
1576 /* DVI-I - primary dac, ext tmds */
1577 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1578 hpd.hpd = RADEON_HPD_2; /* ??? */
1579 radeon_add_legacy_encoder(dev,
1580 radeon_get_encoder_id(dev,
1581 ATOM_DEVICE_DFP2_SUPPORT,
1582 0),
1583 ATOM_DEVICE_DFP2_SUPPORT);
1584 radeon_add_legacy_encoder(dev,
1585 radeon_get_encoder_id(dev,
1586 ATOM_DEVICE_CRT1_SUPPORT,
1587 1),
1588 ATOM_DEVICE_CRT1_SUPPORT);
1589 /* XXX some are SL */
1590 radeon_add_legacy_connector(dev, 1,
1591 ATOM_DEVICE_DFP2_SUPPORT |
1592 ATOM_DEVICE_CRT1_SUPPORT,
1593 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1594 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1595 &hpd);
1596 /* TV - TV DAC */
1597 ddc_i2c.valid = false;
1598 hpd.hpd = RADEON_HPD_NONE;
1599 radeon_add_legacy_encoder(dev,
1600 radeon_get_encoder_id(dev,
1601 ATOM_DEVICE_TV1_SUPPORT,
1602 2),
1603 ATOM_DEVICE_TV1_SUPPORT);
1604 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1605 DRM_MODE_CONNECTOR_SVIDEO,
1606 &ddc_i2c,
1607 CONNECTOR_OBJECT_ID_SVIDEO,
1608 &hpd);
1609 break;
1610 case CT_POWERBOOK_INTERNAL:
1611 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1612 rdev->mode_info.connector_table);
1613 /* LVDS */
1614 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1615 hpd.hpd = RADEON_HPD_NONE;
1616 radeon_add_legacy_encoder(dev,
1617 radeon_get_encoder_id(dev,
1618 ATOM_DEVICE_LCD1_SUPPORT,
1619 0),
1620 ATOM_DEVICE_LCD1_SUPPORT);
1621 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1622 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1623 CONNECTOR_OBJECT_ID_LVDS,
1624 &hpd);
1625 /* DVI-I - primary dac, int tmds */
1626 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1627 hpd.hpd = RADEON_HPD_1; /* ??? */
1628 radeon_add_legacy_encoder(dev,
1629 radeon_get_encoder_id(dev,
1630 ATOM_DEVICE_DFP1_SUPPORT,
1631 0),
1632 ATOM_DEVICE_DFP1_SUPPORT);
1633 radeon_add_legacy_encoder(dev,
1634 radeon_get_encoder_id(dev,
1635 ATOM_DEVICE_CRT1_SUPPORT,
1636 1),
1637 ATOM_DEVICE_CRT1_SUPPORT);
1638 radeon_add_legacy_connector(dev, 1,
1639 ATOM_DEVICE_DFP1_SUPPORT |
1640 ATOM_DEVICE_CRT1_SUPPORT,
1641 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1642 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1643 &hpd);
1644 /* TV - TV DAC */
1645 ddc_i2c.valid = false;
1646 hpd.hpd = RADEON_HPD_NONE;
1647 radeon_add_legacy_encoder(dev,
1648 radeon_get_encoder_id(dev,
1649 ATOM_DEVICE_TV1_SUPPORT,
1650 2),
1651 ATOM_DEVICE_TV1_SUPPORT);
1652 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1653 DRM_MODE_CONNECTOR_SVIDEO,
1654 &ddc_i2c,
1655 CONNECTOR_OBJECT_ID_SVIDEO,
1656 &hpd);
1657 break;
1658 case CT_POWERBOOK_VGA:
1659 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1660 rdev->mode_info.connector_table);
1661 /* LVDS */
1662 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1663 hpd.hpd = RADEON_HPD_NONE;
1664 radeon_add_legacy_encoder(dev,
1665 radeon_get_encoder_id(dev,
1666 ATOM_DEVICE_LCD1_SUPPORT,
1667 0),
1668 ATOM_DEVICE_LCD1_SUPPORT);
1669 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1670 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1671 CONNECTOR_OBJECT_ID_LVDS,
1672 &hpd);
1673 /* VGA - primary dac */
1674 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1675 hpd.hpd = RADEON_HPD_NONE;
1676 radeon_add_legacy_encoder(dev,
1677 radeon_get_encoder_id(dev,
1678 ATOM_DEVICE_CRT1_SUPPORT,
1679 1),
1680 ATOM_DEVICE_CRT1_SUPPORT);
1681 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1682 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1683 CONNECTOR_OBJECT_ID_VGA,
1684 &hpd);
1685 /* TV - TV DAC */
1686 ddc_i2c.valid = false;
1687 hpd.hpd = RADEON_HPD_NONE;
1688 radeon_add_legacy_encoder(dev,
1689 radeon_get_encoder_id(dev,
1690 ATOM_DEVICE_TV1_SUPPORT,
1691 2),
1692 ATOM_DEVICE_TV1_SUPPORT);
1693 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1694 DRM_MODE_CONNECTOR_SVIDEO,
1695 &ddc_i2c,
1696 CONNECTOR_OBJECT_ID_SVIDEO,
1697 &hpd);
1698 break;
1699 case CT_MINI_EXTERNAL:
1700 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1701 rdev->mode_info.connector_table);
1702 /* DVI-I - tv dac, ext tmds */
1703 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1704 hpd.hpd = RADEON_HPD_2; /* ??? */
1705 radeon_add_legacy_encoder(dev,
1706 radeon_get_encoder_id(dev,
1707 ATOM_DEVICE_DFP2_SUPPORT,
1708 0),
1709 ATOM_DEVICE_DFP2_SUPPORT);
1710 radeon_add_legacy_encoder(dev,
1711 radeon_get_encoder_id(dev,
1712 ATOM_DEVICE_CRT2_SUPPORT,
1713 2),
1714 ATOM_DEVICE_CRT2_SUPPORT);
1715 /* XXX are any DL? */
1716 radeon_add_legacy_connector(dev, 0,
1717 ATOM_DEVICE_DFP2_SUPPORT |
1718 ATOM_DEVICE_CRT2_SUPPORT,
1719 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1720 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1721 &hpd);
1722 /* TV - TV DAC */
1723 ddc_i2c.valid = false;
1724 hpd.hpd = RADEON_HPD_NONE;
1725 radeon_add_legacy_encoder(dev,
1726 radeon_get_encoder_id(dev,
1727 ATOM_DEVICE_TV1_SUPPORT,
1728 2),
1729 ATOM_DEVICE_TV1_SUPPORT);
1730 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1731 DRM_MODE_CONNECTOR_SVIDEO,
1732 &ddc_i2c,
1733 CONNECTOR_OBJECT_ID_SVIDEO,
1734 &hpd);
1735 break;
1736 case CT_MINI_INTERNAL:
1737 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1738 rdev->mode_info.connector_table);
1739 /* DVI-I - tv dac, int tmds */
1740 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1741 hpd.hpd = RADEON_HPD_1; /* ??? */
1742 radeon_add_legacy_encoder(dev,
1743 radeon_get_encoder_id(dev,
1744 ATOM_DEVICE_DFP1_SUPPORT,
1745 0),
1746 ATOM_DEVICE_DFP1_SUPPORT);
1747 radeon_add_legacy_encoder(dev,
1748 radeon_get_encoder_id(dev,
1749 ATOM_DEVICE_CRT2_SUPPORT,
1750 2),
1751 ATOM_DEVICE_CRT2_SUPPORT);
1752 radeon_add_legacy_connector(dev, 0,
1753 ATOM_DEVICE_DFP1_SUPPORT |
1754 ATOM_DEVICE_CRT2_SUPPORT,
1755 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1756 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1757 &hpd);
1758 /* TV - TV DAC */
1759 ddc_i2c.valid = false;
1760 hpd.hpd = RADEON_HPD_NONE;
1761 radeon_add_legacy_encoder(dev,
1762 radeon_get_encoder_id(dev,
1763 ATOM_DEVICE_TV1_SUPPORT,
1764 2),
1765 ATOM_DEVICE_TV1_SUPPORT);
1766 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1767 DRM_MODE_CONNECTOR_SVIDEO,
1768 &ddc_i2c,
1769 CONNECTOR_OBJECT_ID_SVIDEO,
1770 &hpd);
1771 break;
1772 case CT_IMAC_G5_ISIGHT:
1773 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1774 rdev->mode_info.connector_table);
1775 /* DVI-D - int tmds */
1776 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1777 hpd.hpd = RADEON_HPD_1; /* ??? */
1778 radeon_add_legacy_encoder(dev,
1779 radeon_get_encoder_id(dev,
1780 ATOM_DEVICE_DFP1_SUPPORT,
1781 0),
1782 ATOM_DEVICE_DFP1_SUPPORT);
1783 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1784 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1785 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1786 &hpd);
1787 /* VGA - tv dac */
1788 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1789 hpd.hpd = RADEON_HPD_NONE;
1790 radeon_add_legacy_encoder(dev,
1791 radeon_get_encoder_id(dev,
1792 ATOM_DEVICE_CRT2_SUPPORT,
1793 2),
1794 ATOM_DEVICE_CRT2_SUPPORT);
1795 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1796 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1797 CONNECTOR_OBJECT_ID_VGA,
1798 &hpd);
1799 /* TV - TV DAC */
1800 ddc_i2c.valid = false;
1801 hpd.hpd = RADEON_HPD_NONE;
1802 radeon_add_legacy_encoder(dev,
1803 radeon_get_encoder_id(dev,
1804 ATOM_DEVICE_TV1_SUPPORT,
1805 2),
1806 ATOM_DEVICE_TV1_SUPPORT);
1807 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1808 DRM_MODE_CONNECTOR_SVIDEO,
1809 &ddc_i2c,
1810 CONNECTOR_OBJECT_ID_SVIDEO,
1811 &hpd);
1812 break;
1813 case CT_EMAC:
1814 DRM_INFO("Connector Table: %d (emac)\n",
1815 rdev->mode_info.connector_table);
1816 /* VGA - primary dac */
1817 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1818 hpd.hpd = RADEON_HPD_NONE;
1819 radeon_add_legacy_encoder(dev,
1820 radeon_get_encoder_id(dev,
1821 ATOM_DEVICE_CRT1_SUPPORT,
1822 1),
1823 ATOM_DEVICE_CRT1_SUPPORT);
1824 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1825 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1826 CONNECTOR_OBJECT_ID_VGA,
1827 &hpd);
1828 /* VGA - tv dac */
1829 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1830 hpd.hpd = RADEON_HPD_NONE;
1831 radeon_add_legacy_encoder(dev,
1832 radeon_get_encoder_id(dev,
1833 ATOM_DEVICE_CRT2_SUPPORT,
1834 2),
1835 ATOM_DEVICE_CRT2_SUPPORT);
1836 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1837 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1838 CONNECTOR_OBJECT_ID_VGA,
1839 &hpd);
1840 /* TV - TV DAC */
1841 ddc_i2c.valid = false;
1842 hpd.hpd = RADEON_HPD_NONE;
1843 radeon_add_legacy_encoder(dev,
1844 radeon_get_encoder_id(dev,
1845 ATOM_DEVICE_TV1_SUPPORT,
1846 2),
1847 ATOM_DEVICE_TV1_SUPPORT);
1848 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1849 DRM_MODE_CONNECTOR_SVIDEO,
1850 &ddc_i2c,
1851 CONNECTOR_OBJECT_ID_SVIDEO,
1852 &hpd);
1853 break;
1854 default:
1855 DRM_INFO("Connector table: %d (invalid)\n",
1856 rdev->mode_info.connector_table);
1857 return false;
1858 }
1859
1860 radeon_link_encoder_connector(dev);
1861
1862 return true;
1863 }
1864
1865 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1866 int bios_index,
1867 enum radeon_combios_connector
1868 *legacy_connector,
1869 struct radeon_i2c_bus_rec *ddc_i2c,
1870 struct radeon_hpd *hpd)
1871 {
1872 struct radeon_device *rdev = dev->dev_private;
1873
1874 /* XPRESS DDC quirks */
1875 if ((rdev->family == CHIP_RS400 ||
1876 rdev->family == CHIP_RS480) &&
1877 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1878 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1879 else if ((rdev->family == CHIP_RS400 ||
1880 rdev->family == CHIP_RS480) &&
1881 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1882 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1883 ddc_i2c->mask_clk_mask = (0x20 << 8);
1884 ddc_i2c->mask_data_mask = 0x80;
1885 ddc_i2c->a_clk_mask = (0x20 << 8);
1886 ddc_i2c->a_data_mask = 0x80;
1887 ddc_i2c->en_clk_mask = (0x20 << 8);
1888 ddc_i2c->en_data_mask = 0x80;
1889 ddc_i2c->y_clk_mask = (0x20 << 8);
1890 ddc_i2c->y_data_mask = 0x80;
1891 }
1892
1893 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1894 if ((rdev->family >= CHIP_R300) &&
1895 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1896 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1897
1898 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1899 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1900 if (dev->pdev->device == 0x515e &&
1901 dev->pdev->subsystem_vendor == 0x1014) {
1902 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1903 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1904 return false;
1905 }
1906
1907 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1908 if (dev->pdev->device == 0x5159 &&
1909 dev->pdev->subsystem_vendor == 0x1002 &&
1910 dev->pdev->subsystem_device == 0x013a) {
1911 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1912 *legacy_connector = CONNECTOR_CRT_LEGACY;
1913
1914 }
1915
1916 /* X300 card with extra non-existent DVI port */
1917 if (dev->pdev->device == 0x5B60 &&
1918 dev->pdev->subsystem_vendor == 0x17af &&
1919 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1920 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1921 return false;
1922 }
1923
1924 return true;
1925 }
1926
1927 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1928 {
1929 /* Acer 5102 has non-existent TV port */
1930 if (dev->pdev->device == 0x5975 &&
1931 dev->pdev->subsystem_vendor == 0x1025 &&
1932 dev->pdev->subsystem_device == 0x009f)
1933 return false;
1934
1935 /* HP dc5750 has non-existent TV port */
1936 if (dev->pdev->device == 0x5974 &&
1937 dev->pdev->subsystem_vendor == 0x103c &&
1938 dev->pdev->subsystem_device == 0x280a)
1939 return false;
1940
1941 /* MSI S270 has non-existent TV port */
1942 if (dev->pdev->device == 0x5955 &&
1943 dev->pdev->subsystem_vendor == 0x1462 &&
1944 dev->pdev->subsystem_device == 0x0131)
1945 return false;
1946
1947 return true;
1948 }
1949
1950 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1951 {
1952 struct radeon_device *rdev = dev->dev_private;
1953 uint32_t ext_tmds_info;
1954
1955 if (rdev->flags & RADEON_IS_IGP) {
1956 if (is_dvi_d)
1957 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1958 else
1959 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1960 }
1961 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1962 if (ext_tmds_info) {
1963 uint8_t rev = RBIOS8(ext_tmds_info);
1964 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1965 if (rev >= 3) {
1966 if (is_dvi_d)
1967 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1968 else
1969 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1970 } else {
1971 if (flags & 1) {
1972 if (is_dvi_d)
1973 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1974 else
1975 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1976 }
1977 }
1978 }
1979 if (is_dvi_d)
1980 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1981 else
1982 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1983 }
1984
1985 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1986 {
1987 struct radeon_device *rdev = dev->dev_private;
1988 uint32_t conn_info, entry, devices;
1989 uint16_t tmp, connector_object_id;
1990 enum radeon_combios_ddc ddc_type;
1991 enum radeon_combios_connector connector;
1992 int i = 0;
1993 struct radeon_i2c_bus_rec ddc_i2c;
1994 struct radeon_hpd hpd;
1995
1996 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1997 if (conn_info) {
1998 for (i = 0; i < 4; i++) {
1999 entry = conn_info + 2 + i * 2;
2000
2001 if (!RBIOS16(entry))
2002 break;
2003
2004 tmp = RBIOS16(entry);
2005
2006 connector = (tmp >> 12) & 0xf;
2007
2008 ddc_type = (tmp >> 8) & 0xf;
2009 switch (ddc_type) {
2010 case DDC_MONID:
2011 ddc_i2c =
2012 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
2013 break;
2014 case DDC_DVI:
2015 ddc_i2c =
2016 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2017 break;
2018 case DDC_VGA:
2019 ddc_i2c =
2020 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2021 break;
2022 case DDC_CRT2:
2023 ddc_i2c =
2024 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
2025 break;
2026 default:
2027 break;
2028 }
2029
2030 switch (connector) {
2031 case CONNECTOR_PROPRIETARY_LEGACY:
2032 case CONNECTOR_DVI_I_LEGACY:
2033 case CONNECTOR_DVI_D_LEGACY:
2034 if ((tmp >> 4) & 0x1)
2035 hpd.hpd = RADEON_HPD_2;
2036 else
2037 hpd.hpd = RADEON_HPD_1;
2038 break;
2039 default:
2040 hpd.hpd = RADEON_HPD_NONE;
2041 break;
2042 }
2043
2044 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2045 &ddc_i2c, &hpd))
2046 continue;
2047
2048 switch (connector) {
2049 case CONNECTOR_PROPRIETARY_LEGACY:
2050 if ((tmp >> 4) & 0x1)
2051 devices = ATOM_DEVICE_DFP2_SUPPORT;
2052 else
2053 devices = ATOM_DEVICE_DFP1_SUPPORT;
2054 radeon_add_legacy_encoder(dev,
2055 radeon_get_encoder_id
2056 (dev, devices, 0),
2057 devices);
2058 radeon_add_legacy_connector(dev, i, devices,
2059 legacy_connector_convert
2060 [connector],
2061 &ddc_i2c,
2062 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2063 &hpd);
2064 break;
2065 case CONNECTOR_CRT_LEGACY:
2066 if (tmp & 0x1) {
2067 devices = ATOM_DEVICE_CRT2_SUPPORT;
2068 radeon_add_legacy_encoder(dev,
2069 radeon_get_encoder_id
2070 (dev,
2071 ATOM_DEVICE_CRT2_SUPPORT,
2072 2),
2073 ATOM_DEVICE_CRT2_SUPPORT);
2074 } else {
2075 devices = ATOM_DEVICE_CRT1_SUPPORT;
2076 radeon_add_legacy_encoder(dev,
2077 radeon_get_encoder_id
2078 (dev,
2079 ATOM_DEVICE_CRT1_SUPPORT,
2080 1),
2081 ATOM_DEVICE_CRT1_SUPPORT);
2082 }
2083 radeon_add_legacy_connector(dev,
2084 i,
2085 devices,
2086 legacy_connector_convert
2087 [connector],
2088 &ddc_i2c,
2089 CONNECTOR_OBJECT_ID_VGA,
2090 &hpd);
2091 break;
2092 case CONNECTOR_DVI_I_LEGACY:
2093 devices = 0;
2094 if (tmp & 0x1) {
2095 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2096 radeon_add_legacy_encoder(dev,
2097 radeon_get_encoder_id
2098 (dev,
2099 ATOM_DEVICE_CRT2_SUPPORT,
2100 2),
2101 ATOM_DEVICE_CRT2_SUPPORT);
2102 } else {
2103 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2104 radeon_add_legacy_encoder(dev,
2105 radeon_get_encoder_id
2106 (dev,
2107 ATOM_DEVICE_CRT1_SUPPORT,
2108 1),
2109 ATOM_DEVICE_CRT1_SUPPORT);
2110 }
2111 if ((tmp >> 4) & 0x1) {
2112 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2113 radeon_add_legacy_encoder(dev,
2114 radeon_get_encoder_id
2115 (dev,
2116 ATOM_DEVICE_DFP2_SUPPORT,
2117 0),
2118 ATOM_DEVICE_DFP2_SUPPORT);
2119 connector_object_id = combios_check_dl_dvi(dev, 0);
2120 } else {
2121 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2122 radeon_add_legacy_encoder(dev,
2123 radeon_get_encoder_id
2124 (dev,
2125 ATOM_DEVICE_DFP1_SUPPORT,
2126 0),
2127 ATOM_DEVICE_DFP1_SUPPORT);
2128 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2129 }
2130 radeon_add_legacy_connector(dev,
2131 i,
2132 devices,
2133 legacy_connector_convert
2134 [connector],
2135 &ddc_i2c,
2136 connector_object_id,
2137 &hpd);
2138 break;
2139 case CONNECTOR_DVI_D_LEGACY:
2140 if ((tmp >> 4) & 0x1) {
2141 devices = ATOM_DEVICE_DFP2_SUPPORT;
2142 connector_object_id = combios_check_dl_dvi(dev, 1);
2143 } else {
2144 devices = ATOM_DEVICE_DFP1_SUPPORT;
2145 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2146 }
2147 radeon_add_legacy_encoder(dev,
2148 radeon_get_encoder_id
2149 (dev, devices, 0),
2150 devices);
2151 radeon_add_legacy_connector(dev, i, devices,
2152 legacy_connector_convert
2153 [connector],
2154 &ddc_i2c,
2155 connector_object_id,
2156 &hpd);
2157 break;
2158 case CONNECTOR_CTV_LEGACY:
2159 case CONNECTOR_STV_LEGACY:
2160 radeon_add_legacy_encoder(dev,
2161 radeon_get_encoder_id
2162 (dev,
2163 ATOM_DEVICE_TV1_SUPPORT,
2164 2),
2165 ATOM_DEVICE_TV1_SUPPORT);
2166 radeon_add_legacy_connector(dev, i,
2167 ATOM_DEVICE_TV1_SUPPORT,
2168 legacy_connector_convert
2169 [connector],
2170 &ddc_i2c,
2171 CONNECTOR_OBJECT_ID_SVIDEO,
2172 &hpd);
2173 break;
2174 default:
2175 DRM_ERROR("Unknown connector type: %d\n",
2176 connector);
2177 continue;
2178 }
2179
2180 }
2181 } else {
2182 uint16_t tmds_info =
2183 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2184 if (tmds_info) {
2185 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2186
2187 radeon_add_legacy_encoder(dev,
2188 radeon_get_encoder_id(dev,
2189 ATOM_DEVICE_CRT1_SUPPORT,
2190 1),
2191 ATOM_DEVICE_CRT1_SUPPORT);
2192 radeon_add_legacy_encoder(dev,
2193 radeon_get_encoder_id(dev,
2194 ATOM_DEVICE_DFP1_SUPPORT,
2195 0),
2196 ATOM_DEVICE_DFP1_SUPPORT);
2197
2198 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2199 hpd.hpd = RADEON_HPD_NONE;
2200 radeon_add_legacy_connector(dev,
2201 0,
2202 ATOM_DEVICE_CRT1_SUPPORT |
2203 ATOM_DEVICE_DFP1_SUPPORT,
2204 DRM_MODE_CONNECTOR_DVII,
2205 &ddc_i2c,
2206 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2207 &hpd);
2208 } else {
2209 uint16_t crt_info =
2210 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2211 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2212 if (crt_info) {
2213 radeon_add_legacy_encoder(dev,
2214 radeon_get_encoder_id(dev,
2215 ATOM_DEVICE_CRT1_SUPPORT,
2216 1),
2217 ATOM_DEVICE_CRT1_SUPPORT);
2218 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2219 hpd.hpd = RADEON_HPD_NONE;
2220 radeon_add_legacy_connector(dev,
2221 0,
2222 ATOM_DEVICE_CRT1_SUPPORT,
2223 DRM_MODE_CONNECTOR_VGA,
2224 &ddc_i2c,
2225 CONNECTOR_OBJECT_ID_VGA,
2226 &hpd);
2227 } else {
2228 DRM_DEBUG("No connector info found\n");
2229 return false;
2230 }
2231 }
2232 }
2233
2234 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2235 uint16_t lcd_info =
2236 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2237 if (lcd_info) {
2238 uint16_t lcd_ddc_info =
2239 combios_get_table_offset(dev,
2240 COMBIOS_LCD_DDC_INFO_TABLE);
2241
2242 radeon_add_legacy_encoder(dev,
2243 radeon_get_encoder_id(dev,
2244 ATOM_DEVICE_LCD1_SUPPORT,
2245 0),
2246 ATOM_DEVICE_LCD1_SUPPORT);
2247
2248 if (lcd_ddc_info) {
2249 ddc_type = RBIOS8(lcd_ddc_info + 2);
2250 switch (ddc_type) {
2251 case DDC_MONID:
2252 ddc_i2c =
2253 combios_setup_i2c_bus
2254 (rdev, RADEON_GPIO_MONID);
2255 break;
2256 case DDC_DVI:
2257 ddc_i2c =
2258 combios_setup_i2c_bus
2259 (rdev, RADEON_GPIO_DVI_DDC);
2260 break;
2261 case DDC_VGA:
2262 ddc_i2c =
2263 combios_setup_i2c_bus
2264 (rdev, RADEON_GPIO_VGA_DDC);
2265 break;
2266 case DDC_CRT2:
2267 ddc_i2c =
2268 combios_setup_i2c_bus
2269 (rdev, RADEON_GPIO_CRT2_DDC);
2270 break;
2271 case DDC_LCD:
2272 ddc_i2c =
2273 combios_setup_i2c_bus
2274 (rdev, RADEON_GPIOPAD_MASK);
2275 ddc_i2c.mask_clk_mask =
2276 RBIOS32(lcd_ddc_info + 3);
2277 ddc_i2c.mask_data_mask =
2278 RBIOS32(lcd_ddc_info + 7);
2279 ddc_i2c.a_clk_mask =
2280 RBIOS32(lcd_ddc_info + 3);
2281 ddc_i2c.a_data_mask =
2282 RBIOS32(lcd_ddc_info + 7);
2283 ddc_i2c.en_clk_mask =
2284 RBIOS32(lcd_ddc_info + 3);
2285 ddc_i2c.en_data_mask =
2286 RBIOS32(lcd_ddc_info + 7);
2287 ddc_i2c.y_clk_mask =
2288 RBIOS32(lcd_ddc_info + 3);
2289 ddc_i2c.y_data_mask =
2290 RBIOS32(lcd_ddc_info + 7);
2291 break;
2292 case DDC_GPIO:
2293 ddc_i2c =
2294 combios_setup_i2c_bus
2295 (rdev, RADEON_MDGPIO_MASK);
2296 ddc_i2c.mask_clk_mask =
2297 RBIOS32(lcd_ddc_info + 3);
2298 ddc_i2c.mask_data_mask =
2299 RBIOS32(lcd_ddc_info + 7);
2300 ddc_i2c.a_clk_mask =
2301 RBIOS32(lcd_ddc_info + 3);
2302 ddc_i2c.a_data_mask =
2303 RBIOS32(lcd_ddc_info + 7);
2304 ddc_i2c.en_clk_mask =
2305 RBIOS32(lcd_ddc_info + 3);
2306 ddc_i2c.en_data_mask =
2307 RBIOS32(lcd_ddc_info + 7);
2308 ddc_i2c.y_clk_mask =
2309 RBIOS32(lcd_ddc_info + 3);
2310 ddc_i2c.y_data_mask =
2311 RBIOS32(lcd_ddc_info + 7);
2312 break;
2313 default:
2314 ddc_i2c.valid = false;
2315 break;
2316 }
2317 DRM_DEBUG("LCD DDC Info Table found!\n");
2318 } else
2319 ddc_i2c.valid = false;
2320
2321 hpd.hpd = RADEON_HPD_NONE;
2322 radeon_add_legacy_connector(dev,
2323 5,
2324 ATOM_DEVICE_LCD1_SUPPORT,
2325 DRM_MODE_CONNECTOR_LVDS,
2326 &ddc_i2c,
2327 CONNECTOR_OBJECT_ID_LVDS,
2328 &hpd);
2329 }
2330 }
2331
2332 /* check TV table */
2333 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2334 uint32_t tv_info =
2335 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2336 if (tv_info) {
2337 if (RBIOS8(tv_info + 6) == 'T') {
2338 if (radeon_apply_legacy_tv_quirks(dev)) {
2339 hpd.hpd = RADEON_HPD_NONE;
2340 radeon_add_legacy_encoder(dev,
2341 radeon_get_encoder_id
2342 (dev,
2343 ATOM_DEVICE_TV1_SUPPORT,
2344 2),
2345 ATOM_DEVICE_TV1_SUPPORT);
2346 radeon_add_legacy_connector(dev, 6,
2347 ATOM_DEVICE_TV1_SUPPORT,
2348 DRM_MODE_CONNECTOR_SVIDEO,
2349 &ddc_i2c,
2350 CONNECTOR_OBJECT_ID_SVIDEO,
2351 &hpd);
2352 }
2353 }
2354 }
2355 }
2356
2357 radeon_link_encoder_connector(dev);
2358
2359 return true;
2360 }
2361
2362 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2363 {
2364 struct drm_device *dev = rdev->ddev;
2365 u16 offset, misc, misc2 = 0;
2366 u8 rev, blocks, tmp;
2367 int state_index = 0;
2368
2369 rdev->pm.default_power_state = NULL;
2370
2371 if (rdev->flags & RADEON_IS_MOBILITY) {
2372 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2373 if (offset) {
2374 rev = RBIOS8(offset);
2375 blocks = RBIOS8(offset + 0x2);
2376 /* power mode 0 tends to be the only valid one */
2377 rdev->pm.power_state[state_index].num_clock_modes = 1;
2378 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2379 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2380 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2381 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2382 goto default_mode;
2383 /* skip overclock modes for now */
2384 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
2385 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
2386 (rdev->pm.power_state[state_index].clock_info[0].sclk >
2387 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
2388 goto default_mode;
2389 rdev->pm.power_state[state_index].type =
2390 POWER_STATE_TYPE_BATTERY;
2391 misc = RBIOS16(offset + 0x5 + 0x0);
2392 if (rev > 4)
2393 misc2 = RBIOS16(offset + 0x5 + 0xe);
2394 if (misc & 0x4) {
2395 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2396 if (misc & 0x8)
2397 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2398 true;
2399 else
2400 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2401 false;
2402 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2403 if (rev < 6) {
2404 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2405 RBIOS16(offset + 0x5 + 0xb) * 4;
2406 tmp = RBIOS8(offset + 0x5 + 0xd);
2407 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2408 } else {
2409 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2410 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2411 if (entries && voltage_table_offset) {
2412 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2413 RBIOS16(voltage_table_offset) * 4;
2414 tmp = RBIOS8(voltage_table_offset + 0x2);
2415 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2416 } else
2417 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2418 }
2419 switch ((misc2 & 0x700) >> 8) {
2420 case 0:
2421 default:
2422 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2423 break;
2424 case 1:
2425 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2426 break;
2427 case 2:
2428 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2429 break;
2430 case 3:
2431 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2432 break;
2433 case 4:
2434 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2435 break;
2436 }
2437 } else
2438 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2439 if (rev > 6)
2440 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
2441 RBIOS8(offset + 0x5 + 0x10);
2442 state_index++;
2443 } else {
2444 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2445 }
2446 } else {
2447 /* XXX figure out some good default low power mode for desktop cards */
2448 }
2449
2450 default_mode:
2451 /* add the default mode */
2452 rdev->pm.power_state[state_index].type =
2453 POWER_STATE_TYPE_DEFAULT;
2454 rdev->pm.power_state[state_index].num_clock_modes = 1;
2455 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2456 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2457 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2458 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2459 if (rdev->asic->get_pcie_lanes)
2460 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
2461 else
2462 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
2463 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
2464 rdev->pm.num_power_states = state_index + 1;
2465
2466 rdev->pm.current_power_state = rdev->pm.default_power_state;
2467 rdev->pm.current_clock_mode =
2468 rdev->pm.default_power_state->default_clock_mode;
2469 }
2470
2471 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2472 {
2473 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2474 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2475
2476 if (!tmds)
2477 return;
2478
2479 switch (tmds->dvo_chip) {
2480 case DVO_SIL164:
2481 /* sil 164 */
2482 radeon_i2c_put_byte(tmds->i2c_bus,
2483 tmds->slave_addr,
2484 0x08, 0x30);
2485 radeon_i2c_put_byte(tmds->i2c_bus,
2486 tmds->slave_addr,
2487 0x09, 0x00);
2488 radeon_i2c_put_byte(tmds->i2c_bus,
2489 tmds->slave_addr,
2490 0x0a, 0x90);
2491 radeon_i2c_put_byte(tmds->i2c_bus,
2492 tmds->slave_addr,
2493 0x0c, 0x89);
2494 radeon_i2c_put_byte(tmds->i2c_bus,
2495 tmds->slave_addr,
2496 0x08, 0x3b);
2497 break;
2498 case DVO_SIL1178:
2499 /* sil 1178 - untested */
2500 /*
2501 * 0x0f, 0x44
2502 * 0x0f, 0x4c
2503 * 0x0e, 0x01
2504 * 0x0a, 0x80
2505 * 0x09, 0x30
2506 * 0x0c, 0xc9
2507 * 0x0d, 0x70
2508 * 0x08, 0x32
2509 * 0x08, 0x33
2510 */
2511 break;
2512 default:
2513 break;
2514 }
2515
2516 }
2517
2518 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2519 {
2520 struct drm_device *dev = encoder->dev;
2521 struct radeon_device *rdev = dev->dev_private;
2522 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2523 uint16_t offset;
2524 uint8_t blocks, slave_addr, rev;
2525 uint32_t index, id;
2526 uint32_t reg, val, and_mask, or_mask;
2527 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2528
2529 if (!tmds)
2530 return false;
2531
2532 if (rdev->flags & RADEON_IS_IGP) {
2533 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2534 rev = RBIOS8(offset);
2535 if (offset) {
2536 rev = RBIOS8(offset);
2537 if (rev > 1) {
2538 blocks = RBIOS8(offset + 3);
2539 index = offset + 4;
2540 while (blocks > 0) {
2541 id = RBIOS16(index);
2542 index += 2;
2543 switch (id >> 13) {
2544 case 0:
2545 reg = (id & 0x1fff) * 4;
2546 val = RBIOS32(index);
2547 index += 4;
2548 WREG32(reg, val);
2549 break;
2550 case 2:
2551 reg = (id & 0x1fff) * 4;
2552 and_mask = RBIOS32(index);
2553 index += 4;
2554 or_mask = RBIOS32(index);
2555 index += 4;
2556 val = RREG32(reg);
2557 val = (val & and_mask) | or_mask;
2558 WREG32(reg, val);
2559 break;
2560 case 3:
2561 val = RBIOS16(index);
2562 index += 2;
2563 udelay(val);
2564 break;
2565 case 4:
2566 val = RBIOS16(index);
2567 index += 2;
2568 udelay(val * 1000);
2569 break;
2570 case 6:
2571 slave_addr = id & 0xff;
2572 slave_addr >>= 1; /* 7 bit addressing */
2573 index++;
2574 reg = RBIOS8(index);
2575 index++;
2576 val = RBIOS8(index);
2577 index++;
2578 radeon_i2c_put_byte(tmds->i2c_bus,
2579 slave_addr,
2580 reg, val);
2581 break;
2582 default:
2583 DRM_ERROR("Unknown id %d\n", id >> 13);
2584 break;
2585 }
2586 blocks--;
2587 }
2588 return true;
2589 }
2590 }
2591 } else {
2592 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2593 if (offset) {
2594 index = offset + 10;
2595 id = RBIOS16(index);
2596 while (id != 0xffff) {
2597 index += 2;
2598 switch (id >> 13) {
2599 case 0:
2600 reg = (id & 0x1fff) * 4;
2601 val = RBIOS32(index);
2602 WREG32(reg, val);
2603 break;
2604 case 2:
2605 reg = (id & 0x1fff) * 4;
2606 and_mask = RBIOS32(index);
2607 index += 4;
2608 or_mask = RBIOS32(index);
2609 index += 4;
2610 val = RREG32(reg);
2611 val = (val & and_mask) | or_mask;
2612 WREG32(reg, val);
2613 break;
2614 case 4:
2615 val = RBIOS16(index);
2616 index += 2;
2617 udelay(val);
2618 break;
2619 case 5:
2620 reg = id & 0x1fff;
2621 and_mask = RBIOS32(index);
2622 index += 4;
2623 or_mask = RBIOS32(index);
2624 index += 4;
2625 val = RREG32_PLL(reg);
2626 val = (val & and_mask) | or_mask;
2627 WREG32_PLL(reg, val);
2628 break;
2629 case 6:
2630 reg = id & 0x1fff;
2631 val = RBIOS8(index);
2632 index += 1;
2633 radeon_i2c_put_byte(tmds->i2c_bus,
2634 tmds->slave_addr,
2635 reg, val);
2636 break;
2637 default:
2638 DRM_ERROR("Unknown id %d\n", id >> 13);
2639 break;
2640 }
2641 id = RBIOS16(index);
2642 }
2643 return true;
2644 }
2645 }
2646 return false;
2647 }
2648
2649 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2650 {
2651 struct radeon_device *rdev = dev->dev_private;
2652
2653 if (offset) {
2654 while (RBIOS16(offset)) {
2655 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2656 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2657 uint32_t val, and_mask, or_mask;
2658 uint32_t tmp;
2659
2660 offset += 2;
2661 switch (cmd) {
2662 case 0:
2663 val = RBIOS32(offset);
2664 offset += 4;
2665 WREG32(addr, val);
2666 break;
2667 case 1:
2668 val = RBIOS32(offset);
2669 offset += 4;
2670 WREG32(addr, val);
2671 break;
2672 case 2:
2673 and_mask = RBIOS32(offset);
2674 offset += 4;
2675 or_mask = RBIOS32(offset);
2676 offset += 4;
2677 tmp = RREG32(addr);
2678 tmp &= and_mask;
2679 tmp |= or_mask;
2680 WREG32(addr, tmp);
2681 break;
2682 case 3:
2683 and_mask = RBIOS32(offset);
2684 offset += 4;
2685 or_mask = RBIOS32(offset);
2686 offset += 4;
2687 tmp = RREG32(addr);
2688 tmp &= and_mask;
2689 tmp |= or_mask;
2690 WREG32(addr, tmp);
2691 break;
2692 case 4:
2693 val = RBIOS16(offset);
2694 offset += 2;
2695 udelay(val);
2696 break;
2697 case 5:
2698 val = RBIOS16(offset);
2699 offset += 2;
2700 switch (addr) {
2701 case 8:
2702 while (val--) {
2703 if (!
2704 (RREG32_PLL
2705 (RADEON_CLK_PWRMGT_CNTL) &
2706 RADEON_MC_BUSY))
2707 break;
2708 }
2709 break;
2710 case 9:
2711 while (val--) {
2712 if ((RREG32(RADEON_MC_STATUS) &
2713 RADEON_MC_IDLE))
2714 break;
2715 }
2716 break;
2717 default:
2718 break;
2719 }
2720 break;
2721 default:
2722 break;
2723 }
2724 }
2725 }
2726 }
2727
2728 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2729 {
2730 struct radeon_device *rdev = dev->dev_private;
2731
2732 if (offset) {
2733 while (RBIOS8(offset)) {
2734 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2735 uint8_t addr = (RBIOS8(offset) & 0x3f);
2736 uint32_t val, shift, tmp;
2737 uint32_t and_mask, or_mask;
2738
2739 offset++;
2740 switch (cmd) {
2741 case 0:
2742 val = RBIOS32(offset);
2743 offset += 4;
2744 WREG32_PLL(addr, val);
2745 break;
2746 case 1:
2747 shift = RBIOS8(offset) * 8;
2748 offset++;
2749 and_mask = RBIOS8(offset) << shift;
2750 and_mask |= ~(0xff << shift);
2751 offset++;
2752 or_mask = RBIOS8(offset) << shift;
2753 offset++;
2754 tmp = RREG32_PLL(addr);
2755 tmp &= and_mask;
2756 tmp |= or_mask;
2757 WREG32_PLL(addr, tmp);
2758 break;
2759 case 2:
2760 case 3:
2761 tmp = 1000;
2762 switch (addr) {
2763 case 1:
2764 udelay(150);
2765 break;
2766 case 2:
2767 udelay(1000);
2768 break;
2769 case 3:
2770 while (tmp--) {
2771 if (!
2772 (RREG32_PLL
2773 (RADEON_CLK_PWRMGT_CNTL) &
2774 RADEON_MC_BUSY))
2775 break;
2776 }
2777 break;
2778 case 4:
2779 while (tmp--) {
2780 if (RREG32_PLL
2781 (RADEON_CLK_PWRMGT_CNTL) &
2782 RADEON_DLL_READY)
2783 break;
2784 }
2785 break;
2786 case 5:
2787 tmp =
2788 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2789 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2790 #if 0
2791 uint32_t mclk_cntl =
2792 RREG32_PLL
2793 (RADEON_MCLK_CNTL);
2794 mclk_cntl &= 0xffff0000;
2795 /*mclk_cntl |= 0x00001111;*//* ??? */
2796 WREG32_PLL(RADEON_MCLK_CNTL,
2797 mclk_cntl);
2798 udelay(10000);
2799 #endif
2800 WREG32_PLL
2801 (RADEON_CLK_PWRMGT_CNTL,
2802 tmp &
2803 ~RADEON_CG_NO1_DEBUG_0);
2804 udelay(10000);
2805 }
2806 break;
2807 default:
2808 break;
2809 }
2810 break;
2811 default:
2812 break;
2813 }
2814 }
2815 }
2816 }
2817
2818 static void combios_parse_ram_reset_table(struct drm_device *dev,
2819 uint16_t offset)
2820 {
2821 struct radeon_device *rdev = dev->dev_private;
2822 uint32_t tmp;
2823
2824 if (offset) {
2825 uint8_t val = RBIOS8(offset);
2826 while (val != 0xff) {
2827 offset++;
2828
2829 if (val == 0x0f) {
2830 uint32_t channel_complete_mask;
2831
2832 if (ASIC_IS_R300(rdev))
2833 channel_complete_mask =
2834 R300_MEM_PWRUP_COMPLETE;
2835 else
2836 channel_complete_mask =
2837 RADEON_MEM_PWRUP_COMPLETE;
2838 tmp = 20000;
2839 while (tmp--) {
2840 if ((RREG32(RADEON_MEM_STR_CNTL) &
2841 channel_complete_mask) ==
2842 channel_complete_mask)
2843 break;
2844 }
2845 } else {
2846 uint32_t or_mask = RBIOS16(offset);
2847 offset += 2;
2848
2849 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2850 tmp &= RADEON_SDRAM_MODE_MASK;
2851 tmp |= or_mask;
2852 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2853
2854 or_mask = val << 24;
2855 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2856 tmp &= RADEON_B3MEM_RESET_MASK;
2857 tmp |= or_mask;
2858 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2859 }
2860 val = RBIOS8(offset);
2861 }
2862 }
2863 }
2864
2865 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2866 int mem_addr_mapping)
2867 {
2868 struct radeon_device *rdev = dev->dev_private;
2869 uint32_t mem_cntl;
2870 uint32_t mem_size;
2871 uint32_t addr = 0;
2872
2873 mem_cntl = RREG32(RADEON_MEM_CNTL);
2874 if (mem_cntl & RV100_HALF_MODE)
2875 ram /= 2;
2876 mem_size = ram;
2877 mem_cntl &= ~(0xff << 8);
2878 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2879 WREG32(RADEON_MEM_CNTL, mem_cntl);
2880 RREG32(RADEON_MEM_CNTL);
2881
2882 /* sdram reset ? */
2883
2884 /* something like this???? */
2885 while (ram--) {
2886 addr = ram * 1024 * 1024;
2887 /* write to each page */
2888 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2889 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2890 /* read back and verify */
2891 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2892 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2893 return 0;
2894 }
2895
2896 return mem_size;
2897 }
2898
2899 static void combios_write_ram_size(struct drm_device *dev)
2900 {
2901 struct radeon_device *rdev = dev->dev_private;
2902 uint8_t rev;
2903 uint16_t offset;
2904 uint32_t mem_size = 0;
2905 uint32_t mem_cntl = 0;
2906
2907 /* should do something smarter here I guess... */
2908 if (rdev->flags & RADEON_IS_IGP)
2909 return;
2910
2911 /* first check detected mem table */
2912 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2913 if (offset) {
2914 rev = RBIOS8(offset);
2915 if (rev < 3) {
2916 mem_cntl = RBIOS32(offset + 1);
2917 mem_size = RBIOS16(offset + 5);
2918 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2919 ((dev->pdev->device != 0x515e)
2920 && (dev->pdev->device != 0x5969)))
2921 WREG32(RADEON_MEM_CNTL, mem_cntl);
2922 }
2923 }
2924
2925 if (!mem_size) {
2926 offset =
2927 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2928 if (offset) {
2929 rev = RBIOS8(offset - 1);
2930 if (rev < 1) {
2931 if (((rdev->flags & RADEON_FAMILY_MASK) <
2932 CHIP_R200)
2933 && ((dev->pdev->device != 0x515e)
2934 && (dev->pdev->device != 0x5969))) {
2935 int ram = 0;
2936 int mem_addr_mapping = 0;
2937
2938 while (RBIOS8(offset)) {
2939 ram = RBIOS8(offset);
2940 mem_addr_mapping =
2941 RBIOS8(offset + 1);
2942 if (mem_addr_mapping != 0x25)
2943 ram *= 2;
2944 mem_size =
2945 combios_detect_ram(dev, ram,
2946 mem_addr_mapping);
2947 if (mem_size)
2948 break;
2949 offset += 2;
2950 }
2951 } else
2952 mem_size = RBIOS8(offset);
2953 } else {
2954 mem_size = RBIOS8(offset);
2955 mem_size *= 2; /* convert to MB */
2956 }
2957 }
2958 }
2959
2960 mem_size *= (1024 * 1024); /* convert to bytes */
2961 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2962 }
2963
2964 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2965 {
2966 uint16_t dyn_clk_info =
2967 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2968
2969 if (dyn_clk_info)
2970 combios_parse_pll_table(dev, dyn_clk_info);
2971 }
2972
2973 void radeon_combios_asic_init(struct drm_device *dev)
2974 {
2975 struct radeon_device *rdev = dev->dev_private;
2976 uint16_t table;
2977
2978 /* port hardcoded mac stuff from radeonfb */
2979 if (rdev->bios == NULL)
2980 return;
2981
2982 /* ASIC INIT 1 */
2983 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2984 if (table)
2985 combios_parse_mmio_table(dev, table);
2986
2987 /* PLL INIT */
2988 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2989 if (table)
2990 combios_parse_pll_table(dev, table);
2991
2992 /* ASIC INIT 2 */
2993 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2994 if (table)
2995 combios_parse_mmio_table(dev, table);
2996
2997 if (!(rdev->flags & RADEON_IS_IGP)) {
2998 /* ASIC INIT 4 */
2999 table =
3000 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3001 if (table)
3002 combios_parse_mmio_table(dev, table);
3003
3004 /* RAM RESET */
3005 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3006 if (table)
3007 combios_parse_ram_reset_table(dev, table);
3008
3009 /* ASIC INIT 3 */
3010 table =
3011 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3012 if (table)
3013 combios_parse_mmio_table(dev, table);
3014
3015 /* write CONFIG_MEMSIZE */
3016 combios_write_ram_size(dev);
3017 }
3018
3019 /* DYN CLK 1 */
3020 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3021 if (table)
3022 combios_parse_pll_table(dev, table);
3023
3024 }
3025
3026 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3027 {
3028 struct radeon_device *rdev = dev->dev_private;
3029 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3030
3031 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3032 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3033 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3034
3035 /* let the bios control the backlight */
3036 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3037
3038 /* tell the bios not to handle mode switching */
3039 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3040 RADEON_ACC_MODE_CHANGE);
3041
3042 /* tell the bios a driver is loaded */
3043 bios_7_scratch |= RADEON_DRV_LOADED;
3044
3045 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3046 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3047 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3048 }
3049
3050 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3051 {
3052 struct drm_device *dev = encoder->dev;
3053 struct radeon_device *rdev = dev->dev_private;
3054 uint32_t bios_6_scratch;
3055
3056 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3057
3058 if (lock)
3059 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3060 else
3061 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3062
3063 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3064 }
3065
3066 void
3067 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3068 struct drm_encoder *encoder,
3069 bool connected)
3070 {
3071 struct drm_device *dev = connector->dev;
3072 struct radeon_device *rdev = dev->dev_private;
3073 struct radeon_connector *radeon_connector =
3074 to_radeon_connector(connector);
3075 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3076 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3077 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3078
3079 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3080 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3081 if (connected) {
3082 DRM_DEBUG("TV1 connected\n");
3083 /* fix me */
3084 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3085 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3086 bios_5_scratch |= RADEON_TV1_ON;
3087 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3088 } else {
3089 DRM_DEBUG("TV1 disconnected\n");
3090 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3091 bios_5_scratch &= ~RADEON_TV1_ON;
3092 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3093 }
3094 }
3095 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3096 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3097 if (connected) {
3098 DRM_DEBUG("LCD1 connected\n");
3099 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3100 bios_5_scratch |= RADEON_LCD1_ON;
3101 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3102 } else {
3103 DRM_DEBUG("LCD1 disconnected\n");
3104 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3105 bios_5_scratch &= ~RADEON_LCD1_ON;
3106 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3107 }
3108 }
3109 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3110 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3111 if (connected) {
3112 DRM_DEBUG("CRT1 connected\n");
3113 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3114 bios_5_scratch |= RADEON_CRT1_ON;
3115 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3116 } else {
3117 DRM_DEBUG("CRT1 disconnected\n");
3118 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3119 bios_5_scratch &= ~RADEON_CRT1_ON;
3120 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3121 }
3122 }
3123 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3124 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3125 if (connected) {
3126 DRM_DEBUG("CRT2 connected\n");
3127 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3128 bios_5_scratch |= RADEON_CRT2_ON;
3129 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3130 } else {
3131 DRM_DEBUG("CRT2 disconnected\n");
3132 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3133 bios_5_scratch &= ~RADEON_CRT2_ON;
3134 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3135 }
3136 }
3137 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3138 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3139 if (connected) {
3140 DRM_DEBUG("DFP1 connected\n");
3141 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3142 bios_5_scratch |= RADEON_DFP1_ON;
3143 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3144 } else {
3145 DRM_DEBUG("DFP1 disconnected\n");
3146 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3147 bios_5_scratch &= ~RADEON_DFP1_ON;
3148 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3149 }
3150 }
3151 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3152 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3153 if (connected) {
3154 DRM_DEBUG("DFP2 connected\n");
3155 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3156 bios_5_scratch |= RADEON_DFP2_ON;
3157 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3158 } else {
3159 DRM_DEBUG("DFP2 disconnected\n");
3160 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3161 bios_5_scratch &= ~RADEON_DFP2_ON;
3162 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3163 }
3164 }
3165 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3166 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3167 }
3168
3169 void
3170 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3171 {
3172 struct drm_device *dev = encoder->dev;
3173 struct radeon_device *rdev = dev->dev_private;
3174 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3175 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3176
3177 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3178 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3179 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3180 }
3181 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3182 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3183 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3184 }
3185 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3186 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3187 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3188 }
3189 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3190 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3191 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3192 }
3193 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3194 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3195 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3196 }
3197 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3198 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3199 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3200 }
3201 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3202 }
3203
3204 void
3205 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3206 {
3207 struct drm_device *dev = encoder->dev;
3208 struct radeon_device *rdev = dev->dev_private;
3209 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3210 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3211
3212 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3213 if (on)
3214 bios_6_scratch |= RADEON_TV_DPMS_ON;
3215 else
3216 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3217 }
3218 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3219 if (on)
3220 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3221 else
3222 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3223 }
3224 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3225 if (on)
3226 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3227 else
3228 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3229 }
3230 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3231 if (on)
3232 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3233 else
3234 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3235 }
3236 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3237 }
Linux kernel - Deliverables
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