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drm: Make drm_local_map use a resource_size_t offset
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_cp.c
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "drm_sarea.h"
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
37 #include "r300_reg.h"
38
39 #include "radeon_microcode.h"
40
41 #define RADEON_FIFO_DEBUG 0
42
43 static int radeon_do_cleanup_cp(struct drm_device * dev);
44 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
45
46 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
47 {
48 u32 ret;
49 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
50 ret = RADEON_READ(R520_MC_IND_DATA);
51 RADEON_WRITE(R520_MC_IND_INDEX, 0);
52 return ret;
53 }
54
55 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
56 {
57 u32 ret;
58 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
59 ret = RADEON_READ(RS480_NB_MC_DATA);
60 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
61 return ret;
62 }
63
64 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
65 {
66 u32 ret;
67 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
68 ret = RADEON_READ(RS690_MC_DATA);
69 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
70 return ret;
71 }
72
73 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
74 {
75 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
76 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
77 return RS690_READ_MCIND(dev_priv, addr);
78 else
79 return RS480_READ_MCIND(dev_priv, addr);
80 }
81
82 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
83 {
84
85 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
86 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
87 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
88 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
89 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
90 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
91 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
92 else
93 return RADEON_READ(RADEON_MC_FB_LOCATION);
94 }
95
96 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
97 {
98 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
99 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
100 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
101 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
102 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
103 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
104 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
105 else
106 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
107 }
108
109 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
110 {
111 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
112 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
113 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
114 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
115 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
116 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
117 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
118 else
119 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
120 }
121
122 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
123 {
124 u32 agp_base_hi = upper_32_bits(agp_base);
125 u32 agp_base_lo = agp_base & 0xffffffff;
126
127 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
128 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
129 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
130 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
131 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
132 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
133 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
134 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
135 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
136 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
137 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
138 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
139 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
140 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
141 } else {
142 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
143 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
144 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
145 }
146 }
147
148 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
149 {
150 drm_radeon_private_t *dev_priv = dev->dev_private;
151
152 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
153 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
154 }
155
156 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
157 {
158 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
159 return RADEON_READ(RADEON_PCIE_DATA);
160 }
161
162 #if RADEON_FIFO_DEBUG
163 static void radeon_status(drm_radeon_private_t * dev_priv)
164 {
165 printk("%s:\n", __func__);
166 printk("RBBM_STATUS = 0x%08x\n",
167 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
168 printk("CP_RB_RTPR = 0x%08x\n",
169 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
170 printk("CP_RB_WTPR = 0x%08x\n",
171 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
172 printk("AIC_CNTL = 0x%08x\n",
173 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
174 printk("AIC_STAT = 0x%08x\n",
175 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
176 printk("AIC_PT_BASE = 0x%08x\n",
177 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
178 printk("TLB_ADDR = 0x%08x\n",
179 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
180 printk("TLB_DATA = 0x%08x\n",
181 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
182 }
183 #endif
184
185 /* ================================================================
186 * Engine, FIFO control
187 */
188
189 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
190 {
191 u32 tmp;
192 int i;
193
194 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
195
196 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
197 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
198 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
199 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
200
201 for (i = 0; i < dev_priv->usec_timeout; i++) {
202 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
203 & RADEON_RB3D_DC_BUSY)) {
204 return 0;
205 }
206 DRM_UDELAY(1);
207 }
208 } else {
209 /* don't flush or purge cache here or lockup */
210 return 0;
211 }
212
213 #if RADEON_FIFO_DEBUG
214 DRM_ERROR("failed!\n");
215 radeon_status(dev_priv);
216 #endif
217 return -EBUSY;
218 }
219
220 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
221 {
222 int i;
223
224 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
225
226 for (i = 0; i < dev_priv->usec_timeout; i++) {
227 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
228 & RADEON_RBBM_FIFOCNT_MASK);
229 if (slots >= entries)
230 return 0;
231 DRM_UDELAY(1);
232 }
233 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
234 RADEON_READ(RADEON_RBBM_STATUS),
235 RADEON_READ(R300_VAP_CNTL_STATUS));
236
237 #if RADEON_FIFO_DEBUG
238 DRM_ERROR("failed!\n");
239 radeon_status(dev_priv);
240 #endif
241 return -EBUSY;
242 }
243
244 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
245 {
246 int i, ret;
247
248 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
249
250 ret = radeon_do_wait_for_fifo(dev_priv, 64);
251 if (ret)
252 return ret;
253
254 for (i = 0; i < dev_priv->usec_timeout; i++) {
255 if (!(RADEON_READ(RADEON_RBBM_STATUS)
256 & RADEON_RBBM_ACTIVE)) {
257 radeon_do_pixcache_flush(dev_priv);
258 return 0;
259 }
260 DRM_UDELAY(1);
261 }
262 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
263 RADEON_READ(RADEON_RBBM_STATUS),
264 RADEON_READ(R300_VAP_CNTL_STATUS));
265
266 #if RADEON_FIFO_DEBUG
267 DRM_ERROR("failed!\n");
268 radeon_status(dev_priv);
269 #endif
270 return -EBUSY;
271 }
272
273 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
274 {
275 uint32_t gb_tile_config, gb_pipe_sel = 0;
276
277 /* RS4xx/RS6xx/R4xx/R5xx */
278 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
279 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
280 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
281 } else {
282 /* R3xx */
283 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
284 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
285 dev_priv->num_gb_pipes = 2;
286 } else {
287 /* R3Vxx */
288 dev_priv->num_gb_pipes = 1;
289 }
290 }
291 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
292
293 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
294
295 switch (dev_priv->num_gb_pipes) {
296 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
297 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
298 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
299 default:
300 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
301 }
302
303 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
304 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
305 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
306 }
307 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
308 radeon_do_wait_for_idle(dev_priv);
309 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
310 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
311 R300_DC_AUTOFLUSH_ENABLE |
312 R300_DC_DC_DISABLE_IGNORE_PE));
313
314
315 }
316
317 /* ================================================================
318 * CP control, initialization
319 */
320
321 /* Load the microcode for the CP */
322 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
323 {
324 int i;
325 DRM_DEBUG("\n");
326
327 radeon_do_wait_for_idle(dev_priv);
328
329 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
330 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
331 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
332 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
333 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
334 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
335 DRM_INFO("Loading R100 Microcode\n");
336 for (i = 0; i < 256; i++) {
337 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
338 R100_cp_microcode[i][1]);
339 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
340 R100_cp_microcode[i][0]);
341 }
342 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
343 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
344 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
345 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
346 DRM_INFO("Loading R200 Microcode\n");
347 for (i = 0; i < 256; i++) {
348 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
349 R200_cp_microcode[i][1]);
350 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
351 R200_cp_microcode[i][0]);
352 }
353 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
354 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
355 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
356 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
357 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
358 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
359 DRM_INFO("Loading R300 Microcode\n");
360 for (i = 0; i < 256; i++) {
361 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
362 R300_cp_microcode[i][1]);
363 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
364 R300_cp_microcode[i][0]);
365 }
366 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
367 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
368 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
369 DRM_INFO("Loading R400 Microcode\n");
370 for (i = 0; i < 256; i++) {
371 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
372 R420_cp_microcode[i][1]);
373 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
374 R420_cp_microcode[i][0]);
375 }
376 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
377 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
378 DRM_INFO("Loading RS690/RS740 Microcode\n");
379 for (i = 0; i < 256; i++) {
380 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
381 RS690_cp_microcode[i][1]);
382 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
383 RS690_cp_microcode[i][0]);
384 }
385 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
386 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
387 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
388 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
389 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
390 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
391 DRM_INFO("Loading R500 Microcode\n");
392 for (i = 0; i < 256; i++) {
393 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
394 R520_cp_microcode[i][1]);
395 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
396 R520_cp_microcode[i][0]);
397 }
398 }
399 }
400
401 /* Flush any pending commands to the CP. This should only be used just
402 * prior to a wait for idle, as it informs the engine that the command
403 * stream is ending.
404 */
405 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
406 {
407 DRM_DEBUG("\n");
408 #if 0
409 u32 tmp;
410
411 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
412 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
413 #endif
414 }
415
416 /* Wait for the CP to go idle.
417 */
418 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
419 {
420 RING_LOCALS;
421 DRM_DEBUG("\n");
422
423 BEGIN_RING(6);
424
425 RADEON_PURGE_CACHE();
426 RADEON_PURGE_ZCACHE();
427 RADEON_WAIT_UNTIL_IDLE();
428
429 ADVANCE_RING();
430 COMMIT_RING();
431
432 return radeon_do_wait_for_idle(dev_priv);
433 }
434
435 /* Start the Command Processor.
436 */
437 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
438 {
439 RING_LOCALS;
440 DRM_DEBUG("\n");
441
442 radeon_do_wait_for_idle(dev_priv);
443
444 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
445
446 dev_priv->cp_running = 1;
447
448 BEGIN_RING(8);
449 /* isync can only be written through cp on r5xx write it here */
450 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
451 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
452 RADEON_ISYNC_ANY3D_IDLE2D |
453 RADEON_ISYNC_WAIT_IDLEGUI |
454 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
455 RADEON_PURGE_CACHE();
456 RADEON_PURGE_ZCACHE();
457 RADEON_WAIT_UNTIL_IDLE();
458 ADVANCE_RING();
459 COMMIT_RING();
460
461 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
462 }
463
464 /* Reset the Command Processor. This will not flush any pending
465 * commands, so you must wait for the CP command stream to complete
466 * before calling this routine.
467 */
468 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
469 {
470 u32 cur_read_ptr;
471 DRM_DEBUG("\n");
472
473 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
474 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
475 SET_RING_HEAD(dev_priv, cur_read_ptr);
476 dev_priv->ring.tail = cur_read_ptr;
477 }
478
479 /* Stop the Command Processor. This will not flush any pending
480 * commands, so you must flush the command stream and wait for the CP
481 * to go idle before calling this routine.
482 */
483 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
484 {
485 DRM_DEBUG("\n");
486
487 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
488
489 dev_priv->cp_running = 0;
490 }
491
492 /* Reset the engine. This will stop the CP if it is running.
493 */
494 static int radeon_do_engine_reset(struct drm_device * dev)
495 {
496 drm_radeon_private_t *dev_priv = dev->dev_private;
497 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
498 DRM_DEBUG("\n");
499
500 radeon_do_pixcache_flush(dev_priv);
501
502 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
503 /* may need something similar for newer chips */
504 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
505 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
506
507 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
508 RADEON_FORCEON_MCLKA |
509 RADEON_FORCEON_MCLKB |
510 RADEON_FORCEON_YCLKA |
511 RADEON_FORCEON_YCLKB |
512 RADEON_FORCEON_MC |
513 RADEON_FORCEON_AIC));
514 }
515
516 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
517
518 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
519 RADEON_SOFT_RESET_CP |
520 RADEON_SOFT_RESET_HI |
521 RADEON_SOFT_RESET_SE |
522 RADEON_SOFT_RESET_RE |
523 RADEON_SOFT_RESET_PP |
524 RADEON_SOFT_RESET_E2 |
525 RADEON_SOFT_RESET_RB));
526 RADEON_READ(RADEON_RBBM_SOFT_RESET);
527 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
528 ~(RADEON_SOFT_RESET_CP |
529 RADEON_SOFT_RESET_HI |
530 RADEON_SOFT_RESET_SE |
531 RADEON_SOFT_RESET_RE |
532 RADEON_SOFT_RESET_PP |
533 RADEON_SOFT_RESET_E2 |
534 RADEON_SOFT_RESET_RB)));
535 RADEON_READ(RADEON_RBBM_SOFT_RESET);
536
537 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
538 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
539 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
540 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
541 }
542
543 /* setup the raster pipes */
544 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
545 radeon_init_pipes(dev_priv);
546
547 /* Reset the CP ring */
548 radeon_do_cp_reset(dev_priv);
549
550 /* The CP is no longer running after an engine reset */
551 dev_priv->cp_running = 0;
552
553 /* Reset any pending vertex, indirect buffers */
554 radeon_freelist_reset(dev);
555
556 return 0;
557 }
558
559 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
560 drm_radeon_private_t *dev_priv,
561 struct drm_file *file_priv)
562 {
563 struct drm_radeon_master_private *master_priv;
564 u32 ring_start, cur_read_ptr;
565 u32 tmp;
566
567 /* Initialize the memory controller. With new memory map, the fb location
568 * is not changed, it should have been properly initialized already. Part
569 * of the problem is that the code below is bogus, assuming the GART is
570 * always appended to the fb which is not necessarily the case
571 */
572 if (!dev_priv->new_memmap)
573 radeon_write_fb_location(dev_priv,
574 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
575 | (dev_priv->fb_location >> 16));
576
577 #if __OS_HAS_AGP
578 if (dev_priv->flags & RADEON_IS_AGP) {
579 radeon_write_agp_base(dev_priv, dev->agp->base);
580
581 radeon_write_agp_location(dev_priv,
582 (((dev_priv->gart_vm_start - 1 +
583 dev_priv->gart_size) & 0xffff0000) |
584 (dev_priv->gart_vm_start >> 16)));
585
586 ring_start = (dev_priv->cp_ring->offset
587 - dev->agp->base
588 + dev_priv->gart_vm_start);
589 } else
590 #endif
591 ring_start = (dev_priv->cp_ring->offset
592 - (unsigned long)dev->sg->virtual
593 + dev_priv->gart_vm_start);
594
595 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
596
597 /* Set the write pointer delay */
598 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
599
600 /* Initialize the ring buffer's read and write pointers */
601 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
602 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
603 SET_RING_HEAD(dev_priv, cur_read_ptr);
604 dev_priv->ring.tail = cur_read_ptr;
605
606 #if __OS_HAS_AGP
607 if (dev_priv->flags & RADEON_IS_AGP) {
608 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
609 dev_priv->ring_rptr->offset
610 - dev->agp->base + dev_priv->gart_vm_start);
611 } else
612 #endif
613 {
614 struct drm_sg_mem *entry = dev->sg;
615 unsigned long tmp_ofs, page_ofs;
616
617 tmp_ofs = dev_priv->ring_rptr->offset -
618 (unsigned long)dev->sg->virtual;
619 page_ofs = tmp_ofs >> PAGE_SHIFT;
620
621 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
622 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
623 (unsigned long)entry->busaddr[page_ofs],
624 entry->handle + tmp_ofs);
625 }
626
627 /* Set ring buffer size */
628 #ifdef __BIG_ENDIAN
629 RADEON_WRITE(RADEON_CP_RB_CNTL,
630 RADEON_BUF_SWAP_32BIT |
631 (dev_priv->ring.fetch_size_l2ow << 18) |
632 (dev_priv->ring.rptr_update_l2qw << 8) |
633 dev_priv->ring.size_l2qw);
634 #else
635 RADEON_WRITE(RADEON_CP_RB_CNTL,
636 (dev_priv->ring.fetch_size_l2ow << 18) |
637 (dev_priv->ring.rptr_update_l2qw << 8) |
638 dev_priv->ring.size_l2qw);
639 #endif
640
641
642 /* Initialize the scratch register pointer. This will cause
643 * the scratch register values to be written out to memory
644 * whenever they are updated.
645 *
646 * We simply put this behind the ring read pointer, this works
647 * with PCI GART as well as (whatever kind of) AGP GART
648 */
649 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
650 + RADEON_SCRATCH_REG_OFFSET);
651
652 dev_priv->scratch = ((__volatile__ u32 *)
653 dev_priv->ring_rptr->handle +
654 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
655
656 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
657
658 /* Turn on bus mastering */
659 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
660 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
661 /* rs600/rs690/rs740 */
662 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
663 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
664 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
665 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
666 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
667 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
668 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
669 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
670 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
671 } /* PCIE cards appears to not need this */
672
673 dev_priv->scratch[0] = 0;
674 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
675
676 dev_priv->scratch[1] = 0;
677 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
678
679 dev_priv->scratch[2] = 0;
680 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
681
682 /* reset sarea copies of these */
683 master_priv = file_priv->master->driver_priv;
684 if (master_priv->sarea_priv) {
685 master_priv->sarea_priv->last_frame = 0;
686 master_priv->sarea_priv->last_dispatch = 0;
687 master_priv->sarea_priv->last_clear = 0;
688 }
689
690 radeon_do_wait_for_idle(dev_priv);
691
692 /* Sync everything up */
693 RADEON_WRITE(RADEON_ISYNC_CNTL,
694 (RADEON_ISYNC_ANY2D_IDLE3D |
695 RADEON_ISYNC_ANY3D_IDLE2D |
696 RADEON_ISYNC_WAIT_IDLEGUI |
697 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
698
699 }
700
701 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
702 {
703 u32 tmp;
704
705 /* Start with assuming that writeback doesn't work */
706 dev_priv->writeback_works = 0;
707
708 /* Writeback doesn't seem to work everywhere, test it here and possibly
709 * enable it if it appears to work
710 */
711 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
712 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
713
714 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
715 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
716 0xdeadbeef)
717 break;
718 DRM_UDELAY(1);
719 }
720
721 if (tmp < dev_priv->usec_timeout) {
722 dev_priv->writeback_works = 1;
723 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
724 } else {
725 dev_priv->writeback_works = 0;
726 DRM_INFO("writeback test failed\n");
727 }
728 if (radeon_no_wb == 1) {
729 dev_priv->writeback_works = 0;
730 DRM_INFO("writeback forced off\n");
731 }
732
733 if (!dev_priv->writeback_works) {
734 /* Disable writeback to avoid unnecessary bus master transfer */
735 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
736 RADEON_RB_NO_UPDATE);
737 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
738 }
739 }
740
741 /* Enable or disable IGP GART on the chip */
742 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
743 {
744 u32 temp;
745
746 if (on) {
747 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
748 dev_priv->gart_vm_start,
749 (long)dev_priv->gart_info.bus_addr,
750 dev_priv->gart_size);
751
752 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
753 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
754 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
755 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
756 RS690_BLOCK_GFX_D3_EN));
757 else
758 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
759
760 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
761 RS480_VA_SIZE_32MB));
762
763 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
764 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
765 RS480_TLB_ENABLE |
766 RS480_GTW_LAC_EN |
767 RS480_1LEVEL_GART));
768
769 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
770 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
771 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
772
773 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
774 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
775 RS480_REQ_TYPE_SNOOP_DIS));
776
777 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
778
779 dev_priv->gart_size = 32*1024*1024;
780 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
781 0xffff0000) | (dev_priv->gart_vm_start >> 16));
782
783 radeon_write_agp_location(dev_priv, temp);
784
785 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
786 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
787 RS480_VA_SIZE_32MB));
788
789 do {
790 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
791 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
792 break;
793 DRM_UDELAY(1);
794 } while (1);
795
796 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
797 RS480_GART_CACHE_INVALIDATE);
798
799 do {
800 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
801 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
802 break;
803 DRM_UDELAY(1);
804 } while (1);
805
806 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
807 } else {
808 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
809 }
810 }
811
812 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
813 {
814 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
815 if (on) {
816
817 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
818 dev_priv->gart_vm_start,
819 (long)dev_priv->gart_info.bus_addr,
820 dev_priv->gart_size);
821 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
822 dev_priv->gart_vm_start);
823 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
824 dev_priv->gart_info.bus_addr);
825 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
826 dev_priv->gart_vm_start);
827 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
828 dev_priv->gart_vm_start +
829 dev_priv->gart_size - 1);
830
831 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
832
833 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
834 RADEON_PCIE_TX_GART_EN);
835 } else {
836 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
837 tmp & ~RADEON_PCIE_TX_GART_EN);
838 }
839 }
840
841 /* Enable or disable PCI GART on the chip */
842 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
843 {
844 u32 tmp;
845
846 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
847 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
848 (dev_priv->flags & RADEON_IS_IGPGART)) {
849 radeon_set_igpgart(dev_priv, on);
850 return;
851 }
852
853 if (dev_priv->flags & RADEON_IS_PCIE) {
854 radeon_set_pciegart(dev_priv, on);
855 return;
856 }
857
858 tmp = RADEON_READ(RADEON_AIC_CNTL);
859
860 if (on) {
861 RADEON_WRITE(RADEON_AIC_CNTL,
862 tmp | RADEON_PCIGART_TRANSLATE_EN);
863
864 /* set PCI GART page-table base address
865 */
866 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
867
868 /* set address range for PCI address translate
869 */
870 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
871 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
872 + dev_priv->gart_size - 1);
873
874 /* Turn off AGP aperture -- is this required for PCI GART?
875 */
876 radeon_write_agp_location(dev_priv, 0xffffffc0);
877 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
878 } else {
879 RADEON_WRITE(RADEON_AIC_CNTL,
880 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
881 }
882 }
883
884 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
885 struct drm_file *file_priv)
886 {
887 drm_radeon_private_t *dev_priv = dev->dev_private;
888 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
889
890 DRM_DEBUG("\n");
891
892 /* if we require new memory map but we don't have it fail */
893 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
894 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
895 radeon_do_cleanup_cp(dev);
896 return -EINVAL;
897 }
898
899 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
900 DRM_DEBUG("Forcing AGP card to PCI mode\n");
901 dev_priv->flags &= ~RADEON_IS_AGP;
902 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
903 && !init->is_pci) {
904 DRM_DEBUG("Restoring AGP flag\n");
905 dev_priv->flags |= RADEON_IS_AGP;
906 }
907
908 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
909 DRM_ERROR("PCI GART memory not allocated!\n");
910 radeon_do_cleanup_cp(dev);
911 return -EINVAL;
912 }
913
914 dev_priv->usec_timeout = init->usec_timeout;
915 if (dev_priv->usec_timeout < 1 ||
916 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
917 DRM_DEBUG("TIMEOUT problem!\n");
918 radeon_do_cleanup_cp(dev);
919 return -EINVAL;
920 }
921
922 /* Enable vblank on CRTC1 for older X servers
923 */
924 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
925
926 switch(init->func) {
927 case RADEON_INIT_R200_CP:
928 dev_priv->microcode_version = UCODE_R200;
929 break;
930 case RADEON_INIT_R300_CP:
931 dev_priv->microcode_version = UCODE_R300;
932 break;
933 default:
934 dev_priv->microcode_version = UCODE_R100;
935 }
936
937 dev_priv->do_boxes = 0;
938 dev_priv->cp_mode = init->cp_mode;
939
940 /* We don't support anything other than bus-mastering ring mode,
941 * but the ring can be in either AGP or PCI space for the ring
942 * read pointer.
943 */
944 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
945 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
946 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
947 radeon_do_cleanup_cp(dev);
948 return -EINVAL;
949 }
950
951 switch (init->fb_bpp) {
952 case 16:
953 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
954 break;
955 case 32:
956 default:
957 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
958 break;
959 }
960 dev_priv->front_offset = init->front_offset;
961 dev_priv->front_pitch = init->front_pitch;
962 dev_priv->back_offset = init->back_offset;
963 dev_priv->back_pitch = init->back_pitch;
964
965 switch (init->depth_bpp) {
966 case 16:
967 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
968 break;
969 case 32:
970 default:
971 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
972 break;
973 }
974 dev_priv->depth_offset = init->depth_offset;
975 dev_priv->depth_pitch = init->depth_pitch;
976
977 /* Hardware state for depth clears. Remove this if/when we no
978 * longer clear the depth buffer with a 3D rectangle. Hard-code
979 * all values to prevent unwanted 3D state from slipping through
980 * and screwing with the clear operation.
981 */
982 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
983 (dev_priv->color_fmt << 10) |
984 (dev_priv->microcode_version ==
985 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
986
987 dev_priv->depth_clear.rb3d_zstencilcntl =
988 (dev_priv->depth_fmt |
989 RADEON_Z_TEST_ALWAYS |
990 RADEON_STENCIL_TEST_ALWAYS |
991 RADEON_STENCIL_S_FAIL_REPLACE |
992 RADEON_STENCIL_ZPASS_REPLACE |
993 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
994
995 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
996 RADEON_BFACE_SOLID |
997 RADEON_FFACE_SOLID |
998 RADEON_FLAT_SHADE_VTX_LAST |
999 RADEON_DIFFUSE_SHADE_FLAT |
1000 RADEON_ALPHA_SHADE_FLAT |
1001 RADEON_SPECULAR_SHADE_FLAT |
1002 RADEON_FOG_SHADE_FLAT |
1003 RADEON_VTX_PIX_CENTER_OGL |
1004 RADEON_ROUND_MODE_TRUNC |
1005 RADEON_ROUND_PREC_8TH_PIX);
1006
1007
1008 dev_priv->ring_offset = init->ring_offset;
1009 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1010 dev_priv->buffers_offset = init->buffers_offset;
1011 dev_priv->gart_textures_offset = init->gart_textures_offset;
1012
1013 master_priv->sarea = drm_getsarea(dev);
1014 if (!master_priv->sarea) {
1015 DRM_ERROR("could not find sarea!\n");
1016 radeon_do_cleanup_cp(dev);
1017 return -EINVAL;
1018 }
1019
1020 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1021 if (!dev_priv->cp_ring) {
1022 DRM_ERROR("could not find cp ring region!\n");
1023 radeon_do_cleanup_cp(dev);
1024 return -EINVAL;
1025 }
1026 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1027 if (!dev_priv->ring_rptr) {
1028 DRM_ERROR("could not find ring read pointer!\n");
1029 radeon_do_cleanup_cp(dev);
1030 return -EINVAL;
1031 }
1032 dev->agp_buffer_token = init->buffers_offset;
1033 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1034 if (!dev->agp_buffer_map) {
1035 DRM_ERROR("could not find dma buffer region!\n");
1036 radeon_do_cleanup_cp(dev);
1037 return -EINVAL;
1038 }
1039
1040 if (init->gart_textures_offset) {
1041 dev_priv->gart_textures =
1042 drm_core_findmap(dev, init->gart_textures_offset);
1043 if (!dev_priv->gart_textures) {
1044 DRM_ERROR("could not find GART texture region!\n");
1045 radeon_do_cleanup_cp(dev);
1046 return -EINVAL;
1047 }
1048 }
1049
1050 #if __OS_HAS_AGP
1051 if (dev_priv->flags & RADEON_IS_AGP) {
1052 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1053 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1054 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1055 if (!dev_priv->cp_ring->handle ||
1056 !dev_priv->ring_rptr->handle ||
1057 !dev->agp_buffer_map->handle) {
1058 DRM_ERROR("could not find ioremap agp regions!\n");
1059 radeon_do_cleanup_cp(dev);
1060 return -EINVAL;
1061 }
1062 } else
1063 #endif
1064 {
1065 dev_priv->cp_ring->handle =
1066 (void *)(unsigned long)dev_priv->cp_ring->offset;
1067 dev_priv->ring_rptr->handle =
1068 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1069 dev->agp_buffer_map->handle =
1070 (void *)(unsigned long)dev->agp_buffer_map->offset;
1071
1072 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1073 dev_priv->cp_ring->handle);
1074 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1075 dev_priv->ring_rptr->handle);
1076 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1077 dev->agp_buffer_map->handle);
1078 }
1079
1080 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1081 dev_priv->fb_size =
1082 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1083 - dev_priv->fb_location;
1084
1085 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1086 ((dev_priv->front_offset
1087 + dev_priv->fb_location) >> 10));
1088
1089 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1090 ((dev_priv->back_offset
1091 + dev_priv->fb_location) >> 10));
1092
1093 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1094 ((dev_priv->depth_offset
1095 + dev_priv->fb_location) >> 10));
1096
1097 dev_priv->gart_size = init->gart_size;
1098
1099 /* New let's set the memory map ... */
1100 if (dev_priv->new_memmap) {
1101 u32 base = 0;
1102
1103 DRM_INFO("Setting GART location based on new memory map\n");
1104
1105 /* If using AGP, try to locate the AGP aperture at the same
1106 * location in the card and on the bus, though we have to
1107 * align it down.
1108 */
1109 #if __OS_HAS_AGP
1110 if (dev_priv->flags & RADEON_IS_AGP) {
1111 base = dev->agp->base;
1112 /* Check if valid */
1113 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1114 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1115 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1116 dev->agp->base);
1117 base = 0;
1118 }
1119 }
1120 #endif
1121 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1122 if (base == 0) {
1123 base = dev_priv->fb_location + dev_priv->fb_size;
1124 if (base < dev_priv->fb_location ||
1125 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1126 base = dev_priv->fb_location
1127 - dev_priv->gart_size;
1128 }
1129 dev_priv->gart_vm_start = base & 0xffc00000u;
1130 if (dev_priv->gart_vm_start != base)
1131 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1132 base, dev_priv->gart_vm_start);
1133 } else {
1134 DRM_INFO("Setting GART location based on old memory map\n");
1135 dev_priv->gart_vm_start = dev_priv->fb_location +
1136 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1137 }
1138
1139 #if __OS_HAS_AGP
1140 if (dev_priv->flags & RADEON_IS_AGP)
1141 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1142 - dev->agp->base
1143 + dev_priv->gart_vm_start);
1144 else
1145 #endif
1146 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1147 - (unsigned long)dev->sg->virtual
1148 + dev_priv->gart_vm_start);
1149
1150 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1151 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1152 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1153 dev_priv->gart_buffers_offset);
1154
1155 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1156 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1157 + init->ring_size / sizeof(u32));
1158 dev_priv->ring.size = init->ring_size;
1159 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1160
1161 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1162 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1163
1164 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1165 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1166 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1167
1168 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1169
1170 #if __OS_HAS_AGP
1171 if (dev_priv->flags & RADEON_IS_AGP) {
1172 /* Turn off PCI GART */
1173 radeon_set_pcigart(dev_priv, 0);
1174 } else
1175 #endif
1176 {
1177 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1178 /* if we have an offset set from userspace */
1179 if (dev_priv->pcigart_offset_set) {
1180 dev_priv->gart_info.bus_addr =
1181 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1182 dev_priv->gart_info.mapping.offset =
1183 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1184 dev_priv->gart_info.mapping.size =
1185 dev_priv->gart_info.table_size;
1186
1187 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1188 dev_priv->gart_info.addr =
1189 dev_priv->gart_info.mapping.handle;
1190
1191 if (dev_priv->flags & RADEON_IS_PCIE)
1192 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1193 else
1194 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1195 dev_priv->gart_info.gart_table_location =
1196 DRM_ATI_GART_FB;
1197
1198 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1199 dev_priv->gart_info.addr,
1200 dev_priv->pcigart_offset);
1201 } else {
1202 if (dev_priv->flags & RADEON_IS_IGPGART)
1203 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1204 else
1205 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1206 dev_priv->gart_info.gart_table_location =
1207 DRM_ATI_GART_MAIN;
1208 dev_priv->gart_info.addr = NULL;
1209 dev_priv->gart_info.bus_addr = 0;
1210 if (dev_priv->flags & RADEON_IS_PCIE) {
1211 DRM_ERROR
1212 ("Cannot use PCI Express without GART in FB memory\n");
1213 radeon_do_cleanup_cp(dev);
1214 return -EINVAL;
1215 }
1216 }
1217
1218 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1219 DRM_ERROR("failed to init PCI GART!\n");
1220 radeon_do_cleanup_cp(dev);
1221 return -ENOMEM;
1222 }
1223
1224 /* Turn on PCI GART */
1225 radeon_set_pcigart(dev_priv, 1);
1226 }
1227
1228 radeon_cp_load_microcode(dev_priv);
1229 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1230
1231 dev_priv->last_buf = 0;
1232
1233 radeon_do_engine_reset(dev);
1234 radeon_test_writeback(dev_priv);
1235
1236 return 0;
1237 }
1238
1239 static int radeon_do_cleanup_cp(struct drm_device * dev)
1240 {
1241 drm_radeon_private_t *dev_priv = dev->dev_private;
1242 DRM_DEBUG("\n");
1243
1244 /* Make sure interrupts are disabled here because the uninstall ioctl
1245 * may not have been called from userspace and after dev_private
1246 * is freed, it's too late.
1247 */
1248 if (dev->irq_enabled)
1249 drm_irq_uninstall(dev);
1250
1251 #if __OS_HAS_AGP
1252 if (dev_priv->flags & RADEON_IS_AGP) {
1253 if (dev_priv->cp_ring != NULL) {
1254 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1255 dev_priv->cp_ring = NULL;
1256 }
1257 if (dev_priv->ring_rptr != NULL) {
1258 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1259 dev_priv->ring_rptr = NULL;
1260 }
1261 if (dev->agp_buffer_map != NULL) {
1262 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1263 dev->agp_buffer_map = NULL;
1264 }
1265 } else
1266 #endif
1267 {
1268
1269 if (dev_priv->gart_info.bus_addr) {
1270 /* Turn off PCI GART */
1271 radeon_set_pcigart(dev_priv, 0);
1272 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1273 DRM_ERROR("failed to cleanup PCI GART!\n");
1274 }
1275
1276 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1277 {
1278 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1279 dev_priv->gart_info.addr = 0;
1280 }
1281 }
1282 /* only clear to the start of flags */
1283 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1284
1285 return 0;
1286 }
1287
1288 /* This code will reinit the Radeon CP hardware after a resume from disc.
1289 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1290 * here we make sure that all Radeon hardware initialisation is re-done without
1291 * affecting running applications.
1292 *
1293 * Charl P. Botha <http://cpbotha.net>
1294 */
1295 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1296 {
1297 drm_radeon_private_t *dev_priv = dev->dev_private;
1298
1299 if (!dev_priv) {
1300 DRM_ERROR("Called with no initialization\n");
1301 return -EINVAL;
1302 }
1303
1304 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1305
1306 #if __OS_HAS_AGP
1307 if (dev_priv->flags & RADEON_IS_AGP) {
1308 /* Turn off PCI GART */
1309 radeon_set_pcigart(dev_priv, 0);
1310 } else
1311 #endif
1312 {
1313 /* Turn on PCI GART */
1314 radeon_set_pcigart(dev_priv, 1);
1315 }
1316
1317 radeon_cp_load_microcode(dev_priv);
1318 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1319
1320 radeon_do_engine_reset(dev);
1321 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1322
1323 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1324
1325 return 0;
1326 }
1327
1328 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1329 {
1330 drm_radeon_init_t *init = data;
1331
1332 LOCK_TEST_WITH_RETURN(dev, file_priv);
1333
1334 if (init->func == RADEON_INIT_R300_CP)
1335 r300_init_reg_flags(dev);
1336
1337 switch (init->func) {
1338 case RADEON_INIT_CP:
1339 case RADEON_INIT_R200_CP:
1340 case RADEON_INIT_R300_CP:
1341 return radeon_do_init_cp(dev, init, file_priv);
1342 case RADEON_CLEANUP_CP:
1343 return radeon_do_cleanup_cp(dev);
1344 }
1345
1346 return -EINVAL;
1347 }
1348
1349 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1350 {
1351 drm_radeon_private_t *dev_priv = dev->dev_private;
1352 DRM_DEBUG("\n");
1353
1354 LOCK_TEST_WITH_RETURN(dev, file_priv);
1355
1356 if (dev_priv->cp_running) {
1357 DRM_DEBUG("while CP running\n");
1358 return 0;
1359 }
1360 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1361 DRM_DEBUG("called with bogus CP mode (%d)\n",
1362 dev_priv->cp_mode);
1363 return 0;
1364 }
1365
1366 radeon_do_cp_start(dev_priv);
1367
1368 return 0;
1369 }
1370
1371 /* Stop the CP. The engine must have been idled before calling this
1372 * routine.
1373 */
1374 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1375 {
1376 drm_radeon_private_t *dev_priv = dev->dev_private;
1377 drm_radeon_cp_stop_t *stop = data;
1378 int ret;
1379 DRM_DEBUG("\n");
1380
1381 LOCK_TEST_WITH_RETURN(dev, file_priv);
1382
1383 if (!dev_priv->cp_running)
1384 return 0;
1385
1386 /* Flush any pending CP commands. This ensures any outstanding
1387 * commands are exectuted by the engine before we turn it off.
1388 */
1389 if (stop->flush) {
1390 radeon_do_cp_flush(dev_priv);
1391 }
1392
1393 /* If we fail to make the engine go idle, we return an error
1394 * code so that the DRM ioctl wrapper can try again.
1395 */
1396 if (stop->idle) {
1397 ret = radeon_do_cp_idle(dev_priv);
1398 if (ret)
1399 return ret;
1400 }
1401
1402 /* Finally, we can turn off the CP. If the engine isn't idle,
1403 * we will get some dropped triangles as they won't be fully
1404 * rendered before the CP is shut down.
1405 */
1406 radeon_do_cp_stop(dev_priv);
1407
1408 /* Reset the engine */
1409 radeon_do_engine_reset(dev);
1410
1411 return 0;
1412 }
1413
1414 void radeon_do_release(struct drm_device * dev)
1415 {
1416 drm_radeon_private_t *dev_priv = dev->dev_private;
1417 int i, ret;
1418
1419 if (dev_priv) {
1420 if (dev_priv->cp_running) {
1421 /* Stop the cp */
1422 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1423 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1424 #ifdef __linux__
1425 schedule();
1426 #else
1427 tsleep(&ret, PZERO, "rdnrel", 1);
1428 #endif
1429 }
1430 radeon_do_cp_stop(dev_priv);
1431 radeon_do_engine_reset(dev);
1432 }
1433
1434 /* Disable *all* interrupts */
1435 if (dev_priv->mmio) /* remove this after permanent addmaps */
1436 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1437
1438 if (dev_priv->mmio) { /* remove all surfaces */
1439 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1440 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1441 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1442 16 * i, 0);
1443 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1444 16 * i, 0);
1445 }
1446 }
1447
1448 /* Free memory heap structures */
1449 radeon_mem_takedown(&(dev_priv->gart_heap));
1450 radeon_mem_takedown(&(dev_priv->fb_heap));
1451
1452 /* deallocate kernel resources */
1453 radeon_do_cleanup_cp(dev);
1454 }
1455 }
1456
1457 /* Just reset the CP ring. Called as part of an X Server engine reset.
1458 */
1459 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1460 {
1461 drm_radeon_private_t *dev_priv = dev->dev_private;
1462 DRM_DEBUG("\n");
1463
1464 LOCK_TEST_WITH_RETURN(dev, file_priv);
1465
1466 if (!dev_priv) {
1467 DRM_DEBUG("called before init done\n");
1468 return -EINVAL;
1469 }
1470
1471 radeon_do_cp_reset(dev_priv);
1472
1473 /* The CP is no longer running after an engine reset */
1474 dev_priv->cp_running = 0;
1475
1476 return 0;
1477 }
1478
1479 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1480 {
1481 drm_radeon_private_t *dev_priv = dev->dev_private;
1482 DRM_DEBUG("\n");
1483
1484 LOCK_TEST_WITH_RETURN(dev, file_priv);
1485
1486 return radeon_do_cp_idle(dev_priv);
1487 }
1488
1489 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1490 */
1491 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1492 {
1493 return radeon_do_resume_cp(dev, file_priv);
1494 }
1495
1496 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1497 {
1498 DRM_DEBUG("\n");
1499
1500 LOCK_TEST_WITH_RETURN(dev, file_priv);
1501
1502 return radeon_do_engine_reset(dev);
1503 }
1504
1505 /* ================================================================
1506 * Fullscreen mode
1507 */
1508
1509 /* KW: Deprecated to say the least:
1510 */
1511 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1512 {
1513 return 0;
1514 }
1515
1516 /* ================================================================
1517 * Freelist management
1518 */
1519
1520 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1521 * bufs until freelist code is used. Note this hides a problem with
1522 * the scratch register * (used to keep track of last buffer
1523 * completed) being written to before * the last buffer has actually
1524 * completed rendering.
1525 *
1526 * KW: It's also a good way to find free buffers quickly.
1527 *
1528 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1529 * sleep. However, bugs in older versions of radeon_accel.c mean that
1530 * we essentially have to do this, else old clients will break.
1531 *
1532 * However, it does leave open a potential deadlock where all the
1533 * buffers are held by other clients, which can't release them because
1534 * they can't get the lock.
1535 */
1536
1537 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1538 {
1539 struct drm_device_dma *dma = dev->dma;
1540 drm_radeon_private_t *dev_priv = dev->dev_private;
1541 drm_radeon_buf_priv_t *buf_priv;
1542 struct drm_buf *buf;
1543 int i, t;
1544 int start;
1545
1546 if (++dev_priv->last_buf >= dma->buf_count)
1547 dev_priv->last_buf = 0;
1548
1549 start = dev_priv->last_buf;
1550
1551 for (t = 0; t < dev_priv->usec_timeout; t++) {
1552 u32 done_age = GET_SCRATCH(1);
1553 DRM_DEBUG("done_age = %d\n", done_age);
1554 for (i = start; i < dma->buf_count; i++) {
1555 buf = dma->buflist[i];
1556 buf_priv = buf->dev_private;
1557 if (buf->file_priv == NULL || (buf->pending &&
1558 buf_priv->age <=
1559 done_age)) {
1560 dev_priv->stats.requested_bufs++;
1561 buf->pending = 0;
1562 return buf;
1563 }
1564 start = 0;
1565 }
1566
1567 if (t) {
1568 DRM_UDELAY(1);
1569 dev_priv->stats.freelist_loops++;
1570 }
1571 }
1572
1573 DRM_DEBUG("returning NULL!\n");
1574 return NULL;
1575 }
1576
1577 #if 0
1578 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1579 {
1580 struct drm_device_dma *dma = dev->dma;
1581 drm_radeon_private_t *dev_priv = dev->dev_private;
1582 drm_radeon_buf_priv_t *buf_priv;
1583 struct drm_buf *buf;
1584 int i, t;
1585 int start;
1586 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1587
1588 if (++dev_priv->last_buf >= dma->buf_count)
1589 dev_priv->last_buf = 0;
1590
1591 start = dev_priv->last_buf;
1592 dev_priv->stats.freelist_loops++;
1593
1594 for (t = 0; t < 2; t++) {
1595 for (i = start; i < dma->buf_count; i++) {
1596 buf = dma->buflist[i];
1597 buf_priv = buf->dev_private;
1598 if (buf->file_priv == 0 || (buf->pending &&
1599 buf_priv->age <=
1600 done_age)) {
1601 dev_priv->stats.requested_bufs++;
1602 buf->pending = 0;
1603 return buf;
1604 }
1605 }
1606 start = 0;
1607 }
1608
1609 return NULL;
1610 }
1611 #endif
1612
1613 void radeon_freelist_reset(struct drm_device * dev)
1614 {
1615 struct drm_device_dma *dma = dev->dma;
1616 drm_radeon_private_t *dev_priv = dev->dev_private;
1617 int i;
1618
1619 dev_priv->last_buf = 0;
1620 for (i = 0; i < dma->buf_count; i++) {
1621 struct drm_buf *buf = dma->buflist[i];
1622 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1623 buf_priv->age = 0;
1624 }
1625 }
1626
1627 /* ================================================================
1628 * CP command submission
1629 */
1630
1631 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1632 {
1633 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1634 int i;
1635 u32 last_head = GET_RING_HEAD(dev_priv);
1636
1637 for (i = 0; i < dev_priv->usec_timeout; i++) {
1638 u32 head = GET_RING_HEAD(dev_priv);
1639
1640 ring->space = (head - ring->tail) * sizeof(u32);
1641 if (ring->space <= 0)
1642 ring->space += ring->size;
1643 if (ring->space > n)
1644 return 0;
1645
1646 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1647
1648 if (head != last_head)
1649 i = 0;
1650 last_head = head;
1651
1652 DRM_UDELAY(1);
1653 }
1654
1655 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1656 #if RADEON_FIFO_DEBUG
1657 radeon_status(dev_priv);
1658 DRM_ERROR("failed!\n");
1659 #endif
1660 return -EBUSY;
1661 }
1662
1663 static int radeon_cp_get_buffers(struct drm_device *dev,
1664 struct drm_file *file_priv,
1665 struct drm_dma * d)
1666 {
1667 int i;
1668 struct drm_buf *buf;
1669
1670 for (i = d->granted_count; i < d->request_count; i++) {
1671 buf = radeon_freelist_get(dev);
1672 if (!buf)
1673 return -EBUSY; /* NOTE: broken client */
1674
1675 buf->file_priv = file_priv;
1676
1677 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1678 sizeof(buf->idx)))
1679 return -EFAULT;
1680 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1681 sizeof(buf->total)))
1682 return -EFAULT;
1683
1684 d->granted_count++;
1685 }
1686 return 0;
1687 }
1688
1689 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1690 {
1691 struct drm_device_dma *dma = dev->dma;
1692 int ret = 0;
1693 struct drm_dma *d = data;
1694
1695 LOCK_TEST_WITH_RETURN(dev, file_priv);
1696
1697 /* Please don't send us buffers.
1698 */
1699 if (d->send_count != 0) {
1700 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1701 DRM_CURRENTPID, d->send_count);
1702 return -EINVAL;
1703 }
1704
1705 /* We'll send you buffers.
1706 */
1707 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1708 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1709 DRM_CURRENTPID, d->request_count, dma->buf_count);
1710 return -EINVAL;
1711 }
1712
1713 d->granted_count = 0;
1714
1715 if (d->request_count) {
1716 ret = radeon_cp_get_buffers(dev, file_priv, d);
1717 }
1718
1719 return ret;
1720 }
1721
1722 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1723 {
1724 drm_radeon_private_t *dev_priv;
1725 int ret = 0;
1726
1727 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1728 if (dev_priv == NULL)
1729 return -ENOMEM;
1730
1731 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1732 dev->dev_private = (void *)dev_priv;
1733 dev_priv->flags = flags;
1734
1735 switch (flags & RADEON_FAMILY_MASK) {
1736 case CHIP_R100:
1737 case CHIP_RV200:
1738 case CHIP_R200:
1739 case CHIP_R300:
1740 case CHIP_R350:
1741 case CHIP_R420:
1742 case CHIP_R423:
1743 case CHIP_RV410:
1744 case CHIP_RV515:
1745 case CHIP_R520:
1746 case CHIP_RV570:
1747 case CHIP_R580:
1748 dev_priv->flags |= RADEON_HAS_HIERZ;
1749 break;
1750 default:
1751 /* all other chips have no hierarchical z buffer */
1752 break;
1753 }
1754
1755 if (drm_device_is_agp(dev))
1756 dev_priv->flags |= RADEON_IS_AGP;
1757 else if (drm_device_is_pcie(dev))
1758 dev_priv->flags |= RADEON_IS_PCIE;
1759 else
1760 dev_priv->flags |= RADEON_IS_PCI;
1761
1762 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1763 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1764 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
1765 if (ret != 0)
1766 return ret;
1767
1768 ret = drm_vblank_init(dev, 2);
1769 if (ret) {
1770 radeon_driver_unload(dev);
1771 return ret;
1772 }
1773
1774 DRM_DEBUG("%s card detected\n",
1775 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1776 return ret;
1777 }
1778
1779 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
1780 {
1781 struct drm_radeon_master_private *master_priv;
1782 unsigned long sareapage;
1783 int ret;
1784
1785 master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
1786 if (!master_priv)
1787 return -ENOMEM;
1788
1789 /* prebuild the SAREA */
1790 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
1791 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
1792 &master_priv->sarea);
1793 if (ret) {
1794 DRM_ERROR("SAREA setup failed\n");
1795 return ret;
1796 }
1797 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
1798 master_priv->sarea_priv->pfCurrentPage = 0;
1799
1800 master->driver_priv = master_priv;
1801 return 0;
1802 }
1803
1804 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
1805 {
1806 struct drm_radeon_master_private *master_priv = master->driver_priv;
1807
1808 if (!master_priv)
1809 return;
1810
1811 if (master_priv->sarea_priv &&
1812 master_priv->sarea_priv->pfCurrentPage != 0)
1813 radeon_cp_dispatch_flip(dev, master);
1814
1815 master_priv->sarea_priv = NULL;
1816 if (master_priv->sarea)
1817 drm_rmmap_locked(dev, master_priv->sarea);
1818
1819 drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
1820
1821 master->driver_priv = NULL;
1822 }
1823
1824 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1825 * have to find them.
1826 */
1827 int radeon_driver_firstopen(struct drm_device *dev)
1828 {
1829 int ret;
1830 drm_local_map_t *map;
1831 drm_radeon_private_t *dev_priv = dev->dev_private;
1832
1833 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1834
1835 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1836 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1837 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1838 _DRM_WRITE_COMBINING, &map);
1839 if (ret != 0)
1840 return ret;
1841
1842 return 0;
1843 }
1844
1845 int radeon_driver_unload(struct drm_device *dev)
1846 {
1847 drm_radeon_private_t *dev_priv = dev->dev_private;
1848
1849 DRM_DEBUG("\n");
1850
1851 drm_rmmap(dev, dev_priv->mmio);
1852
1853 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1854
1855 dev->dev_private = NULL;
1856 return 0;
1857 }
Linux kernel - Deliverables
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