projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/radeon: add GET_PARAM/INFO support for Z pipes
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_cp.c
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "drm_sarea.h"
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
37 #include "r300_reg.h"
38
39 #include "radeon_microcode.h"
40
41 #define RADEON_FIFO_DEBUG 0
42
43 static int radeon_do_cleanup_cp(struct drm_device * dev);
44 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
45
46 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
47 {
48 u32 val;
49
50 if (dev_priv->flags & RADEON_IS_AGP) {
51 val = DRM_READ32(dev_priv->ring_rptr, off);
52 } else {
53 val = *(((volatile u32 *)
54 dev_priv->ring_rptr->handle) +
55 (off / sizeof(u32)));
56 val = le32_to_cpu(val);
57 }
58 return val;
59 }
60
61 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
62 {
63 if (dev_priv->writeback_works)
64 return radeon_read_ring_rptr(dev_priv, 0);
65 else {
66 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
67 return RADEON_READ(R600_CP_RB_RPTR);
68 else
69 return RADEON_READ(RADEON_CP_RB_RPTR);
70 }
71 }
72
73 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
74 {
75 if (dev_priv->flags & RADEON_IS_AGP)
76 DRM_WRITE32(dev_priv->ring_rptr, off, val);
77 else
78 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
79 (off / sizeof(u32))) = cpu_to_le32(val);
80 }
81
82 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
83 {
84 radeon_write_ring_rptr(dev_priv, 0, val);
85 }
86
87 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
88 {
89 if (dev_priv->writeback_works) {
90 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
91 return radeon_read_ring_rptr(dev_priv,
92 R600_SCRATCHOFF(index));
93 else
94 return radeon_read_ring_rptr(dev_priv,
95 RADEON_SCRATCHOFF(index));
96 } else {
97 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
98 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
99 else
100 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
101 }
102 }
103
104 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
105 {
106 u32 ret;
107
108 if (addr < 0x10000)
109 ret = DRM_READ32(dev_priv->mmio, addr);
110 else {
111 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
112 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
113 }
114
115 return ret;
116 }
117
118 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
119 {
120 u32 ret;
121 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
122 ret = RADEON_READ(R520_MC_IND_DATA);
123 RADEON_WRITE(R520_MC_IND_INDEX, 0);
124 return ret;
125 }
126
127 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
128 {
129 u32 ret;
130 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
131 ret = RADEON_READ(RS480_NB_MC_DATA);
132 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
133 return ret;
134 }
135
136 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
137 {
138 u32 ret;
139 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
140 ret = RADEON_READ(RS690_MC_DATA);
141 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
142 return ret;
143 }
144
145 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
146 {
147 u32 ret;
148 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
149 RS600_MC_IND_CITF_ARB0));
150 ret = RADEON_READ(RS600_MC_DATA);
151 return ret;
152 }
153
154 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
155 {
156 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
157 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
158 return RS690_READ_MCIND(dev_priv, addr);
159 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
160 return RS600_READ_MCIND(dev_priv, addr);
161 else
162 return RS480_READ_MCIND(dev_priv, addr);
163 }
164
165 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
166 {
167
168 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
169 return RADEON_READ(R700_MC_VM_FB_LOCATION);
170 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
171 return RADEON_READ(R600_MC_VM_FB_LOCATION);
172 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
173 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
174 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
175 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
176 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
177 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
178 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
179 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
180 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
181 else
182 return RADEON_READ(RADEON_MC_FB_LOCATION);
183 }
184
185 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
186 {
187 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
188 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
189 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
190 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
191 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
192 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
193 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
194 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
195 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
196 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
197 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
198 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
199 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
200 else
201 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
202 }
203
204 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
205 {
206 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
207 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
208 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
209 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
210 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
211 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
212 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
213 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
214 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
215 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
216 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
217 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
218 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
219 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
220 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
221 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
222 else
223 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
224 }
225
226 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
227 {
228 u32 agp_base_hi = upper_32_bits(agp_base);
229 u32 agp_base_lo = agp_base & 0xffffffff;
230 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
231
232 /* R6xx/R7xx must be aligned to a 4MB boundry */
233 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
234 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
235 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
236 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
237 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
238 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
239 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
240 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
241 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
242 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
243 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
244 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
245 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
246 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
247 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
248 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
249 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
250 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
251 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
252 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
253 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
254 } else {
255 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
256 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
257 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
258 }
259 }
260
261 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
262 {
263 u32 tmp;
264 /* Turn on bus mastering */
265 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
266 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
267 /* rs600/rs690/rs740 */
268 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
269 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
270 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
271 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
272 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
273 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
274 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
275 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
276 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
277 } /* PCIE cards appears to not need this */
278 }
279
280 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
281 {
282 drm_radeon_private_t *dev_priv = dev->dev_private;
283
284 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
285 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
286 }
287
288 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
289 {
290 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
291 return RADEON_READ(RADEON_PCIE_DATA);
292 }
293
294 #if RADEON_FIFO_DEBUG
295 static void radeon_status(drm_radeon_private_t * dev_priv)
296 {
297 printk("%s:\n", __func__);
298 printk("RBBM_STATUS = 0x%08x\n",
299 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
300 printk("CP_RB_RTPR = 0x%08x\n",
301 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
302 printk("CP_RB_WTPR = 0x%08x\n",
303 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
304 printk("AIC_CNTL = 0x%08x\n",
305 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
306 printk("AIC_STAT = 0x%08x\n",
307 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
308 printk("AIC_PT_BASE = 0x%08x\n",
309 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
310 printk("TLB_ADDR = 0x%08x\n",
311 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
312 printk("TLB_DATA = 0x%08x\n",
313 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
314 }
315 #endif
316
317 /* ================================================================
318 * Engine, FIFO control
319 */
320
321 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
322 {
323 u32 tmp;
324 int i;
325
326 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
327
328 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
329 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
330 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
331 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
332
333 for (i = 0; i < dev_priv->usec_timeout; i++) {
334 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
335 & RADEON_RB3D_DC_BUSY)) {
336 return 0;
337 }
338 DRM_UDELAY(1);
339 }
340 } else {
341 /* don't flush or purge cache here or lockup */
342 return 0;
343 }
344
345 #if RADEON_FIFO_DEBUG
346 DRM_ERROR("failed!\n");
347 radeon_status(dev_priv);
348 #endif
349 return -EBUSY;
350 }
351
352 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
353 {
354 int i;
355
356 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
357
358 for (i = 0; i < dev_priv->usec_timeout; i++) {
359 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
360 & RADEON_RBBM_FIFOCNT_MASK);
361 if (slots >= entries)
362 return 0;
363 DRM_UDELAY(1);
364 }
365 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
366 RADEON_READ(RADEON_RBBM_STATUS),
367 RADEON_READ(R300_VAP_CNTL_STATUS));
368
369 #if RADEON_FIFO_DEBUG
370 DRM_ERROR("failed!\n");
371 radeon_status(dev_priv);
372 #endif
373 return -EBUSY;
374 }
375
376 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
377 {
378 int i, ret;
379
380 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
381
382 ret = radeon_do_wait_for_fifo(dev_priv, 64);
383 if (ret)
384 return ret;
385
386 for (i = 0; i < dev_priv->usec_timeout; i++) {
387 if (!(RADEON_READ(RADEON_RBBM_STATUS)
388 & RADEON_RBBM_ACTIVE)) {
389 radeon_do_pixcache_flush(dev_priv);
390 return 0;
391 }
392 DRM_UDELAY(1);
393 }
394 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
395 RADEON_READ(RADEON_RBBM_STATUS),
396 RADEON_READ(R300_VAP_CNTL_STATUS));
397
398 #if RADEON_FIFO_DEBUG
399 DRM_ERROR("failed!\n");
400 radeon_status(dev_priv);
401 #endif
402 return -EBUSY;
403 }
404
405 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
406 {
407 uint32_t gb_tile_config, gb_pipe_sel = 0;
408
409 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
410 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
411 if ((z_pipe_sel & 3) == 3)
412 dev_priv->num_z_pipes = 2;
413 else
414 dev_priv->num_z_pipes = 1;
415 } else
416 dev_priv->num_z_pipes = 1;
417
418 /* RS4xx/RS6xx/R4xx/R5xx */
419 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
420 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
421 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
422 } else {
423 /* R3xx */
424 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
425 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
426 dev_priv->num_gb_pipes = 2;
427 } else {
428 /* R3Vxx */
429 dev_priv->num_gb_pipes = 1;
430 }
431 }
432 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
433
434 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
435
436 switch (dev_priv->num_gb_pipes) {
437 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
438 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
439 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
440 default:
441 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
442 }
443
444 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
445 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
446 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
447 }
448 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
449 radeon_do_wait_for_idle(dev_priv);
450 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
451 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
452 R300_DC_AUTOFLUSH_ENABLE |
453 R300_DC_DC_DISABLE_IGNORE_PE));
454
455
456 }
457
458 /* ================================================================
459 * CP control, initialization
460 */
461
462 /* Load the microcode for the CP */
463 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
464 {
465 int i;
466 DRM_DEBUG("\n");
467
468 radeon_do_wait_for_idle(dev_priv);
469
470 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
471 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
472 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
473 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
474 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
475 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
476 DRM_INFO("Loading R100 Microcode\n");
477 for (i = 0; i < 256; i++) {
478 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
479 R100_cp_microcode[i][1]);
480 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
481 R100_cp_microcode[i][0]);
482 }
483 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
484 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
485 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
486 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
487 DRM_INFO("Loading R200 Microcode\n");
488 for (i = 0; i < 256; i++) {
489 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
490 R200_cp_microcode[i][1]);
491 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
492 R200_cp_microcode[i][0]);
493 }
494 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
495 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
496 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
497 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
498 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
499 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
500 DRM_INFO("Loading R300 Microcode\n");
501 for (i = 0; i < 256; i++) {
502 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
503 R300_cp_microcode[i][1]);
504 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
505 R300_cp_microcode[i][0]);
506 }
507 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
508 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
509 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
510 DRM_INFO("Loading R400 Microcode\n");
511 for (i = 0; i < 256; i++) {
512 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
513 R420_cp_microcode[i][1]);
514 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
515 R420_cp_microcode[i][0]);
516 }
517 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
518 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
519 DRM_INFO("Loading RS690/RS740 Microcode\n");
520 for (i = 0; i < 256; i++) {
521 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
522 RS690_cp_microcode[i][1]);
523 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
524 RS690_cp_microcode[i][0]);
525 }
526 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
527 DRM_INFO("Loading RS600 Microcode\n");
528 for (i = 0; i < 256; i++) {
529 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
530 RS600_cp_microcode[i][1]);
531 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
532 RS600_cp_microcode[i][0]);
533 }
534 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
535 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
536 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
537 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
538 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
539 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
540 DRM_INFO("Loading R500 Microcode\n");
541 for (i = 0; i < 256; i++) {
542 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
543 R520_cp_microcode[i][1]);
544 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
545 R520_cp_microcode[i][0]);
546 }
547 }
548 }
549
550 /* Flush any pending commands to the CP. This should only be used just
551 * prior to a wait for idle, as it informs the engine that the command
552 * stream is ending.
553 */
554 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
555 {
556 DRM_DEBUG("\n");
557 #if 0
558 u32 tmp;
559
560 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
561 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
562 #endif
563 }
564
565 /* Wait for the CP to go idle.
566 */
567 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
568 {
569 RING_LOCALS;
570 DRM_DEBUG("\n");
571
572 BEGIN_RING(6);
573
574 RADEON_PURGE_CACHE();
575 RADEON_PURGE_ZCACHE();
576 RADEON_WAIT_UNTIL_IDLE();
577
578 ADVANCE_RING();
579 COMMIT_RING();
580
581 return radeon_do_wait_for_idle(dev_priv);
582 }
583
584 /* Start the Command Processor.
585 */
586 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
587 {
588 RING_LOCALS;
589 DRM_DEBUG("\n");
590
591 radeon_do_wait_for_idle(dev_priv);
592
593 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
594
595 dev_priv->cp_running = 1;
596
597 BEGIN_RING(8);
598 /* isync can only be written through cp on r5xx write it here */
599 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
600 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
601 RADEON_ISYNC_ANY3D_IDLE2D |
602 RADEON_ISYNC_WAIT_IDLEGUI |
603 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
604 RADEON_PURGE_CACHE();
605 RADEON_PURGE_ZCACHE();
606 RADEON_WAIT_UNTIL_IDLE();
607 ADVANCE_RING();
608 COMMIT_RING();
609
610 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
611 }
612
613 /* Reset the Command Processor. This will not flush any pending
614 * commands, so you must wait for the CP command stream to complete
615 * before calling this routine.
616 */
617 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
618 {
619 u32 cur_read_ptr;
620 DRM_DEBUG("\n");
621
622 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
623 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
624 SET_RING_HEAD(dev_priv, cur_read_ptr);
625 dev_priv->ring.tail = cur_read_ptr;
626 }
627
628 /* Stop the Command Processor. This will not flush any pending
629 * commands, so you must flush the command stream and wait for the CP
630 * to go idle before calling this routine.
631 */
632 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
633 {
634 DRM_DEBUG("\n");
635
636 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
637
638 dev_priv->cp_running = 0;
639 }
640
641 /* Reset the engine. This will stop the CP if it is running.
642 */
643 static int radeon_do_engine_reset(struct drm_device * dev)
644 {
645 drm_radeon_private_t *dev_priv = dev->dev_private;
646 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
647 DRM_DEBUG("\n");
648
649 radeon_do_pixcache_flush(dev_priv);
650
651 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
652 /* may need something similar for newer chips */
653 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
654 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
655
656 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
657 RADEON_FORCEON_MCLKA |
658 RADEON_FORCEON_MCLKB |
659 RADEON_FORCEON_YCLKA |
660 RADEON_FORCEON_YCLKB |
661 RADEON_FORCEON_MC |
662 RADEON_FORCEON_AIC));
663 }
664
665 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
666
667 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
668 RADEON_SOFT_RESET_CP |
669 RADEON_SOFT_RESET_HI |
670 RADEON_SOFT_RESET_SE |
671 RADEON_SOFT_RESET_RE |
672 RADEON_SOFT_RESET_PP |
673 RADEON_SOFT_RESET_E2 |
674 RADEON_SOFT_RESET_RB));
675 RADEON_READ(RADEON_RBBM_SOFT_RESET);
676 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
677 ~(RADEON_SOFT_RESET_CP |
678 RADEON_SOFT_RESET_HI |
679 RADEON_SOFT_RESET_SE |
680 RADEON_SOFT_RESET_RE |
681 RADEON_SOFT_RESET_PP |
682 RADEON_SOFT_RESET_E2 |
683 RADEON_SOFT_RESET_RB)));
684 RADEON_READ(RADEON_RBBM_SOFT_RESET);
685
686 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
687 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
688 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
689 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
690 }
691
692 /* setup the raster pipes */
693 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
694 radeon_init_pipes(dev_priv);
695
696 /* Reset the CP ring */
697 radeon_do_cp_reset(dev_priv);
698
699 /* The CP is no longer running after an engine reset */
700 dev_priv->cp_running = 0;
701
702 /* Reset any pending vertex, indirect buffers */
703 radeon_freelist_reset(dev);
704
705 return 0;
706 }
707
708 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
709 drm_radeon_private_t *dev_priv,
710 struct drm_file *file_priv)
711 {
712 struct drm_radeon_master_private *master_priv;
713 u32 ring_start, cur_read_ptr;
714
715 /* Initialize the memory controller. With new memory map, the fb location
716 * is not changed, it should have been properly initialized already. Part
717 * of the problem is that the code below is bogus, assuming the GART is
718 * always appended to the fb which is not necessarily the case
719 */
720 if (!dev_priv->new_memmap)
721 radeon_write_fb_location(dev_priv,
722 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
723 | (dev_priv->fb_location >> 16));
724
725 #if __OS_HAS_AGP
726 if (dev_priv->flags & RADEON_IS_AGP) {
727 radeon_write_agp_base(dev_priv, dev->agp->base);
728
729 radeon_write_agp_location(dev_priv,
730 (((dev_priv->gart_vm_start - 1 +
731 dev_priv->gart_size) & 0xffff0000) |
732 (dev_priv->gart_vm_start >> 16)));
733
734 ring_start = (dev_priv->cp_ring->offset
735 - dev->agp->base
736 + dev_priv->gart_vm_start);
737 } else
738 #endif
739 ring_start = (dev_priv->cp_ring->offset
740 - (unsigned long)dev->sg->virtual
741 + dev_priv->gart_vm_start);
742
743 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
744
745 /* Set the write pointer delay */
746 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
747
748 /* Initialize the ring buffer's read and write pointers */
749 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
750 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
751 SET_RING_HEAD(dev_priv, cur_read_ptr);
752 dev_priv->ring.tail = cur_read_ptr;
753
754 #if __OS_HAS_AGP
755 if (dev_priv->flags & RADEON_IS_AGP) {
756 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
757 dev_priv->ring_rptr->offset
758 - dev->agp->base + dev_priv->gart_vm_start);
759 } else
760 #endif
761 {
762 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
763 dev_priv->ring_rptr->offset
764 - ((unsigned long) dev->sg->virtual)
765 + dev_priv->gart_vm_start);
766 }
767
768 /* Set ring buffer size */
769 #ifdef __BIG_ENDIAN
770 RADEON_WRITE(RADEON_CP_RB_CNTL,
771 RADEON_BUF_SWAP_32BIT |
772 (dev_priv->ring.fetch_size_l2ow << 18) |
773 (dev_priv->ring.rptr_update_l2qw << 8) |
774 dev_priv->ring.size_l2qw);
775 #else
776 RADEON_WRITE(RADEON_CP_RB_CNTL,
777 (dev_priv->ring.fetch_size_l2ow << 18) |
778 (dev_priv->ring.rptr_update_l2qw << 8) |
779 dev_priv->ring.size_l2qw);
780 #endif
781
782
783 /* Initialize the scratch register pointer. This will cause
784 * the scratch register values to be written out to memory
785 * whenever they are updated.
786 *
787 * We simply put this behind the ring read pointer, this works
788 * with PCI GART as well as (whatever kind of) AGP GART
789 */
790 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
791 + RADEON_SCRATCH_REG_OFFSET);
792
793 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
794
795 radeon_enable_bm(dev_priv);
796
797 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
798 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
799
800 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
801 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
802
803 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
804 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
805
806 /* reset sarea copies of these */
807 master_priv = file_priv->master->driver_priv;
808 if (master_priv->sarea_priv) {
809 master_priv->sarea_priv->last_frame = 0;
810 master_priv->sarea_priv->last_dispatch = 0;
811 master_priv->sarea_priv->last_clear = 0;
812 }
813
814 radeon_do_wait_for_idle(dev_priv);
815
816 /* Sync everything up */
817 RADEON_WRITE(RADEON_ISYNC_CNTL,
818 (RADEON_ISYNC_ANY2D_IDLE3D |
819 RADEON_ISYNC_ANY3D_IDLE2D |
820 RADEON_ISYNC_WAIT_IDLEGUI |
821 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
822
823 }
824
825 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
826 {
827 u32 tmp;
828
829 /* Start with assuming that writeback doesn't work */
830 dev_priv->writeback_works = 0;
831
832 /* Writeback doesn't seem to work everywhere, test it here and possibly
833 * enable it if it appears to work
834 */
835 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
836
837 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
838
839 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
840 u32 val;
841
842 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
843 if (val == 0xdeadbeef)
844 break;
845 DRM_UDELAY(1);
846 }
847
848 if (tmp < dev_priv->usec_timeout) {
849 dev_priv->writeback_works = 1;
850 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
851 } else {
852 dev_priv->writeback_works = 0;
853 DRM_INFO("writeback test failed\n");
854 }
855 if (radeon_no_wb == 1) {
856 dev_priv->writeback_works = 0;
857 DRM_INFO("writeback forced off\n");
858 }
859
860 if (!dev_priv->writeback_works) {
861 /* Disable writeback to avoid unnecessary bus master transfer */
862 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
863 RADEON_RB_NO_UPDATE);
864 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
865 }
866 }
867
868 /* Enable or disable IGP GART on the chip */
869 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
870 {
871 u32 temp;
872
873 if (on) {
874 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
875 dev_priv->gart_vm_start,
876 (long)dev_priv->gart_info.bus_addr,
877 dev_priv->gart_size);
878
879 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
880 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
881 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
882 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
883 RS690_BLOCK_GFX_D3_EN));
884 else
885 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
886
887 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
888 RS480_VA_SIZE_32MB));
889
890 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
891 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
892 RS480_TLB_ENABLE |
893 RS480_GTW_LAC_EN |
894 RS480_1LEVEL_GART));
895
896 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
897 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
898 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
899
900 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
901 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
902 RS480_REQ_TYPE_SNOOP_DIS));
903
904 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
905
906 dev_priv->gart_size = 32*1024*1024;
907 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
908 0xffff0000) | (dev_priv->gart_vm_start >> 16));
909
910 radeon_write_agp_location(dev_priv, temp);
911
912 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
913 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
914 RS480_VA_SIZE_32MB));
915
916 do {
917 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
918 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
919 break;
920 DRM_UDELAY(1);
921 } while (1);
922
923 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
924 RS480_GART_CACHE_INVALIDATE);
925
926 do {
927 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
928 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
929 break;
930 DRM_UDELAY(1);
931 } while (1);
932
933 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
934 } else {
935 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
936 }
937 }
938
939 /* Enable or disable IGP GART on the chip */
940 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
941 {
942 u32 temp;
943 int i;
944
945 if (on) {
946 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
947 dev_priv->gart_vm_start,
948 (long)dev_priv->gart_info.bus_addr,
949 dev_priv->gart_size);
950
951 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
952 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
953
954 for (i = 0; i < 19; i++)
955 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
956 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
957 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
958 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
959 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
960 RS600_ENABLE_FRAGMENT_PROCESSING |
961 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
962
963 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
964 RS600_PAGE_TABLE_TYPE_FLAT));
965
966 /* disable all other contexts */
967 for (i = 1; i < 8; i++)
968 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
969
970 /* setup the page table aperture */
971 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
972 dev_priv->gart_info.bus_addr);
973 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
974 dev_priv->gart_vm_start);
975 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
976 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
977 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
978
979 /* setup the system aperture */
980 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
981 dev_priv->gart_vm_start);
982 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
983 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
984
985 /* enable page tables */
986 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
987 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
988
989 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
990 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
991
992 /* invalidate the cache */
993 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
994
995 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
996 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
997 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
998
999 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1000 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1001 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1002
1003 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1004 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1005 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1006
1007 } else {
1008 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1009 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1010 temp &= ~RS600_ENABLE_PAGE_TABLES;
1011 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1012 }
1013 }
1014
1015 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1016 {
1017 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1018 if (on) {
1019
1020 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1021 dev_priv->gart_vm_start,
1022 (long)dev_priv->gart_info.bus_addr,
1023 dev_priv->gart_size);
1024 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1025 dev_priv->gart_vm_start);
1026 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1027 dev_priv->gart_info.bus_addr);
1028 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1029 dev_priv->gart_vm_start);
1030 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1031 dev_priv->gart_vm_start +
1032 dev_priv->gart_size - 1);
1033
1034 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1035
1036 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1037 RADEON_PCIE_TX_GART_EN);
1038 } else {
1039 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1040 tmp & ~RADEON_PCIE_TX_GART_EN);
1041 }
1042 }
1043
1044 /* Enable or disable PCI GART on the chip */
1045 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1046 {
1047 u32 tmp;
1048
1049 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1050 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1051 (dev_priv->flags & RADEON_IS_IGPGART)) {
1052 radeon_set_igpgart(dev_priv, on);
1053 return;
1054 }
1055
1056 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1057 rs600_set_igpgart(dev_priv, on);
1058 return;
1059 }
1060
1061 if (dev_priv->flags & RADEON_IS_PCIE) {
1062 radeon_set_pciegart(dev_priv, on);
1063 return;
1064 }
1065
1066 tmp = RADEON_READ(RADEON_AIC_CNTL);
1067
1068 if (on) {
1069 RADEON_WRITE(RADEON_AIC_CNTL,
1070 tmp | RADEON_PCIGART_TRANSLATE_EN);
1071
1072 /* set PCI GART page-table base address
1073 */
1074 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1075
1076 /* set address range for PCI address translate
1077 */
1078 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1079 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1080 + dev_priv->gart_size - 1);
1081
1082 /* Turn off AGP aperture -- is this required for PCI GART?
1083 */
1084 radeon_write_agp_location(dev_priv, 0xffffffc0);
1085 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1086 } else {
1087 RADEON_WRITE(RADEON_AIC_CNTL,
1088 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1089 }
1090 }
1091
1092 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1093 {
1094 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1095 struct radeon_virt_surface *vp;
1096 int i;
1097
1098 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1099 if (!dev_priv->virt_surfaces[i].file_priv ||
1100 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1101 break;
1102 }
1103 if (i >= 2 * RADEON_MAX_SURFACES)
1104 return -ENOMEM;
1105 vp = &dev_priv->virt_surfaces[i];
1106
1107 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1108 struct radeon_surface *sp = &dev_priv->surfaces[i];
1109 if (sp->refcount)
1110 continue;
1111
1112 vp->surface_index = i;
1113 vp->lower = gart_info->bus_addr;
1114 vp->upper = vp->lower + gart_info->table_size;
1115 vp->flags = 0;
1116 vp->file_priv = PCIGART_FILE_PRIV;
1117
1118 sp->refcount = 1;
1119 sp->lower = vp->lower;
1120 sp->upper = vp->upper;
1121 sp->flags = 0;
1122
1123 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1124 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1125 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1126 return 0;
1127 }
1128
1129 return -ENOMEM;
1130 }
1131
1132 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1133 struct drm_file *file_priv)
1134 {
1135 drm_radeon_private_t *dev_priv = dev->dev_private;
1136 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1137
1138 DRM_DEBUG("\n");
1139
1140 /* if we require new memory map but we don't have it fail */
1141 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1142 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1143 radeon_do_cleanup_cp(dev);
1144 return -EINVAL;
1145 }
1146
1147 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1148 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1149 dev_priv->flags &= ~RADEON_IS_AGP;
1150 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1151 && !init->is_pci) {
1152 DRM_DEBUG("Restoring AGP flag\n");
1153 dev_priv->flags |= RADEON_IS_AGP;
1154 }
1155
1156 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1157 DRM_ERROR("PCI GART memory not allocated!\n");
1158 radeon_do_cleanup_cp(dev);
1159 return -EINVAL;
1160 }
1161
1162 dev_priv->usec_timeout = init->usec_timeout;
1163 if (dev_priv->usec_timeout < 1 ||
1164 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1165 DRM_DEBUG("TIMEOUT problem!\n");
1166 radeon_do_cleanup_cp(dev);
1167 return -EINVAL;
1168 }
1169
1170 /* Enable vblank on CRTC1 for older X servers
1171 */
1172 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1173
1174 switch(init->func) {
1175 case RADEON_INIT_R200_CP:
1176 dev_priv->microcode_version = UCODE_R200;
1177 break;
1178 case RADEON_INIT_R300_CP:
1179 dev_priv->microcode_version = UCODE_R300;
1180 break;
1181 default:
1182 dev_priv->microcode_version = UCODE_R100;
1183 }
1184
1185 dev_priv->do_boxes = 0;
1186 dev_priv->cp_mode = init->cp_mode;
1187
1188 /* We don't support anything other than bus-mastering ring mode,
1189 * but the ring can be in either AGP or PCI space for the ring
1190 * read pointer.
1191 */
1192 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1193 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1194 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1195 radeon_do_cleanup_cp(dev);
1196 return -EINVAL;
1197 }
1198
1199 switch (init->fb_bpp) {
1200 case 16:
1201 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1202 break;
1203 case 32:
1204 default:
1205 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1206 break;
1207 }
1208 dev_priv->front_offset = init->front_offset;
1209 dev_priv->front_pitch = init->front_pitch;
1210 dev_priv->back_offset = init->back_offset;
1211 dev_priv->back_pitch = init->back_pitch;
1212
1213 switch (init->depth_bpp) {
1214 case 16:
1215 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1216 break;
1217 case 32:
1218 default:
1219 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1220 break;
1221 }
1222 dev_priv->depth_offset = init->depth_offset;
1223 dev_priv->depth_pitch = init->depth_pitch;
1224
1225 /* Hardware state for depth clears. Remove this if/when we no
1226 * longer clear the depth buffer with a 3D rectangle. Hard-code
1227 * all values to prevent unwanted 3D state from slipping through
1228 * and screwing with the clear operation.
1229 */
1230 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1231 (dev_priv->color_fmt << 10) |
1232 (dev_priv->microcode_version ==
1233 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1234
1235 dev_priv->depth_clear.rb3d_zstencilcntl =
1236 (dev_priv->depth_fmt |
1237 RADEON_Z_TEST_ALWAYS |
1238 RADEON_STENCIL_TEST_ALWAYS |
1239 RADEON_STENCIL_S_FAIL_REPLACE |
1240 RADEON_STENCIL_ZPASS_REPLACE |
1241 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1242
1243 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1244 RADEON_BFACE_SOLID |
1245 RADEON_FFACE_SOLID |
1246 RADEON_FLAT_SHADE_VTX_LAST |
1247 RADEON_DIFFUSE_SHADE_FLAT |
1248 RADEON_ALPHA_SHADE_FLAT |
1249 RADEON_SPECULAR_SHADE_FLAT |
1250 RADEON_FOG_SHADE_FLAT |
1251 RADEON_VTX_PIX_CENTER_OGL |
1252 RADEON_ROUND_MODE_TRUNC |
1253 RADEON_ROUND_PREC_8TH_PIX);
1254
1255
1256 dev_priv->ring_offset = init->ring_offset;
1257 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1258 dev_priv->buffers_offset = init->buffers_offset;
1259 dev_priv->gart_textures_offset = init->gart_textures_offset;
1260
1261 master_priv->sarea = drm_getsarea(dev);
1262 if (!master_priv->sarea) {
1263 DRM_ERROR("could not find sarea!\n");
1264 radeon_do_cleanup_cp(dev);
1265 return -EINVAL;
1266 }
1267
1268 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1269 if (!dev_priv->cp_ring) {
1270 DRM_ERROR("could not find cp ring region!\n");
1271 radeon_do_cleanup_cp(dev);
1272 return -EINVAL;
1273 }
1274 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1275 if (!dev_priv->ring_rptr) {
1276 DRM_ERROR("could not find ring read pointer!\n");
1277 radeon_do_cleanup_cp(dev);
1278 return -EINVAL;
1279 }
1280 dev->agp_buffer_token = init->buffers_offset;
1281 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1282 if (!dev->agp_buffer_map) {
1283 DRM_ERROR("could not find dma buffer region!\n");
1284 radeon_do_cleanup_cp(dev);
1285 return -EINVAL;
1286 }
1287
1288 if (init->gart_textures_offset) {
1289 dev_priv->gart_textures =
1290 drm_core_findmap(dev, init->gart_textures_offset);
1291 if (!dev_priv->gart_textures) {
1292 DRM_ERROR("could not find GART texture region!\n");
1293 radeon_do_cleanup_cp(dev);
1294 return -EINVAL;
1295 }
1296 }
1297
1298 #if __OS_HAS_AGP
1299 if (dev_priv->flags & RADEON_IS_AGP) {
1300 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1301 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1302 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1303 if (!dev_priv->cp_ring->handle ||
1304 !dev_priv->ring_rptr->handle ||
1305 !dev->agp_buffer_map->handle) {
1306 DRM_ERROR("could not find ioremap agp regions!\n");
1307 radeon_do_cleanup_cp(dev);
1308 return -EINVAL;
1309 }
1310 } else
1311 #endif
1312 {
1313 dev_priv->cp_ring->handle =
1314 (void *)(unsigned long)dev_priv->cp_ring->offset;
1315 dev_priv->ring_rptr->handle =
1316 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1317 dev->agp_buffer_map->handle =
1318 (void *)(unsigned long)dev->agp_buffer_map->offset;
1319
1320 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1321 dev_priv->cp_ring->handle);
1322 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1323 dev_priv->ring_rptr->handle);
1324 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1325 dev->agp_buffer_map->handle);
1326 }
1327
1328 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1329 dev_priv->fb_size =
1330 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1331 - dev_priv->fb_location;
1332
1333 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1334 ((dev_priv->front_offset
1335 + dev_priv->fb_location) >> 10));
1336
1337 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1338 ((dev_priv->back_offset
1339 + dev_priv->fb_location) >> 10));
1340
1341 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1342 ((dev_priv->depth_offset
1343 + dev_priv->fb_location) >> 10));
1344
1345 dev_priv->gart_size = init->gart_size;
1346
1347 /* New let's set the memory map ... */
1348 if (dev_priv->new_memmap) {
1349 u32 base = 0;
1350
1351 DRM_INFO("Setting GART location based on new memory map\n");
1352
1353 /* If using AGP, try to locate the AGP aperture at the same
1354 * location in the card and on the bus, though we have to
1355 * align it down.
1356 */
1357 #if __OS_HAS_AGP
1358 if (dev_priv->flags & RADEON_IS_AGP) {
1359 base = dev->agp->base;
1360 /* Check if valid */
1361 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1362 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1363 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1364 dev->agp->base);
1365 base = 0;
1366 }
1367 }
1368 #endif
1369 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1370 if (base == 0) {
1371 base = dev_priv->fb_location + dev_priv->fb_size;
1372 if (base < dev_priv->fb_location ||
1373 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1374 base = dev_priv->fb_location
1375 - dev_priv->gart_size;
1376 }
1377 dev_priv->gart_vm_start = base & 0xffc00000u;
1378 if (dev_priv->gart_vm_start != base)
1379 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1380 base, dev_priv->gart_vm_start);
1381 } else {
1382 DRM_INFO("Setting GART location based on old memory map\n");
1383 dev_priv->gart_vm_start = dev_priv->fb_location +
1384 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1385 }
1386
1387 #if __OS_HAS_AGP
1388 if (dev_priv->flags & RADEON_IS_AGP)
1389 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1390 - dev->agp->base
1391 + dev_priv->gart_vm_start);
1392 else
1393 #endif
1394 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1395 - (unsigned long)dev->sg->virtual
1396 + dev_priv->gart_vm_start);
1397
1398 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1399 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1400 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1401 dev_priv->gart_buffers_offset);
1402
1403 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1404 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1405 + init->ring_size / sizeof(u32));
1406 dev_priv->ring.size = init->ring_size;
1407 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1408
1409 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1410 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1411
1412 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1413 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1414 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1415
1416 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1417
1418 #if __OS_HAS_AGP
1419 if (dev_priv->flags & RADEON_IS_AGP) {
1420 /* Turn off PCI GART */
1421 radeon_set_pcigart(dev_priv, 0);
1422 } else
1423 #endif
1424 {
1425 u32 sctrl;
1426 int ret;
1427
1428 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1429 /* if we have an offset set from userspace */
1430 if (dev_priv->pcigart_offset_set) {
1431 dev_priv->gart_info.bus_addr =
1432 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1433 dev_priv->gart_info.mapping.offset =
1434 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1435 dev_priv->gart_info.mapping.size =
1436 dev_priv->gart_info.table_size;
1437
1438 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1439 dev_priv->gart_info.addr =
1440 dev_priv->gart_info.mapping.handle;
1441
1442 if (dev_priv->flags & RADEON_IS_PCIE)
1443 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1444 else
1445 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1446 dev_priv->gart_info.gart_table_location =
1447 DRM_ATI_GART_FB;
1448
1449 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1450 dev_priv->gart_info.addr,
1451 dev_priv->pcigart_offset);
1452 } else {
1453 if (dev_priv->flags & RADEON_IS_IGPGART)
1454 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1455 else
1456 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1457 dev_priv->gart_info.gart_table_location =
1458 DRM_ATI_GART_MAIN;
1459 dev_priv->gart_info.addr = NULL;
1460 dev_priv->gart_info.bus_addr = 0;
1461 if (dev_priv->flags & RADEON_IS_PCIE) {
1462 DRM_ERROR
1463 ("Cannot use PCI Express without GART in FB memory\n");
1464 radeon_do_cleanup_cp(dev);
1465 return -EINVAL;
1466 }
1467 }
1468
1469 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1470 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1471 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1472 ret = r600_page_table_init(dev);
1473 else
1474 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1475 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1476
1477 if (!ret) {
1478 DRM_ERROR("failed to init PCI GART!\n");
1479 radeon_do_cleanup_cp(dev);
1480 return -ENOMEM;
1481 }
1482
1483 ret = radeon_setup_pcigart_surface(dev_priv);
1484 if (ret) {
1485 DRM_ERROR("failed to setup GART surface!\n");
1486 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1487 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1488 else
1489 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1490 radeon_do_cleanup_cp(dev);
1491 return ret;
1492 }
1493
1494 /* Turn on PCI GART */
1495 radeon_set_pcigart(dev_priv, 1);
1496 }
1497
1498 radeon_cp_load_microcode(dev_priv);
1499 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1500
1501 dev_priv->last_buf = 0;
1502
1503 radeon_do_engine_reset(dev);
1504 radeon_test_writeback(dev_priv);
1505
1506 return 0;
1507 }
1508
1509 static int radeon_do_cleanup_cp(struct drm_device * dev)
1510 {
1511 drm_radeon_private_t *dev_priv = dev->dev_private;
1512 DRM_DEBUG("\n");
1513
1514 /* Make sure interrupts are disabled here because the uninstall ioctl
1515 * may not have been called from userspace and after dev_private
1516 * is freed, it's too late.
1517 */
1518 if (dev->irq_enabled)
1519 drm_irq_uninstall(dev);
1520
1521 #if __OS_HAS_AGP
1522 if (dev_priv->flags & RADEON_IS_AGP) {
1523 if (dev_priv->cp_ring != NULL) {
1524 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1525 dev_priv->cp_ring = NULL;
1526 }
1527 if (dev_priv->ring_rptr != NULL) {
1528 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1529 dev_priv->ring_rptr = NULL;
1530 }
1531 if (dev->agp_buffer_map != NULL) {
1532 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1533 dev->agp_buffer_map = NULL;
1534 }
1535 } else
1536 #endif
1537 {
1538
1539 if (dev_priv->gart_info.bus_addr) {
1540 /* Turn off PCI GART */
1541 radeon_set_pcigart(dev_priv, 0);
1542 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1543 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1544 else {
1545 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1546 DRM_ERROR("failed to cleanup PCI GART!\n");
1547 }
1548 }
1549
1550 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1551 {
1552 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1553 dev_priv->gart_info.addr = NULL;
1554 }
1555 }
1556 /* only clear to the start of flags */
1557 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1558
1559 return 0;
1560 }
1561
1562 /* This code will reinit the Radeon CP hardware after a resume from disc.
1563 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1564 * here we make sure that all Radeon hardware initialisation is re-done without
1565 * affecting running applications.
1566 *
1567 * Charl P. Botha <http://cpbotha.net>
1568 */
1569 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1570 {
1571 drm_radeon_private_t *dev_priv = dev->dev_private;
1572
1573 if (!dev_priv) {
1574 DRM_ERROR("Called with no initialization\n");
1575 return -EINVAL;
1576 }
1577
1578 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1579
1580 #if __OS_HAS_AGP
1581 if (dev_priv->flags & RADEON_IS_AGP) {
1582 /* Turn off PCI GART */
1583 radeon_set_pcigart(dev_priv, 0);
1584 } else
1585 #endif
1586 {
1587 /* Turn on PCI GART */
1588 radeon_set_pcigart(dev_priv, 1);
1589 }
1590
1591 radeon_cp_load_microcode(dev_priv);
1592 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1593
1594 radeon_do_engine_reset(dev);
1595 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1596
1597 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1598
1599 return 0;
1600 }
1601
1602 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1603 {
1604 drm_radeon_private_t *dev_priv = dev->dev_private;
1605 drm_radeon_init_t *init = data;
1606
1607 LOCK_TEST_WITH_RETURN(dev, file_priv);
1608
1609 if (init->func == RADEON_INIT_R300_CP)
1610 r300_init_reg_flags(dev);
1611
1612 switch (init->func) {
1613 case RADEON_INIT_CP:
1614 case RADEON_INIT_R200_CP:
1615 case RADEON_INIT_R300_CP:
1616 return radeon_do_init_cp(dev, init, file_priv);
1617 case RADEON_INIT_R600_CP:
1618 return r600_do_init_cp(dev, init, file_priv);
1619 case RADEON_CLEANUP_CP:
1620 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1621 return r600_do_cleanup_cp(dev);
1622 else
1623 return radeon_do_cleanup_cp(dev);
1624 }
1625
1626 return -EINVAL;
1627 }
1628
1629 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1630 {
1631 drm_radeon_private_t *dev_priv = dev->dev_private;
1632 DRM_DEBUG("\n");
1633
1634 LOCK_TEST_WITH_RETURN(dev, file_priv);
1635
1636 if (dev_priv->cp_running) {
1637 DRM_DEBUG("while CP running\n");
1638 return 0;
1639 }
1640 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1641 DRM_DEBUG("called with bogus CP mode (%d)\n",
1642 dev_priv->cp_mode);
1643 return 0;
1644 }
1645
1646 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1647 r600_do_cp_start(dev_priv);
1648 else
1649 radeon_do_cp_start(dev_priv);
1650
1651 return 0;
1652 }
1653
1654 /* Stop the CP. The engine must have been idled before calling this
1655 * routine.
1656 */
1657 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1658 {
1659 drm_radeon_private_t *dev_priv = dev->dev_private;
1660 drm_radeon_cp_stop_t *stop = data;
1661 int ret;
1662 DRM_DEBUG("\n");
1663
1664 LOCK_TEST_WITH_RETURN(dev, file_priv);
1665
1666 if (!dev_priv->cp_running)
1667 return 0;
1668
1669 /* Flush any pending CP commands. This ensures any outstanding
1670 * commands are exectuted by the engine before we turn it off.
1671 */
1672 if (stop->flush) {
1673 radeon_do_cp_flush(dev_priv);
1674 }
1675
1676 /* If we fail to make the engine go idle, we return an error
1677 * code so that the DRM ioctl wrapper can try again.
1678 */
1679 if (stop->idle) {
1680 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1681 ret = r600_do_cp_idle(dev_priv);
1682 else
1683 ret = radeon_do_cp_idle(dev_priv);
1684 if (ret)
1685 return ret;
1686 }
1687
1688 /* Finally, we can turn off the CP. If the engine isn't idle,
1689 * we will get some dropped triangles as they won't be fully
1690 * rendered before the CP is shut down.
1691 */
1692 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1693 r600_do_cp_stop(dev_priv);
1694 else
1695 radeon_do_cp_stop(dev_priv);
1696
1697 /* Reset the engine */
1698 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1699 r600_do_engine_reset(dev);
1700 else
1701 radeon_do_engine_reset(dev);
1702
1703 return 0;
1704 }
1705
1706 void radeon_do_release(struct drm_device * dev)
1707 {
1708 drm_radeon_private_t *dev_priv = dev->dev_private;
1709 int i, ret;
1710
1711 if (dev_priv) {
1712 if (dev_priv->cp_running) {
1713 /* Stop the cp */
1714 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1715 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1716 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1717 #ifdef __linux__
1718 schedule();
1719 #else
1720 tsleep(&ret, PZERO, "rdnrel", 1);
1721 #endif
1722 }
1723 } else {
1724 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1725 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1726 #ifdef __linux__
1727 schedule();
1728 #else
1729 tsleep(&ret, PZERO, "rdnrel", 1);
1730 #endif
1731 }
1732 }
1733 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1734 r600_do_cp_stop(dev_priv);
1735 r600_do_engine_reset(dev);
1736 } else {
1737 radeon_do_cp_stop(dev_priv);
1738 radeon_do_engine_reset(dev);
1739 }
1740 }
1741
1742 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1743 /* Disable *all* interrupts */
1744 if (dev_priv->mmio) /* remove this after permanent addmaps */
1745 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1746
1747 if (dev_priv->mmio) { /* remove all surfaces */
1748 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1749 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1750 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1751 16 * i, 0);
1752 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1753 16 * i, 0);
1754 }
1755 }
1756 }
1757
1758 /* Free memory heap structures */
1759 radeon_mem_takedown(&(dev_priv->gart_heap));
1760 radeon_mem_takedown(&(dev_priv->fb_heap));
1761
1762 /* deallocate kernel resources */
1763 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1764 r600_do_cleanup_cp(dev);
1765 else
1766 radeon_do_cleanup_cp(dev);
1767 }
1768 }
1769
1770 /* Just reset the CP ring. Called as part of an X Server engine reset.
1771 */
1772 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1773 {
1774 drm_radeon_private_t *dev_priv = dev->dev_private;
1775 DRM_DEBUG("\n");
1776
1777 LOCK_TEST_WITH_RETURN(dev, file_priv);
1778
1779 if (!dev_priv) {
1780 DRM_DEBUG("called before init done\n");
1781 return -EINVAL;
1782 }
1783
1784 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1785 r600_do_cp_reset(dev_priv);
1786 else
1787 radeon_do_cp_reset(dev_priv);
1788
1789 /* The CP is no longer running after an engine reset */
1790 dev_priv->cp_running = 0;
1791
1792 return 0;
1793 }
1794
1795 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1796 {
1797 drm_radeon_private_t *dev_priv = dev->dev_private;
1798 DRM_DEBUG("\n");
1799
1800 LOCK_TEST_WITH_RETURN(dev, file_priv);
1801
1802 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1803 return r600_do_cp_idle(dev_priv);
1804 else
1805 return radeon_do_cp_idle(dev_priv);
1806 }
1807
1808 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1809 */
1810 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1811 {
1812 drm_radeon_private_t *dev_priv = dev->dev_private;
1813 DRM_DEBUG("\n");
1814
1815 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1816 return r600_do_resume_cp(dev, file_priv);
1817 else
1818 return radeon_do_resume_cp(dev, file_priv);
1819 }
1820
1821 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1822 {
1823 drm_radeon_private_t *dev_priv = dev->dev_private;
1824 DRM_DEBUG("\n");
1825
1826 LOCK_TEST_WITH_RETURN(dev, file_priv);
1827
1828 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1829 return r600_do_engine_reset(dev);
1830 else
1831 return radeon_do_engine_reset(dev);
1832 }
1833
1834 /* ================================================================
1835 * Fullscreen mode
1836 */
1837
1838 /* KW: Deprecated to say the least:
1839 */
1840 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1841 {
1842 return 0;
1843 }
1844
1845 /* ================================================================
1846 * Freelist management
1847 */
1848
1849 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1850 * bufs until freelist code is used. Note this hides a problem with
1851 * the scratch register * (used to keep track of last buffer
1852 * completed) being written to before * the last buffer has actually
1853 * completed rendering.
1854 *
1855 * KW: It's also a good way to find free buffers quickly.
1856 *
1857 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1858 * sleep. However, bugs in older versions of radeon_accel.c mean that
1859 * we essentially have to do this, else old clients will break.
1860 *
1861 * However, it does leave open a potential deadlock where all the
1862 * buffers are held by other clients, which can't release them because
1863 * they can't get the lock.
1864 */
1865
1866 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1867 {
1868 struct drm_device_dma *dma = dev->dma;
1869 drm_radeon_private_t *dev_priv = dev->dev_private;
1870 drm_radeon_buf_priv_t *buf_priv;
1871 struct drm_buf *buf;
1872 int i, t;
1873 int start;
1874
1875 if (++dev_priv->last_buf >= dma->buf_count)
1876 dev_priv->last_buf = 0;
1877
1878 start = dev_priv->last_buf;
1879
1880 for (t = 0; t < dev_priv->usec_timeout; t++) {
1881 u32 done_age = GET_SCRATCH(dev_priv, 1);
1882 DRM_DEBUG("done_age = %d\n", done_age);
1883 for (i = start; i < dma->buf_count; i++) {
1884 buf = dma->buflist[i];
1885 buf_priv = buf->dev_private;
1886 if (buf->file_priv == NULL || (buf->pending &&
1887 buf_priv->age <=
1888 done_age)) {
1889 dev_priv->stats.requested_bufs++;
1890 buf->pending = 0;
1891 return buf;
1892 }
1893 start = 0;
1894 }
1895
1896 if (t) {
1897 DRM_UDELAY(1);
1898 dev_priv->stats.freelist_loops++;
1899 }
1900 }
1901
1902 DRM_DEBUG("returning NULL!\n");
1903 return NULL;
1904 }
1905
1906 #if 0
1907 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1908 {
1909 struct drm_device_dma *dma = dev->dma;
1910 drm_radeon_private_t *dev_priv = dev->dev_private;
1911 drm_radeon_buf_priv_t *buf_priv;
1912 struct drm_buf *buf;
1913 int i, t;
1914 int start;
1915 u32 done_age;
1916
1917 done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1918 if (++dev_priv->last_buf >= dma->buf_count)
1919 dev_priv->last_buf = 0;
1920
1921 start = dev_priv->last_buf;
1922 dev_priv->stats.freelist_loops++;
1923
1924 for (t = 0; t < 2; t++) {
1925 for (i = start; i < dma->buf_count; i++) {
1926 buf = dma->buflist[i];
1927 buf_priv = buf->dev_private;
1928 if (buf->file_priv == 0 || (buf->pending &&
1929 buf_priv->age <=
1930 done_age)) {
1931 dev_priv->stats.requested_bufs++;
1932 buf->pending = 0;
1933 return buf;
1934 }
1935 }
1936 start = 0;
1937 }
1938
1939 return NULL;
1940 }
1941 #endif
1942
1943 void radeon_freelist_reset(struct drm_device * dev)
1944 {
1945 struct drm_device_dma *dma = dev->dma;
1946 drm_radeon_private_t *dev_priv = dev->dev_private;
1947 int i;
1948
1949 dev_priv->last_buf = 0;
1950 for (i = 0; i < dma->buf_count; i++) {
1951 struct drm_buf *buf = dma->buflist[i];
1952 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1953 buf_priv->age = 0;
1954 }
1955 }
1956
1957 /* ================================================================
1958 * CP command submission
1959 */
1960
1961 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1962 {
1963 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1964 int i;
1965 u32 last_head = GET_RING_HEAD(dev_priv);
1966
1967 for (i = 0; i < dev_priv->usec_timeout; i++) {
1968 u32 head = GET_RING_HEAD(dev_priv);
1969
1970 ring->space = (head - ring->tail) * sizeof(u32);
1971 if (ring->space <= 0)
1972 ring->space += ring->size;
1973 if (ring->space > n)
1974 return 0;
1975
1976 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1977
1978 if (head != last_head)
1979 i = 0;
1980 last_head = head;
1981
1982 DRM_UDELAY(1);
1983 }
1984
1985 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1986 #if RADEON_FIFO_DEBUG
1987 radeon_status(dev_priv);
1988 DRM_ERROR("failed!\n");
1989 #endif
1990 return -EBUSY;
1991 }
1992
1993 static int radeon_cp_get_buffers(struct drm_device *dev,
1994 struct drm_file *file_priv,
1995 struct drm_dma * d)
1996 {
1997 int i;
1998 struct drm_buf *buf;
1999
2000 for (i = d->granted_count; i < d->request_count; i++) {
2001 buf = radeon_freelist_get(dev);
2002 if (!buf)
2003 return -EBUSY; /* NOTE: broken client */
2004
2005 buf->file_priv = file_priv;
2006
2007 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2008 sizeof(buf->idx)))
2009 return -EFAULT;
2010 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2011 sizeof(buf->total)))
2012 return -EFAULT;
2013
2014 d->granted_count++;
2015 }
2016 return 0;
2017 }
2018
2019 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2020 {
2021 struct drm_device_dma *dma = dev->dma;
2022 int ret = 0;
2023 struct drm_dma *d = data;
2024
2025 LOCK_TEST_WITH_RETURN(dev, file_priv);
2026
2027 /* Please don't send us buffers.
2028 */
2029 if (d->send_count != 0) {
2030 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2031 DRM_CURRENTPID, d->send_count);
2032 return -EINVAL;
2033 }
2034
2035 /* We'll send you buffers.
2036 */
2037 if (d->request_count < 0 || d->request_count > dma->buf_count) {
2038 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2039 DRM_CURRENTPID, d->request_count, dma->buf_count);
2040 return -EINVAL;
2041 }
2042
2043 d->granted_count = 0;
2044
2045 if (d->request_count) {
2046 ret = radeon_cp_get_buffers(dev, file_priv, d);
2047 }
2048
2049 return ret;
2050 }
2051
2052 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2053 {
2054 drm_radeon_private_t *dev_priv;
2055 int ret = 0;
2056
2057 dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
2058 if (dev_priv == NULL)
2059 return -ENOMEM;
2060
2061 dev->dev_private = (void *)dev_priv;
2062 dev_priv->flags = flags;
2063
2064 switch (flags & RADEON_FAMILY_MASK) {
2065 case CHIP_R100:
2066 case CHIP_RV200:
2067 case CHIP_R200:
2068 case CHIP_R300:
2069 case CHIP_R350:
2070 case CHIP_R420:
2071 case CHIP_R423:
2072 case CHIP_RV410:
2073 case CHIP_RV515:
2074 case CHIP_R520:
2075 case CHIP_RV570:
2076 case CHIP_R580:
2077 dev_priv->flags |= RADEON_HAS_HIERZ;
2078 break;
2079 default:
2080 /* all other chips have no hierarchical z buffer */
2081 break;
2082 }
2083
2084 if (drm_device_is_agp(dev))
2085 dev_priv->flags |= RADEON_IS_AGP;
2086 else if (drm_device_is_pcie(dev))
2087 dev_priv->flags |= RADEON_IS_PCIE;
2088 else
2089 dev_priv->flags |= RADEON_IS_PCI;
2090
2091 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2092 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2093 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2094 if (ret != 0)
2095 return ret;
2096
2097 ret = drm_vblank_init(dev, 2);
2098 if (ret) {
2099 radeon_driver_unload(dev);
2100 return ret;
2101 }
2102
2103 DRM_DEBUG("%s card detected\n",
2104 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2105 return ret;
2106 }
2107
2108 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2109 {
2110 struct drm_radeon_master_private *master_priv;
2111 unsigned long sareapage;
2112 int ret;
2113
2114 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
2115 if (!master_priv)
2116 return -ENOMEM;
2117
2118 /* prebuild the SAREA */
2119 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2120 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2121 &master_priv->sarea);
2122 if (ret) {
2123 DRM_ERROR("SAREA setup failed\n");
2124 return ret;
2125 }
2126 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2127 master_priv->sarea_priv->pfCurrentPage = 0;
2128
2129 master->driver_priv = master_priv;
2130 return 0;
2131 }
2132
2133 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2134 {
2135 struct drm_radeon_master_private *master_priv = master->driver_priv;
2136
2137 if (!master_priv)
2138 return;
2139
2140 if (master_priv->sarea_priv &&
2141 master_priv->sarea_priv->pfCurrentPage != 0)
2142 radeon_cp_dispatch_flip(dev, master);
2143
2144 master_priv->sarea_priv = NULL;
2145 if (master_priv->sarea)
2146 drm_rmmap_locked(dev, master_priv->sarea);
2147
2148 kfree(master_priv);
2149
2150 master->driver_priv = NULL;
2151 }
2152
2153 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2154 * have to find them.
2155 */
2156 int radeon_driver_firstopen(struct drm_device *dev)
2157 {
2158 int ret;
2159 drm_local_map_t *map;
2160 drm_radeon_private_t *dev_priv = dev->dev_private;
2161
2162 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2163
2164 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2165 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2166 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2167 _DRM_WRITE_COMBINING, &map);
2168 if (ret != 0)
2169 return ret;
2170
2171 return 0;
2172 }
2173
2174 int radeon_driver_unload(struct drm_device *dev)
2175 {
2176 drm_radeon_private_t *dev_priv = dev->dev_private;
2177
2178 DRM_DEBUG("\n");
2179
2180 drm_rmmap(dev, dev_priv->mmio);
2181
2182 kfree(dev_priv);
2183
2184 dev->dev_private = NULL;
2185 return 0;
2186 }
2187
2188 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2189 {
2190 int i;
2191 u32 *ring;
2192 int tail_aligned;
2193
2194 /* check if the ring is padded out to 16-dword alignment */
2195
2196 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2197 if (tail_aligned) {
2198 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2199
2200 ring = dev_priv->ring.start;
2201 /* pad with some CP_PACKET2 */
2202 for (i = 0; i < num_p2; i++)
2203 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2204
2205 dev_priv->ring.tail += i;
2206
2207 dev_priv->ring.space -= num_p2 * sizeof(u32);
2208 }
2209
2210 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2211
2212 DRM_MEMORYBARRIER();
2213 GET_RING_HEAD( dev_priv );
2214
2215 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2216 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2217 /* read from PCI bus to ensure correct posting */
2218 RADEON_READ(R600_CP_RB_RPTR);
2219 } else {
2220 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2221 /* read from PCI bus to ensure correct posting */
2222 RADEON_READ(RADEON_CP_RB_RPTR);
2223 }
2224 }
Linux kernel - Deliverables
This page took 0.181255 seconds and 5 git commands to generate.