1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
34 #include "drm_sarea.h"
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
39 #include "radeon_microcode.h"
41 #define RADEON_FIFO_DEBUG 0
43 static int radeon_do_cleanup_cp(struct drm_device
* dev
);
44 static void radeon_do_cp_start(drm_radeon_private_t
* dev_priv
);
46 u32
radeon_read_ring_rptr(drm_radeon_private_t
*dev_priv
, u32 off
)
50 if (dev_priv
->flags
& RADEON_IS_AGP
) {
51 val
= DRM_READ32(dev_priv
->ring_rptr
, off
);
53 val
= *(((volatile u32
*)
54 dev_priv
->ring_rptr
->handle
) +
56 val
= le32_to_cpu(val
);
61 u32
radeon_get_ring_head(drm_radeon_private_t
*dev_priv
)
63 if (dev_priv
->writeback_works
)
64 return radeon_read_ring_rptr(dev_priv
, 0);
66 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
67 return RADEON_READ(R600_CP_RB_RPTR
);
69 return RADEON_READ(RADEON_CP_RB_RPTR
);
73 void radeon_write_ring_rptr(drm_radeon_private_t
*dev_priv
, u32 off
, u32 val
)
75 if (dev_priv
->flags
& RADEON_IS_AGP
)
76 DRM_WRITE32(dev_priv
->ring_rptr
, off
, val
);
78 *(((volatile u32
*) dev_priv
->ring_rptr
->handle
) +
79 (off
/ sizeof(u32
))) = cpu_to_le32(val
);
82 void radeon_set_ring_head(drm_radeon_private_t
*dev_priv
, u32 val
)
84 radeon_write_ring_rptr(dev_priv
, 0, val
);
87 u32
radeon_get_scratch(drm_radeon_private_t
*dev_priv
, int index
)
89 if (dev_priv
->writeback_works
) {
90 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
91 return radeon_read_ring_rptr(dev_priv
,
92 R600_SCRATCHOFF(index
));
94 return radeon_read_ring_rptr(dev_priv
,
95 RADEON_SCRATCHOFF(index
));
97 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
98 return RADEON_READ(R600_SCRATCH_REG0
+ 4*index
);
100 return RADEON_READ(RADEON_SCRATCH_REG0
+ 4*index
);
104 u32
RADEON_READ_MM(drm_radeon_private_t
*dev_priv
, int addr
)
109 ret
= DRM_READ32(dev_priv
->mmio
, addr
);
111 DRM_WRITE32(dev_priv
->mmio
, RADEON_MM_INDEX
, addr
);
112 ret
= DRM_READ32(dev_priv
->mmio
, RADEON_MM_DATA
);
118 static u32
R500_READ_MCIND(drm_radeon_private_t
*dev_priv
, int addr
)
121 RADEON_WRITE(R520_MC_IND_INDEX
, 0x7f0000 | (addr
& 0xff));
122 ret
= RADEON_READ(R520_MC_IND_DATA
);
123 RADEON_WRITE(R520_MC_IND_INDEX
, 0);
127 static u32
RS480_READ_MCIND(drm_radeon_private_t
*dev_priv
, int addr
)
130 RADEON_WRITE(RS480_NB_MC_INDEX
, addr
& 0xff);
131 ret
= RADEON_READ(RS480_NB_MC_DATA
);
132 RADEON_WRITE(RS480_NB_MC_INDEX
, 0xff);
136 static u32
RS690_READ_MCIND(drm_radeon_private_t
*dev_priv
, int addr
)
139 RADEON_WRITE(RS690_MC_INDEX
, (addr
& RS690_MC_INDEX_MASK
));
140 ret
= RADEON_READ(RS690_MC_DATA
);
141 RADEON_WRITE(RS690_MC_INDEX
, RS690_MC_INDEX_MASK
);
145 static u32
RS600_READ_MCIND(drm_radeon_private_t
*dev_priv
, int addr
)
148 RADEON_WRITE(RS600_MC_INDEX
, ((addr
& RS600_MC_ADDR_MASK
) |
149 RS600_MC_IND_CITF_ARB0
));
150 ret
= RADEON_READ(RS600_MC_DATA
);
154 static u32
IGP_READ_MCIND(drm_radeon_private_t
*dev_priv
, int addr
)
156 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
157 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
))
158 return RS690_READ_MCIND(dev_priv
, addr
);
159 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS600
)
160 return RS600_READ_MCIND(dev_priv
, addr
);
162 return RS480_READ_MCIND(dev_priv
, addr
);
165 u32
radeon_read_fb_location(drm_radeon_private_t
*dev_priv
)
168 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
)
169 return RADEON_READ(R700_MC_VM_FB_LOCATION
);
170 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
171 return RADEON_READ(R600_MC_VM_FB_LOCATION
);
172 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV515
)
173 return R500_READ_MCIND(dev_priv
, RV515_MC_FB_LOCATION
);
174 else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
175 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
))
176 return RS690_READ_MCIND(dev_priv
, RS690_MC_FB_LOCATION
);
177 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS600
)
178 return RS600_READ_MCIND(dev_priv
, RS600_MC_FB_LOCATION
);
179 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) > CHIP_RV515
)
180 return R500_READ_MCIND(dev_priv
, R520_MC_FB_LOCATION
);
182 return RADEON_READ(RADEON_MC_FB_LOCATION
);
185 static void radeon_write_fb_location(drm_radeon_private_t
*dev_priv
, u32 fb_loc
)
187 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
)
188 RADEON_WRITE(R700_MC_VM_FB_LOCATION
, fb_loc
);
189 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
190 RADEON_WRITE(R600_MC_VM_FB_LOCATION
, fb_loc
);
191 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV515
)
192 R500_WRITE_MCIND(RV515_MC_FB_LOCATION
, fb_loc
);
193 else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
194 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
))
195 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION
, fb_loc
);
196 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS600
)
197 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION
, fb_loc
);
198 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) > CHIP_RV515
)
199 R500_WRITE_MCIND(R520_MC_FB_LOCATION
, fb_loc
);
201 RADEON_WRITE(RADEON_MC_FB_LOCATION
, fb_loc
);
204 void radeon_write_agp_location(drm_radeon_private_t
*dev_priv
, u32 agp_loc
)
206 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
207 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
) {
208 RADEON_WRITE(R700_MC_VM_AGP_BOT
, agp_loc
& 0xffff); /* FIX ME */
209 RADEON_WRITE(R700_MC_VM_AGP_TOP
, (agp_loc
>> 16) & 0xffff);
210 } else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
) {
211 RADEON_WRITE(R600_MC_VM_AGP_BOT
, agp_loc
& 0xffff); /* FIX ME */
212 RADEON_WRITE(R600_MC_VM_AGP_TOP
, (agp_loc
>> 16) & 0xffff);
213 } else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV515
)
214 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION
, agp_loc
);
215 else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
216 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
))
217 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION
, agp_loc
);
218 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS600
)
219 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION
, agp_loc
);
220 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) > CHIP_RV515
)
221 R500_WRITE_MCIND(R520_MC_AGP_LOCATION
, agp_loc
);
223 RADEON_WRITE(RADEON_MC_AGP_LOCATION
, agp_loc
);
226 void radeon_write_agp_base(drm_radeon_private_t
*dev_priv
, u64 agp_base
)
228 u32 agp_base_hi
= upper_32_bits(agp_base
);
229 u32 agp_base_lo
= agp_base
& 0xffffffff;
230 u32 r6xx_agp_base
= (agp_base
>> 22) & 0x3ffff;
232 /* R6xx/R7xx must be aligned to a 4MB boundry */
233 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
)
234 RADEON_WRITE(R700_MC_VM_AGP_BASE
, r6xx_agp_base
);
235 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
236 RADEON_WRITE(R600_MC_VM_AGP_BASE
, r6xx_agp_base
);
237 else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV515
) {
238 R500_WRITE_MCIND(RV515_MC_AGP_BASE
, agp_base_lo
);
239 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2
, agp_base_hi
);
240 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
241 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
)) {
242 RS690_WRITE_MCIND(RS690_MC_AGP_BASE
, agp_base_lo
);
243 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2
, agp_base_hi
);
244 } else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS600
) {
245 RS600_WRITE_MCIND(RS600_AGP_BASE
, agp_base_lo
);
246 RS600_WRITE_MCIND(RS600_AGP_BASE_2
, agp_base_hi
);
247 } else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) > CHIP_RV515
) {
248 R500_WRITE_MCIND(R520_MC_AGP_BASE
, agp_base_lo
);
249 R500_WRITE_MCIND(R520_MC_AGP_BASE_2
, agp_base_hi
);
250 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS400
) ||
251 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS480
)) {
252 RADEON_WRITE(RADEON_AGP_BASE
, agp_base_lo
);
253 RADEON_WRITE(RS480_AGP_BASE_2
, agp_base_hi
);
255 RADEON_WRITE(RADEON_AGP_BASE
, agp_base_lo
);
256 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R200
)
257 RADEON_WRITE(RADEON_AGP_BASE_2
, agp_base_hi
);
261 void radeon_enable_bm(struct drm_radeon_private
*dev_priv
)
264 /* Turn on bus mastering */
265 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
266 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
)) {
267 /* rs600/rs690/rs740 */
268 tmp
= RADEON_READ(RADEON_BUS_CNTL
) & ~RS600_BUS_MASTER_DIS
;
269 RADEON_WRITE(RADEON_BUS_CNTL
, tmp
);
270 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) <= CHIP_RV350
) ||
271 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R420
) ||
272 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS400
) ||
273 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS480
)) {
274 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
275 tmp
= RADEON_READ(RADEON_BUS_CNTL
) & ~RADEON_BUS_MASTER_DIS
;
276 RADEON_WRITE(RADEON_BUS_CNTL
, tmp
);
277 } /* PCIE cards appears to not need this */
280 static int RADEON_READ_PLL(struct drm_device
* dev
, int addr
)
282 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
284 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX
, addr
& 0x1f);
285 return RADEON_READ(RADEON_CLOCK_CNTL_DATA
);
288 static u32
RADEON_READ_PCIE(drm_radeon_private_t
*dev_priv
, int addr
)
290 RADEON_WRITE8(RADEON_PCIE_INDEX
, addr
& 0xff);
291 return RADEON_READ(RADEON_PCIE_DATA
);
294 #if RADEON_FIFO_DEBUG
295 static void radeon_status(drm_radeon_private_t
* dev_priv
)
297 printk("%s:\n", __func__
);
298 printk("RBBM_STATUS = 0x%08x\n",
299 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS
));
300 printk("CP_RB_RTPR = 0x%08x\n",
301 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR
));
302 printk("CP_RB_WTPR = 0x%08x\n",
303 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR
));
304 printk("AIC_CNTL = 0x%08x\n",
305 (unsigned int)RADEON_READ(RADEON_AIC_CNTL
));
306 printk("AIC_STAT = 0x%08x\n",
307 (unsigned int)RADEON_READ(RADEON_AIC_STAT
));
308 printk("AIC_PT_BASE = 0x%08x\n",
309 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE
));
310 printk("TLB_ADDR = 0x%08x\n",
311 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR
));
312 printk("TLB_DATA = 0x%08x\n",
313 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA
));
317 /* ================================================================
318 * Engine, FIFO control
321 static int radeon_do_pixcache_flush(drm_radeon_private_t
* dev_priv
)
326 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
328 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) <= CHIP_RV280
) {
329 tmp
= RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT
);
330 tmp
|= RADEON_RB3D_DC_FLUSH_ALL
;
331 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT
, tmp
);
333 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
334 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT
)
335 & RADEON_RB3D_DC_BUSY
)) {
341 /* don't flush or purge cache here or lockup */
345 #if RADEON_FIFO_DEBUG
346 DRM_ERROR("failed!\n");
347 radeon_status(dev_priv
);
352 static int radeon_do_wait_for_fifo(drm_radeon_private_t
* dev_priv
, int entries
)
356 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
358 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
359 int slots
= (RADEON_READ(RADEON_RBBM_STATUS
)
360 & RADEON_RBBM_FIFOCNT_MASK
);
361 if (slots
>= entries
)
365 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
366 RADEON_READ(RADEON_RBBM_STATUS
),
367 RADEON_READ(R300_VAP_CNTL_STATUS
));
369 #if RADEON_FIFO_DEBUG
370 DRM_ERROR("failed!\n");
371 radeon_status(dev_priv
);
376 static int radeon_do_wait_for_idle(drm_radeon_private_t
* dev_priv
)
380 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
382 ret
= radeon_do_wait_for_fifo(dev_priv
, 64);
386 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
387 if (!(RADEON_READ(RADEON_RBBM_STATUS
)
388 & RADEON_RBBM_ACTIVE
)) {
389 radeon_do_pixcache_flush(dev_priv
);
394 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
395 RADEON_READ(RADEON_RBBM_STATUS
),
396 RADEON_READ(R300_VAP_CNTL_STATUS
));
398 #if RADEON_FIFO_DEBUG
399 DRM_ERROR("failed!\n");
400 radeon_status(dev_priv
);
405 static void radeon_init_pipes(drm_radeon_private_t
*dev_priv
)
407 uint32_t gb_tile_config
, gb_pipe_sel
= 0;
409 /* RS4xx/RS6xx/R4xx/R5xx */
410 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R420
) {
411 gb_pipe_sel
= RADEON_READ(R400_GB_PIPE_SELECT
);
412 dev_priv
->num_gb_pipes
= ((gb_pipe_sel
>> 12) & 0x3) + 1;
415 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R300
) ||
416 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R350
)) {
417 dev_priv
->num_gb_pipes
= 2;
420 dev_priv
->num_gb_pipes
= 1;
423 DRM_INFO("Num pipes: %d\n", dev_priv
->num_gb_pipes
);
425 gb_tile_config
= (R300_ENABLE_TILING
| R300_TILE_SIZE_16
/*| R300_SUBPIXEL_1_16*/);
427 switch (dev_priv
->num_gb_pipes
) {
428 case 2: gb_tile_config
|= R300_PIPE_COUNT_R300
; break;
429 case 3: gb_tile_config
|= R300_PIPE_COUNT_R420_3P
; break;
430 case 4: gb_tile_config
|= R300_PIPE_COUNT_R420
; break;
432 case 1: gb_tile_config
|= R300_PIPE_COUNT_RV350
; break;
435 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV515
) {
436 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE
, (1 | ((gb_pipe_sel
>> 8) & 0xf) << 4));
437 RADEON_WRITE(R300_SU_REG_DEST
, ((1 << dev_priv
->num_gb_pipes
) - 1));
439 RADEON_WRITE(R300_GB_TILE_CONFIG
, gb_tile_config
);
440 radeon_do_wait_for_idle(dev_priv
);
441 RADEON_WRITE(R300_DST_PIPE_CONFIG
, RADEON_READ(R300_DST_PIPE_CONFIG
) | R300_PIPE_AUTO_CONFIG
);
442 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE
, (RADEON_READ(R300_RB2D_DSTCACHE_MODE
) |
443 R300_DC_AUTOFLUSH_ENABLE
|
444 R300_DC_DC_DISABLE_IGNORE_PE
));
449 /* ================================================================
450 * CP control, initialization
453 /* Load the microcode for the CP */
454 static void radeon_cp_load_microcode(drm_radeon_private_t
* dev_priv
)
459 radeon_do_wait_for_idle(dev_priv
);
461 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR
, 0);
462 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R100
) ||
463 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV100
) ||
464 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV200
) ||
465 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS100
) ||
466 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS200
)) {
467 DRM_INFO("Loading R100 Microcode\n");
468 for (i
= 0; i
< 256; i
++) {
469 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
470 R100_cp_microcode
[i
][1]);
471 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
472 R100_cp_microcode
[i
][0]);
474 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R200
) ||
475 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV250
) ||
476 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV280
) ||
477 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS300
)) {
478 DRM_INFO("Loading R200 Microcode\n");
479 for (i
= 0; i
< 256; i
++) {
480 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
481 R200_cp_microcode
[i
][1]);
482 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
483 R200_cp_microcode
[i
][0]);
485 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R300
) ||
486 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R350
) ||
487 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV350
) ||
488 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV380
) ||
489 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS400
) ||
490 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS480
)) {
491 DRM_INFO("Loading R300 Microcode\n");
492 for (i
= 0; i
< 256; i
++) {
493 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
494 R300_cp_microcode
[i
][1]);
495 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
496 R300_cp_microcode
[i
][0]);
498 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R420
) ||
499 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R423
) ||
500 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV410
)) {
501 DRM_INFO("Loading R400 Microcode\n");
502 for (i
= 0; i
< 256; i
++) {
503 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
504 R420_cp_microcode
[i
][1]);
505 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
506 R420_cp_microcode
[i
][0]);
508 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
509 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
)) {
510 DRM_INFO("Loading RS690/RS740 Microcode\n");
511 for (i
= 0; i
< 256; i
++) {
512 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
513 RS690_cp_microcode
[i
][1]);
514 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
515 RS690_cp_microcode
[i
][0]);
517 } else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS600
) {
518 DRM_INFO("Loading RS600 Microcode\n");
519 for (i
= 0; i
< 256; i
++) {
520 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
521 RS600_cp_microcode
[i
][1]);
522 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
523 RS600_cp_microcode
[i
][0]);
525 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV515
) ||
526 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R520
) ||
527 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV530
) ||
528 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R580
) ||
529 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV560
) ||
530 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV570
)) {
531 DRM_INFO("Loading R500 Microcode\n");
532 for (i
= 0; i
< 256; i
++) {
533 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
534 R520_cp_microcode
[i
][1]);
535 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
536 R520_cp_microcode
[i
][0]);
541 /* Flush any pending commands to the CP. This should only be used just
542 * prior to a wait for idle, as it informs the engine that the command
545 static void radeon_do_cp_flush(drm_radeon_private_t
* dev_priv
)
551 tmp
= RADEON_READ(RADEON_CP_RB_WPTR
) | (1 << 31);
552 RADEON_WRITE(RADEON_CP_RB_WPTR
, tmp
);
556 /* Wait for the CP to go idle.
558 int radeon_do_cp_idle(drm_radeon_private_t
* dev_priv
)
565 RADEON_PURGE_CACHE();
566 RADEON_PURGE_ZCACHE();
567 RADEON_WAIT_UNTIL_IDLE();
572 return radeon_do_wait_for_idle(dev_priv
);
575 /* Start the Command Processor.
577 static void radeon_do_cp_start(drm_radeon_private_t
* dev_priv
)
582 radeon_do_wait_for_idle(dev_priv
);
584 RADEON_WRITE(RADEON_CP_CSQ_CNTL
, dev_priv
->cp_mode
);
586 dev_priv
->cp_running
= 1;
589 /* isync can only be written through cp on r5xx write it here */
590 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL
, 0));
591 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D
|
592 RADEON_ISYNC_ANY3D_IDLE2D
|
593 RADEON_ISYNC_WAIT_IDLEGUI
|
594 RADEON_ISYNC_CPSCRATCH_IDLEGUI
);
595 RADEON_PURGE_CACHE();
596 RADEON_PURGE_ZCACHE();
597 RADEON_WAIT_UNTIL_IDLE();
601 dev_priv
->track_flush
|= RADEON_FLUSH_EMITED
| RADEON_PURGE_EMITED
;
604 /* Reset the Command Processor. This will not flush any pending
605 * commands, so you must wait for the CP command stream to complete
606 * before calling this routine.
608 static void radeon_do_cp_reset(drm_radeon_private_t
* dev_priv
)
613 cur_read_ptr
= RADEON_READ(RADEON_CP_RB_RPTR
);
614 RADEON_WRITE(RADEON_CP_RB_WPTR
, cur_read_ptr
);
615 SET_RING_HEAD(dev_priv
, cur_read_ptr
);
616 dev_priv
->ring
.tail
= cur_read_ptr
;
619 /* Stop the Command Processor. This will not flush any pending
620 * commands, so you must flush the command stream and wait for the CP
621 * to go idle before calling this routine.
623 static void radeon_do_cp_stop(drm_radeon_private_t
* dev_priv
)
627 RADEON_WRITE(RADEON_CP_CSQ_CNTL
, RADEON_CSQ_PRIDIS_INDDIS
);
629 dev_priv
->cp_running
= 0;
632 /* Reset the engine. This will stop the CP if it is running.
634 static int radeon_do_engine_reset(struct drm_device
* dev
)
636 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
637 u32 clock_cntl_index
= 0, mclk_cntl
= 0, rbbm_soft_reset
;
640 radeon_do_pixcache_flush(dev_priv
);
642 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) <= CHIP_RV410
) {
643 /* may need something similar for newer chips */
644 clock_cntl_index
= RADEON_READ(RADEON_CLOCK_CNTL_INDEX
);
645 mclk_cntl
= RADEON_READ_PLL(dev
, RADEON_MCLK_CNTL
);
647 RADEON_WRITE_PLL(RADEON_MCLK_CNTL
, (mclk_cntl
|
648 RADEON_FORCEON_MCLKA
|
649 RADEON_FORCEON_MCLKB
|
650 RADEON_FORCEON_YCLKA
|
651 RADEON_FORCEON_YCLKB
|
653 RADEON_FORCEON_AIC
));
656 rbbm_soft_reset
= RADEON_READ(RADEON_RBBM_SOFT_RESET
);
658 RADEON_WRITE(RADEON_RBBM_SOFT_RESET
, (rbbm_soft_reset
|
659 RADEON_SOFT_RESET_CP
|
660 RADEON_SOFT_RESET_HI
|
661 RADEON_SOFT_RESET_SE
|
662 RADEON_SOFT_RESET_RE
|
663 RADEON_SOFT_RESET_PP
|
664 RADEON_SOFT_RESET_E2
|
665 RADEON_SOFT_RESET_RB
));
666 RADEON_READ(RADEON_RBBM_SOFT_RESET
);
667 RADEON_WRITE(RADEON_RBBM_SOFT_RESET
, (rbbm_soft_reset
&
668 ~(RADEON_SOFT_RESET_CP
|
669 RADEON_SOFT_RESET_HI
|
670 RADEON_SOFT_RESET_SE
|
671 RADEON_SOFT_RESET_RE
|
672 RADEON_SOFT_RESET_PP
|
673 RADEON_SOFT_RESET_E2
|
674 RADEON_SOFT_RESET_RB
)));
675 RADEON_READ(RADEON_RBBM_SOFT_RESET
);
677 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) <= CHIP_RV410
) {
678 RADEON_WRITE_PLL(RADEON_MCLK_CNTL
, mclk_cntl
);
679 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX
, clock_cntl_index
);
680 RADEON_WRITE(RADEON_RBBM_SOFT_RESET
, rbbm_soft_reset
);
683 /* setup the raster pipes */
684 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R300
)
685 radeon_init_pipes(dev_priv
);
687 /* Reset the CP ring */
688 radeon_do_cp_reset(dev_priv
);
690 /* The CP is no longer running after an engine reset */
691 dev_priv
->cp_running
= 0;
693 /* Reset any pending vertex, indirect buffers */
694 radeon_freelist_reset(dev
);
699 static void radeon_cp_init_ring_buffer(struct drm_device
* dev
,
700 drm_radeon_private_t
*dev_priv
,
701 struct drm_file
*file_priv
)
703 struct drm_radeon_master_private
*master_priv
;
704 u32 ring_start
, cur_read_ptr
;
706 /* Initialize the memory controller. With new memory map, the fb location
707 * is not changed, it should have been properly initialized already. Part
708 * of the problem is that the code below is bogus, assuming the GART is
709 * always appended to the fb which is not necessarily the case
711 if (!dev_priv
->new_memmap
)
712 radeon_write_fb_location(dev_priv
,
713 ((dev_priv
->gart_vm_start
- 1) & 0xffff0000)
714 | (dev_priv
->fb_location
>> 16));
717 if (dev_priv
->flags
& RADEON_IS_AGP
) {
718 radeon_write_agp_base(dev_priv
, dev
->agp
->base
);
720 radeon_write_agp_location(dev_priv
,
721 (((dev_priv
->gart_vm_start
- 1 +
722 dev_priv
->gart_size
) & 0xffff0000) |
723 (dev_priv
->gart_vm_start
>> 16)));
725 ring_start
= (dev_priv
->cp_ring
->offset
727 + dev_priv
->gart_vm_start
);
730 ring_start
= (dev_priv
->cp_ring
->offset
731 - (unsigned long)dev
->sg
->virtual
732 + dev_priv
->gart_vm_start
);
734 RADEON_WRITE(RADEON_CP_RB_BASE
, ring_start
);
736 /* Set the write pointer delay */
737 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY
, 0);
739 /* Initialize the ring buffer's read and write pointers */
740 cur_read_ptr
= RADEON_READ(RADEON_CP_RB_RPTR
);
741 RADEON_WRITE(RADEON_CP_RB_WPTR
, cur_read_ptr
);
742 SET_RING_HEAD(dev_priv
, cur_read_ptr
);
743 dev_priv
->ring
.tail
= cur_read_ptr
;
746 if (dev_priv
->flags
& RADEON_IS_AGP
) {
747 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR
,
748 dev_priv
->ring_rptr
->offset
749 - dev
->agp
->base
+ dev_priv
->gart_vm_start
);
753 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR
,
754 dev_priv
->ring_rptr
->offset
755 - ((unsigned long) dev
->sg
->virtual)
756 + dev_priv
->gart_vm_start
);
759 /* Set ring buffer size */
761 RADEON_WRITE(RADEON_CP_RB_CNTL
,
762 RADEON_BUF_SWAP_32BIT
|
763 (dev_priv
->ring
.fetch_size_l2ow
<< 18) |
764 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
765 dev_priv
->ring
.size_l2qw
);
767 RADEON_WRITE(RADEON_CP_RB_CNTL
,
768 (dev_priv
->ring
.fetch_size_l2ow
<< 18) |
769 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
770 dev_priv
->ring
.size_l2qw
);
774 /* Initialize the scratch register pointer. This will cause
775 * the scratch register values to be written out to memory
776 * whenever they are updated.
778 * We simply put this behind the ring read pointer, this works
779 * with PCI GART as well as (whatever kind of) AGP GART
781 RADEON_WRITE(RADEON_SCRATCH_ADDR
, RADEON_READ(RADEON_CP_RB_RPTR_ADDR
)
782 + RADEON_SCRATCH_REG_OFFSET
);
784 RADEON_WRITE(RADEON_SCRATCH_UMSK
, 0x7);
786 radeon_enable_bm(dev_priv
);
788 radeon_write_ring_rptr(dev_priv
, RADEON_SCRATCHOFF(0), 0);
789 RADEON_WRITE(RADEON_LAST_FRAME_REG
, 0);
791 radeon_write_ring_rptr(dev_priv
, RADEON_SCRATCHOFF(1), 0);
792 RADEON_WRITE(RADEON_LAST_DISPATCH_REG
, 0);
794 radeon_write_ring_rptr(dev_priv
, RADEON_SCRATCHOFF(2), 0);
795 RADEON_WRITE(RADEON_LAST_CLEAR_REG
, 0);
797 /* reset sarea copies of these */
798 master_priv
= file_priv
->master
->driver_priv
;
799 if (master_priv
->sarea_priv
) {
800 master_priv
->sarea_priv
->last_frame
= 0;
801 master_priv
->sarea_priv
->last_dispatch
= 0;
802 master_priv
->sarea_priv
->last_clear
= 0;
805 radeon_do_wait_for_idle(dev_priv
);
807 /* Sync everything up */
808 RADEON_WRITE(RADEON_ISYNC_CNTL
,
809 (RADEON_ISYNC_ANY2D_IDLE3D
|
810 RADEON_ISYNC_ANY3D_IDLE2D
|
811 RADEON_ISYNC_WAIT_IDLEGUI
|
812 RADEON_ISYNC_CPSCRATCH_IDLEGUI
));
816 static void radeon_test_writeback(drm_radeon_private_t
* dev_priv
)
820 /* Start with assuming that writeback doesn't work */
821 dev_priv
->writeback_works
= 0;
823 /* Writeback doesn't seem to work everywhere, test it here and possibly
824 * enable it if it appears to work
826 radeon_write_ring_rptr(dev_priv
, RADEON_SCRATCHOFF(1), 0);
828 RADEON_WRITE(RADEON_SCRATCH_REG1
, 0xdeadbeef);
830 for (tmp
= 0; tmp
< dev_priv
->usec_timeout
; tmp
++) {
833 val
= radeon_read_ring_rptr(dev_priv
, RADEON_SCRATCHOFF(1));
834 if (val
== 0xdeadbeef)
839 if (tmp
< dev_priv
->usec_timeout
) {
840 dev_priv
->writeback_works
= 1;
841 DRM_INFO("writeback test succeeded in %d usecs\n", tmp
);
843 dev_priv
->writeback_works
= 0;
844 DRM_INFO("writeback test failed\n");
846 if (radeon_no_wb
== 1) {
847 dev_priv
->writeback_works
= 0;
848 DRM_INFO("writeback forced off\n");
851 if (!dev_priv
->writeback_works
) {
852 /* Disable writeback to avoid unnecessary bus master transfer */
853 RADEON_WRITE(RADEON_CP_RB_CNTL
, RADEON_READ(RADEON_CP_RB_CNTL
) |
854 RADEON_RB_NO_UPDATE
);
855 RADEON_WRITE(RADEON_SCRATCH_UMSK
, 0);
859 /* Enable or disable IGP GART on the chip */
860 static void radeon_set_igpgart(drm_radeon_private_t
* dev_priv
, int on
)
865 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
866 dev_priv
->gart_vm_start
,
867 (long)dev_priv
->gart_info
.bus_addr
,
868 dev_priv
->gart_size
);
870 temp
= IGP_READ_MCIND(dev_priv
, RS480_MC_MISC_CNTL
);
871 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
872 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
))
873 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL
, (RS480_GART_INDEX_REG_EN
|
874 RS690_BLOCK_GFX_D3_EN
));
876 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL
, RS480_GART_INDEX_REG_EN
);
878 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE
, (RS480_GART_EN
|
879 RS480_VA_SIZE_32MB
));
881 temp
= IGP_READ_MCIND(dev_priv
, RS480_GART_FEATURE_ID
);
882 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID
, (RS480_HANG_EN
|
887 temp
= dev_priv
->gart_info
.bus_addr
& 0xfffff000;
888 temp
|= (upper_32_bits(dev_priv
->gart_info
.bus_addr
) & 0xff) << 4;
889 IGP_WRITE_MCIND(RS480_GART_BASE
, temp
);
891 temp
= IGP_READ_MCIND(dev_priv
, RS480_AGP_MODE_CNTL
);
892 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL
, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT
) |
893 RS480_REQ_TYPE_SNOOP_DIS
));
895 radeon_write_agp_base(dev_priv
, dev_priv
->gart_vm_start
);
897 dev_priv
->gart_size
= 32*1024*1024;
898 temp
= (((dev_priv
->gart_vm_start
- 1 + dev_priv
->gart_size
) &
899 0xffff0000) | (dev_priv
->gart_vm_start
>> 16));
901 radeon_write_agp_location(dev_priv
, temp
);
903 temp
= IGP_READ_MCIND(dev_priv
, RS480_AGP_ADDRESS_SPACE_SIZE
);
904 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE
, (RS480_GART_EN
|
905 RS480_VA_SIZE_32MB
));
908 temp
= IGP_READ_MCIND(dev_priv
, RS480_GART_CACHE_CNTRL
);
909 if ((temp
& RS480_GART_CACHE_INVALIDATE
) == 0)
914 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL
,
915 RS480_GART_CACHE_INVALIDATE
);
918 temp
= IGP_READ_MCIND(dev_priv
, RS480_GART_CACHE_CNTRL
);
919 if ((temp
& RS480_GART_CACHE_INVALIDATE
) == 0)
924 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL
, 0);
926 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE
, 0);
930 /* Enable or disable IGP GART on the chip */
931 static void rs600_set_igpgart(drm_radeon_private_t
*dev_priv
, int on
)
937 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
938 dev_priv
->gart_vm_start
,
939 (long)dev_priv
->gart_info
.bus_addr
,
940 dev_priv
->gart_size
);
942 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL
, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
943 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
945 for (i
= 0; i
< 19; i
++)
946 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL
+ i
,
947 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE
|
948 RS600_SYSTEM_ACCESS_MODE_IN_SYS
|
949 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH
|
950 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
951 RS600_ENABLE_FRAGMENT_PROCESSING
|
952 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
954 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL
, (RS600_ENABLE_PAGE_TABLE
|
955 RS600_PAGE_TABLE_TYPE_FLAT
));
957 /* disable all other contexts */
958 for (i
= 1; i
< 8; i
++)
959 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL
+ i
, 0);
961 /* setup the page table aperture */
962 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR
,
963 dev_priv
->gart_info
.bus_addr
);
964 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR
,
965 dev_priv
->gart_vm_start
);
966 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR
,
967 (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1));
968 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR
, 0);
970 /* setup the system aperture */
971 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR
,
972 dev_priv
->gart_vm_start
);
973 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR
,
974 (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1));
976 /* enable page tables */
977 temp
= IGP_READ_MCIND(dev_priv
, RS600_MC_PT0_CNTL
);
978 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL
, (temp
| RS600_ENABLE_PT
));
980 temp
= IGP_READ_MCIND(dev_priv
, RS600_MC_CNTL1
);
981 IGP_WRITE_MCIND(RS600_MC_CNTL1
, (temp
| RS600_ENABLE_PAGE_TABLES
));
983 /* invalidate the cache */
984 temp
= IGP_READ_MCIND(dev_priv
, RS600_MC_PT0_CNTL
);
986 temp
&= ~(RS600_INVALIDATE_ALL_L1_TLBS
| RS600_INVALIDATE_L2_CACHE
);
987 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL
, temp
);
988 temp
= IGP_READ_MCIND(dev_priv
, RS600_MC_PT0_CNTL
);
990 temp
|= RS600_INVALIDATE_ALL_L1_TLBS
| RS600_INVALIDATE_L2_CACHE
;
991 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL
, temp
);
992 temp
= IGP_READ_MCIND(dev_priv
, RS600_MC_PT0_CNTL
);
994 temp
&= ~(RS600_INVALIDATE_ALL_L1_TLBS
| RS600_INVALIDATE_L2_CACHE
);
995 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL
, temp
);
996 temp
= IGP_READ_MCIND(dev_priv
, RS600_MC_PT0_CNTL
);
999 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL
, 0);
1000 temp
= IGP_READ_MCIND(dev_priv
, RS600_MC_CNTL1
);
1001 temp
&= ~RS600_ENABLE_PAGE_TABLES
;
1002 IGP_WRITE_MCIND(RS600_MC_CNTL1
, temp
);
1006 static void radeon_set_pciegart(drm_radeon_private_t
* dev_priv
, int on
)
1008 u32 tmp
= RADEON_READ_PCIE(dev_priv
, RADEON_PCIE_TX_GART_CNTL
);
1011 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1012 dev_priv
->gart_vm_start
,
1013 (long)dev_priv
->gart_info
.bus_addr
,
1014 dev_priv
->gart_size
);
1015 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO
,
1016 dev_priv
->gart_vm_start
);
1017 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE
,
1018 dev_priv
->gart_info
.bus_addr
);
1019 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO
,
1020 dev_priv
->gart_vm_start
);
1021 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO
,
1022 dev_priv
->gart_vm_start
+
1023 dev_priv
->gart_size
- 1);
1025 radeon_write_agp_location(dev_priv
, 0xffffffc0); /* ?? */
1027 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL
,
1028 RADEON_PCIE_TX_GART_EN
);
1030 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL
,
1031 tmp
& ~RADEON_PCIE_TX_GART_EN
);
1035 /* Enable or disable PCI GART on the chip */
1036 static void radeon_set_pcigart(drm_radeon_private_t
* dev_priv
, int on
)
1040 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS690
) ||
1041 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS740
) ||
1042 (dev_priv
->flags
& RADEON_IS_IGPGART
)) {
1043 radeon_set_igpgart(dev_priv
, on
);
1047 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS600
) {
1048 rs600_set_igpgart(dev_priv
, on
);
1052 if (dev_priv
->flags
& RADEON_IS_PCIE
) {
1053 radeon_set_pciegart(dev_priv
, on
);
1057 tmp
= RADEON_READ(RADEON_AIC_CNTL
);
1060 RADEON_WRITE(RADEON_AIC_CNTL
,
1061 tmp
| RADEON_PCIGART_TRANSLATE_EN
);
1063 /* set PCI GART page-table base address
1065 RADEON_WRITE(RADEON_AIC_PT_BASE
, dev_priv
->gart_info
.bus_addr
);
1067 /* set address range for PCI address translate
1069 RADEON_WRITE(RADEON_AIC_LO_ADDR
, dev_priv
->gart_vm_start
);
1070 RADEON_WRITE(RADEON_AIC_HI_ADDR
, dev_priv
->gart_vm_start
1071 + dev_priv
->gart_size
- 1);
1073 /* Turn off AGP aperture -- is this required for PCI GART?
1075 radeon_write_agp_location(dev_priv
, 0xffffffc0);
1076 RADEON_WRITE(RADEON_AGP_COMMAND
, 0); /* clear AGP_COMMAND */
1078 RADEON_WRITE(RADEON_AIC_CNTL
,
1079 tmp
& ~RADEON_PCIGART_TRANSLATE_EN
);
1083 static int radeon_setup_pcigart_surface(drm_radeon_private_t
*dev_priv
)
1085 struct drm_ati_pcigart_info
*gart_info
= &dev_priv
->gart_info
;
1086 struct radeon_virt_surface
*vp
;
1089 for (i
= 0; i
< RADEON_MAX_SURFACES
* 2; i
++) {
1090 if (!dev_priv
->virt_surfaces
[i
].file_priv
||
1091 dev_priv
->virt_surfaces
[i
].file_priv
== PCIGART_FILE_PRIV
)
1094 if (i
>= 2 * RADEON_MAX_SURFACES
)
1096 vp
= &dev_priv
->virt_surfaces
[i
];
1098 for (i
= 0; i
< RADEON_MAX_SURFACES
; i
++) {
1099 struct radeon_surface
*sp
= &dev_priv
->surfaces
[i
];
1103 vp
->surface_index
= i
;
1104 vp
->lower
= gart_info
->bus_addr
;
1105 vp
->upper
= vp
->lower
+ gart_info
->table_size
;
1107 vp
->file_priv
= PCIGART_FILE_PRIV
;
1110 sp
->lower
= vp
->lower
;
1111 sp
->upper
= vp
->upper
;
1114 RADEON_WRITE(RADEON_SURFACE0_INFO
+ 16 * i
, sp
->flags
);
1115 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND
+ 16 * i
, sp
->lower
);
1116 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND
+ 16 * i
, sp
->upper
);
1123 static int radeon_do_init_cp(struct drm_device
*dev
, drm_radeon_init_t
*init
,
1124 struct drm_file
*file_priv
)
1126 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1127 struct drm_radeon_master_private
*master_priv
= file_priv
->master
->driver_priv
;
1131 /* if we require new memory map but we don't have it fail */
1132 if ((dev_priv
->flags
& RADEON_NEW_MEMMAP
) && !dev_priv
->new_memmap
) {
1133 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1134 radeon_do_cleanup_cp(dev
);
1138 if (init
->is_pci
&& (dev_priv
->flags
& RADEON_IS_AGP
)) {
1139 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1140 dev_priv
->flags
&= ~RADEON_IS_AGP
;
1141 } else if (!(dev_priv
->flags
& (RADEON_IS_AGP
| RADEON_IS_PCI
| RADEON_IS_PCIE
))
1143 DRM_DEBUG("Restoring AGP flag\n");
1144 dev_priv
->flags
|= RADEON_IS_AGP
;
1147 if ((!(dev_priv
->flags
& RADEON_IS_AGP
)) && !dev
->sg
) {
1148 DRM_ERROR("PCI GART memory not allocated!\n");
1149 radeon_do_cleanup_cp(dev
);
1153 dev_priv
->usec_timeout
= init
->usec_timeout
;
1154 if (dev_priv
->usec_timeout
< 1 ||
1155 dev_priv
->usec_timeout
> RADEON_MAX_USEC_TIMEOUT
) {
1156 DRM_DEBUG("TIMEOUT problem!\n");
1157 radeon_do_cleanup_cp(dev
);
1161 /* Enable vblank on CRTC1 for older X servers
1163 dev_priv
->vblank_crtc
= DRM_RADEON_VBLANK_CRTC1
;
1165 switch(init
->func
) {
1166 case RADEON_INIT_R200_CP
:
1167 dev_priv
->microcode_version
= UCODE_R200
;
1169 case RADEON_INIT_R300_CP
:
1170 dev_priv
->microcode_version
= UCODE_R300
;
1173 dev_priv
->microcode_version
= UCODE_R100
;
1176 dev_priv
->do_boxes
= 0;
1177 dev_priv
->cp_mode
= init
->cp_mode
;
1179 /* We don't support anything other than bus-mastering ring mode,
1180 * but the ring can be in either AGP or PCI space for the ring
1183 if ((init
->cp_mode
!= RADEON_CSQ_PRIBM_INDDIS
) &&
1184 (init
->cp_mode
!= RADEON_CSQ_PRIBM_INDBM
)) {
1185 DRM_DEBUG("BAD cp_mode (%x)!\n", init
->cp_mode
);
1186 radeon_do_cleanup_cp(dev
);
1190 switch (init
->fb_bpp
) {
1192 dev_priv
->color_fmt
= RADEON_COLOR_FORMAT_RGB565
;
1196 dev_priv
->color_fmt
= RADEON_COLOR_FORMAT_ARGB8888
;
1199 dev_priv
->front_offset
= init
->front_offset
;
1200 dev_priv
->front_pitch
= init
->front_pitch
;
1201 dev_priv
->back_offset
= init
->back_offset
;
1202 dev_priv
->back_pitch
= init
->back_pitch
;
1204 switch (init
->depth_bpp
) {
1206 dev_priv
->depth_fmt
= RADEON_DEPTH_FORMAT_16BIT_INT_Z
;
1210 dev_priv
->depth_fmt
= RADEON_DEPTH_FORMAT_24BIT_INT_Z
;
1213 dev_priv
->depth_offset
= init
->depth_offset
;
1214 dev_priv
->depth_pitch
= init
->depth_pitch
;
1216 /* Hardware state for depth clears. Remove this if/when we no
1217 * longer clear the depth buffer with a 3D rectangle. Hard-code
1218 * all values to prevent unwanted 3D state from slipping through
1219 * and screwing with the clear operation.
1221 dev_priv
->depth_clear
.rb3d_cntl
= (RADEON_PLANE_MASK_ENABLE
|
1222 (dev_priv
->color_fmt
<< 10) |
1223 (dev_priv
->microcode_version
==
1224 UCODE_R100
? RADEON_ZBLOCK16
: 0));
1226 dev_priv
->depth_clear
.rb3d_zstencilcntl
=
1227 (dev_priv
->depth_fmt
|
1228 RADEON_Z_TEST_ALWAYS
|
1229 RADEON_STENCIL_TEST_ALWAYS
|
1230 RADEON_STENCIL_S_FAIL_REPLACE
|
1231 RADEON_STENCIL_ZPASS_REPLACE
|
1232 RADEON_STENCIL_ZFAIL_REPLACE
| RADEON_Z_WRITE_ENABLE
);
1234 dev_priv
->depth_clear
.se_cntl
= (RADEON_FFACE_CULL_CW
|
1235 RADEON_BFACE_SOLID
|
1236 RADEON_FFACE_SOLID
|
1237 RADEON_FLAT_SHADE_VTX_LAST
|
1238 RADEON_DIFFUSE_SHADE_FLAT
|
1239 RADEON_ALPHA_SHADE_FLAT
|
1240 RADEON_SPECULAR_SHADE_FLAT
|
1241 RADEON_FOG_SHADE_FLAT
|
1242 RADEON_VTX_PIX_CENTER_OGL
|
1243 RADEON_ROUND_MODE_TRUNC
|
1244 RADEON_ROUND_PREC_8TH_PIX
);
1247 dev_priv
->ring_offset
= init
->ring_offset
;
1248 dev_priv
->ring_rptr_offset
= init
->ring_rptr_offset
;
1249 dev_priv
->buffers_offset
= init
->buffers_offset
;
1250 dev_priv
->gart_textures_offset
= init
->gart_textures_offset
;
1252 master_priv
->sarea
= drm_getsarea(dev
);
1253 if (!master_priv
->sarea
) {
1254 DRM_ERROR("could not find sarea!\n");
1255 radeon_do_cleanup_cp(dev
);
1259 dev_priv
->cp_ring
= drm_core_findmap(dev
, init
->ring_offset
);
1260 if (!dev_priv
->cp_ring
) {
1261 DRM_ERROR("could not find cp ring region!\n");
1262 radeon_do_cleanup_cp(dev
);
1265 dev_priv
->ring_rptr
= drm_core_findmap(dev
, init
->ring_rptr_offset
);
1266 if (!dev_priv
->ring_rptr
) {
1267 DRM_ERROR("could not find ring read pointer!\n");
1268 radeon_do_cleanup_cp(dev
);
1271 dev
->agp_buffer_token
= init
->buffers_offset
;
1272 dev
->agp_buffer_map
= drm_core_findmap(dev
, init
->buffers_offset
);
1273 if (!dev
->agp_buffer_map
) {
1274 DRM_ERROR("could not find dma buffer region!\n");
1275 radeon_do_cleanup_cp(dev
);
1279 if (init
->gart_textures_offset
) {
1280 dev_priv
->gart_textures
=
1281 drm_core_findmap(dev
, init
->gart_textures_offset
);
1282 if (!dev_priv
->gart_textures
) {
1283 DRM_ERROR("could not find GART texture region!\n");
1284 radeon_do_cleanup_cp(dev
);
1290 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1291 drm_core_ioremap_wc(dev_priv
->cp_ring
, dev
);
1292 drm_core_ioremap_wc(dev_priv
->ring_rptr
, dev
);
1293 drm_core_ioremap_wc(dev
->agp_buffer_map
, dev
);
1294 if (!dev_priv
->cp_ring
->handle
||
1295 !dev_priv
->ring_rptr
->handle
||
1296 !dev
->agp_buffer_map
->handle
) {
1297 DRM_ERROR("could not find ioremap agp regions!\n");
1298 radeon_do_cleanup_cp(dev
);
1304 dev_priv
->cp_ring
->handle
=
1305 (void *)(unsigned long)dev_priv
->cp_ring
->offset
;
1306 dev_priv
->ring_rptr
->handle
=
1307 (void *)(unsigned long)dev_priv
->ring_rptr
->offset
;
1308 dev
->agp_buffer_map
->handle
=
1309 (void *)(unsigned long)dev
->agp_buffer_map
->offset
;
1311 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1312 dev_priv
->cp_ring
->handle
);
1313 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1314 dev_priv
->ring_rptr
->handle
);
1315 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1316 dev
->agp_buffer_map
->handle
);
1319 dev_priv
->fb_location
= (radeon_read_fb_location(dev_priv
) & 0xffff) << 16;
1321 ((radeon_read_fb_location(dev_priv
) & 0xffff0000u
) + 0x10000)
1322 - dev_priv
->fb_location
;
1324 dev_priv
->front_pitch_offset
= (((dev_priv
->front_pitch
/ 64) << 22) |
1325 ((dev_priv
->front_offset
1326 + dev_priv
->fb_location
) >> 10));
1328 dev_priv
->back_pitch_offset
= (((dev_priv
->back_pitch
/ 64) << 22) |
1329 ((dev_priv
->back_offset
1330 + dev_priv
->fb_location
) >> 10));
1332 dev_priv
->depth_pitch_offset
= (((dev_priv
->depth_pitch
/ 64) << 22) |
1333 ((dev_priv
->depth_offset
1334 + dev_priv
->fb_location
) >> 10));
1336 dev_priv
->gart_size
= init
->gart_size
;
1338 /* New let's set the memory map ... */
1339 if (dev_priv
->new_memmap
) {
1342 DRM_INFO("Setting GART location based on new memory map\n");
1344 /* If using AGP, try to locate the AGP aperture at the same
1345 * location in the card and on the bus, though we have to
1349 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1350 base
= dev
->agp
->base
;
1351 /* Check if valid */
1352 if ((base
+ dev_priv
->gart_size
- 1) >= dev_priv
->fb_location
&&
1353 base
< (dev_priv
->fb_location
+ dev_priv
->fb_size
- 1)) {
1354 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1360 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1362 base
= dev_priv
->fb_location
+ dev_priv
->fb_size
;
1363 if (base
< dev_priv
->fb_location
||
1364 ((base
+ dev_priv
->gart_size
) & 0xfffffffful
) < base
)
1365 base
= dev_priv
->fb_location
1366 - dev_priv
->gart_size
;
1368 dev_priv
->gart_vm_start
= base
& 0xffc00000u
;
1369 if (dev_priv
->gart_vm_start
!= base
)
1370 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1371 base
, dev_priv
->gart_vm_start
);
1373 DRM_INFO("Setting GART location based on old memory map\n");
1374 dev_priv
->gart_vm_start
= dev_priv
->fb_location
+
1375 RADEON_READ(RADEON_CONFIG_APER_SIZE
);
1379 if (dev_priv
->flags
& RADEON_IS_AGP
)
1380 dev_priv
->gart_buffers_offset
= (dev
->agp_buffer_map
->offset
1382 + dev_priv
->gart_vm_start
);
1385 dev_priv
->gart_buffers_offset
= (dev
->agp_buffer_map
->offset
1386 - (unsigned long)dev
->sg
->virtual
1387 + dev_priv
->gart_vm_start
);
1389 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv
->gart_size
);
1390 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv
->gart_vm_start
);
1391 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1392 dev_priv
->gart_buffers_offset
);
1394 dev_priv
->ring
.start
= (u32
*) dev_priv
->cp_ring
->handle
;
1395 dev_priv
->ring
.end
= ((u32
*) dev_priv
->cp_ring
->handle
1396 + init
->ring_size
/ sizeof(u32
));
1397 dev_priv
->ring
.size
= init
->ring_size
;
1398 dev_priv
->ring
.size_l2qw
= drm_order(init
->ring_size
/ 8);
1400 dev_priv
->ring
.rptr_update
= /* init->rptr_update */ 4096;
1401 dev_priv
->ring
.rptr_update_l2qw
= drm_order( /* init->rptr_update */ 4096 / 8);
1403 dev_priv
->ring
.fetch_size
= /* init->fetch_size */ 32;
1404 dev_priv
->ring
.fetch_size_l2ow
= drm_order( /* init->fetch_size */ 32 / 16);
1405 dev_priv
->ring
.tail_mask
= (dev_priv
->ring
.size
/ sizeof(u32
)) - 1;
1407 dev_priv
->ring
.high_mark
= RADEON_RING_HIGH_MARK
;
1410 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1411 /* Turn off PCI GART */
1412 radeon_set_pcigart(dev_priv
, 0);
1419 dev_priv
->gart_info
.table_mask
= DMA_BIT_MASK(32);
1420 /* if we have an offset set from userspace */
1421 if (dev_priv
->pcigart_offset_set
) {
1422 dev_priv
->gart_info
.bus_addr
=
1423 (resource_size_t
)dev_priv
->pcigart_offset
+ dev_priv
->fb_location
;
1424 dev_priv
->gart_info
.mapping
.offset
=
1425 dev_priv
->pcigart_offset
+ dev_priv
->fb_aper_offset
;
1426 dev_priv
->gart_info
.mapping
.size
=
1427 dev_priv
->gart_info
.table_size
;
1429 drm_core_ioremap_wc(&dev_priv
->gart_info
.mapping
, dev
);
1430 dev_priv
->gart_info
.addr
=
1431 dev_priv
->gart_info
.mapping
.handle
;
1433 if (dev_priv
->flags
& RADEON_IS_PCIE
)
1434 dev_priv
->gart_info
.gart_reg_if
= DRM_ATI_GART_PCIE
;
1436 dev_priv
->gart_info
.gart_reg_if
= DRM_ATI_GART_PCI
;
1437 dev_priv
->gart_info
.gart_table_location
=
1440 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1441 dev_priv
->gart_info
.addr
,
1442 dev_priv
->pcigart_offset
);
1444 if (dev_priv
->flags
& RADEON_IS_IGPGART
)
1445 dev_priv
->gart_info
.gart_reg_if
= DRM_ATI_GART_IGP
;
1447 dev_priv
->gart_info
.gart_reg_if
= DRM_ATI_GART_PCI
;
1448 dev_priv
->gart_info
.gart_table_location
=
1450 dev_priv
->gart_info
.addr
= NULL
;
1451 dev_priv
->gart_info
.bus_addr
= 0;
1452 if (dev_priv
->flags
& RADEON_IS_PCIE
) {
1454 ("Cannot use PCI Express without GART in FB memory\n");
1455 radeon_do_cleanup_cp(dev
);
1460 sctrl
= RADEON_READ(RADEON_SURFACE_CNTL
);
1461 RADEON_WRITE(RADEON_SURFACE_CNTL
, 0);
1462 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS600
)
1463 ret
= r600_page_table_init(dev
);
1465 ret
= drm_ati_pcigart_init(dev
, &dev_priv
->gart_info
);
1466 RADEON_WRITE(RADEON_SURFACE_CNTL
, sctrl
);
1469 DRM_ERROR("failed to init PCI GART!\n");
1470 radeon_do_cleanup_cp(dev
);
1474 ret
= radeon_setup_pcigart_surface(dev_priv
);
1476 DRM_ERROR("failed to setup GART surface!\n");
1477 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS600
)
1478 r600_page_table_cleanup(dev
, &dev_priv
->gart_info
);
1480 drm_ati_pcigart_cleanup(dev
, &dev_priv
->gart_info
);
1481 radeon_do_cleanup_cp(dev
);
1485 /* Turn on PCI GART */
1486 radeon_set_pcigart(dev_priv
, 1);
1489 radeon_cp_load_microcode(dev_priv
);
1490 radeon_cp_init_ring_buffer(dev
, dev_priv
, file_priv
);
1492 dev_priv
->last_buf
= 0;
1494 radeon_do_engine_reset(dev
);
1495 radeon_test_writeback(dev_priv
);
1500 static int radeon_do_cleanup_cp(struct drm_device
* dev
)
1502 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1505 /* Make sure interrupts are disabled here because the uninstall ioctl
1506 * may not have been called from userspace and after dev_private
1507 * is freed, it's too late.
1509 if (dev
->irq_enabled
)
1510 drm_irq_uninstall(dev
);
1513 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1514 if (dev_priv
->cp_ring
!= NULL
) {
1515 drm_core_ioremapfree(dev_priv
->cp_ring
, dev
);
1516 dev_priv
->cp_ring
= NULL
;
1518 if (dev_priv
->ring_rptr
!= NULL
) {
1519 drm_core_ioremapfree(dev_priv
->ring_rptr
, dev
);
1520 dev_priv
->ring_rptr
= NULL
;
1522 if (dev
->agp_buffer_map
!= NULL
) {
1523 drm_core_ioremapfree(dev
->agp_buffer_map
, dev
);
1524 dev
->agp_buffer_map
= NULL
;
1530 if (dev_priv
->gart_info
.bus_addr
) {
1531 /* Turn off PCI GART */
1532 radeon_set_pcigart(dev_priv
, 0);
1533 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS600
)
1534 r600_page_table_cleanup(dev
, &dev_priv
->gart_info
);
1536 if (!drm_ati_pcigart_cleanup(dev
, &dev_priv
->gart_info
))
1537 DRM_ERROR("failed to cleanup PCI GART!\n");
1541 if (dev_priv
->gart_info
.gart_table_location
== DRM_ATI_GART_FB
)
1543 drm_core_ioremapfree(&dev_priv
->gart_info
.mapping
, dev
);
1544 dev_priv
->gart_info
.addr
= NULL
;
1547 /* only clear to the start of flags */
1548 memset(dev_priv
, 0, offsetof(drm_radeon_private_t
, flags
));
1553 /* This code will reinit the Radeon CP hardware after a resume from disc.
1554 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1555 * here we make sure that all Radeon hardware initialisation is re-done without
1556 * affecting running applications.
1558 * Charl P. Botha <http://cpbotha.net>
1560 static int radeon_do_resume_cp(struct drm_device
*dev
, struct drm_file
*file_priv
)
1562 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1565 DRM_ERROR("Called with no initialization\n");
1569 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1572 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1573 /* Turn off PCI GART */
1574 radeon_set_pcigart(dev_priv
, 0);
1578 /* Turn on PCI GART */
1579 radeon_set_pcigart(dev_priv
, 1);
1582 radeon_cp_load_microcode(dev_priv
);
1583 radeon_cp_init_ring_buffer(dev
, dev_priv
, file_priv
);
1585 radeon_do_engine_reset(dev
);
1586 radeon_irq_set_state(dev
, RADEON_SW_INT_ENABLE
, 1);
1588 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1593 int radeon_cp_init(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1595 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1596 drm_radeon_init_t
*init
= data
;
1598 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1600 if (init
->func
== RADEON_INIT_R300_CP
)
1601 r300_init_reg_flags(dev
);
1603 switch (init
->func
) {
1604 case RADEON_INIT_CP
:
1605 case RADEON_INIT_R200_CP
:
1606 case RADEON_INIT_R300_CP
:
1607 return radeon_do_init_cp(dev
, init
, file_priv
);
1608 case RADEON_INIT_R600_CP
:
1609 return r600_do_init_cp(dev
, init
, file_priv
);
1610 case RADEON_CLEANUP_CP
:
1611 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
1612 return r600_do_cleanup_cp(dev
);
1614 return radeon_do_cleanup_cp(dev
);
1620 int radeon_cp_start(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1622 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1625 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1627 if (dev_priv
->cp_running
) {
1628 DRM_DEBUG("while CP running\n");
1631 if (dev_priv
->cp_mode
== RADEON_CSQ_PRIDIS_INDDIS
) {
1632 DRM_DEBUG("called with bogus CP mode (%d)\n",
1637 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
1638 r600_do_cp_start(dev_priv
);
1640 radeon_do_cp_start(dev_priv
);
1645 /* Stop the CP. The engine must have been idled before calling this
1648 int radeon_cp_stop(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1650 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1651 drm_radeon_cp_stop_t
*stop
= data
;
1655 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1657 if (!dev_priv
->cp_running
)
1660 /* Flush any pending CP commands. This ensures any outstanding
1661 * commands are exectuted by the engine before we turn it off.
1664 radeon_do_cp_flush(dev_priv
);
1667 /* If we fail to make the engine go idle, we return an error
1668 * code so that the DRM ioctl wrapper can try again.
1671 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
1672 ret
= r600_do_cp_idle(dev_priv
);
1674 ret
= radeon_do_cp_idle(dev_priv
);
1679 /* Finally, we can turn off the CP. If the engine isn't idle,
1680 * we will get some dropped triangles as they won't be fully
1681 * rendered before the CP is shut down.
1683 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
1684 r600_do_cp_stop(dev_priv
);
1686 radeon_do_cp_stop(dev_priv
);
1688 /* Reset the engine */
1689 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
1690 r600_do_engine_reset(dev
);
1692 radeon_do_engine_reset(dev
);
1697 void radeon_do_release(struct drm_device
* dev
)
1699 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1703 if (dev_priv
->cp_running
) {
1705 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
) {
1706 while ((ret
= r600_do_cp_idle(dev_priv
)) != 0) {
1707 DRM_DEBUG("radeon_do_cp_idle %d\n", ret
);
1711 tsleep(&ret
, PZERO
, "rdnrel", 1);
1715 while ((ret
= radeon_do_cp_idle(dev_priv
)) != 0) {
1716 DRM_DEBUG("radeon_do_cp_idle %d\n", ret
);
1720 tsleep(&ret
, PZERO
, "rdnrel", 1);
1724 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
) {
1725 r600_do_cp_stop(dev_priv
);
1726 r600_do_engine_reset(dev
);
1728 radeon_do_cp_stop(dev_priv
);
1729 radeon_do_engine_reset(dev
);
1733 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) < CHIP_R600
) {
1734 /* Disable *all* interrupts */
1735 if (dev_priv
->mmio
) /* remove this after permanent addmaps */
1736 RADEON_WRITE(RADEON_GEN_INT_CNTL
, 0);
1738 if (dev_priv
->mmio
) { /* remove all surfaces */
1739 for (i
= 0; i
< RADEON_MAX_SURFACES
; i
++) {
1740 RADEON_WRITE(RADEON_SURFACE0_INFO
+ 16 * i
, 0);
1741 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND
+
1743 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND
+
1749 /* Free memory heap structures */
1750 radeon_mem_takedown(&(dev_priv
->gart_heap
));
1751 radeon_mem_takedown(&(dev_priv
->fb_heap
));
1753 /* deallocate kernel resources */
1754 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
1755 r600_do_cleanup_cp(dev
);
1757 radeon_do_cleanup_cp(dev
);
1761 /* Just reset the CP ring. Called as part of an X Server engine reset.
1763 int radeon_cp_reset(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1765 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1768 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1771 DRM_DEBUG("called before init done\n");
1775 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
1776 r600_do_cp_reset(dev_priv
);
1778 radeon_do_cp_reset(dev_priv
);
1780 /* The CP is no longer running after an engine reset */
1781 dev_priv
->cp_running
= 0;
1786 int radeon_cp_idle(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1788 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1791 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1793 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
1794 return r600_do_cp_idle(dev_priv
);
1796 return radeon_do_cp_idle(dev_priv
);
1799 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1801 int radeon_cp_resume(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1803 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1806 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
1807 return r600_do_resume_cp(dev
, file_priv
);
1809 return radeon_do_resume_cp(dev
, file_priv
);
1812 int radeon_engine_reset(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1814 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1817 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1819 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
1820 return r600_do_engine_reset(dev
);
1822 return radeon_do_engine_reset(dev
);
1825 /* ================================================================
1829 /* KW: Deprecated to say the least:
1831 int radeon_fullscreen(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1836 /* ================================================================
1837 * Freelist management
1840 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1841 * bufs until freelist code is used. Note this hides a problem with
1842 * the scratch register * (used to keep track of last buffer
1843 * completed) being written to before * the last buffer has actually
1844 * completed rendering.
1846 * KW: It's also a good way to find free buffers quickly.
1848 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1849 * sleep. However, bugs in older versions of radeon_accel.c mean that
1850 * we essentially have to do this, else old clients will break.
1852 * However, it does leave open a potential deadlock where all the
1853 * buffers are held by other clients, which can't release them because
1854 * they can't get the lock.
1857 struct drm_buf
*radeon_freelist_get(struct drm_device
* dev
)
1859 struct drm_device_dma
*dma
= dev
->dma
;
1860 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1861 drm_radeon_buf_priv_t
*buf_priv
;
1862 struct drm_buf
*buf
;
1866 if (++dev_priv
->last_buf
>= dma
->buf_count
)
1867 dev_priv
->last_buf
= 0;
1869 start
= dev_priv
->last_buf
;
1871 for (t
= 0; t
< dev_priv
->usec_timeout
; t
++) {
1872 u32 done_age
= GET_SCRATCH(dev_priv
, 1);
1873 DRM_DEBUG("done_age = %d\n", done_age
);
1874 for (i
= start
; i
< dma
->buf_count
; i
++) {
1875 buf
= dma
->buflist
[i
];
1876 buf_priv
= buf
->dev_private
;
1877 if (buf
->file_priv
== NULL
|| (buf
->pending
&&
1880 dev_priv
->stats
.requested_bufs
++;
1889 dev_priv
->stats
.freelist_loops
++;
1893 DRM_DEBUG("returning NULL!\n");
1898 struct drm_buf
*radeon_freelist_get(struct drm_device
* dev
)
1900 struct drm_device_dma
*dma
= dev
->dma
;
1901 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1902 drm_radeon_buf_priv_t
*buf_priv
;
1903 struct drm_buf
*buf
;
1908 done_age
= radeon_read_ring_rptr(dev_priv
, RADEON_SCRATCHOFF(1));
1909 if (++dev_priv
->last_buf
>= dma
->buf_count
)
1910 dev_priv
->last_buf
= 0;
1912 start
= dev_priv
->last_buf
;
1913 dev_priv
->stats
.freelist_loops
++;
1915 for (t
= 0; t
< 2; t
++) {
1916 for (i
= start
; i
< dma
->buf_count
; i
++) {
1917 buf
= dma
->buflist
[i
];
1918 buf_priv
= buf
->dev_private
;
1919 if (buf
->file_priv
== 0 || (buf
->pending
&&
1922 dev_priv
->stats
.requested_bufs
++;
1934 void radeon_freelist_reset(struct drm_device
* dev
)
1936 struct drm_device_dma
*dma
= dev
->dma
;
1937 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1940 dev_priv
->last_buf
= 0;
1941 for (i
= 0; i
< dma
->buf_count
; i
++) {
1942 struct drm_buf
*buf
= dma
->buflist
[i
];
1943 drm_radeon_buf_priv_t
*buf_priv
= buf
->dev_private
;
1948 /* ================================================================
1949 * CP command submission
1952 int radeon_wait_ring(drm_radeon_private_t
* dev_priv
, int n
)
1954 drm_radeon_ring_buffer_t
*ring
= &dev_priv
->ring
;
1956 u32 last_head
= GET_RING_HEAD(dev_priv
);
1958 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
1959 u32 head
= GET_RING_HEAD(dev_priv
);
1961 ring
->space
= (head
- ring
->tail
) * sizeof(u32
);
1962 if (ring
->space
<= 0)
1963 ring
->space
+= ring
->size
;
1964 if (ring
->space
> n
)
1967 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
1969 if (head
!= last_head
)
1976 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1977 #if RADEON_FIFO_DEBUG
1978 radeon_status(dev_priv
);
1979 DRM_ERROR("failed!\n");
1984 static int radeon_cp_get_buffers(struct drm_device
*dev
,
1985 struct drm_file
*file_priv
,
1989 struct drm_buf
*buf
;
1991 for (i
= d
->granted_count
; i
< d
->request_count
; i
++) {
1992 buf
= radeon_freelist_get(dev
);
1994 return -EBUSY
; /* NOTE: broken client */
1996 buf
->file_priv
= file_priv
;
1998 if (DRM_COPY_TO_USER(&d
->request_indices
[i
], &buf
->idx
,
2001 if (DRM_COPY_TO_USER(&d
->request_sizes
[i
], &buf
->total
,
2002 sizeof(buf
->total
)))
2010 int radeon_cp_buffers(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
2012 struct drm_device_dma
*dma
= dev
->dma
;
2014 struct drm_dma
*d
= data
;
2016 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
2018 /* Please don't send us buffers.
2020 if (d
->send_count
!= 0) {
2021 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2022 DRM_CURRENTPID
, d
->send_count
);
2026 /* We'll send you buffers.
2028 if (d
->request_count
< 0 || d
->request_count
> dma
->buf_count
) {
2029 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2030 DRM_CURRENTPID
, d
->request_count
, dma
->buf_count
);
2034 d
->granted_count
= 0;
2036 if (d
->request_count
) {
2037 ret
= radeon_cp_get_buffers(dev
, file_priv
, d
);
2043 int radeon_driver_load(struct drm_device
*dev
, unsigned long flags
)
2045 drm_radeon_private_t
*dev_priv
;
2048 dev_priv
= drm_alloc(sizeof(drm_radeon_private_t
), DRM_MEM_DRIVER
);
2049 if (dev_priv
== NULL
)
2052 memset(dev_priv
, 0, sizeof(drm_radeon_private_t
));
2053 dev
->dev_private
= (void *)dev_priv
;
2054 dev_priv
->flags
= flags
;
2056 switch (flags
& RADEON_FAMILY_MASK
) {
2069 dev_priv
->flags
|= RADEON_HAS_HIERZ
;
2072 /* all other chips have no hierarchical z buffer */
2076 if (drm_device_is_agp(dev
))
2077 dev_priv
->flags
|= RADEON_IS_AGP
;
2078 else if (drm_device_is_pcie(dev
))
2079 dev_priv
->flags
|= RADEON_IS_PCIE
;
2081 dev_priv
->flags
|= RADEON_IS_PCI
;
2083 ret
= drm_addmap(dev
, drm_get_resource_start(dev
, 2),
2084 drm_get_resource_len(dev
, 2), _DRM_REGISTERS
,
2085 _DRM_READ_ONLY
| _DRM_DRIVER
, &dev_priv
->mmio
);
2089 ret
= drm_vblank_init(dev
, 2);
2091 radeon_driver_unload(dev
);
2095 DRM_DEBUG("%s card detected\n",
2096 ((dev_priv
->flags
& RADEON_IS_AGP
) ? "AGP" : (((dev_priv
->flags
& RADEON_IS_PCIE
) ? "PCIE" : "PCI"))));
2100 int radeon_master_create(struct drm_device
*dev
, struct drm_master
*master
)
2102 struct drm_radeon_master_private
*master_priv
;
2103 unsigned long sareapage
;
2106 master_priv
= drm_calloc(1, sizeof(*master_priv
), DRM_MEM_DRIVER
);
2110 /* prebuild the SAREA */
2111 sareapage
= max_t(unsigned long, SAREA_MAX
, PAGE_SIZE
);
2112 ret
= drm_addmap(dev
, 0, sareapage
, _DRM_SHM
, _DRM_CONTAINS_LOCK
|_DRM_DRIVER
,
2113 &master_priv
->sarea
);
2115 DRM_ERROR("SAREA setup failed\n");
2118 master_priv
->sarea_priv
= master_priv
->sarea
->handle
+ sizeof(struct drm_sarea
);
2119 master_priv
->sarea_priv
->pfCurrentPage
= 0;
2121 master
->driver_priv
= master_priv
;
2125 void radeon_master_destroy(struct drm_device
*dev
, struct drm_master
*master
)
2127 struct drm_radeon_master_private
*master_priv
= master
->driver_priv
;
2132 if (master_priv
->sarea_priv
&&
2133 master_priv
->sarea_priv
->pfCurrentPage
!= 0)
2134 radeon_cp_dispatch_flip(dev
, master
);
2136 master_priv
->sarea_priv
= NULL
;
2137 if (master_priv
->sarea
)
2138 drm_rmmap_locked(dev
, master_priv
->sarea
);
2140 drm_free(master_priv
, sizeof(*master_priv
), DRM_MEM_DRIVER
);
2142 master
->driver_priv
= NULL
;
2145 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2146 * have to find them.
2148 int radeon_driver_firstopen(struct drm_device
*dev
)
2151 drm_local_map_t
*map
;
2152 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2154 dev_priv
->gart_info
.table_size
= RADEON_PCIGART_TABLE_SIZE
;
2156 dev_priv
->fb_aper_offset
= drm_get_resource_start(dev
, 0);
2157 ret
= drm_addmap(dev
, dev_priv
->fb_aper_offset
,
2158 drm_get_resource_len(dev
, 0), _DRM_FRAME_BUFFER
,
2159 _DRM_WRITE_COMBINING
, &map
);
2166 int radeon_driver_unload(struct drm_device
*dev
)
2168 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2172 drm_rmmap(dev
, dev_priv
->mmio
);
2174 drm_free(dev_priv
, sizeof(*dev_priv
), DRM_MEM_DRIVER
);
2176 dev
->dev_private
= NULL
;
2180 void radeon_commit_ring(drm_radeon_private_t
*dev_priv
)
2186 /* check if the ring is padded out to 16-dword alignment */
2188 tail_aligned
= dev_priv
->ring
.tail
& 0xf;
2190 int num_p2
= 16 - tail_aligned
;
2192 ring
= dev_priv
->ring
.start
;
2193 /* pad with some CP_PACKET2 */
2194 for (i
= 0; i
< num_p2
; i
++)
2195 ring
[dev_priv
->ring
.tail
+ i
] = CP_PACKET2();
2197 dev_priv
->ring
.tail
+= i
;
2199 dev_priv
->ring
.space
-= num_p2
* sizeof(u32
);
2202 dev_priv
->ring
.tail
&= dev_priv
->ring
.tail_mask
;
2204 DRM_MEMORYBARRIER();
2205 GET_RING_HEAD( dev_priv
);
2207 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
) {
2208 RADEON_WRITE(R600_CP_RB_WPTR
, dev_priv
->ring
.tail
);
2209 /* read from PCI bus to ensure correct posting */
2210 RADEON_READ(R600_CP_RB_RPTR
);
2212 RADEON_WRITE(RADEON_CP_RB_WPTR
, dev_priv
->ring
.tail
);
2213 /* read from PCI bus to ensure correct posting */
2214 RADEON_READ(RADEON_CP_RB_RPTR
);