drivers/gpu/drm/radeon/radeon_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <glisse@freedesktop.org>
  26  */
  27 #include <linux/list_sort.h>
  28 #include <drm/drmP.h>
  29 #include <drm/radeon_drm.h>
  30 #include "radeon_reg.h"
  31 #include "radeon.h"
  32 #include "radeon_trace.h"
  33
  34 #define RADEON_CS_MAX_PRIORITY          32u
  35 #define RADEON_CS_NUM_BUCKETS           (RADEON_CS_MAX_PRIORITY + 1)
  36
  37 /* This is based on the bucket sort with O(n) time complexity.
  38  * An item with priority "i" is added to bucket[i]. The lists are then
  39  * concatenated in descending order.
  40  */
  41 struct radeon_cs_buckets {
  42         struct list_head bucket[RADEON_CS_NUM_BUCKETS];
  43 };
  44
  45 static void radeon_cs_buckets_init(struct radeon_cs_buckets *b)
  46 {
  47         unsigned i;
  48
  49         for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++)
  50                 INIT_LIST_HEAD(&b->bucket[i]);
  51 }
  52
  53 static void radeon_cs_buckets_add(struct radeon_cs_buckets *b,
  54                                   struct list_head *item, unsigned priority)
  55 {
  56         /* Since buffers which appear sooner in the relocation list are
  57          * likely to be used more often than buffers which appear later
  58          * in the list, the sort mustn't change the ordering of buffers
  59          * with the same priority, i.e. it must be stable.
  60          */
  61         list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]);
  62 }
  63
  64 static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b,
  65                                        struct list_head *out_list)
  66 {
  67         unsigned i;
  68
  69         /* Connect the sorted buckets in the output list. */
  70         for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) {
  71                 list_splice(&b->bucket[i], out_list);
  72         }
  73 }
  74
  75 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
  76 {
  77         struct drm_device *ddev = p->rdev->ddev;
  78         struct radeon_cs_chunk *chunk;
  79         struct radeon_cs_buckets buckets;
  80         unsigned i, j;
  81         bool duplicate;
  82
  83         if (p->chunk_relocs_idx == -1) {
  84                 return 0;
  85         }
  86         chunk = &p->chunks[p->chunk_relocs_idx];
  87         p->dma_reloc_idx = 0;
  88         /* FIXME: we assume that each relocs use 4 dwords */
  89         p->nrelocs = chunk->length_dw / 4;
  90         p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
  91         if (p->relocs_ptr == NULL) {
  92                 return -ENOMEM;
  93         }
  94         p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
  95         if (p->relocs == NULL) {
  96                 return -ENOMEM;
  97         }
  98
  99         radeon_cs_buckets_init(&buckets);
 100
 101         for (i = 0; i < p->nrelocs; i++) {
 102                 struct drm_radeon_cs_reloc *r;
 103                 unsigned priority;
 104
 105                 duplicate = false;
 106                 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
 107                 for (j = 0; j < i; j++) {
 108                         if (r->handle == p->relocs[j].handle) {
 109                                 p->relocs_ptr[i] = &p->relocs[j];
 110                                 duplicate = true;
 111                                 break;
 112                         }
 113                 }
 114                 if (duplicate) {
 115                         p->relocs[i].handle = 0;
 116                         continue;
 117                 }
 118
 119                 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
 120                                                           r->handle);
 121                 if (p->relocs[i].gobj == NULL) {
 122                         DRM_ERROR("gem object lookup failed 0x%x\n",
 123                                   r->handle);
 124                         return -ENOENT;
 125                 }
 126                 p->relocs_ptr[i] = &p->relocs[i];
 127                 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
 128
 129                 /* The userspace buffer priorities are from 0 to 15. A higher
 130                  * number means the buffer is more important.
 131                  * Also, the buffers used for write have a higher priority than
 132                  * the buffers used for read only, which doubles the range
 133                  * to 0 to 31. 32 is reserved for the kernel driver.
 134                  */
 135                 priority = (r->flags & 0xf) * 2 + !!r->write_domain;
 136
 137                 /* the first reloc of an UVD job is the msg and that must be in
 138                    VRAM, also but everything into VRAM on AGP cards to avoid
 139                    image corruptions */
 140                 if (p->ring == R600_RING_TYPE_UVD_INDEX &&
 141                     (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
 142                         /* TODO: is this still needed for NI+ ? */
 143                         p->relocs[i].domain =
 144                                 RADEON_GEM_DOMAIN_VRAM;
 145
 146                         p->relocs[i].alt_domain =
 147                                 RADEON_GEM_DOMAIN_VRAM;
 148
 149                         /* prioritize this over any other relocation */
 150                         priority = RADEON_CS_MAX_PRIORITY;
 151                 } else {
 152                         uint32_t domain = r->write_domain ?
 153                                 r->write_domain : r->read_domains;
 154
 155                         p->relocs[i].domain = domain;
 156                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 157                                 domain |= RADEON_GEM_DOMAIN_GTT;
 158                         p->relocs[i].alt_domain = domain;
 159                 }
 160
 161                 p->relocs[i].tv.bo = &p->relocs[i].robj->tbo;
 162                 p->relocs[i].handle = r->handle;
 163
 164                 radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head,
 165                                       priority);
 166         }
 167
 168         radeon_cs_buckets_get_list(&buckets, &p->validated);
 169
 170         if (p->cs_flags & RADEON_CS_USE_VM)
 171                 p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm,
 172                                               &p->validated);
 173
 174         return radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring);
 175 }
 176
 177 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
 178 {
 179         p->priority = priority;
 180
 181         switch (ring) {
 182         default:
 183                 DRM_ERROR("unknown ring id: %d\n", ring);
 184                 return -EINVAL;
 185         case RADEON_CS_RING_GFX:
 186                 p->ring = RADEON_RING_TYPE_GFX_INDEX;
 187                 break;
 188         case RADEON_CS_RING_COMPUTE:
 189                 if (p->rdev->family >= CHIP_TAHITI) {
 190                         if (p->priority > 0)
 191                                 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
 192                         else
 193                                 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
 194                 } else
 195                         p->ring = RADEON_RING_TYPE_GFX_INDEX;
 196                 break;
 197         case RADEON_CS_RING_DMA:
 198                 if (p->rdev->family >= CHIP_CAYMAN) {
 199                         if (p->priority > 0)
 200                                 p->ring = R600_RING_TYPE_DMA_INDEX;
 201                         else
 202                                 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
 203                 } else if (p->rdev->family >= CHIP_RV770) {
 204                         p->ring = R600_RING_TYPE_DMA_INDEX;
 205                 } else {
 206                         return -EINVAL;
 207                 }
 208                 break;
 209         case RADEON_CS_RING_UVD:
 210                 p->ring = R600_RING_TYPE_UVD_INDEX;
 211                 break;
 212         case RADEON_CS_RING_VCE:
 213                 /* TODO: only use the low priority ring for now */
 214                 p->ring = TN_RING_TYPE_VCE1_INDEX;
 215                 break;
 216         }
 217         return 0;
 218 }
 219
 220 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
 221 {
 222         int i;
 223
 224         for (i = 0; i < p->nrelocs; i++) {
 225                 if (!p->relocs[i].robj)
 226                         continue;
 227
 228                 radeon_semaphore_sync_to(p->ib.semaphore,
 229                                          p->relocs[i].robj->tbo.sync_obj);
 230         }
 231 }
 232
 233 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
 234 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
 235 {
 236         struct drm_radeon_cs *cs = data;
 237         uint64_t *chunk_array_ptr;
 238         unsigned size, i;
 239         u32 ring = RADEON_CS_RING_GFX;
 240         s32 priority = 0;
 241
 242         if (!cs->num_chunks) {
 243                 return 0;
 244         }
 245         /* get chunks */
 246         INIT_LIST_HEAD(&p->validated);
 247         p->idx = 0;
 248         p->ib.sa_bo = NULL;
 249         p->ib.semaphore = NULL;
 250         p->const_ib.sa_bo = NULL;
 251         p->const_ib.semaphore = NULL;
 252         p->chunk_ib_idx = -1;
 253         p->chunk_relocs_idx = -1;
 254         p->chunk_flags_idx = -1;
 255         p->chunk_const_ib_idx = -1;
 256         p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
 257         if (p->chunks_array == NULL) {
 258                 return -ENOMEM;
 259         }
 260         chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
 261         if (copy_from_user(p->chunks_array, chunk_array_ptr,
 262                                sizeof(uint64_t)*cs->num_chunks)) {
 263                 return -EFAULT;
 264         }
 265         p->cs_flags = 0;
 266         p->nchunks = cs->num_chunks;
 267         p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
 268         if (p->chunks == NULL) {
 269                 return -ENOMEM;
 270         }
 271         for (i = 0; i < p->nchunks; i++) {
 272                 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
 273                 struct drm_radeon_cs_chunk user_chunk;
 274                 uint32_t __user *cdata;
 275
 276                 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
 277                 if (copy_from_user(&user_chunk, chunk_ptr,
 278                                        sizeof(struct drm_radeon_cs_chunk))) {
 279                         return -EFAULT;
 280                 }
 281                 p->chunks[i].length_dw = user_chunk.length_dw;
 282                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 283                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
 284                         p->chunk_relocs_idx = i;
 285                 }
 286                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
 287                         p->chunk_ib_idx = i;
 288                         /* zero length IB isn't useful */
 289                         if (p->chunks[i].length_dw == 0)
 290                                 return -EINVAL;
 291                 }
 292                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
 293                         p->chunk_const_ib_idx = i;
 294                         /* zero length CONST IB isn't useful */
 295                         if (p->chunks[i].length_dw == 0)
 296                                 return -EINVAL;
 297                 }
 298                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
 299                         p->chunk_flags_idx = i;
 300                         /* zero length flags aren't useful */
 301                         if (p->chunks[i].length_dw == 0)
 302                                 return -EINVAL;
 303                 }
 304
 305                 size = p->chunks[i].length_dw;
 306                 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
 307                 p->chunks[i].user_ptr = cdata;
 308                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB)
 309                         continue;
 310
 311                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
 312                         if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP))
 313                                 continue;
 314                 }
 315
 316                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 317                 size *= sizeof(uint32_t);
 318                 if (p->chunks[i].kdata == NULL) {
 319                         return -ENOMEM;
 320                 }
 321                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 322                         return -EFAULT;
 323                 }
 324                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
 325                         p->cs_flags = p->chunks[i].kdata[0];
 326                         if (p->chunks[i].length_dw > 1)
 327                                 ring = p->chunks[i].kdata[1];
 328                         if (p->chunks[i].length_dw > 2)
 329                                 priority = (s32)p->chunks[i].kdata[2];
 330                 }
 331         }
 332
 333         /* these are KMS only */
 334         if (p->rdev) {
 335                 if ((p->cs_flags & RADEON_CS_USE_VM) &&
 336                     !p->rdev->vm_manager.enabled) {
 337                         DRM_ERROR("VM not active on asic!\n");
 338                         return -EINVAL;
 339                 }
 340
 341                 if (radeon_cs_get_ring(p, ring, priority))
 342                         return -EINVAL;
 343
 344                 /* we only support VM on some SI+ rings */
 345                 if ((p->rdev->asic->ring[p->ring]->cs_parse == NULL) &&
 346                    ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
 347                         DRM_ERROR("Ring %d requires VM!\n", p->ring);
 348                         return -EINVAL;
 349                 }
 350         }
 351
 352         return 0;
 353 }
 354
 355 static int cmp_size_smaller_first(void *priv, struct list_head *a,
 356                                   struct list_head *b)
 357 {
 358         struct radeon_cs_reloc *la = list_entry(a, struct radeon_cs_reloc, tv.head);
 359         struct radeon_cs_reloc *lb = list_entry(b, struct radeon_cs_reloc, tv.head);
 360
 361         /* Sort A before B if A is smaller. */
 362         return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
 363 }
 364
 365 /**
 366  * cs_parser_fini() - clean parser states
 367  * @parser:     parser structure holding parsing context.
 368  * @error:      error number
 369  *
 370  * If error is set than unvalidate buffer, otherwise just free memory
 371  * used by parsing context.
 372  **/
 373 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff)
 374 {
 375         unsigned i;
 376
 377         if (!error) {
 378                 /* Sort the buffer list from the smallest to largest buffer,
 379                  * which affects the order of buffers in the LRU list.
 380                  * This assures that the smallest buffers are added first
 381                  * to the LRU list, so they are likely to be later evicted
 382                  * first, instead of large buffers whose eviction is more
 383                  * expensive.
 384                  *
 385                  * This slightly lowers the number of bytes moved by TTM
 386                  * per frame under memory pressure.
 387                  */
 388                 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 389
 390                 ttm_eu_fence_buffer_objects(&parser->ticket,
 391                                             &parser->validated,
 392                                             parser->ib.fence);
 393         } else if (backoff) {
 394                 ttm_eu_backoff_reservation(&parser->ticket,
 395                                            &parser->validated);
 396         }
 397
 398         if (parser->relocs != NULL) {
 399                 for (i = 0; i < parser->nrelocs; i++) {
 400                         if (parser->relocs[i].gobj)
 401                                 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
 402                 }
 403         }
 404         kfree(parser->track);
 405         kfree(parser->relocs);
 406         kfree(parser->relocs_ptr);
 407         kfree(parser->vm_bos);
 408         for (i = 0; i < parser->nchunks; i++)
 409                 drm_free_large(parser->chunks[i].kdata);
 410         kfree(parser->chunks);
 411         kfree(parser->chunks_array);
 412         radeon_ib_free(parser->rdev, &parser->ib);
 413         radeon_ib_free(parser->rdev, &parser->const_ib);
 414 }
 415
 416 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
 417                               struct radeon_cs_parser *parser)
 418 {
 419         int r;
 420
 421         if (parser->chunk_ib_idx == -1)
 422                 return 0;
 423
 424         if (parser->cs_flags & RADEON_CS_USE_VM)
 425                 return 0;
 426
 427         r = radeon_cs_parse(rdev, parser->ring, parser);
 428         if (r || parser->parser_error) {
 429                 DRM_ERROR("Invalid command stream !\n");
 430                 return r;
 431         }
 432
 433         if (parser->ring == R600_RING_TYPE_UVD_INDEX)
 434                 radeon_uvd_note_usage(rdev);
 435         else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) ||
 436                  (parser->ring == TN_RING_TYPE_VCE2_INDEX))
 437                 radeon_vce_note_usage(rdev);
 438
 439         radeon_cs_sync_rings(parser);
 440         r = radeon_ib_schedule(rdev, &parser->ib, NULL);
 441         if (r) {
 442                 DRM_ERROR("Failed to schedule IB !\n");
 443         }
 444         return r;
 445 }
 446
 447 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p,
 448                                    struct radeon_vm *vm)
 449 {
 450         struct radeon_device *rdev = p->rdev;
 451         int i, r;
 452
 453         r = radeon_vm_update_page_directory(rdev, vm);
 454         if (r)
 455                 return r;
 456
 457         r = radeon_vm_bo_update(rdev, vm, rdev->ring_tmp_bo.bo,
 458                                 &rdev->ring_tmp_bo.bo->tbo.mem);
 459         if (r)
 460                 return r;
 461
 462         for (i = 0; i < p->nrelocs; i++) {
 463                 struct radeon_bo *bo;
 464
 465                 /* ignore duplicates */
 466                 if (p->relocs_ptr[i] != &p->relocs[i])
 467                         continue;
 468
 469                 bo = p->relocs[i].robj;
 470                 r = radeon_vm_bo_update(rdev, vm, bo, &bo->tbo.mem);
 471                 if (r)
 472                         return r;
 473         }
 474         return 0;
 475 }
 476
 477 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
 478                                  struct radeon_cs_parser *parser)
 479 {
 480         struct radeon_fpriv *fpriv = parser->filp->driver_priv;
 481         struct radeon_vm *vm = &fpriv->vm;
 482         int r;
 483
 484         if (parser->chunk_ib_idx == -1)
 485                 return 0;
 486         if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
 487                 return 0;
 488
 489         if (parser->const_ib.length_dw) {
 490                 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
 491                 if (r) {
 492                         return r;
 493                 }
 494         }
 495
 496         r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
 497         if (r) {
 498                 return r;
 499         }
 500
 501         if (parser->ring == R600_RING_TYPE_UVD_INDEX)
 502                 radeon_uvd_note_usage(rdev);
 503
 504         mutex_lock(&vm->mutex);
 505         r = radeon_bo_vm_update_pte(parser, vm);
 506         if (r) {
 507                 goto out;
 508         }
 509         radeon_cs_sync_rings(parser);
 510         radeon_semaphore_sync_to(parser->ib.semaphore, vm->fence);
 511
 512         if ((rdev->family >= CHIP_TAHITI) &&
 513             (parser->chunk_const_ib_idx != -1)) {
 514                 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
 515         } else {
 516                 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
 517         }
 518
 519 out:
 520         mutex_unlock(&vm->mutex);
 521         return r;
 522 }
 523
 524 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
 525 {
 526         if (r == -EDEADLK) {
 527                 r = radeon_gpu_reset(rdev);
 528                 if (!r)
 529                         r = -EAGAIN;
 530         }
 531         return r;
 532 }
 533
 534 static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser)
 535 {
 536         struct radeon_cs_chunk *ib_chunk;
 537         struct radeon_vm *vm = NULL;
 538         int r;
 539
 540         if (parser->chunk_ib_idx == -1)
 541                 return 0;
 542
 543         if (parser->cs_flags & RADEON_CS_USE_VM) {
 544                 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
 545                 vm = &fpriv->vm;
 546
 547                 if ((rdev->family >= CHIP_TAHITI) &&
 548                     (parser->chunk_const_ib_idx != -1)) {
 549                         ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
 550                         if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
 551                                 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
 552                                 return -EINVAL;
 553                         }
 554                         r =  radeon_ib_get(rdev, parser->ring, &parser->const_ib,
 555                                            vm, ib_chunk->length_dw * 4);
 556                         if (r) {
 557                                 DRM_ERROR("Failed to get const ib !\n");
 558                                 return r;
 559                         }
 560                         parser->const_ib.is_const_ib = true;
 561                         parser->const_ib.length_dw = ib_chunk->length_dw;
 562                         if (copy_from_user(parser->const_ib.ptr,
 563                                                ib_chunk->user_ptr,
 564                                                ib_chunk->length_dw * 4))
 565                                 return -EFAULT;
 566                 }
 567
 568                 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
 569                 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
 570                         DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
 571                         return -EINVAL;
 572                 }
 573         }
 574         ib_chunk = &parser->chunks[parser->chunk_ib_idx];
 575
 576         r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
 577                            vm, ib_chunk->length_dw * 4);
 578         if (r) {
 579                 DRM_ERROR("Failed to get ib !\n");
 580                 return r;
 581         }
 582         parser->ib.length_dw = ib_chunk->length_dw;
 583         if (ib_chunk->kdata)
 584                 memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4);
 585         else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4))
 586                 return -EFAULT;
 587         return 0;
 588 }
 589
 590 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 591 {
 592         struct radeon_device *rdev = dev->dev_private;
 593         struct radeon_cs_parser parser;
 594         int r;
 595
 596         down_read(&rdev->exclusive_lock);
 597         if (!rdev->accel_working) {
 598                 up_read(&rdev->exclusive_lock);
 599                 return -EBUSY;
 600         }
 601         /* initialize parser */
 602         memset(&parser, 0, sizeof(struct radeon_cs_parser));
 603         parser.filp = filp;
 604         parser.rdev = rdev;
 605         parser.dev = rdev->dev;
 606         parser.family = rdev->family;
 607         r = radeon_cs_parser_init(&parser, data);
 608         if (r) {
 609                 DRM_ERROR("Failed to initialize parser !\n");
 610                 radeon_cs_parser_fini(&parser, r, false);
 611                 up_read(&rdev->exclusive_lock);
 612                 r = radeon_cs_handle_lockup(rdev, r);
 613                 return r;
 614         }
 615
 616         r = radeon_cs_ib_fill(rdev, &parser);
 617         if (!r) {
 618                 r = radeon_cs_parser_relocs(&parser);
 619                 if (r && r != -ERESTARTSYS)
 620                         DRM_ERROR("Failed to parse relocation %d!\n", r);
 621         }
 622
 623         if (r) {
 624                 radeon_cs_parser_fini(&parser, r, false);
 625                 up_read(&rdev->exclusive_lock);
 626                 r = radeon_cs_handle_lockup(rdev, r);
 627                 return r;
 628         }
 629
 630         trace_radeon_cs(&parser);
 631
 632         r = radeon_cs_ib_chunk(rdev, &parser);
 633         if (r) {
 634                 goto out;
 635         }
 636         r = radeon_cs_ib_vm_chunk(rdev, &parser);
 637         if (r) {
 638                 goto out;
 639         }
 640 out:
 641         radeon_cs_parser_fini(&parser, r, true);
 642         up_read(&rdev->exclusive_lock);
 643         r = radeon_cs_handle_lockup(rdev, r);
 644         return r;
 645 }
 646
 647 /**
 648  * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
 649  * @parser:     parser structure holding parsing context.
 650  * @pkt:        where to store packet information
 651  *
 652  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 653  * if packet is bigger than remaining ib size. or if packets is unknown.
 654  **/
 655 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
 656                            struct radeon_cs_packet *pkt,
 657                            unsigned idx)
 658 {
 659         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 660         struct radeon_device *rdev = p->rdev;
 661         uint32_t header;
 662
 663         if (idx >= ib_chunk->length_dw) {
 664                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 665                           idx, ib_chunk->length_dw);
 666                 return -EINVAL;
 667         }
 668         header = radeon_get_ib_value(p, idx);
 669         pkt->idx = idx;
 670         pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
 671         pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
 672         pkt->one_reg_wr = 0;
 673         switch (pkt->type) {
 674         case RADEON_PACKET_TYPE0:
 675                 if (rdev->family < CHIP_R600) {
 676                         pkt->reg = R100_CP_PACKET0_GET_REG(header);
 677                         pkt->one_reg_wr =
 678                                 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
 679                 } else
 680                         pkt->reg = R600_CP_PACKET0_GET_REG(header);
 681                 break;
 682         case RADEON_PACKET_TYPE3:
 683                 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
 684                 break;
 685         case RADEON_PACKET_TYPE2:
 686                 pkt->count = -1;
 687                 break;
 688         default:
 689                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 690                 return -EINVAL;
 691         }
 692         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 693                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 694                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 695                 return -EINVAL;
 696         }
 697         return 0;
 698 }
 699
 700 /**
 701  * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
 702  * @p:          structure holding the parser context.
 703  *
 704  * Check if the next packet is NOP relocation packet3.
 705  **/
 706 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
 707 {
 708         struct radeon_cs_packet p3reloc;
 709         int r;
 710
 711         r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
 712         if (r)
 713                 return false;
 714         if (p3reloc.type != RADEON_PACKET_TYPE3)
 715                 return false;
 716         if (p3reloc.opcode != RADEON_PACKET3_NOP)
 717                 return false;
 718         return true;
 719 }
 720
 721 /**
 722  * radeon_cs_dump_packet() - dump raw packet context
 723  * @p:          structure holding the parser context.
 724  * @pkt:        structure holding the packet.
 725  *
 726  * Used mostly for debugging and error reporting.
 727  **/
 728 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
 729                            struct radeon_cs_packet *pkt)
 730 {
 731         volatile uint32_t *ib;
 732         unsigned i;
 733         unsigned idx;
 734
 735         ib = p->ib.ptr;
 736         idx = pkt->idx;
 737         for (i = 0; i <= (pkt->count + 1); i++, idx++)
 738                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 739 }
 740
 741 /**
 742  * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
 743  * @parser:             parser structure holding parsing context.
 744  * @data:               pointer to relocation data
 745  * @offset_start:       starting offset
 746  * @offset_mask:        offset mask (to align start offset on)
 747  * @reloc:              reloc informations
 748  *
 749  * Check if next packet is relocation packet3, do bo validation and compute
 750  * GPU offset using the provided start.
 751  **/
 752 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
 753                                 struct radeon_cs_reloc **cs_reloc,
 754                                 int nomm)
 755 {
 756         struct radeon_cs_chunk *relocs_chunk;
 757         struct radeon_cs_packet p3reloc;
 758         unsigned idx;
 759         int r;
 760
 761         if (p->chunk_relocs_idx == -1) {
 762                 DRM_ERROR("No relocation chunk !\n");
 763                 return -EINVAL;
 764         }
 765         *cs_reloc = NULL;
 766         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 767         r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
 768         if (r)
 769                 return r;
 770         p->idx += p3reloc.count + 2;
 771         if (p3reloc.type != RADEON_PACKET_TYPE3 ||
 772             p3reloc.opcode != RADEON_PACKET3_NOP) {
 773                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 774                           p3reloc.idx);
 775                 radeon_cs_dump_packet(p, &p3reloc);
 776                 return -EINVAL;
 777         }
 778         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 779         if (idx >= relocs_chunk->length_dw) {
 780                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 781                           idx, relocs_chunk->length_dw);
 782                 radeon_cs_dump_packet(p, &p3reloc);
 783                 return -EINVAL;
 784         }
 785         /* FIXME: we assume reloc size is 4 dwords */
 786         if (nomm) {
 787                 *cs_reloc = p->relocs;
 788                 (*cs_reloc)->gpu_offset =
 789                         (u64)relocs_chunk->kdata[idx + 3] << 32;
 790                 (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0];
 791         } else
 792                 *cs_reloc = p->relocs_ptr[(idx / 4)];
 793         return 0;
 794 }