drivers/gpu/drm/radeon/radeon_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <glisse@freedesktop.org>
  26  */
  27 #include <drm/drmP.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31 #include "radeon_trace.h"
  32
  33 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
  34 {
  35         struct drm_device *ddev = p->rdev->ddev;
  36         struct radeon_cs_chunk *chunk;
  37         unsigned i, j;
  38         bool duplicate;
  39
  40         if (p->chunk_relocs_idx == -1) {
  41                 return 0;
  42         }
  43         chunk = &p->chunks[p->chunk_relocs_idx];
  44         p->dma_reloc_idx = 0;
  45         /* FIXME: we assume that each relocs use 4 dwords */
  46         p->nrelocs = chunk->length_dw / 4;
  47         p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
  48         if (p->relocs_ptr == NULL) {
  49                 return -ENOMEM;
  50         }
  51         p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
  52         if (p->relocs == NULL) {
  53                 return -ENOMEM;
  54         }
  55         for (i = 0; i < p->nrelocs; i++) {
  56                 struct drm_radeon_cs_reloc *r;
  57
  58                 duplicate = false;
  59                 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
  60                 for (j = 0; j < i; j++) {
  61                         if (r->handle == p->relocs[j].handle) {
  62                                 p->relocs_ptr[i] = &p->relocs[j];
  63                                 duplicate = true;
  64                                 break;
  65                         }
  66                 }
  67                 if (duplicate) {
  68                         p->relocs[i].handle = 0;
  69                         continue;
  70                 }
  71
  72                 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
  73                                                           r->handle);
  74                 if (p->relocs[i].gobj == NULL) {
  75                         DRM_ERROR("gem object lookup failed 0x%x\n",
  76                                   r->handle);
  77                         return -ENOENT;
  78                 }
  79                 p->relocs_ptr[i] = &p->relocs[i];
  80                 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
  81                 p->relocs[i].lobj.bo = p->relocs[i].robj;
  82                 p->relocs[i].lobj.written = !!r->write_domain;
  83
  84                 /* the first reloc of an UVD job is the msg and that must be in
  85                    VRAM, also but everything into VRAM on AGP cards to avoid
  86                    image corruptions */
  87                 if (p->ring == R600_RING_TYPE_UVD_INDEX &&
  88                     (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
  89                         /* TODO: is this still needed for NI+ ? */
  90                         p->relocs[i].lobj.domain =
  91                                 RADEON_GEM_DOMAIN_VRAM;
  92
  93                         p->relocs[i].lobj.alt_domain =
  94                                 RADEON_GEM_DOMAIN_VRAM;
  95
  96                 } else {
  97                         uint32_t domain = r->write_domain ?
  98                                 r->write_domain : r->read_domains;
  99
 100                         p->relocs[i].lobj.domain = domain;
 101                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 102                                 domain |= RADEON_GEM_DOMAIN_GTT;
 103                         p->relocs[i].lobj.alt_domain = domain;
 104                 }
 105
 106                 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
 107                 p->relocs[i].handle = r->handle;
 108
 109                 radeon_bo_list_add_object(&p->relocs[i].lobj,
 110                                           &p->validated);
 111         }
 112         return radeon_bo_list_validate(&p->ticket, &p->validated, p->ring);
 113 }
 114
 115 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
 116 {
 117         p->priority = priority;
 118
 119         switch (ring) {
 120         default:
 121                 DRM_ERROR("unknown ring id: %d\n", ring);
 122                 return -EINVAL;
 123         case RADEON_CS_RING_GFX:
 124                 p->ring = RADEON_RING_TYPE_GFX_INDEX;
 125                 break;
 126         case RADEON_CS_RING_COMPUTE:
 127                 if (p->rdev->family >= CHIP_TAHITI) {
 128                         if (p->priority > 0)
 129                                 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
 130                         else
 131                                 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
 132                 } else
 133                         p->ring = RADEON_RING_TYPE_GFX_INDEX;
 134                 break;
 135         case RADEON_CS_RING_DMA:
 136                 if (p->rdev->family >= CHIP_CAYMAN) {
 137                         if (p->priority > 0)
 138                                 p->ring = R600_RING_TYPE_DMA_INDEX;
 139                         else
 140                                 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
 141                 } else if (p->rdev->family >= CHIP_R600) {
 142                         p->ring = R600_RING_TYPE_DMA_INDEX;
 143                 } else {
 144                         return -EINVAL;
 145                 }
 146                 break;
 147         case RADEON_CS_RING_UVD:
 148                 p->ring = R600_RING_TYPE_UVD_INDEX;
 149                 break;
 150         }
 151         return 0;
 152 }
 153
 154 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
 155 {
 156         int i;
 157
 158         for (i = 0; i < p->nrelocs; i++) {
 159                 if (!p->relocs[i].robj)
 160                         continue;
 161
 162                 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj);
 163         }
 164 }
 165
 166 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
 167 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
 168 {
 169         struct drm_radeon_cs *cs = data;
 170         uint64_t *chunk_array_ptr;
 171         unsigned size, i;
 172         u32 ring = RADEON_CS_RING_GFX;
 173         s32 priority = 0;
 174
 175         if (!cs->num_chunks) {
 176                 return 0;
 177         }
 178         /* get chunks */
 179         INIT_LIST_HEAD(&p->validated);
 180         p->idx = 0;
 181         p->ib.sa_bo = NULL;
 182         p->ib.semaphore = NULL;
 183         p->const_ib.sa_bo = NULL;
 184         p->const_ib.semaphore = NULL;
 185         p->chunk_ib_idx = -1;
 186         p->chunk_relocs_idx = -1;
 187         p->chunk_flags_idx = -1;
 188         p->chunk_const_ib_idx = -1;
 189         p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
 190         if (p->chunks_array == NULL) {
 191                 return -ENOMEM;
 192         }
 193         chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
 194         if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
 195                                sizeof(uint64_t)*cs->num_chunks)) {
 196                 return -EFAULT;
 197         }
 198         p->cs_flags = 0;
 199         p->nchunks = cs->num_chunks;
 200         p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
 201         if (p->chunks == NULL) {
 202                 return -ENOMEM;
 203         }
 204         for (i = 0; i < p->nchunks; i++) {
 205                 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
 206                 struct drm_radeon_cs_chunk user_chunk;
 207                 uint32_t __user *cdata;
 208
 209                 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
 210                 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
 211                                        sizeof(struct drm_radeon_cs_chunk))) {
 212                         return -EFAULT;
 213                 }
 214                 p->chunks[i].length_dw = user_chunk.length_dw;
 215                 p->chunks[i].kdata = NULL;
 216                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 217                 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
 218                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
 219                         p->chunk_relocs_idx = i;
 220                 }
 221                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
 222                         p->chunk_ib_idx = i;
 223                         /* zero length IB isn't useful */
 224                         if (p->chunks[i].length_dw == 0)
 225                                 return -EINVAL;
 226                 }
 227                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
 228                         p->chunk_const_ib_idx = i;
 229                         /* zero length CONST IB isn't useful */
 230                         if (p->chunks[i].length_dw == 0)
 231                                 return -EINVAL;
 232                 }
 233                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
 234                         p->chunk_flags_idx = i;
 235                         /* zero length flags aren't useful */
 236                         if (p->chunks[i].length_dw == 0)
 237                                 return -EINVAL;
 238                 }
 239
 240                 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
 241                 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
 242                     (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
 243                         size = p->chunks[i].length_dw * sizeof(uint32_t);
 244                         p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
 245                         if (p->chunks[i].kdata == NULL) {
 246                                 return -ENOMEM;
 247                         }
 248                         if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
 249                                                p->chunks[i].user_ptr, size)) {
 250                                 return -EFAULT;
 251                         }
 252                         if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
 253                                 p->cs_flags = p->chunks[i].kdata[0];
 254                                 if (p->chunks[i].length_dw > 1)
 255                                         ring = p->chunks[i].kdata[1];
 256                                 if (p->chunks[i].length_dw > 2)
 257                                         priority = (s32)p->chunks[i].kdata[2];
 258                         }
 259                 }
 260         }
 261
 262         /* these are KMS only */
 263         if (p->rdev) {
 264                 if ((p->cs_flags & RADEON_CS_USE_VM) &&
 265                     !p->rdev->vm_manager.enabled) {
 266                         DRM_ERROR("VM not active on asic!\n");
 267                         return -EINVAL;
 268                 }
 269
 270                 if (radeon_cs_get_ring(p, ring, priority))
 271                         return -EINVAL;
 272
 273                 /* we only support VM on some SI+ rings */
 274                 if ((p->rdev->asic->ring[p->ring]->cs_parse == NULL) &&
 275                    ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
 276                         DRM_ERROR("Ring %d requires VM!\n", p->ring);
 277                         return -EINVAL;
 278                 }
 279         }
 280
 281         /* deal with non-vm */
 282         if ((p->chunk_ib_idx != -1) &&
 283             ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
 284             (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
 285                 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
 286                         DRM_ERROR("cs IB too big: %d\n",
 287                                   p->chunks[p->chunk_ib_idx].length_dw);
 288                         return -EINVAL;
 289                 }
 290                 if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) {
 291                         p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
 292                         p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
 293                         if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
 294                             p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
 295                                 kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
 296                                 kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
 297                                 p->chunks[p->chunk_ib_idx].kpage[0] = NULL;
 298                                 p->chunks[p->chunk_ib_idx].kpage[1] = NULL;
 299                                 return -ENOMEM;
 300                         }
 301                 }
 302                 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
 303                 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
 304                 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
 305                 p->chunks[p->chunk_ib_idx].last_page_index =
 306                         ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
 307         }
 308
 309         return 0;
 310 }
 311
 312 /**
 313  * cs_parser_fini() - clean parser states
 314  * @parser:     parser structure holding parsing context.
 315  * @error:      error number
 316  *
 317  * If error is set than unvalidate buffer, otherwise just free memory
 318  * used by parsing context.
 319  **/
 320 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff)
 321 {
 322         unsigned i;
 323
 324         if (!error) {
 325                 ttm_eu_fence_buffer_objects(&parser->ticket,
 326                                             &parser->validated,
 327                                             parser->ib.fence);
 328         } else if (backoff) {
 329                 ttm_eu_backoff_reservation(&parser->ticket,
 330                                            &parser->validated);
 331         }
 332
 333         if (parser->relocs != NULL) {
 334                 for (i = 0; i < parser->nrelocs; i++) {
 335                         if (parser->relocs[i].gobj)
 336                                 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
 337                 }
 338         }
 339         kfree(parser->track);
 340         kfree(parser->relocs);
 341         kfree(parser->relocs_ptr);
 342         for (i = 0; i < parser->nchunks; i++) {
 343                 kfree(parser->chunks[i].kdata);
 344                 if ((parser->rdev->flags & RADEON_IS_AGP)) {
 345                         kfree(parser->chunks[i].kpage[0]);
 346                         kfree(parser->chunks[i].kpage[1]);
 347                 }
 348         }
 349         kfree(parser->chunks);
 350         kfree(parser->chunks_array);
 351         radeon_ib_free(parser->rdev, &parser->ib);
 352         radeon_ib_free(parser->rdev, &parser->const_ib);
 353 }
 354
 355 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
 356                               struct radeon_cs_parser *parser)
 357 {
 358         struct radeon_cs_chunk *ib_chunk;
 359         int r;
 360
 361         if (parser->chunk_ib_idx == -1)
 362                 return 0;
 363
 364         if (parser->cs_flags & RADEON_CS_USE_VM)
 365                 return 0;
 366
 367         ib_chunk = &parser->chunks[parser->chunk_ib_idx];
 368         /* Copy the packet into the IB, the parser will read from the
 369          * input memory (cached) and write to the IB (which can be
 370          * uncached).
 371          */
 372         r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
 373                            NULL, ib_chunk->length_dw * 4);
 374         if (r) {
 375                 DRM_ERROR("Failed to get ib !\n");
 376                 return r;
 377         }
 378         parser->ib.length_dw = ib_chunk->length_dw;
 379         r = radeon_cs_parse(rdev, parser->ring, parser);
 380         if (r || parser->parser_error) {
 381                 DRM_ERROR("Invalid command stream !\n");
 382                 return r;
 383         }
 384         r = radeon_cs_finish_pages(parser);
 385         if (r) {
 386                 DRM_ERROR("Invalid command stream !\n");
 387                 return r;
 388         }
 389
 390         if (parser->ring == R600_RING_TYPE_UVD_INDEX)
 391                 radeon_uvd_note_usage(rdev);
 392
 393         radeon_cs_sync_rings(parser);
 394         r = radeon_ib_schedule(rdev, &parser->ib, NULL);
 395         if (r) {
 396                 DRM_ERROR("Failed to schedule IB !\n");
 397         }
 398         return r;
 399 }
 400
 401 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
 402                                    struct radeon_vm *vm)
 403 {
 404         struct radeon_device *rdev = parser->rdev;
 405         struct radeon_bo_list *lobj;
 406         struct radeon_bo *bo;
 407         int r;
 408
 409         r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
 410         if (r) {
 411                 return r;
 412         }
 413         list_for_each_entry(lobj, &parser->validated, tv.head) {
 414                 bo = lobj->bo;
 415                 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
 416                 if (r) {
 417                         return r;
 418                 }
 419         }
 420         return 0;
 421 }
 422
 423 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
 424                                  struct radeon_cs_parser *parser)
 425 {
 426         struct radeon_cs_chunk *ib_chunk;
 427         struct radeon_fpriv *fpriv = parser->filp->driver_priv;
 428         struct radeon_vm *vm = &fpriv->vm;
 429         int r;
 430
 431         if (parser->chunk_ib_idx == -1)
 432                 return 0;
 433         if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
 434                 return 0;
 435
 436         if ((rdev->family >= CHIP_TAHITI) &&
 437             (parser->chunk_const_ib_idx != -1)) {
 438                 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
 439                 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
 440                         DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
 441                         return -EINVAL;
 442                 }
 443                 r =  radeon_ib_get(rdev, parser->ring, &parser->const_ib,
 444                                    vm, ib_chunk->length_dw * 4);
 445                 if (r) {
 446                         DRM_ERROR("Failed to get const ib !\n");
 447                         return r;
 448                 }
 449                 parser->const_ib.is_const_ib = true;
 450                 parser->const_ib.length_dw = ib_chunk->length_dw;
 451                 /* Copy the packet into the IB */
 452                 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
 453                                        ib_chunk->length_dw * 4)) {
 454                         return -EFAULT;
 455                 }
 456                 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
 457                 if (r) {
 458                         return r;
 459                 }
 460         }
 461
 462         ib_chunk = &parser->chunks[parser->chunk_ib_idx];
 463         if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
 464                 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
 465                 return -EINVAL;
 466         }
 467         r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
 468                            vm, ib_chunk->length_dw * 4);
 469         if (r) {
 470                 DRM_ERROR("Failed to get ib !\n");
 471                 return r;
 472         }
 473         parser->ib.length_dw = ib_chunk->length_dw;
 474         /* Copy the packet into the IB */
 475         if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
 476                                ib_chunk->length_dw * 4)) {
 477                 return -EFAULT;
 478         }
 479         r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
 480         if (r) {
 481                 return r;
 482         }
 483
 484         if (parser->ring == R600_RING_TYPE_UVD_INDEX)
 485                 radeon_uvd_note_usage(rdev);
 486
 487         mutex_lock(&rdev->vm_manager.lock);
 488         mutex_lock(&vm->mutex);
 489         r = radeon_vm_alloc_pt(rdev, vm);
 490         if (r) {
 491                 goto out;
 492         }
 493         r = radeon_bo_vm_update_pte(parser, vm);
 494         if (r) {
 495                 goto out;
 496         }
 497         radeon_cs_sync_rings(parser);
 498         radeon_ib_sync_to(&parser->ib, vm->fence);
 499         radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id(
 500                 rdev, vm, parser->ring));
 501
 502         if ((rdev->family >= CHIP_TAHITI) &&
 503             (parser->chunk_const_ib_idx != -1)) {
 504                 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
 505         } else {
 506                 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
 507         }
 508
 509         if (!r) {
 510                 radeon_vm_fence(rdev, vm, parser->ib.fence);
 511         }
 512
 513 out:
 514         radeon_vm_add_to_lru(rdev, vm);
 515         mutex_unlock(&vm->mutex);
 516         mutex_unlock(&rdev->vm_manager.lock);
 517         return r;
 518 }
 519
 520 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
 521 {
 522         if (r == -EDEADLK) {
 523                 r = radeon_gpu_reset(rdev);
 524                 if (!r)
 525                         r = -EAGAIN;
 526         }
 527         return r;
 528 }
 529
 530 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 531 {
 532         struct radeon_device *rdev = dev->dev_private;
 533         struct radeon_cs_parser parser;
 534         int r;
 535
 536         down_read(&rdev->exclusive_lock);
 537         if (!rdev->accel_working) {
 538                 up_read(&rdev->exclusive_lock);
 539                 return -EBUSY;
 540         }
 541         /* initialize parser */
 542         memset(&parser, 0, sizeof(struct radeon_cs_parser));
 543         parser.filp = filp;
 544         parser.rdev = rdev;
 545         parser.dev = rdev->dev;
 546         parser.family = rdev->family;
 547         r = radeon_cs_parser_init(&parser, data);
 548         if (r) {
 549                 DRM_ERROR("Failed to initialize parser !\n");
 550                 radeon_cs_parser_fini(&parser, r, false);
 551                 up_read(&rdev->exclusive_lock);
 552                 r = radeon_cs_handle_lockup(rdev, r);
 553                 return r;
 554         }
 555         r = radeon_cs_parser_relocs(&parser);
 556         if (r) {
 557                 if (r != -ERESTARTSYS)
 558                         DRM_ERROR("Failed to parse relocation %d!\n", r);
 559                 radeon_cs_parser_fini(&parser, r, false);
 560                 up_read(&rdev->exclusive_lock);
 561                 r = radeon_cs_handle_lockup(rdev, r);
 562                 return r;
 563         }
 564
 565         trace_radeon_cs(&parser);
 566
 567         r = radeon_cs_ib_chunk(rdev, &parser);
 568         if (r) {
 569                 goto out;
 570         }
 571         r = radeon_cs_ib_vm_chunk(rdev, &parser);
 572         if (r) {
 573                 goto out;
 574         }
 575 out:
 576         radeon_cs_parser_fini(&parser, r, true);
 577         up_read(&rdev->exclusive_lock);
 578         r = radeon_cs_handle_lockup(rdev, r);
 579         return r;
 580 }
 581
 582 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
 583 {
 584         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 585         int i;
 586         int size = PAGE_SIZE;
 587
 588         for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
 589                 if (i == ibc->last_page_index) {
 590                         size = (ibc->length_dw * 4) % PAGE_SIZE;
 591                         if (size == 0)
 592                                 size = PAGE_SIZE;
 593                 }
 594
 595                 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
 596                                        ibc->user_ptr + (i * PAGE_SIZE),
 597                                        size))
 598                         return -EFAULT;
 599         }
 600         return 0;
 601 }
 602
 603 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
 604 {
 605         int new_page;
 606         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 607         int i;
 608         int size = PAGE_SIZE;
 609         bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ?
 610                 false : true;
 611
 612         for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
 613                 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
 614                                        ibc->user_ptr + (i * PAGE_SIZE),
 615                                        PAGE_SIZE)) {
 616                         p->parser_error = -EFAULT;
 617                         return 0;
 618                 }
 619         }
 620
 621         if (pg_idx == ibc->last_page_index) {
 622                 size = (ibc->length_dw * 4) % PAGE_SIZE;
 623                 if (size == 0)
 624                         size = PAGE_SIZE;
 625         }
 626
 627         new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
 628         if (copy1)
 629                 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
 630
 631         if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
 632                                ibc->user_ptr + (pg_idx * PAGE_SIZE),
 633                                size)) {
 634                 p->parser_error = -EFAULT;
 635                 return 0;
 636         }
 637
 638         /* copy to IB for non single case */
 639         if (!copy1)
 640                 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
 641
 642         ibc->last_copied_page = pg_idx;
 643         ibc->kpage_idx[new_page] = pg_idx;
 644
 645         return new_page;
 646 }
 647
 648 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
 649 {
 650         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 651         u32 pg_idx, pg_offset;
 652         u32 idx_value = 0;
 653         int new_page;
 654
 655         pg_idx = (idx * 4) / PAGE_SIZE;
 656         pg_offset = (idx * 4) % PAGE_SIZE;
 657
 658         if (ibc->kpage_idx[0] == pg_idx)
 659                 return ibc->kpage[0][pg_offset/4];
 660         if (ibc->kpage_idx[1] == pg_idx)
 661                 return ibc->kpage[1][pg_offset/4];
 662
 663         new_page = radeon_cs_update_pages(p, pg_idx);
 664         if (new_page < 0) {
 665                 p->parser_error = new_page;
 666                 return 0;
 667         }
 668
 669         idx_value = ibc->kpage[new_page][pg_offset/4];
 670         return idx_value;
 671 }
 672
 673 /**
 674  * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
 675  * @parser:     parser structure holding parsing context.
 676  * @pkt:        where to store packet information
 677  *
 678  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 679  * if packet is bigger than remaining ib size. or if packets is unknown.
 680  **/
 681 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
 682                            struct radeon_cs_packet *pkt,
 683                            unsigned idx)
 684 {
 685         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 686         struct radeon_device *rdev = p->rdev;
 687         uint32_t header;
 688
 689         if (idx >= ib_chunk->length_dw) {
 690                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 691                           idx, ib_chunk->length_dw);
 692                 return -EINVAL;
 693         }
 694         header = radeon_get_ib_value(p, idx);
 695         pkt->idx = idx;
 696         pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
 697         pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
 698         pkt->one_reg_wr = 0;
 699         switch (pkt->type) {
 700         case RADEON_PACKET_TYPE0:
 701                 if (rdev->family < CHIP_R600) {
 702                         pkt->reg = R100_CP_PACKET0_GET_REG(header);
 703                         pkt->one_reg_wr =
 704                                 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
 705                 } else
 706                         pkt->reg = R600_CP_PACKET0_GET_REG(header);
 707                 break;
 708         case RADEON_PACKET_TYPE3:
 709                 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
 710                 break;
 711         case RADEON_PACKET_TYPE2:
 712                 pkt->count = -1;
 713                 break;
 714         default:
 715                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 716                 return -EINVAL;
 717         }
 718         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 719                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 720                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 721                 return -EINVAL;
 722         }
 723         return 0;
 724 }
 725
 726 /**
 727  * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
 728  * @p:          structure holding the parser context.
 729  *
 730  * Check if the next packet is NOP relocation packet3.
 731  **/
 732 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
 733 {
 734         struct radeon_cs_packet p3reloc;
 735         int r;
 736
 737         r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
 738         if (r)
 739                 return false;
 740         if (p3reloc.type != RADEON_PACKET_TYPE3)
 741                 return false;
 742         if (p3reloc.opcode != RADEON_PACKET3_NOP)
 743                 return false;
 744         return true;
 745 }
 746
 747 /**
 748  * radeon_cs_dump_packet() - dump raw packet context
 749  * @p:          structure holding the parser context.
 750  * @pkt:        structure holding the packet.
 751  *
 752  * Used mostly for debugging and error reporting.
 753  **/
 754 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
 755                            struct radeon_cs_packet *pkt)
 756 {
 757         volatile uint32_t *ib;
 758         unsigned i;
 759         unsigned idx;
 760
 761         ib = p->ib.ptr;
 762         idx = pkt->idx;
 763         for (i = 0; i <= (pkt->count + 1); i++, idx++)
 764                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 765 }
 766
 767 /**
 768  * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
 769  * @parser:             parser structure holding parsing context.
 770  * @data:               pointer to relocation data
 771  * @offset_start:       starting offset
 772  * @offset_mask:        offset mask (to align start offset on)
 773  * @reloc:              reloc informations
 774  *
 775  * Check if next packet is relocation packet3, do bo validation and compute
 776  * GPU offset using the provided start.
 777  **/
 778 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
 779                                 struct radeon_cs_reloc **cs_reloc,
 780                                 int nomm)
 781 {
 782         struct radeon_cs_chunk *relocs_chunk;
 783         struct radeon_cs_packet p3reloc;
 784         unsigned idx;
 785         int r;
 786
 787         if (p->chunk_relocs_idx == -1) {
 788                 DRM_ERROR("No relocation chunk !\n");
 789                 return -EINVAL;
 790         }
 791         *cs_reloc = NULL;
 792         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 793         r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
 794         if (r)
 795                 return r;
 796         p->idx += p3reloc.count + 2;
 797         if (p3reloc.type != RADEON_PACKET_TYPE3 ||
 798             p3reloc.opcode != RADEON_PACKET3_NOP) {
 799                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 800                           p3reloc.idx);
 801                 radeon_cs_dump_packet(p, &p3reloc);
 802                 return -EINVAL;
 803         }
 804         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 805         if (idx >= relocs_chunk->length_dw) {
 806                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 807                           idx, relocs_chunk->length_dw);
 808                 radeon_cs_dump_packet(p, &p3reloc);
 809                 return -EINVAL;
 810         }
 811         /* FIXME: we assume reloc size is 4 dwords */
 812         if (nomm) {
 813                 *cs_reloc = p->relocs;
 814                 (*cs_reloc)->lobj.gpu_offset =
 815                         (u64)relocs_chunk->kdata[idx + 3] << 32;
 816                 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
 817         } else
 818                 *cs_reloc = p->relocs_ptr[(idx / 4)];
 819         return 0;
 820 }