2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/radeon_drm.h>
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
34 #include "radeon_reg.h"
39 * Clear GPU surface registers.
41 void radeon_surface_init(struct radeon_device
*rdev
)
43 /* FIXME: check this out */
44 if (rdev
->family
< CHIP_R600
) {
47 for (i
= 0; i
< RADEON_GEM_MAX_SURFACES
; i
++) {
48 if (rdev
->surface_regs
[i
].bo
)
49 radeon_bo_get_surface_reg(rdev
->surface_regs
[i
].bo
);
51 radeon_clear_surface_reg(rdev
, i
);
54 WREG32(RADEON_SURFACE_CNTL
, 0);
59 * GPU scratch registers helpers function.
61 void radeon_scratch_init(struct radeon_device
*rdev
)
65 /* FIXME: check this out */
66 if (rdev
->family
< CHIP_R300
) {
67 rdev
->scratch
.num_reg
= 5;
69 rdev
->scratch
.num_reg
= 7;
71 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
72 rdev
->scratch
.free
[i
] = true;
73 rdev
->scratch
.reg
[i
] = RADEON_SCRATCH_REG0
+ (i
* 4);
77 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
)
81 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
82 if (rdev
->scratch
.free
[i
]) {
83 rdev
->scratch
.free
[i
] = false;
84 *reg
= rdev
->scratch
.reg
[i
];
91 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
)
95 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
96 if (rdev
->scratch
.reg
[i
] == reg
) {
97 rdev
->scratch
.free
[i
] = true;
104 * radeon_vram_location - try to find VRAM location
105 * @rdev: radeon device structure holding all necessary informations
106 * @mc: memory controller structure holding memory informations
107 * @base: base address at which to put VRAM
109 * Function will place try to place VRAM at base address provided
110 * as parameter (which is so far either PCI aperture address or
111 * for IGP TOM base address).
113 * If there is not enough space to fit the unvisible VRAM in the 32bits
114 * address space then we limit the VRAM size to the aperture.
116 * If we are using AGP and if the AGP aperture doesn't allow us to have
117 * room for all the VRAM than we restrict the VRAM to the PCI aperture
118 * size and print a warning.
120 * This function will never fails, worst case are limiting VRAM.
122 * Note: GTT start, end, size should be initialized before calling this
123 * function on AGP platform.
125 * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
126 * this shouldn't be a problem as we are using the PCI aperture as a reference.
127 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
130 * Note: we use mc_vram_size as on some board we need to program the mc to
131 * cover the whole aperture even if VRAM size is inferior to aperture size
132 * Novell bug 204882 + along with lots of ubuntu ones
134 * Note: when limiting vram it's safe to overwritte real_vram_size because
135 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
136 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
139 * Note: IGP TOM addr should be the same as the aperture addr, we don't
140 * explicitly check for that thought.
142 * FIXME: when reducing VRAM size align new size on power of 2.
144 void radeon_vram_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
, u64 base
)
146 mc
->vram_start
= base
;
147 if (mc
->mc_vram_size
> (0xFFFFFFFF - base
+ 1)) {
148 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
149 mc
->real_vram_size
= mc
->aper_size
;
150 mc
->mc_vram_size
= mc
->aper_size
;
152 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
153 if (rdev
->flags
& RADEON_IS_AGP
&& mc
->vram_end
> mc
->gtt_start
&& mc
->vram_end
<= mc
->gtt_end
) {
154 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
155 mc
->real_vram_size
= mc
->aper_size
;
156 mc
->mc_vram_size
= mc
->aper_size
;
158 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
159 dev_info(rdev
->dev
, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
160 mc
->mc_vram_size
>> 20, mc
->vram_start
,
161 mc
->vram_end
, mc
->real_vram_size
>> 20);
165 * radeon_gtt_location - try to find GTT location
166 * @rdev: radeon device structure holding all necessary informations
167 * @mc: memory controller structure holding memory informations
169 * Function will place try to place GTT before or after VRAM.
171 * If GTT size is bigger than space left then we ajust GTT size.
172 * Thus function will never fails.
174 * FIXME: when reducing GTT size align new size on power of 2.
176 void radeon_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
178 u64 size_af
, size_bf
;
180 size_af
= 0xFFFFFFFF - mc
->vram_end
;
181 size_bf
= mc
->vram_start
;
182 if (size_bf
> size_af
) {
183 if (mc
->gtt_size
> size_bf
) {
184 dev_warn(rdev
->dev
, "limiting GTT\n");
185 mc
->gtt_size
= size_bf
;
187 mc
->gtt_start
= mc
->vram_start
- mc
->gtt_size
;
189 if (mc
->gtt_size
> size_af
) {
190 dev_warn(rdev
->dev
, "limiting GTT\n");
191 mc
->gtt_size
= size_af
;
193 mc
->gtt_start
= mc
->vram_end
+ 1;
195 mc
->gtt_end
= mc
->gtt_start
+ mc
->gtt_size
- 1;
196 dev_info(rdev
->dev
, "GTT: %lluM 0x%08llX - 0x%08llX\n",
197 mc
->gtt_size
>> 20, mc
->gtt_start
, mc
->gtt_end
);
201 * GPU helpers function.
203 bool radeon_card_posted(struct radeon_device
*rdev
)
207 /* first check CRTCs */
208 if (ASIC_IS_DCE4(rdev
)) {
209 reg
= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) |
210 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
) |
211 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) |
212 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
) |
213 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) |
214 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
215 if (reg
& EVERGREEN_CRTC_MASTER_EN
)
217 } else if (ASIC_IS_AVIVO(rdev
)) {
218 reg
= RREG32(AVIVO_D1CRTC_CONTROL
) |
219 RREG32(AVIVO_D2CRTC_CONTROL
);
220 if (reg
& AVIVO_CRTC_EN
) {
224 reg
= RREG32(RADEON_CRTC_GEN_CNTL
) |
225 RREG32(RADEON_CRTC2_GEN_CNTL
);
226 if (reg
& RADEON_CRTC_EN
) {
231 /* then check MEM_SIZE, in case the crtcs are off */
232 if (rdev
->family
>= CHIP_R600
)
233 reg
= RREG32(R600_CONFIG_MEMSIZE
);
235 reg
= RREG32(RADEON_CONFIG_MEMSIZE
);
244 bool radeon_boot_test_post_card(struct radeon_device
*rdev
)
246 if (radeon_card_posted(rdev
))
250 DRM_INFO("GPU not posted. posting now...\n");
251 if (rdev
->is_atom_bios
)
252 atom_asic_init(rdev
->mode_info
.atom_context
);
254 radeon_combios_asic_init(rdev
->ddev
);
257 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
262 int radeon_dummy_page_init(struct radeon_device
*rdev
)
264 if (rdev
->dummy_page
.page
)
266 rdev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
267 if (rdev
->dummy_page
.page
== NULL
)
269 rdev
->dummy_page
.addr
= pci_map_page(rdev
->pdev
, rdev
->dummy_page
.page
,
270 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
271 if (!rdev
->dummy_page
.addr
) {
272 __free_page(rdev
->dummy_page
.page
);
273 rdev
->dummy_page
.page
= NULL
;
279 void radeon_dummy_page_fini(struct radeon_device
*rdev
)
281 if (rdev
->dummy_page
.page
== NULL
)
283 pci_unmap_page(rdev
->pdev
, rdev
->dummy_page
.addr
,
284 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
285 __free_page(rdev
->dummy_page
.page
);
286 rdev
->dummy_page
.page
= NULL
;
290 /* ATOM accessor methods */
291 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
293 struct radeon_device
*rdev
= info
->dev
->dev_private
;
296 r
= rdev
->pll_rreg(rdev
, reg
);
300 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
302 struct radeon_device
*rdev
= info
->dev
->dev_private
;
304 rdev
->pll_wreg(rdev
, reg
, val
);
307 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
309 struct radeon_device
*rdev
= info
->dev
->dev_private
;
312 r
= rdev
->mc_rreg(rdev
, reg
);
316 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
318 struct radeon_device
*rdev
= info
->dev
->dev_private
;
320 rdev
->mc_wreg(rdev
, reg
, val
);
323 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
325 struct radeon_device
*rdev
= info
->dev
->dev_private
;
330 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
332 struct radeon_device
*rdev
= info
->dev
->dev_private
;
339 int radeon_atombios_init(struct radeon_device
*rdev
)
341 struct card_info
*atom_card_info
=
342 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
347 rdev
->mode_info
.atom_card_info
= atom_card_info
;
348 atom_card_info
->dev
= rdev
->ddev
;
349 atom_card_info
->reg_read
= cail_reg_read
;
350 atom_card_info
->reg_write
= cail_reg_write
;
351 atom_card_info
->mc_read
= cail_mc_read
;
352 atom_card_info
->mc_write
= cail_mc_write
;
353 atom_card_info
->pll_read
= cail_pll_read
;
354 atom_card_info
->pll_write
= cail_pll_write
;
356 rdev
->mode_info
.atom_context
= atom_parse(atom_card_info
, rdev
->bios
);
357 mutex_init(&rdev
->mode_info
.atom_context
->mutex
);
358 radeon_atom_initialize_bios_scratch_regs(rdev
->ddev
);
359 atom_allocate_fb_scratch(rdev
->mode_info
.atom_context
);
363 void radeon_atombios_fini(struct radeon_device
*rdev
)
365 if (rdev
->mode_info
.atom_context
) {
366 kfree(rdev
->mode_info
.atom_context
->scratch
);
367 kfree(rdev
->mode_info
.atom_context
);
369 kfree(rdev
->mode_info
.atom_card_info
);
372 int radeon_combios_init(struct radeon_device
*rdev
)
374 radeon_combios_initialize_bios_scratch_regs(rdev
->ddev
);
378 void radeon_combios_fini(struct radeon_device
*rdev
)
382 /* if we get transitioned to only one device, tak VGA back */
383 static unsigned int radeon_vga_set_decode(void *cookie
, bool state
)
385 struct radeon_device
*rdev
= cookie
;
386 radeon_vga_set_state(rdev
, state
);
388 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
389 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
391 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
394 void radeon_check_arguments(struct radeon_device
*rdev
)
396 /* vramlimit must be a power of two */
397 switch (radeon_vram_limit
) {
412 dev_warn(rdev
->dev
, "vram limit (%d) must be a power of 2\n",
414 radeon_vram_limit
= 0;
417 radeon_vram_limit
= radeon_vram_limit
<< 20;
418 /* gtt size must be power of two and greater or equal to 32M */
419 switch (radeon_gart_size
) {
423 dev_warn(rdev
->dev
, "gart size (%d) too small forcing to 512M\n",
425 radeon_gart_size
= 512;
437 dev_warn(rdev
->dev
, "gart size (%d) must be a power of 2\n",
439 radeon_gart_size
= 512;
442 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
443 /* AGP mode can only be -1, 1, 2, 4, 8 */
444 switch (radeon_agpmode
) {
453 dev_warn(rdev
->dev
, "invalid AGP mode %d (valid mode: "
454 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode
);
460 static void radeon_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
462 struct drm_device
*dev
= pci_get_drvdata(pdev
);
463 struct radeon_device
*rdev
= dev
->dev_private
;
464 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
465 if (state
== VGA_SWITCHEROO_ON
) {
466 printk(KERN_INFO
"radeon: switched on\n");
467 /* don't suspend or resume card normally */
468 rdev
->powered_down
= false;
469 radeon_resume_kms(dev
);
471 printk(KERN_INFO
"radeon: switched off\n");
472 radeon_suspend_kms(dev
, pmm
);
473 /* don't suspend or resume card normally */
474 rdev
->powered_down
= true;
478 static bool radeon_switcheroo_can_switch(struct pci_dev
*pdev
)
480 struct drm_device
*dev
= pci_get_drvdata(pdev
);
483 spin_lock(&dev
->count_lock
);
484 can_switch
= (dev
->open_count
== 0);
485 spin_unlock(&dev
->count_lock
);
490 int radeon_device_init(struct radeon_device
*rdev
,
491 struct drm_device
*ddev
,
492 struct pci_dev
*pdev
,
498 DRM_INFO("radeon: Initializing kernel modesetting.\n");
499 rdev
->shutdown
= false;
500 rdev
->dev
= &pdev
->dev
;
504 rdev
->family
= flags
& RADEON_FAMILY_MASK
;
505 rdev
->is_atom_bios
= false;
506 rdev
->usec_timeout
= RADEON_MAX_USEC_TIMEOUT
;
507 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
508 rdev
->gpu_lockup
= false;
509 rdev
->accel_working
= false;
510 /* mutex initialization are all done here so we
511 * can recall function without having locking issues */
512 mutex_init(&rdev
->cs_mutex
);
513 mutex_init(&rdev
->ib_pool
.mutex
);
514 mutex_init(&rdev
->cp
.mutex
);
515 mutex_init(&rdev
->dc_hw_i2c_mutex
);
516 if (rdev
->family
>= CHIP_R600
)
517 spin_lock_init(&rdev
->ih
.lock
);
518 mutex_init(&rdev
->gem
.mutex
);
519 mutex_init(&rdev
->pm
.mutex
);
520 rwlock_init(&rdev
->fence_drv
.lock
);
521 INIT_LIST_HEAD(&rdev
->gem
.objects
);
522 init_waitqueue_head(&rdev
->irq
.vblank_queue
);
524 /* setup workqueue */
525 rdev
->wq
= create_workqueue("radeon");
526 if (rdev
->wq
== NULL
)
529 /* Set asic functions */
530 r
= radeon_asic_init(rdev
);
533 radeon_check_arguments(rdev
);
535 if (rdev
->flags
& RADEON_IS_AGP
&& radeon_agpmode
== -1) {
536 radeon_agp_disable(rdev
);
539 /* set DMA mask + need_dma32 flags.
540 * PCIE - can handle 40-bits.
541 * IGP - can handle 40-bits (in theory)
542 * AGP - generally dma32 is safest
545 rdev
->need_dma32
= false;
546 if (rdev
->flags
& RADEON_IS_AGP
)
547 rdev
->need_dma32
= true;
548 if (rdev
->flags
& RADEON_IS_PCI
)
549 rdev
->need_dma32
= true;
551 dma_bits
= rdev
->need_dma32
? 32 : 40;
552 r
= pci_set_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
554 printk(KERN_WARNING
"radeon: No suitable DMA available.\n");
557 /* Registers mapping */
558 /* TODO: block userspace mapping of io register */
559 rdev
->rmmio_base
= drm_get_resource_start(rdev
->ddev
, 2);
560 rdev
->rmmio_size
= drm_get_resource_len(rdev
->ddev
, 2);
561 rdev
->rmmio
= ioremap(rdev
->rmmio_base
, rdev
->rmmio_size
);
562 if (rdev
->rmmio
== NULL
) {
565 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev
->rmmio_base
);
566 DRM_INFO("register mmio size: %u\n", (unsigned)rdev
->rmmio_size
);
568 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
569 /* this will fail for cards that aren't VGA class devices, just
571 vga_client_register(rdev
->pdev
, rdev
, NULL
, radeon_vga_set_decode
);
572 vga_switcheroo_register_client(rdev
->pdev
,
573 radeon_switcheroo_set_state
,
574 radeon_switcheroo_can_switch
);
576 r
= radeon_init(rdev
);
580 if (rdev
->flags
& RADEON_IS_AGP
&& !rdev
->accel_working
) {
581 /* Acceleration not working on AGP card try again
582 * with fallback to PCI or PCIE GART
584 radeon_gpu_reset(rdev
);
586 radeon_agp_disable(rdev
);
587 r
= radeon_init(rdev
);
591 if (radeon_testing
) {
592 radeon_test_moves(rdev
);
594 if (radeon_benchmarking
) {
595 radeon_benchmark(rdev
);
600 void radeon_device_fini(struct radeon_device
*rdev
)
602 DRM_INFO("radeon: finishing device.\n");
603 rdev
->shutdown
= true;
605 destroy_workqueue(rdev
->wq
);
606 vga_switcheroo_unregister_client(rdev
->pdev
);
607 vga_client_register(rdev
->pdev
, NULL
, NULL
, NULL
);
608 iounmap(rdev
->rmmio
);
616 int radeon_suspend_kms(struct drm_device
*dev
, pm_message_t state
)
618 struct radeon_device
*rdev
;
619 struct drm_crtc
*crtc
;
622 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
625 if (state
.event
== PM_EVENT_PRETHAW
) {
628 rdev
= dev
->dev_private
;
630 if (rdev
->powered_down
)
632 /* unpin the front buffers */
633 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
634 struct radeon_framebuffer
*rfb
= to_radeon_framebuffer(crtc
->fb
);
635 struct radeon_bo
*robj
;
637 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
640 robj
= rfb
->obj
->driver_private
;
641 if (robj
!= rdev
->fbdev_rbo
) {
642 r
= radeon_bo_reserve(robj
, false);
643 if (unlikely(r
== 0)) {
644 radeon_bo_unpin(robj
);
645 radeon_bo_unreserve(robj
);
649 /* evict vram memory */
650 radeon_bo_evict_vram(rdev
);
651 /* wait for gpu to finish processing current batch */
652 radeon_fence_wait_last(rdev
);
654 radeon_save_bios_scratch_regs(rdev
);
656 radeon_suspend(rdev
);
657 radeon_hpd_fini(rdev
);
658 /* evict remaining vram memory */
659 radeon_bo_evict_vram(rdev
);
661 pci_save_state(dev
->pdev
);
662 if (state
.event
== PM_EVENT_SUSPEND
) {
663 /* Shut down the device */
664 pci_disable_device(dev
->pdev
);
665 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
667 acquire_console_sem();
668 fb_set_suspend(rdev
->fbdev_info
, 1);
669 release_console_sem();
673 int radeon_resume_kms(struct drm_device
*dev
)
675 struct radeon_device
*rdev
= dev
->dev_private
;
677 if (rdev
->powered_down
)
680 acquire_console_sem();
681 pci_set_power_state(dev
->pdev
, PCI_D0
);
682 pci_restore_state(dev
->pdev
);
683 if (pci_enable_device(dev
->pdev
)) {
684 release_console_sem();
687 pci_set_master(dev
->pdev
);
688 /* resume AGP if in use */
689 radeon_agp_resume(rdev
);
691 radeon_restore_bios_scratch_regs(rdev
);
692 fb_set_suspend(rdev
->fbdev_info
, 0);
693 release_console_sem();
695 /* reset hpd state */
696 radeon_hpd_init(rdev
);
697 /* blat the mode back in */
698 drm_helper_resume_force_mode(dev
);
706 struct radeon_debugfs
{
707 struct drm_info_list
*files
;
710 static struct radeon_debugfs _radeon_debugfs
[RADEON_DEBUGFS_MAX_NUM_FILES
];
711 static unsigned _radeon_debugfs_count
= 0;
713 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
714 struct drm_info_list
*files
,
719 for (i
= 0; i
< _radeon_debugfs_count
; i
++) {
720 if (_radeon_debugfs
[i
].files
== files
) {
721 /* Already registered */
725 if ((_radeon_debugfs_count
+ nfiles
) > RADEON_DEBUGFS_MAX_NUM_FILES
) {
726 DRM_ERROR("Reached maximum number of debugfs files.\n");
727 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
730 _radeon_debugfs
[_radeon_debugfs_count
].files
= files
;
731 _radeon_debugfs
[_radeon_debugfs_count
].num_files
= nfiles
;
732 _radeon_debugfs_count
++;
733 #if defined(CONFIG_DEBUG_FS)
734 drm_debugfs_create_files(files
, nfiles
,
735 rdev
->ddev
->control
->debugfs_root
,
736 rdev
->ddev
->control
);
737 drm_debugfs_create_files(files
, nfiles
,
738 rdev
->ddev
->primary
->debugfs_root
,
739 rdev
->ddev
->primary
);
744 #if defined(CONFIG_DEBUG_FS)
745 int radeon_debugfs_init(struct drm_minor
*minor
)
750 void radeon_debugfs_cleanup(struct drm_minor
*minor
)
754 for (i
= 0; i
< _radeon_debugfs_count
; i
++) {
755 drm_debugfs_remove_files(_radeon_debugfs
[i
].files
,
756 _radeon_debugfs
[i
].num_files
, minor
);