2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include <linux/efi.h>
36 #include "radeon_reg.h"
40 static const char radeon_family_name
[][16] = {
106 #if defined(CONFIG_VGA_SWITCHEROO)
107 bool radeon_has_atpx_dgpu_power_cntl(void);
109 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
112 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
113 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
115 struct radeon_px_quirk
{
123 static struct radeon_px_quirk radeon_px_quirk_list
[] = {
124 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
125 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
127 { PCI_VENDOR_ID_ATI
, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX
},
128 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
129 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
131 { PCI_VENDOR_ID_ATI
, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX
},
132 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
133 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
135 { PCI_VENDOR_ID_ATI
, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX
},
136 /* macbook pro 8.2 */
137 { PCI_VENDOR_ID_ATI
, 0x6741, PCI_VENDOR_ID_APPLE
, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP
},
141 bool radeon_is_px(struct drm_device
*dev
)
143 struct radeon_device
*rdev
= dev
->dev_private
;
145 if (rdev
->flags
& RADEON_IS_PX
)
150 static void radeon_device_handle_px_quirks(struct radeon_device
*rdev
)
152 struct radeon_px_quirk
*p
= radeon_px_quirk_list
;
154 /* Apply PX quirks */
155 while (p
&& p
->chip_device
!= 0) {
156 if (rdev
->pdev
->vendor
== p
->chip_vendor
&&
157 rdev
->pdev
->device
== p
->chip_device
&&
158 rdev
->pdev
->subsystem_vendor
== p
->subsys_vendor
&&
159 rdev
->pdev
->subsystem_device
== p
->subsys_device
) {
160 rdev
->px_quirk_flags
= p
->px_quirk_flags
;
166 if (rdev
->px_quirk_flags
& RADEON_PX_QUIRK_DISABLE_PX
)
167 rdev
->flags
&= ~RADEON_IS_PX
;
171 * radeon_program_register_sequence - program an array of registers.
173 * @rdev: radeon_device pointer
174 * @registers: pointer to the register array
175 * @array_size: size of the register array
177 * Programs an array or registers with and and or masks.
178 * This is a helper for setting golden registers.
180 void radeon_program_register_sequence(struct radeon_device
*rdev
,
181 const u32
*registers
,
182 const u32 array_size
)
184 u32 tmp
, reg
, and_mask
, or_mask
;
190 for (i
= 0; i
< array_size
; i
+=3) {
191 reg
= registers
[i
+ 0];
192 and_mask
= registers
[i
+ 1];
193 or_mask
= registers
[i
+ 2];
195 if (and_mask
== 0xffffffff) {
206 void radeon_pci_config_reset(struct radeon_device
*rdev
)
208 pci_write_config_dword(rdev
->pdev
, 0x7c, RADEON_ASIC_RESET_DATA
);
212 * radeon_surface_init - Clear GPU surface registers.
214 * @rdev: radeon_device pointer
216 * Clear GPU surface registers (r1xx-r5xx).
218 void radeon_surface_init(struct radeon_device
*rdev
)
220 /* FIXME: check this out */
221 if (rdev
->family
< CHIP_R600
) {
224 for (i
= 0; i
< RADEON_GEM_MAX_SURFACES
; i
++) {
225 if (rdev
->surface_regs
[i
].bo
)
226 radeon_bo_get_surface_reg(rdev
->surface_regs
[i
].bo
);
228 radeon_clear_surface_reg(rdev
, i
);
230 /* enable surfaces */
231 WREG32(RADEON_SURFACE_CNTL
, 0);
236 * GPU scratch registers helpers function.
239 * radeon_scratch_init - Init scratch register driver information.
241 * @rdev: radeon_device pointer
243 * Init CP scratch register driver information (r1xx-r5xx)
245 void radeon_scratch_init(struct radeon_device
*rdev
)
249 /* FIXME: check this out */
250 if (rdev
->family
< CHIP_R300
) {
251 rdev
->scratch
.num_reg
= 5;
253 rdev
->scratch
.num_reg
= 7;
255 rdev
->scratch
.reg_base
= RADEON_SCRATCH_REG0
;
256 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
257 rdev
->scratch
.free
[i
] = true;
258 rdev
->scratch
.reg
[i
] = rdev
->scratch
.reg_base
+ (i
* 4);
263 * radeon_scratch_get - Allocate a scratch register
265 * @rdev: radeon_device pointer
266 * @reg: scratch register mmio offset
268 * Allocate a CP scratch register for use by the driver (all asics).
269 * Returns 0 on success or -EINVAL on failure.
271 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
)
275 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
276 if (rdev
->scratch
.free
[i
]) {
277 rdev
->scratch
.free
[i
] = false;
278 *reg
= rdev
->scratch
.reg
[i
];
286 * radeon_scratch_free - Free a scratch register
288 * @rdev: radeon_device pointer
289 * @reg: scratch register mmio offset
291 * Free a CP scratch register allocated for use by the driver (all asics)
293 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
)
297 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
298 if (rdev
->scratch
.reg
[i
] == reg
) {
299 rdev
->scratch
.free
[i
] = true;
306 * GPU doorbell aperture helpers function.
309 * radeon_doorbell_init - Init doorbell driver information.
311 * @rdev: radeon_device pointer
313 * Init doorbell driver information (CIK)
314 * Returns 0 on success, error on failure.
316 static int radeon_doorbell_init(struct radeon_device
*rdev
)
318 /* doorbell bar mapping */
319 rdev
->doorbell
.base
= pci_resource_start(rdev
->pdev
, 2);
320 rdev
->doorbell
.size
= pci_resource_len(rdev
->pdev
, 2);
322 rdev
->doorbell
.num_doorbells
= min_t(u32
, rdev
->doorbell
.size
/ sizeof(u32
), RADEON_MAX_DOORBELLS
);
323 if (rdev
->doorbell
.num_doorbells
== 0)
326 rdev
->doorbell
.ptr
= ioremap(rdev
->doorbell
.base
, rdev
->doorbell
.num_doorbells
* sizeof(u32
));
327 if (rdev
->doorbell
.ptr
== NULL
) {
330 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev
->doorbell
.base
);
331 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev
->doorbell
.size
);
333 memset(&rdev
->doorbell
.used
, 0, sizeof(rdev
->doorbell
.used
));
339 * radeon_doorbell_fini - Tear down doorbell driver information.
341 * @rdev: radeon_device pointer
343 * Tear down doorbell driver information (CIK)
345 static void radeon_doorbell_fini(struct radeon_device
*rdev
)
347 iounmap(rdev
->doorbell
.ptr
);
348 rdev
->doorbell
.ptr
= NULL
;
352 * radeon_doorbell_get - Allocate a doorbell entry
354 * @rdev: radeon_device pointer
355 * @doorbell: doorbell index
357 * Allocate a doorbell for use by the driver (all asics).
358 * Returns 0 on success or -EINVAL on failure.
360 int radeon_doorbell_get(struct radeon_device
*rdev
, u32
*doorbell
)
362 unsigned long offset
= find_first_zero_bit(rdev
->doorbell
.used
, rdev
->doorbell
.num_doorbells
);
363 if (offset
< rdev
->doorbell
.num_doorbells
) {
364 __set_bit(offset
, rdev
->doorbell
.used
);
373 * radeon_doorbell_free - Free a doorbell entry
375 * @rdev: radeon_device pointer
376 * @doorbell: doorbell index
378 * Free a doorbell allocated for use by the driver (all asics)
380 void radeon_doorbell_free(struct radeon_device
*rdev
, u32 doorbell
)
382 if (doorbell
< rdev
->doorbell
.num_doorbells
)
383 __clear_bit(doorbell
, rdev
->doorbell
.used
);
387 * radeon_doorbell_get_kfd_info - Report doorbell configuration required to
390 * @rdev: radeon_device pointer
391 * @aperture_base: output returning doorbell aperture base physical address
392 * @aperture_size: output returning doorbell aperture size in bytes
393 * @start_offset: output returning # of doorbell bytes reserved for radeon.
395 * Radeon and the KFD share the doorbell aperture. Radeon sets it up,
396 * takes doorbells required for its own rings and reports the setup to KFD.
397 * Radeon reserved doorbells are at the start of the doorbell aperture.
399 void radeon_doorbell_get_kfd_info(struct radeon_device
*rdev
,
400 phys_addr_t
*aperture_base
,
401 size_t *aperture_size
,
402 size_t *start_offset
)
404 /* The first num_doorbells are used by radeon.
405 * KFD takes whatever's left in the aperture. */
406 if (rdev
->doorbell
.size
> rdev
->doorbell
.num_doorbells
* sizeof(u32
)) {
407 *aperture_base
= rdev
->doorbell
.base
;
408 *aperture_size
= rdev
->doorbell
.size
;
409 *start_offset
= rdev
->doorbell
.num_doorbells
* sizeof(u32
);
419 * Writeback is the the method by which the the GPU updates special pages
420 * in memory with the status of certain GPU events (fences, ring pointers,
425 * radeon_wb_disable - Disable Writeback
427 * @rdev: radeon_device pointer
429 * Disables Writeback (all asics). Used for suspend.
431 void radeon_wb_disable(struct radeon_device
*rdev
)
433 rdev
->wb
.enabled
= false;
437 * radeon_wb_fini - Disable Writeback and free memory
439 * @rdev: radeon_device pointer
441 * Disables Writeback and frees the Writeback memory (all asics).
442 * Used at driver shutdown.
444 void radeon_wb_fini(struct radeon_device
*rdev
)
446 radeon_wb_disable(rdev
);
447 if (rdev
->wb
.wb_obj
) {
448 if (!radeon_bo_reserve(rdev
->wb
.wb_obj
, false)) {
449 radeon_bo_kunmap(rdev
->wb
.wb_obj
);
450 radeon_bo_unpin(rdev
->wb
.wb_obj
);
451 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
453 radeon_bo_unref(&rdev
->wb
.wb_obj
);
455 rdev
->wb
.wb_obj
= NULL
;
460 * radeon_wb_init- Init Writeback driver info and allocate memory
462 * @rdev: radeon_device pointer
464 * Disables Writeback and frees the Writeback memory (all asics).
465 * Used at driver startup.
466 * Returns 0 on success or an -error on failure.
468 int radeon_wb_init(struct radeon_device
*rdev
)
472 if (rdev
->wb
.wb_obj
== NULL
) {
473 r
= radeon_bo_create(rdev
, RADEON_GPU_PAGE_SIZE
, PAGE_SIZE
, true,
474 RADEON_GEM_DOMAIN_GTT
, 0, NULL
, NULL
,
477 dev_warn(rdev
->dev
, "(%d) create WB bo failed\n", r
);
480 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
481 if (unlikely(r
!= 0)) {
482 radeon_wb_fini(rdev
);
485 r
= radeon_bo_pin(rdev
->wb
.wb_obj
, RADEON_GEM_DOMAIN_GTT
,
488 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
489 dev_warn(rdev
->dev
, "(%d) pin WB bo failed\n", r
);
490 radeon_wb_fini(rdev
);
493 r
= radeon_bo_kmap(rdev
->wb
.wb_obj
, (void **)&rdev
->wb
.wb
);
494 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
496 dev_warn(rdev
->dev
, "(%d) map WB bo failed\n", r
);
497 radeon_wb_fini(rdev
);
502 /* clear wb memory */
503 memset((char *)rdev
->wb
.wb
, 0, RADEON_GPU_PAGE_SIZE
);
504 /* disable event_write fences */
505 rdev
->wb
.use_event
= false;
506 /* disabled via module param */
507 if (radeon_no_wb
== 1) {
508 rdev
->wb
.enabled
= false;
510 if (rdev
->flags
& RADEON_IS_AGP
) {
511 /* often unreliable on AGP */
512 rdev
->wb
.enabled
= false;
513 } else if (rdev
->family
< CHIP_R300
) {
514 /* often unreliable on pre-r300 */
515 rdev
->wb
.enabled
= false;
517 rdev
->wb
.enabled
= true;
518 /* event_write fences are only available on r600+ */
519 if (rdev
->family
>= CHIP_R600
) {
520 rdev
->wb
.use_event
= true;
524 /* always use writeback/events on NI, APUs */
525 if (rdev
->family
>= CHIP_PALM
) {
526 rdev
->wb
.enabled
= true;
527 rdev
->wb
.use_event
= true;
530 dev_info(rdev
->dev
, "WB %sabled\n", rdev
->wb
.enabled
? "en" : "dis");
536 * radeon_vram_location - try to find VRAM location
537 * @rdev: radeon device structure holding all necessary informations
538 * @mc: memory controller structure holding memory informations
539 * @base: base address at which to put VRAM
541 * Function will place try to place VRAM at base address provided
542 * as parameter (which is so far either PCI aperture address or
543 * for IGP TOM base address).
545 * If there is not enough space to fit the unvisible VRAM in the 32bits
546 * address space then we limit the VRAM size to the aperture.
548 * If we are using AGP and if the AGP aperture doesn't allow us to have
549 * room for all the VRAM than we restrict the VRAM to the PCI aperture
550 * size and print a warning.
552 * This function will never fails, worst case are limiting VRAM.
554 * Note: GTT start, end, size should be initialized before calling this
555 * function on AGP platform.
557 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
558 * this shouldn't be a problem as we are using the PCI aperture as a reference.
559 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
562 * Note: we use mc_vram_size as on some board we need to program the mc to
563 * cover the whole aperture even if VRAM size is inferior to aperture size
564 * Novell bug 204882 + along with lots of ubuntu ones
566 * Note: when limiting vram it's safe to overwritte real_vram_size because
567 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
568 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
571 * Note: IGP TOM addr should be the same as the aperture addr, we don't
572 * explicitly check for that thought.
574 * FIXME: when reducing VRAM size align new size on power of 2.
576 void radeon_vram_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
, u64 base
)
578 uint64_t limit
= (uint64_t)radeon_vram_limit
<< 20;
580 mc
->vram_start
= base
;
581 if (mc
->mc_vram_size
> (rdev
->mc
.mc_mask
- base
+ 1)) {
582 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
583 mc
->real_vram_size
= mc
->aper_size
;
584 mc
->mc_vram_size
= mc
->aper_size
;
586 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
587 if (rdev
->flags
& RADEON_IS_AGP
&& mc
->vram_end
> mc
->gtt_start
&& mc
->vram_start
<= mc
->gtt_end
) {
588 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
589 mc
->real_vram_size
= mc
->aper_size
;
590 mc
->mc_vram_size
= mc
->aper_size
;
592 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
593 if (limit
&& limit
< mc
->real_vram_size
)
594 mc
->real_vram_size
= limit
;
595 dev_info(rdev
->dev
, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
596 mc
->mc_vram_size
>> 20, mc
->vram_start
,
597 mc
->vram_end
, mc
->real_vram_size
>> 20);
601 * radeon_gtt_location - try to find GTT location
602 * @rdev: radeon device structure holding all necessary informations
603 * @mc: memory controller structure holding memory informations
605 * Function will place try to place GTT before or after VRAM.
607 * If GTT size is bigger than space left then we ajust GTT size.
608 * Thus function will never fails.
610 * FIXME: when reducing GTT size align new size on power of 2.
612 void radeon_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
614 u64 size_af
, size_bf
;
616 size_af
= ((rdev
->mc
.mc_mask
- mc
->vram_end
) + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
617 size_bf
= mc
->vram_start
& ~mc
->gtt_base_align
;
618 if (size_bf
> size_af
) {
619 if (mc
->gtt_size
> size_bf
) {
620 dev_warn(rdev
->dev
, "limiting GTT\n");
621 mc
->gtt_size
= size_bf
;
623 mc
->gtt_start
= (mc
->vram_start
& ~mc
->gtt_base_align
) - mc
->gtt_size
;
625 if (mc
->gtt_size
> size_af
) {
626 dev_warn(rdev
->dev
, "limiting GTT\n");
627 mc
->gtt_size
= size_af
;
629 mc
->gtt_start
= (mc
->vram_end
+ 1 + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
631 mc
->gtt_end
= mc
->gtt_start
+ mc
->gtt_size
- 1;
632 dev_info(rdev
->dev
, "GTT: %lluM 0x%016llX - 0x%016llX\n",
633 mc
->gtt_size
>> 20, mc
->gtt_start
, mc
->gtt_end
);
637 * GPU helpers function.
640 * radeon_card_posted - check if the hw has already been initialized
642 * @rdev: radeon_device pointer
644 * Check if the asic has been initialized (all asics).
645 * Used at driver startup.
646 * Returns true if initialized or false if not.
648 bool radeon_card_posted(struct radeon_device
*rdev
)
652 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
653 if (efi_enabled(EFI_BOOT
) &&
654 (rdev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
) &&
655 (rdev
->family
< CHIP_R600
))
658 if (ASIC_IS_NODCE(rdev
))
661 /* first check CRTCs */
662 if (ASIC_IS_DCE4(rdev
)) {
663 reg
= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) |
664 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
665 if (rdev
->num_crtc
>= 4) {
666 reg
|= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) |
667 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
669 if (rdev
->num_crtc
>= 6) {
670 reg
|= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) |
671 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
673 if (reg
& EVERGREEN_CRTC_MASTER_EN
)
675 } else if (ASIC_IS_AVIVO(rdev
)) {
676 reg
= RREG32(AVIVO_D1CRTC_CONTROL
) |
677 RREG32(AVIVO_D2CRTC_CONTROL
);
678 if (reg
& AVIVO_CRTC_EN
) {
682 reg
= RREG32(RADEON_CRTC_GEN_CNTL
) |
683 RREG32(RADEON_CRTC2_GEN_CNTL
);
684 if (reg
& RADEON_CRTC_EN
) {
690 /* then check MEM_SIZE, in case the crtcs are off */
691 if (rdev
->family
>= CHIP_R600
)
692 reg
= RREG32(R600_CONFIG_MEMSIZE
);
694 reg
= RREG32(RADEON_CONFIG_MEMSIZE
);
704 * radeon_update_bandwidth_info - update display bandwidth params
706 * @rdev: radeon_device pointer
708 * Used when sclk/mclk are switched or display modes are set.
709 * params are used to calculate display watermarks (all asics)
711 void radeon_update_bandwidth_info(struct radeon_device
*rdev
)
714 u32 sclk
= rdev
->pm
.current_sclk
;
715 u32 mclk
= rdev
->pm
.current_mclk
;
717 /* sclk/mclk in Mhz */
718 a
.full
= dfixed_const(100);
719 rdev
->pm
.sclk
.full
= dfixed_const(sclk
);
720 rdev
->pm
.sclk
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
721 rdev
->pm
.mclk
.full
= dfixed_const(mclk
);
722 rdev
->pm
.mclk
.full
= dfixed_div(rdev
->pm
.mclk
, a
);
724 if (rdev
->flags
& RADEON_IS_IGP
) {
725 a
.full
= dfixed_const(16);
726 /* core_bandwidth = sclk(Mhz) * 16 */
727 rdev
->pm
.core_bandwidth
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
732 * radeon_boot_test_post_card - check and possibly initialize the hw
734 * @rdev: radeon_device pointer
736 * Check if the asic is initialized and if not, attempt to initialize
738 * Returns true if initialized or false if not.
740 bool radeon_boot_test_post_card(struct radeon_device
*rdev
)
742 if (radeon_card_posted(rdev
))
746 DRM_INFO("GPU not posted. posting now...\n");
747 if (rdev
->is_atom_bios
)
748 atom_asic_init(rdev
->mode_info
.atom_context
);
750 radeon_combios_asic_init(rdev
->ddev
);
753 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
759 * radeon_dummy_page_init - init dummy page used by the driver
761 * @rdev: radeon_device pointer
763 * Allocate the dummy page used by the driver (all asics).
764 * This dummy page is used by the driver as a filler for gart entries
765 * when pages are taken out of the GART
766 * Returns 0 on sucess, -ENOMEM on failure.
768 int radeon_dummy_page_init(struct radeon_device
*rdev
)
770 if (rdev
->dummy_page
.page
)
772 rdev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
773 if (rdev
->dummy_page
.page
== NULL
)
775 rdev
->dummy_page
.addr
= pci_map_page(rdev
->pdev
, rdev
->dummy_page
.page
,
776 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
777 if (pci_dma_mapping_error(rdev
->pdev
, rdev
->dummy_page
.addr
)) {
778 dev_err(&rdev
->pdev
->dev
, "Failed to DMA MAP the dummy page\n");
779 __free_page(rdev
->dummy_page
.page
);
780 rdev
->dummy_page
.page
= NULL
;
783 rdev
->dummy_page
.entry
= radeon_gart_get_page_entry(rdev
->dummy_page
.addr
,
784 RADEON_GART_PAGE_DUMMY
);
789 * radeon_dummy_page_fini - free dummy page used by the driver
791 * @rdev: radeon_device pointer
793 * Frees the dummy page used by the driver (all asics).
795 void radeon_dummy_page_fini(struct radeon_device
*rdev
)
797 if (rdev
->dummy_page
.page
== NULL
)
799 pci_unmap_page(rdev
->pdev
, rdev
->dummy_page
.addr
,
800 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
801 __free_page(rdev
->dummy_page
.page
);
802 rdev
->dummy_page
.page
= NULL
;
806 /* ATOM accessor methods */
808 * ATOM is an interpreted byte code stored in tables in the vbios. The
809 * driver registers callbacks to access registers and the interpreter
810 * in the driver parses the tables and executes then to program specific
811 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
812 * atombios.h, and atom.c
816 * cail_pll_read - read PLL register
818 * @info: atom card_info pointer
819 * @reg: PLL register offset
821 * Provides a PLL register accessor for the atom interpreter (r4xx+).
822 * Returns the value of the PLL register.
824 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
826 struct radeon_device
*rdev
= info
->dev
->dev_private
;
829 r
= rdev
->pll_rreg(rdev
, reg
);
834 * cail_pll_write - write PLL register
836 * @info: atom card_info pointer
837 * @reg: PLL register offset
838 * @val: value to write to the pll register
840 * Provides a PLL register accessor for the atom interpreter (r4xx+).
842 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
844 struct radeon_device
*rdev
= info
->dev
->dev_private
;
846 rdev
->pll_wreg(rdev
, reg
, val
);
850 * cail_mc_read - read MC (Memory Controller) register
852 * @info: atom card_info pointer
853 * @reg: MC register offset
855 * Provides an MC register accessor for the atom interpreter (r4xx+).
856 * Returns the value of the MC register.
858 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
860 struct radeon_device
*rdev
= info
->dev
->dev_private
;
863 r
= rdev
->mc_rreg(rdev
, reg
);
868 * cail_mc_write - write MC (Memory Controller) register
870 * @info: atom card_info pointer
871 * @reg: MC register offset
872 * @val: value to write to the pll register
874 * Provides a MC register accessor for the atom interpreter (r4xx+).
876 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
878 struct radeon_device
*rdev
= info
->dev
->dev_private
;
880 rdev
->mc_wreg(rdev
, reg
, val
);
884 * cail_reg_write - write MMIO register
886 * @info: atom card_info pointer
887 * @reg: MMIO register offset
888 * @val: value to write to the pll register
890 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
892 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
894 struct radeon_device
*rdev
= info
->dev
->dev_private
;
900 * cail_reg_read - read MMIO register
902 * @info: atom card_info pointer
903 * @reg: MMIO register offset
905 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
906 * Returns the value of the MMIO register.
908 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
910 struct radeon_device
*rdev
= info
->dev
->dev_private
;
918 * cail_ioreg_write - write IO register
920 * @info: atom card_info pointer
921 * @reg: IO register offset
922 * @val: value to write to the pll register
924 * Provides a IO register accessor for the atom interpreter (r4xx+).
926 static void cail_ioreg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
928 struct radeon_device
*rdev
= info
->dev
->dev_private
;
930 WREG32_IO(reg
*4, val
);
934 * cail_ioreg_read - read IO register
936 * @info: atom card_info pointer
937 * @reg: IO register offset
939 * Provides an IO register accessor for the atom interpreter (r4xx+).
940 * Returns the value of the IO register.
942 static uint32_t cail_ioreg_read(struct card_info
*info
, uint32_t reg
)
944 struct radeon_device
*rdev
= info
->dev
->dev_private
;
947 r
= RREG32_IO(reg
*4);
952 * radeon_atombios_init - init the driver info and callbacks for atombios
954 * @rdev: radeon_device pointer
956 * Initializes the driver info and register access callbacks for the
957 * ATOM interpreter (r4xx+).
958 * Returns 0 on sucess, -ENOMEM on failure.
959 * Called at driver startup.
961 int radeon_atombios_init(struct radeon_device
*rdev
)
963 struct card_info
*atom_card_info
=
964 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
969 rdev
->mode_info
.atom_card_info
= atom_card_info
;
970 atom_card_info
->dev
= rdev
->ddev
;
971 atom_card_info
->reg_read
= cail_reg_read
;
972 atom_card_info
->reg_write
= cail_reg_write
;
973 /* needed for iio ops */
975 atom_card_info
->ioreg_read
= cail_ioreg_read
;
976 atom_card_info
->ioreg_write
= cail_ioreg_write
;
978 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
979 atom_card_info
->ioreg_read
= cail_reg_read
;
980 atom_card_info
->ioreg_write
= cail_reg_write
;
982 atom_card_info
->mc_read
= cail_mc_read
;
983 atom_card_info
->mc_write
= cail_mc_write
;
984 atom_card_info
->pll_read
= cail_pll_read
;
985 atom_card_info
->pll_write
= cail_pll_write
;
987 rdev
->mode_info
.atom_context
= atom_parse(atom_card_info
, rdev
->bios
);
988 if (!rdev
->mode_info
.atom_context
) {
989 radeon_atombios_fini(rdev
);
993 mutex_init(&rdev
->mode_info
.atom_context
->mutex
);
994 mutex_init(&rdev
->mode_info
.atom_context
->scratch_mutex
);
995 radeon_atom_initialize_bios_scratch_regs(rdev
->ddev
);
996 atom_allocate_fb_scratch(rdev
->mode_info
.atom_context
);
1001 * radeon_atombios_fini - free the driver info and callbacks for atombios
1003 * @rdev: radeon_device pointer
1005 * Frees the driver info and register access callbacks for the ATOM
1006 * interpreter (r4xx+).
1007 * Called at driver shutdown.
1009 void radeon_atombios_fini(struct radeon_device
*rdev
)
1011 if (rdev
->mode_info
.atom_context
) {
1012 kfree(rdev
->mode_info
.atom_context
->scratch
);
1014 kfree(rdev
->mode_info
.atom_context
);
1015 rdev
->mode_info
.atom_context
= NULL
;
1016 kfree(rdev
->mode_info
.atom_card_info
);
1017 rdev
->mode_info
.atom_card_info
= NULL
;
1022 * COMBIOS is the bios format prior to ATOM. It provides
1023 * command tables similar to ATOM, but doesn't have a unified
1024 * parser. See radeon_combios.c
1028 * radeon_combios_init - init the driver info for combios
1030 * @rdev: radeon_device pointer
1032 * Initializes the driver info for combios (r1xx-r3xx).
1033 * Returns 0 on sucess.
1034 * Called at driver startup.
1036 int radeon_combios_init(struct radeon_device
*rdev
)
1038 radeon_combios_initialize_bios_scratch_regs(rdev
->ddev
);
1043 * radeon_combios_fini - free the driver info for combios
1045 * @rdev: radeon_device pointer
1047 * Frees the driver info for combios (r1xx-r3xx).
1048 * Called at driver shutdown.
1050 void radeon_combios_fini(struct radeon_device
*rdev
)
1054 /* if we get transitioned to only one device, take VGA back */
1056 * radeon_vga_set_decode - enable/disable vga decode
1058 * @cookie: radeon_device pointer
1059 * @state: enable/disable vga decode
1061 * Enable/disable vga decode (all asics).
1062 * Returns VGA resource flags.
1064 static unsigned int radeon_vga_set_decode(void *cookie
, bool state
)
1066 struct radeon_device
*rdev
= cookie
;
1067 radeon_vga_set_state(rdev
, state
);
1069 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
1070 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1072 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1076 * radeon_check_pot_argument - check that argument is a power of two
1078 * @arg: value to check
1080 * Validates that a certain argument is a power of two (all asics).
1081 * Returns true if argument is valid.
1083 static bool radeon_check_pot_argument(int arg
)
1085 return (arg
& (arg
- 1)) == 0;
1089 * Determine a sensible default GART size according to ASIC family.
1091 * @family ASIC family name
1093 static int radeon_gart_size_auto(enum radeon_family family
)
1095 /* default to a larger gart size on newer asics */
1096 if (family
>= CHIP_TAHITI
)
1098 else if (family
>= CHIP_RV770
)
1105 * radeon_check_arguments - validate module params
1107 * @rdev: radeon_device pointer
1109 * Validates certain module parameters and updates
1110 * the associated values used by the driver (all asics).
1112 static void radeon_check_arguments(struct radeon_device
*rdev
)
1114 /* vramlimit must be a power of two */
1115 if (!radeon_check_pot_argument(radeon_vram_limit
)) {
1116 dev_warn(rdev
->dev
, "vram limit (%d) must be a power of 2\n",
1118 radeon_vram_limit
= 0;
1121 if (radeon_gart_size
== -1) {
1122 radeon_gart_size
= radeon_gart_size_auto(rdev
->family
);
1124 /* gtt size must be power of two and greater or equal to 32M */
1125 if (radeon_gart_size
< 32) {
1126 dev_warn(rdev
->dev
, "gart size (%d) too small\n",
1128 radeon_gart_size
= radeon_gart_size_auto(rdev
->family
);
1129 } else if (!radeon_check_pot_argument(radeon_gart_size
)) {
1130 dev_warn(rdev
->dev
, "gart size (%d) must be a power of 2\n",
1132 radeon_gart_size
= radeon_gart_size_auto(rdev
->family
);
1134 rdev
->mc
.gtt_size
= (uint64_t)radeon_gart_size
<< 20;
1136 /* AGP mode can only be -1, 1, 2, 4, 8 */
1137 switch (radeon_agpmode
) {
1146 dev_warn(rdev
->dev
, "invalid AGP mode %d (valid mode: "
1147 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode
);
1152 if (!radeon_check_pot_argument(radeon_vm_size
)) {
1153 dev_warn(rdev
->dev
, "VM size (%d) must be a power of 2\n",
1158 if (radeon_vm_size
< 1) {
1159 dev_warn(rdev
->dev
, "VM size (%d) too small, min is 1GB\n",
1165 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1167 if (radeon_vm_size
> 1024) {
1168 dev_warn(rdev
->dev
, "VM size (%d) too large, max is 1TB\n",
1173 /* defines number of bits in page table versus page directory,
1174 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1175 * page table and the remaining bits are in the page directory */
1176 if (radeon_vm_block_size
== -1) {
1178 /* Total bits covered by PD + PTs */
1179 unsigned bits
= ilog2(radeon_vm_size
) + 18;
1181 /* Make sure the PD is 4K in size up to 8GB address space.
1182 Above that split equal between PD and PTs */
1183 if (radeon_vm_size
<= 8)
1184 radeon_vm_block_size
= bits
- 9;
1186 radeon_vm_block_size
= (bits
+ 3) / 2;
1188 } else if (radeon_vm_block_size
< 9) {
1189 dev_warn(rdev
->dev
, "VM page table size (%d) too small\n",
1190 radeon_vm_block_size
);
1191 radeon_vm_block_size
= 9;
1194 if (radeon_vm_block_size
> 24 ||
1195 (radeon_vm_size
* 1024) < (1ull << radeon_vm_block_size
)) {
1196 dev_warn(rdev
->dev
, "VM page table size (%d) too large\n",
1197 radeon_vm_block_size
);
1198 radeon_vm_block_size
= 9;
1203 * radeon_switcheroo_set_state - set switcheroo state
1205 * @pdev: pci dev pointer
1206 * @state: vga_switcheroo state
1208 * Callback for the switcheroo driver. Suspends or resumes the
1209 * the asics before or after it is powered up using ACPI methods.
1211 static void radeon_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1213 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1214 struct radeon_device
*rdev
= dev
->dev_private
;
1216 if (radeon_is_px(dev
) && state
== VGA_SWITCHEROO_OFF
)
1219 if (state
== VGA_SWITCHEROO_ON
) {
1220 unsigned d3_delay
= dev
->pdev
->d3_delay
;
1222 printk(KERN_INFO
"radeon: switched on\n");
1223 /* don't suspend or resume card normally */
1224 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1226 if (d3_delay
< 20 && (rdev
->px_quirk_flags
& RADEON_PX_QUIRK_LONG_WAKEUP
))
1227 dev
->pdev
->d3_delay
= 20;
1229 radeon_resume_kms(dev
, true, true);
1231 dev
->pdev
->d3_delay
= d3_delay
;
1233 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1234 drm_kms_helper_poll_enable(dev
);
1236 printk(KERN_INFO
"radeon: switched off\n");
1237 drm_kms_helper_poll_disable(dev
);
1238 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1239 radeon_suspend_kms(dev
, true, true);
1240 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1245 * radeon_switcheroo_can_switch - see if switcheroo state can change
1247 * @pdev: pci dev pointer
1249 * Callback for the switcheroo driver. Check of the switcheroo
1250 * state can be changed.
1251 * Returns true if the state can be changed, false if not.
1253 static bool radeon_switcheroo_can_switch(struct pci_dev
*pdev
)
1255 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1258 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1259 * locking inversion with the driver load path. And the access here is
1260 * completely racy anyway. So don't bother with locking for now.
1262 return dev
->open_count
== 0;
1265 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops
= {
1266 .set_gpu_state
= radeon_switcheroo_set_state
,
1268 .can_switch
= radeon_switcheroo_can_switch
,
1272 * radeon_device_init - initialize the driver
1274 * @rdev: radeon_device pointer
1275 * @pdev: drm dev pointer
1276 * @pdev: pci dev pointer
1277 * @flags: driver flags
1279 * Initializes the driver info and hw (all asics).
1280 * Returns 0 for success or an error on failure.
1281 * Called at driver startup.
1283 int radeon_device_init(struct radeon_device
*rdev
,
1284 struct drm_device
*ddev
,
1285 struct pci_dev
*pdev
,
1290 bool runtime
= false;
1292 rdev
->shutdown
= false;
1293 rdev
->dev
= &pdev
->dev
;
1296 rdev
->flags
= flags
;
1297 rdev
->family
= flags
& RADEON_FAMILY_MASK
;
1298 rdev
->is_atom_bios
= false;
1299 rdev
->usec_timeout
= RADEON_MAX_USEC_TIMEOUT
;
1300 rdev
->mc
.gtt_size
= 512 * 1024 * 1024;
1301 rdev
->accel_working
= false;
1302 /* set up ring ids */
1303 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
1304 rdev
->ring
[i
].idx
= i
;
1306 rdev
->fence_context
= fence_context_alloc(RADEON_NUM_RINGS
);
1308 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1309 radeon_family_name
[rdev
->family
], pdev
->vendor
, pdev
->device
,
1310 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
1312 /* mutex initialization are all done here so we
1313 * can recall function without having locking issues */
1314 mutex_init(&rdev
->ring_lock
);
1315 mutex_init(&rdev
->dc_hw_i2c_mutex
);
1316 atomic_set(&rdev
->ih
.lock
, 0);
1317 mutex_init(&rdev
->gem
.mutex
);
1318 mutex_init(&rdev
->pm
.mutex
);
1319 mutex_init(&rdev
->gpu_clock_mutex
);
1320 mutex_init(&rdev
->srbm_mutex
);
1321 mutex_init(&rdev
->grbm_idx_mutex
);
1322 init_rwsem(&rdev
->pm
.mclk_lock
);
1323 init_rwsem(&rdev
->exclusive_lock
);
1324 init_waitqueue_head(&rdev
->irq
.vblank_queue
);
1325 mutex_init(&rdev
->mn_lock
);
1326 hash_init(rdev
->mn_hash
);
1327 r
= radeon_gem_init(rdev
);
1331 radeon_check_arguments(rdev
);
1332 /* Adjust VM size here.
1333 * Max GPUVM size for cayman+ is 40 bits.
1335 rdev
->vm_manager
.max_pfn
= radeon_vm_size
<< 18;
1337 /* Set asic functions */
1338 r
= radeon_asic_init(rdev
);
1342 /* all of the newer IGP chips have an internal gart
1343 * However some rs4xx report as AGP, so remove that here.
1345 if ((rdev
->family
>= CHIP_RS400
) &&
1346 (rdev
->flags
& RADEON_IS_IGP
)) {
1347 rdev
->flags
&= ~RADEON_IS_AGP
;
1350 if (rdev
->flags
& RADEON_IS_AGP
&& radeon_agpmode
== -1) {
1351 radeon_agp_disable(rdev
);
1354 /* Set the internal MC address mask
1355 * This is the max address of the GPU's
1356 * internal address space.
1358 if (rdev
->family
>= CHIP_CAYMAN
)
1359 rdev
->mc
.mc_mask
= 0xffffffffffULL
; /* 40 bit MC */
1360 else if (rdev
->family
>= CHIP_CEDAR
)
1361 rdev
->mc
.mc_mask
= 0xfffffffffULL
; /* 36 bit MC */
1363 rdev
->mc
.mc_mask
= 0xffffffffULL
; /* 32 bit MC */
1365 /* set DMA mask + need_dma32 flags.
1366 * PCIE - can handle 40-bits.
1367 * IGP - can handle 40-bits
1368 * AGP - generally dma32 is safest
1369 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1371 rdev
->need_dma32
= false;
1372 if (rdev
->flags
& RADEON_IS_AGP
)
1373 rdev
->need_dma32
= true;
1374 if ((rdev
->flags
& RADEON_IS_PCI
) &&
1375 (rdev
->family
<= CHIP_RS740
))
1376 rdev
->need_dma32
= true;
1378 dma_bits
= rdev
->need_dma32
? 32 : 40;
1379 r
= pci_set_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
1381 rdev
->need_dma32
= true;
1383 printk(KERN_WARNING
"radeon: No suitable DMA available.\n");
1385 r
= pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
1387 pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(32));
1388 printk(KERN_WARNING
"radeon: No coherent DMA available.\n");
1391 /* Registers mapping */
1392 /* TODO: block userspace mapping of io register */
1393 spin_lock_init(&rdev
->mmio_idx_lock
);
1394 spin_lock_init(&rdev
->smc_idx_lock
);
1395 spin_lock_init(&rdev
->pll_idx_lock
);
1396 spin_lock_init(&rdev
->mc_idx_lock
);
1397 spin_lock_init(&rdev
->pcie_idx_lock
);
1398 spin_lock_init(&rdev
->pciep_idx_lock
);
1399 spin_lock_init(&rdev
->pif_idx_lock
);
1400 spin_lock_init(&rdev
->cg_idx_lock
);
1401 spin_lock_init(&rdev
->uvd_idx_lock
);
1402 spin_lock_init(&rdev
->rcu_idx_lock
);
1403 spin_lock_init(&rdev
->didt_idx_lock
);
1404 spin_lock_init(&rdev
->end_idx_lock
);
1405 if (rdev
->family
>= CHIP_BONAIRE
) {
1406 rdev
->rmmio_base
= pci_resource_start(rdev
->pdev
, 5);
1407 rdev
->rmmio_size
= pci_resource_len(rdev
->pdev
, 5);
1409 rdev
->rmmio_base
= pci_resource_start(rdev
->pdev
, 2);
1410 rdev
->rmmio_size
= pci_resource_len(rdev
->pdev
, 2);
1412 rdev
->rmmio
= ioremap(rdev
->rmmio_base
, rdev
->rmmio_size
);
1413 if (rdev
->rmmio
== NULL
) {
1416 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev
->rmmio_base
);
1417 DRM_INFO("register mmio size: %u\n", (unsigned)rdev
->rmmio_size
);
1419 /* doorbell bar mapping */
1420 if (rdev
->family
>= CHIP_BONAIRE
)
1421 radeon_doorbell_init(rdev
);
1423 /* io port mapping */
1424 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1425 if (pci_resource_flags(rdev
->pdev
, i
) & IORESOURCE_IO
) {
1426 rdev
->rio_mem_size
= pci_resource_len(rdev
->pdev
, i
);
1427 rdev
->rio_mem
= pci_iomap(rdev
->pdev
, i
, rdev
->rio_mem_size
);
1431 if (rdev
->rio_mem
== NULL
)
1432 DRM_ERROR("Unable to find PCI I/O BAR\n");
1434 if (rdev
->flags
& RADEON_IS_PX
)
1435 radeon_device_handle_px_quirks(rdev
);
1437 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1438 /* this will fail for cards that aren't VGA class devices, just
1440 vga_client_register(rdev
->pdev
, rdev
, NULL
, radeon_vga_set_decode
);
1442 if ((rdev
->flags
& RADEON_IS_PX
) && radeon_has_atpx_dgpu_power_cntl())
1444 vga_switcheroo_register_client(rdev
->pdev
, &radeon_switcheroo_ops
, runtime
);
1446 vga_switcheroo_init_domain_pm_ops(rdev
->dev
, &rdev
->vga_pm_domain
);
1448 r
= radeon_init(rdev
);
1452 r
= radeon_gem_debugfs_init(rdev
);
1454 DRM_ERROR("registering gem debugfs failed (%d).\n", r
);
1457 r
= radeon_mst_debugfs_init(rdev
);
1459 DRM_ERROR("registering mst debugfs failed (%d).\n", r
);
1462 if (rdev
->flags
& RADEON_IS_AGP
&& !rdev
->accel_working
) {
1463 /* Acceleration not working on AGP card try again
1464 * with fallback to PCI or PCIE GART
1466 radeon_asic_reset(rdev
);
1468 radeon_agp_disable(rdev
);
1469 r
= radeon_init(rdev
);
1474 r
= radeon_ib_ring_tests(rdev
);
1476 DRM_ERROR("ib ring test failed (%d).\n", r
);
1479 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted
1480 * after the CP ring have chew one packet at least. Hence here we stop
1481 * and restart DPM after the radeon_ib_ring_tests().
1483 if (rdev
->pm
.dpm_enabled
&&
1484 (rdev
->pm
.pm_method
== PM_METHOD_DPM
) &&
1485 (rdev
->family
== CHIP_TURKS
) &&
1486 (rdev
->flags
& RADEON_IS_MOBILITY
)) {
1487 mutex_lock(&rdev
->pm
.mutex
);
1488 radeon_dpm_disable(rdev
);
1489 radeon_dpm_enable(rdev
);
1490 mutex_unlock(&rdev
->pm
.mutex
);
1493 if ((radeon_testing
& 1)) {
1494 if (rdev
->accel_working
)
1495 radeon_test_moves(rdev
);
1497 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1499 if ((radeon_testing
& 2)) {
1500 if (rdev
->accel_working
)
1501 radeon_test_syncing(rdev
);
1503 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1505 if (radeon_benchmarking
) {
1506 if (rdev
->accel_working
)
1507 radeon_benchmark(rdev
, radeon_benchmarking
);
1509 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1515 vga_switcheroo_fini_domain_pm_ops(rdev
->dev
);
1519 static void radeon_debugfs_remove_files(struct radeon_device
*rdev
);
1522 * radeon_device_fini - tear down the driver
1524 * @rdev: radeon_device pointer
1526 * Tear down the driver info (all asics).
1527 * Called at driver shutdown.
1529 void radeon_device_fini(struct radeon_device
*rdev
)
1531 DRM_INFO("radeon: finishing device.\n");
1532 rdev
->shutdown
= true;
1533 /* evict vram memory */
1534 radeon_bo_evict_vram(rdev
);
1536 vga_switcheroo_unregister_client(rdev
->pdev
);
1537 if (rdev
->flags
& RADEON_IS_PX
)
1538 vga_switcheroo_fini_domain_pm_ops(rdev
->dev
);
1539 vga_client_register(rdev
->pdev
, NULL
, NULL
, NULL
);
1541 pci_iounmap(rdev
->pdev
, rdev
->rio_mem
);
1542 rdev
->rio_mem
= NULL
;
1543 iounmap(rdev
->rmmio
);
1545 if (rdev
->family
>= CHIP_BONAIRE
)
1546 radeon_doorbell_fini(rdev
);
1547 radeon_debugfs_remove_files(rdev
);
1555 * radeon_suspend_kms - initiate device suspend
1557 * @pdev: drm dev pointer
1558 * @state: suspend state
1560 * Puts the hw in the suspend state (all asics).
1561 * Returns 0 for success or an error on failure.
1562 * Called at driver suspend.
1564 int radeon_suspend_kms(struct drm_device
*dev
, bool suspend
, bool fbcon
)
1566 struct radeon_device
*rdev
;
1567 struct drm_crtc
*crtc
;
1568 struct drm_connector
*connector
;
1571 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
1575 rdev
= dev
->dev_private
;
1577 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1580 drm_kms_helper_poll_disable(dev
);
1582 drm_modeset_lock_all(dev
);
1583 /* turn off display hw */
1584 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1585 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_OFF
);
1587 drm_modeset_unlock_all(dev
);
1589 /* unpin the front buffers and cursors */
1590 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1591 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1592 struct radeon_framebuffer
*rfb
= to_radeon_framebuffer(crtc
->primary
->fb
);
1593 struct radeon_bo
*robj
;
1595 if (radeon_crtc
->cursor_bo
) {
1596 struct radeon_bo
*robj
= gem_to_radeon_bo(radeon_crtc
->cursor_bo
);
1597 r
= radeon_bo_reserve(robj
, false);
1599 radeon_bo_unpin(robj
);
1600 radeon_bo_unreserve(robj
);
1604 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
1607 robj
= gem_to_radeon_bo(rfb
->obj
);
1608 /* don't unpin kernel fb objects */
1609 if (!radeon_fbdev_robj_is_fb(rdev
, robj
)) {
1610 r
= radeon_bo_reserve(robj
, false);
1612 radeon_bo_unpin(robj
);
1613 radeon_bo_unreserve(robj
);
1617 /* evict vram memory */
1618 radeon_bo_evict_vram(rdev
);
1620 /* wait for gpu to finish processing current batch */
1621 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
1622 r
= radeon_fence_wait_empty(rdev
, i
);
1624 /* delay GPU reset to resume */
1625 radeon_fence_driver_force_completion(rdev
, i
);
1629 radeon_save_bios_scratch_regs(rdev
);
1631 radeon_suspend(rdev
);
1632 radeon_hpd_fini(rdev
);
1633 /* evict remaining vram memory */
1634 radeon_bo_evict_vram(rdev
);
1636 radeon_agp_suspend(rdev
);
1638 pci_save_state(dev
->pdev
);
1640 /* Shut down the device */
1641 pci_disable_device(dev
->pdev
);
1642 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
1647 radeon_fbdev_set_suspend(rdev
, 1);
1654 * radeon_resume_kms - initiate device resume
1656 * @pdev: drm dev pointer
1658 * Bring the hw back to operating state (all asics).
1659 * Returns 0 for success or an error on failure.
1660 * Called at driver resume.
1662 int radeon_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
)
1664 struct drm_connector
*connector
;
1665 struct radeon_device
*rdev
= dev
->dev_private
;
1666 struct drm_crtc
*crtc
;
1669 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1676 pci_set_power_state(dev
->pdev
, PCI_D0
);
1677 pci_restore_state(dev
->pdev
);
1678 if (pci_enable_device(dev
->pdev
)) {
1684 /* resume AGP if in use */
1685 radeon_agp_resume(rdev
);
1686 radeon_resume(rdev
);
1688 r
= radeon_ib_ring_tests(rdev
);
1690 DRM_ERROR("ib ring test failed (%d).\n", r
);
1692 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
) {
1693 /* do dpm late init */
1694 r
= radeon_pm_late_init(rdev
);
1696 rdev
->pm
.dpm_enabled
= false;
1697 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1700 /* resume old pm late */
1701 radeon_pm_resume(rdev
);
1704 radeon_restore_bios_scratch_regs(rdev
);
1707 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1708 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1710 if (radeon_crtc
->cursor_bo
) {
1711 struct radeon_bo
*robj
= gem_to_radeon_bo(radeon_crtc
->cursor_bo
);
1712 r
= radeon_bo_reserve(robj
, false);
1714 /* Only 27 bit offset for legacy cursor */
1715 r
= radeon_bo_pin_restricted(robj
,
1716 RADEON_GEM_DOMAIN_VRAM
,
1717 ASIC_IS_AVIVO(rdev
) ?
1719 &radeon_crtc
->cursor_addr
);
1721 DRM_ERROR("Failed to pin cursor BO (%d)\n", r
);
1722 radeon_bo_unreserve(robj
);
1727 /* init dig PHYs, disp eng pll */
1728 if (rdev
->is_atom_bios
) {
1729 radeon_atom_encoder_init(rdev
);
1730 radeon_atom_disp_eng_pll_init(rdev
);
1731 /* turn on the BL */
1732 if (rdev
->mode_info
.bl_encoder
) {
1733 u8 bl_level
= radeon_get_backlight_level(rdev
,
1734 rdev
->mode_info
.bl_encoder
);
1735 radeon_set_backlight_level(rdev
, rdev
->mode_info
.bl_encoder
,
1739 /* reset hpd state */
1740 radeon_hpd_init(rdev
);
1741 /* blat the mode back in */
1743 drm_helper_resume_force_mode(dev
);
1744 /* turn on display hw */
1745 drm_modeset_lock_all(dev
);
1746 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1747 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_ON
);
1749 drm_modeset_unlock_all(dev
);
1752 drm_kms_helper_poll_enable(dev
);
1754 /* set the power state here in case we are a PX system or headless */
1755 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
)
1756 radeon_pm_compute_clocks(rdev
);
1759 radeon_fbdev_set_suspend(rdev
, 0);
1767 * radeon_gpu_reset - reset the asic
1769 * @rdev: radeon device pointer
1771 * Attempt the reset the GPU if it has hung (all asics).
1772 * Returns 0 for success or an error on failure.
1774 int radeon_gpu_reset(struct radeon_device
*rdev
)
1776 unsigned ring_sizes
[RADEON_NUM_RINGS
];
1777 uint32_t *ring_data
[RADEON_NUM_RINGS
];
1784 down_write(&rdev
->exclusive_lock
);
1786 if (!rdev
->needs_reset
) {
1787 up_write(&rdev
->exclusive_lock
);
1791 atomic_inc(&rdev
->gpu_reset_counter
);
1793 radeon_save_bios_scratch_regs(rdev
);
1795 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
1796 radeon_suspend(rdev
);
1797 radeon_hpd_fini(rdev
);
1799 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1800 ring_sizes
[i
] = radeon_ring_backup(rdev
, &rdev
->ring
[i
],
1802 if (ring_sizes
[i
]) {
1804 dev_info(rdev
->dev
, "Saved %d dwords of commands "
1805 "on ring %d.\n", ring_sizes
[i
], i
);
1809 r
= radeon_asic_reset(rdev
);
1811 dev_info(rdev
->dev
, "GPU reset succeeded, trying to resume\n");
1812 radeon_resume(rdev
);
1815 radeon_restore_bios_scratch_regs(rdev
);
1817 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1818 if (!r
&& ring_data
[i
]) {
1819 radeon_ring_restore(rdev
, &rdev
->ring
[i
],
1820 ring_sizes
[i
], ring_data
[i
]);
1822 radeon_fence_driver_force_completion(rdev
, i
);
1823 kfree(ring_data
[i
]);
1827 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
) {
1828 /* do dpm late init */
1829 r
= radeon_pm_late_init(rdev
);
1831 rdev
->pm
.dpm_enabled
= false;
1832 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1835 /* resume old pm late */
1836 radeon_pm_resume(rdev
);
1839 /* init dig PHYs, disp eng pll */
1840 if (rdev
->is_atom_bios
) {
1841 radeon_atom_encoder_init(rdev
);
1842 radeon_atom_disp_eng_pll_init(rdev
);
1843 /* turn on the BL */
1844 if (rdev
->mode_info
.bl_encoder
) {
1845 u8 bl_level
= radeon_get_backlight_level(rdev
,
1846 rdev
->mode_info
.bl_encoder
);
1847 radeon_set_backlight_level(rdev
, rdev
->mode_info
.bl_encoder
,
1851 /* reset hpd state */
1852 radeon_hpd_init(rdev
);
1854 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
1856 rdev
->in_reset
= true;
1857 rdev
->needs_reset
= false;
1859 downgrade_write(&rdev
->exclusive_lock
);
1861 drm_helper_resume_force_mode(rdev
->ddev
);
1863 /* set the power state here in case we are a PX system or headless */
1864 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
)
1865 radeon_pm_compute_clocks(rdev
);
1868 r
= radeon_ib_ring_tests(rdev
);
1872 /* bad news, how to tell it to userspace ? */
1873 dev_info(rdev
->dev
, "GPU reset failed\n");
1876 rdev
->needs_reset
= r
== -EAGAIN
;
1877 rdev
->in_reset
= false;
1879 up_read(&rdev
->exclusive_lock
);
1887 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
1888 struct drm_info_list
*files
,
1893 for (i
= 0; i
< rdev
->debugfs_count
; i
++) {
1894 if (rdev
->debugfs
[i
].files
== files
) {
1895 /* Already registered */
1900 i
= rdev
->debugfs_count
+ 1;
1901 if (i
> RADEON_DEBUGFS_MAX_COMPONENTS
) {
1902 DRM_ERROR("Reached maximum number of debugfs components.\n");
1903 DRM_ERROR("Report so we increase "
1904 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1907 rdev
->debugfs
[rdev
->debugfs_count
].files
= files
;
1908 rdev
->debugfs
[rdev
->debugfs_count
].num_files
= nfiles
;
1909 rdev
->debugfs_count
= i
;
1910 #if defined(CONFIG_DEBUG_FS)
1911 drm_debugfs_create_files(files
, nfiles
,
1912 rdev
->ddev
->control
->debugfs_root
,
1913 rdev
->ddev
->control
);
1914 drm_debugfs_create_files(files
, nfiles
,
1915 rdev
->ddev
->primary
->debugfs_root
,
1916 rdev
->ddev
->primary
);
1921 static void radeon_debugfs_remove_files(struct radeon_device
*rdev
)
1923 #if defined(CONFIG_DEBUG_FS)
1926 for (i
= 0; i
< rdev
->debugfs_count
; i
++) {
1927 drm_debugfs_remove_files(rdev
->debugfs
[i
].files
,
1928 rdev
->debugfs
[i
].num_files
,
1929 rdev
->ddev
->control
);
1930 drm_debugfs_remove_files(rdev
->debugfs
[i
].files
,
1931 rdev
->debugfs
[i
].num_files
,
1932 rdev
->ddev
->primary
);
1937 #if defined(CONFIG_DEBUG_FS)
1938 int radeon_debugfs_init(struct drm_minor
*minor
)
1943 void radeon_debugfs_cleanup(struct drm_minor
*minor
)