2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include <linux/efi.h>
36 #include "radeon_reg.h"
40 static const char radeon_family_name
[][16] = {
100 * Clear GPU surface registers.
102 void radeon_surface_init(struct radeon_device
*rdev
)
104 /* FIXME: check this out */
105 if (rdev
->family
< CHIP_R600
) {
108 for (i
= 0; i
< RADEON_GEM_MAX_SURFACES
; i
++) {
109 if (rdev
->surface_regs
[i
].bo
)
110 radeon_bo_get_surface_reg(rdev
->surface_regs
[i
].bo
);
112 radeon_clear_surface_reg(rdev
, i
);
114 /* enable surfaces */
115 WREG32(RADEON_SURFACE_CNTL
, 0);
120 * GPU scratch registers helpers function.
122 void radeon_scratch_init(struct radeon_device
*rdev
)
126 /* FIXME: check this out */
127 if (rdev
->family
< CHIP_R300
) {
128 rdev
->scratch
.num_reg
= 5;
130 rdev
->scratch
.num_reg
= 7;
132 rdev
->scratch
.reg_base
= RADEON_SCRATCH_REG0
;
133 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
134 rdev
->scratch
.free
[i
] = true;
135 rdev
->scratch
.reg
[i
] = rdev
->scratch
.reg_base
+ (i
* 4);
139 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
)
143 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
144 if (rdev
->scratch
.free
[i
]) {
145 rdev
->scratch
.free
[i
] = false;
146 *reg
= rdev
->scratch
.reg
[i
];
153 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
)
157 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
158 if (rdev
->scratch
.reg
[i
] == reg
) {
159 rdev
->scratch
.free
[i
] = true;
165 void radeon_wb_disable(struct radeon_device
*rdev
)
169 if (rdev
->wb
.wb_obj
) {
170 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
171 if (unlikely(r
!= 0))
173 radeon_bo_kunmap(rdev
->wb
.wb_obj
);
174 radeon_bo_unpin(rdev
->wb
.wb_obj
);
175 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
177 rdev
->wb
.enabled
= false;
180 void radeon_wb_fini(struct radeon_device
*rdev
)
182 radeon_wb_disable(rdev
);
183 if (rdev
->wb
.wb_obj
) {
184 radeon_bo_unref(&rdev
->wb
.wb_obj
);
186 rdev
->wb
.wb_obj
= NULL
;
190 int radeon_wb_init(struct radeon_device
*rdev
)
194 if (rdev
->wb
.wb_obj
== NULL
) {
195 r
= radeon_bo_create(rdev
, RADEON_GPU_PAGE_SIZE
, PAGE_SIZE
, true,
196 RADEON_GEM_DOMAIN_GTT
, &rdev
->wb
.wb_obj
);
198 dev_warn(rdev
->dev
, "(%d) create WB bo failed\n", r
);
202 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
203 if (unlikely(r
!= 0)) {
204 radeon_wb_fini(rdev
);
207 r
= radeon_bo_pin(rdev
->wb
.wb_obj
, RADEON_GEM_DOMAIN_GTT
,
210 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
211 dev_warn(rdev
->dev
, "(%d) pin WB bo failed\n", r
);
212 radeon_wb_fini(rdev
);
215 r
= radeon_bo_kmap(rdev
->wb
.wb_obj
, (void **)&rdev
->wb
.wb
);
216 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
218 dev_warn(rdev
->dev
, "(%d) map WB bo failed\n", r
);
219 radeon_wb_fini(rdev
);
223 /* clear wb memory */
224 memset((char *)rdev
->wb
.wb
, 0, RADEON_GPU_PAGE_SIZE
);
225 /* disable event_write fences */
226 rdev
->wb
.use_event
= false;
227 /* disabled via module param */
228 if (radeon_no_wb
== 1) {
229 rdev
->wb
.enabled
= false;
231 if (rdev
->flags
& RADEON_IS_AGP
) {
232 /* often unreliable on AGP */
233 rdev
->wb
.enabled
= false;
234 } else if (rdev
->family
< CHIP_R300
) {
235 /* often unreliable on pre-r300 */
236 rdev
->wb
.enabled
= false;
238 rdev
->wb
.enabled
= true;
239 /* event_write fences are only available on r600+ */
240 if (rdev
->family
>= CHIP_R600
) {
241 rdev
->wb
.use_event
= true;
245 /* always use writeback/events on NI, APUs */
246 if (rdev
->family
>= CHIP_PALM
) {
247 rdev
->wb
.enabled
= true;
248 rdev
->wb
.use_event
= true;
251 dev_info(rdev
->dev
, "WB %sabled\n", rdev
->wb
.enabled
? "en" : "dis");
257 * radeon_vram_location - try to find VRAM location
258 * @rdev: radeon device structure holding all necessary informations
259 * @mc: memory controller structure holding memory informations
260 * @base: base address at which to put VRAM
262 * Function will place try to place VRAM at base address provided
263 * as parameter (which is so far either PCI aperture address or
264 * for IGP TOM base address).
266 * If there is not enough space to fit the unvisible VRAM in the 32bits
267 * address space then we limit the VRAM size to the aperture.
269 * If we are using AGP and if the AGP aperture doesn't allow us to have
270 * room for all the VRAM than we restrict the VRAM to the PCI aperture
271 * size and print a warning.
273 * This function will never fails, worst case are limiting VRAM.
275 * Note: GTT start, end, size should be initialized before calling this
276 * function on AGP platform.
278 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
279 * this shouldn't be a problem as we are using the PCI aperture as a reference.
280 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
283 * Note: we use mc_vram_size as on some board we need to program the mc to
284 * cover the whole aperture even if VRAM size is inferior to aperture size
285 * Novell bug 204882 + along with lots of ubuntu ones
287 * Note: when limiting vram it's safe to overwritte real_vram_size because
288 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
289 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
292 * Note: IGP TOM addr should be the same as the aperture addr, we don't
293 * explicitly check for that thought.
295 * FIXME: when reducing VRAM size align new size on power of 2.
297 void radeon_vram_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
, u64 base
)
299 mc
->vram_start
= base
;
300 if (mc
->mc_vram_size
> (0xFFFFFFFF - base
+ 1)) {
301 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
302 mc
->real_vram_size
= mc
->aper_size
;
303 mc
->mc_vram_size
= mc
->aper_size
;
305 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
306 if (rdev
->flags
& RADEON_IS_AGP
&& mc
->vram_end
> mc
->gtt_start
&& mc
->vram_start
<= mc
->gtt_end
) {
307 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
308 mc
->real_vram_size
= mc
->aper_size
;
309 mc
->mc_vram_size
= mc
->aper_size
;
311 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
312 if (radeon_vram_limit
&& radeon_vram_limit
< mc
->real_vram_size
)
313 mc
->real_vram_size
= radeon_vram_limit
;
314 dev_info(rdev
->dev
, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
315 mc
->mc_vram_size
>> 20, mc
->vram_start
,
316 mc
->vram_end
, mc
->real_vram_size
>> 20);
320 * radeon_gtt_location - try to find GTT location
321 * @rdev: radeon device structure holding all necessary informations
322 * @mc: memory controller structure holding memory informations
324 * Function will place try to place GTT before or after VRAM.
326 * If GTT size is bigger than space left then we ajust GTT size.
327 * Thus function will never fails.
329 * FIXME: when reducing GTT size align new size on power of 2.
331 void radeon_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
333 u64 size_af
, size_bf
;
335 size_af
= ((0xFFFFFFFF - mc
->vram_end
) + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
336 size_bf
= mc
->vram_start
& ~mc
->gtt_base_align
;
337 if (size_bf
> size_af
) {
338 if (mc
->gtt_size
> size_bf
) {
339 dev_warn(rdev
->dev
, "limiting GTT\n");
340 mc
->gtt_size
= size_bf
;
342 mc
->gtt_start
= (mc
->vram_start
& ~mc
->gtt_base_align
) - mc
->gtt_size
;
344 if (mc
->gtt_size
> size_af
) {
345 dev_warn(rdev
->dev
, "limiting GTT\n");
346 mc
->gtt_size
= size_af
;
348 mc
->gtt_start
= (mc
->vram_end
+ 1 + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
350 mc
->gtt_end
= mc
->gtt_start
+ mc
->gtt_size
- 1;
351 dev_info(rdev
->dev
, "GTT: %lluM 0x%016llX - 0x%016llX\n",
352 mc
->gtt_size
>> 20, mc
->gtt_start
, mc
->gtt_end
);
356 * GPU helpers function.
358 bool radeon_card_posted(struct radeon_device
*rdev
)
362 if (efi_enabled
&& rdev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
)
365 /* first check CRTCs */
366 if (ASIC_IS_DCE41(rdev
)) {
367 reg
= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) |
368 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
369 if (reg
& EVERGREEN_CRTC_MASTER_EN
)
371 } else if (ASIC_IS_DCE4(rdev
)) {
372 reg
= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) |
373 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
) |
374 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) |
375 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
) |
376 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) |
377 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
378 if (reg
& EVERGREEN_CRTC_MASTER_EN
)
380 } else if (ASIC_IS_AVIVO(rdev
)) {
381 reg
= RREG32(AVIVO_D1CRTC_CONTROL
) |
382 RREG32(AVIVO_D2CRTC_CONTROL
);
383 if (reg
& AVIVO_CRTC_EN
) {
387 reg
= RREG32(RADEON_CRTC_GEN_CNTL
) |
388 RREG32(RADEON_CRTC2_GEN_CNTL
);
389 if (reg
& RADEON_CRTC_EN
) {
394 /* then check MEM_SIZE, in case the crtcs are off */
395 if (rdev
->family
>= CHIP_R600
)
396 reg
= RREG32(R600_CONFIG_MEMSIZE
);
398 reg
= RREG32(RADEON_CONFIG_MEMSIZE
);
407 void radeon_update_bandwidth_info(struct radeon_device
*rdev
)
410 u32 sclk
= rdev
->pm
.current_sclk
;
411 u32 mclk
= rdev
->pm
.current_mclk
;
413 /* sclk/mclk in Mhz */
414 a
.full
= dfixed_const(100);
415 rdev
->pm
.sclk
.full
= dfixed_const(sclk
);
416 rdev
->pm
.sclk
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
417 rdev
->pm
.mclk
.full
= dfixed_const(mclk
);
418 rdev
->pm
.mclk
.full
= dfixed_div(rdev
->pm
.mclk
, a
);
420 if (rdev
->flags
& RADEON_IS_IGP
) {
421 a
.full
= dfixed_const(16);
422 /* core_bandwidth = sclk(Mhz) * 16 */
423 rdev
->pm
.core_bandwidth
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
427 bool radeon_boot_test_post_card(struct radeon_device
*rdev
)
429 if (radeon_card_posted(rdev
))
433 DRM_INFO("GPU not posted. posting now...\n");
434 if (rdev
->is_atom_bios
)
435 atom_asic_init(rdev
->mode_info
.atom_context
);
437 radeon_combios_asic_init(rdev
->ddev
);
440 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
445 int radeon_dummy_page_init(struct radeon_device
*rdev
)
447 if (rdev
->dummy_page
.page
)
449 rdev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
450 if (rdev
->dummy_page
.page
== NULL
)
452 rdev
->dummy_page
.addr
= pci_map_page(rdev
->pdev
, rdev
->dummy_page
.page
,
453 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
454 if (pci_dma_mapping_error(rdev
->pdev
, rdev
->dummy_page
.addr
)) {
455 dev_err(&rdev
->pdev
->dev
, "Failed to DMA MAP the dummy page\n");
456 __free_page(rdev
->dummy_page
.page
);
457 rdev
->dummy_page
.page
= NULL
;
463 void radeon_dummy_page_fini(struct radeon_device
*rdev
)
465 if (rdev
->dummy_page
.page
== NULL
)
467 pci_unmap_page(rdev
->pdev
, rdev
->dummy_page
.addr
,
468 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
469 __free_page(rdev
->dummy_page
.page
);
470 rdev
->dummy_page
.page
= NULL
;
474 /* ATOM accessor methods */
475 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
477 struct radeon_device
*rdev
= info
->dev
->dev_private
;
480 r
= rdev
->pll_rreg(rdev
, reg
);
484 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
486 struct radeon_device
*rdev
= info
->dev
->dev_private
;
488 rdev
->pll_wreg(rdev
, reg
, val
);
491 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
493 struct radeon_device
*rdev
= info
->dev
->dev_private
;
496 r
= rdev
->mc_rreg(rdev
, reg
);
500 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
502 struct radeon_device
*rdev
= info
->dev
->dev_private
;
504 rdev
->mc_wreg(rdev
, reg
, val
);
507 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
509 struct radeon_device
*rdev
= info
->dev
->dev_private
;
514 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
516 struct radeon_device
*rdev
= info
->dev
->dev_private
;
523 static void cail_ioreg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
525 struct radeon_device
*rdev
= info
->dev
->dev_private
;
527 WREG32_IO(reg
*4, val
);
530 static uint32_t cail_ioreg_read(struct card_info
*info
, uint32_t reg
)
532 struct radeon_device
*rdev
= info
->dev
->dev_private
;
535 r
= RREG32_IO(reg
*4);
539 int radeon_atombios_init(struct radeon_device
*rdev
)
541 struct card_info
*atom_card_info
=
542 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
547 rdev
->mode_info
.atom_card_info
= atom_card_info
;
548 atom_card_info
->dev
= rdev
->ddev
;
549 atom_card_info
->reg_read
= cail_reg_read
;
550 atom_card_info
->reg_write
= cail_reg_write
;
551 /* needed for iio ops */
553 atom_card_info
->ioreg_read
= cail_ioreg_read
;
554 atom_card_info
->ioreg_write
= cail_ioreg_write
;
556 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
557 atom_card_info
->ioreg_read
= cail_reg_read
;
558 atom_card_info
->ioreg_write
= cail_reg_write
;
560 atom_card_info
->mc_read
= cail_mc_read
;
561 atom_card_info
->mc_write
= cail_mc_write
;
562 atom_card_info
->pll_read
= cail_pll_read
;
563 atom_card_info
->pll_write
= cail_pll_write
;
565 rdev
->mode_info
.atom_context
= atom_parse(atom_card_info
, rdev
->bios
);
566 mutex_init(&rdev
->mode_info
.atom_context
->mutex
);
567 radeon_atom_initialize_bios_scratch_regs(rdev
->ddev
);
568 atom_allocate_fb_scratch(rdev
->mode_info
.atom_context
);
572 void radeon_atombios_fini(struct radeon_device
*rdev
)
574 if (rdev
->mode_info
.atom_context
) {
575 kfree(rdev
->mode_info
.atom_context
->scratch
);
576 kfree(rdev
->mode_info
.atom_context
);
578 kfree(rdev
->mode_info
.atom_card_info
);
581 int radeon_combios_init(struct radeon_device
*rdev
)
583 radeon_combios_initialize_bios_scratch_regs(rdev
->ddev
);
587 void radeon_combios_fini(struct radeon_device
*rdev
)
591 /* if we get transitioned to only one device, tak VGA back */
592 static unsigned int radeon_vga_set_decode(void *cookie
, bool state
)
594 struct radeon_device
*rdev
= cookie
;
595 radeon_vga_set_state(rdev
, state
);
597 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
598 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
600 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
603 void radeon_check_arguments(struct radeon_device
*rdev
)
605 /* vramlimit must be a power of two */
606 switch (radeon_vram_limit
) {
621 dev_warn(rdev
->dev
, "vram limit (%d) must be a power of 2\n",
623 radeon_vram_limit
= 0;
626 radeon_vram_limit
= radeon_vram_limit
<< 20;
627 /* gtt size must be power of two and greater or equal to 32M */
628 switch (radeon_gart_size
) {
632 dev_warn(rdev
->dev
, "gart size (%d) too small forcing to 512M\n",
634 radeon_gart_size
= 512;
646 dev_warn(rdev
->dev
, "gart size (%d) must be a power of 2\n",
648 radeon_gart_size
= 512;
651 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
652 /* AGP mode can only be -1, 1, 2, 4, 8 */
653 switch (radeon_agpmode
) {
662 dev_warn(rdev
->dev
, "invalid AGP mode %d (valid mode: "
663 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode
);
669 static void radeon_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
671 struct drm_device
*dev
= pci_get_drvdata(pdev
);
672 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
673 if (state
== VGA_SWITCHEROO_ON
) {
674 printk(KERN_INFO
"radeon: switched on\n");
675 /* don't suspend or resume card normally */
676 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
677 radeon_resume_kms(dev
);
678 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
679 drm_kms_helper_poll_enable(dev
);
681 printk(KERN_INFO
"radeon: switched off\n");
682 drm_kms_helper_poll_disable(dev
);
683 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
684 radeon_suspend_kms(dev
, pmm
);
685 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
689 static bool radeon_switcheroo_can_switch(struct pci_dev
*pdev
)
691 struct drm_device
*dev
= pci_get_drvdata(pdev
);
694 spin_lock(&dev
->count_lock
);
695 can_switch
= (dev
->open_count
== 0);
696 spin_unlock(&dev
->count_lock
);
701 int radeon_device_init(struct radeon_device
*rdev
,
702 struct drm_device
*ddev
,
703 struct pci_dev
*pdev
,
709 rdev
->shutdown
= false;
710 rdev
->dev
= &pdev
->dev
;
714 rdev
->family
= flags
& RADEON_FAMILY_MASK
;
715 rdev
->is_atom_bios
= false;
716 rdev
->usec_timeout
= RADEON_MAX_USEC_TIMEOUT
;
717 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
718 rdev
->accel_working
= false;
720 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
721 radeon_family_name
[rdev
->family
], pdev
->vendor
, pdev
->device
,
722 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
724 /* mutex initialization are all done here so we
725 * can recall function without having locking issues */
726 radeon_mutex_init(&rdev
->cs_mutex
);
727 mutex_init(&rdev
->ring_lock
);
728 mutex_init(&rdev
->dc_hw_i2c_mutex
);
729 if (rdev
->family
>= CHIP_R600
)
730 spin_lock_init(&rdev
->ih
.lock
);
731 mutex_init(&rdev
->gem
.mutex
);
732 mutex_init(&rdev
->pm
.mutex
);
733 mutex_init(&rdev
->vram_mutex
);
734 INIT_LIST_HEAD(&rdev
->gem
.objects
);
735 init_waitqueue_head(&rdev
->irq
.vblank_queue
);
736 init_waitqueue_head(&rdev
->irq
.idle_queue
);
737 /* initialize vm here */
738 rdev
->vm_manager
.use_bitmap
= 1;
739 rdev
->vm_manager
.max_pfn
= 1 << 20;
740 INIT_LIST_HEAD(&rdev
->vm_manager
.lru_vm
);
742 /* Set asic functions */
743 r
= radeon_asic_init(rdev
);
746 radeon_check_arguments(rdev
);
748 /* all of the newer IGP chips have an internal gart
749 * However some rs4xx report as AGP, so remove that here.
751 if ((rdev
->family
>= CHIP_RS400
) &&
752 (rdev
->flags
& RADEON_IS_IGP
)) {
753 rdev
->flags
&= ~RADEON_IS_AGP
;
756 if (rdev
->flags
& RADEON_IS_AGP
&& radeon_agpmode
== -1) {
757 radeon_agp_disable(rdev
);
760 /* set DMA mask + need_dma32 flags.
761 * PCIE - can handle 40-bits.
762 * IGP - can handle 40-bits
763 * AGP - generally dma32 is safest
764 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
766 rdev
->need_dma32
= false;
767 if (rdev
->flags
& RADEON_IS_AGP
)
768 rdev
->need_dma32
= true;
769 if ((rdev
->flags
& RADEON_IS_PCI
) &&
770 (rdev
->family
< CHIP_RS400
))
771 rdev
->need_dma32
= true;
773 dma_bits
= rdev
->need_dma32
? 32 : 40;
774 r
= pci_set_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
776 rdev
->need_dma32
= true;
778 printk(KERN_WARNING
"radeon: No suitable DMA available.\n");
780 r
= pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
782 pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(32));
783 printk(KERN_WARNING
"radeon: No coherent DMA available.\n");
786 /* Registers mapping */
787 /* TODO: block userspace mapping of io register */
788 rdev
->rmmio_base
= pci_resource_start(rdev
->pdev
, 2);
789 rdev
->rmmio_size
= pci_resource_len(rdev
->pdev
, 2);
790 rdev
->rmmio
= ioremap(rdev
->rmmio_base
, rdev
->rmmio_size
);
791 if (rdev
->rmmio
== NULL
) {
794 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev
->rmmio_base
);
795 DRM_INFO("register mmio size: %u\n", (unsigned)rdev
->rmmio_size
);
797 /* io port mapping */
798 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
799 if (pci_resource_flags(rdev
->pdev
, i
) & IORESOURCE_IO
) {
800 rdev
->rio_mem_size
= pci_resource_len(rdev
->pdev
, i
);
801 rdev
->rio_mem
= pci_iomap(rdev
->pdev
, i
, rdev
->rio_mem_size
);
805 if (rdev
->rio_mem
== NULL
)
806 DRM_ERROR("Unable to find PCI I/O BAR\n");
808 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
809 /* this will fail for cards that aren't VGA class devices, just
811 vga_client_register(rdev
->pdev
, rdev
, NULL
, radeon_vga_set_decode
);
812 vga_switcheroo_register_client(rdev
->pdev
,
813 radeon_switcheroo_set_state
,
815 radeon_switcheroo_can_switch
);
817 r
= radeon_init(rdev
);
821 if (rdev
->flags
& RADEON_IS_AGP
&& !rdev
->accel_working
) {
822 /* Acceleration not working on AGP card try again
823 * with fallback to PCI or PCIE GART
825 radeon_asic_reset(rdev
);
827 radeon_agp_disable(rdev
);
828 r
= radeon_init(rdev
);
832 if ((radeon_testing
& 1)) {
833 radeon_test_moves(rdev
);
835 if ((radeon_testing
& 2)) {
836 radeon_test_syncing(rdev
);
838 if (radeon_benchmarking
) {
839 radeon_benchmark(rdev
, radeon_benchmarking
);
844 static void radeon_debugfs_remove_files(struct radeon_device
*rdev
);
846 void radeon_device_fini(struct radeon_device
*rdev
)
848 DRM_INFO("radeon: finishing device.\n");
849 rdev
->shutdown
= true;
850 /* evict vram memory */
851 radeon_bo_evict_vram(rdev
);
853 vga_switcheroo_unregister_client(rdev
->pdev
);
854 vga_client_register(rdev
->pdev
, NULL
, NULL
, NULL
);
856 pci_iounmap(rdev
->pdev
, rdev
->rio_mem
);
857 rdev
->rio_mem
= NULL
;
858 iounmap(rdev
->rmmio
);
860 radeon_debugfs_remove_files(rdev
);
867 int radeon_suspend_kms(struct drm_device
*dev
, pm_message_t state
)
869 struct radeon_device
*rdev
;
870 struct drm_crtc
*crtc
;
871 struct drm_connector
*connector
;
874 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
877 if (state
.event
== PM_EVENT_PRETHAW
) {
880 rdev
= dev
->dev_private
;
882 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
885 drm_kms_helper_poll_disable(dev
);
887 /* turn off display hw */
888 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
889 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_OFF
);
892 /* unpin the front buffers */
893 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
894 struct radeon_framebuffer
*rfb
= to_radeon_framebuffer(crtc
->fb
);
895 struct radeon_bo
*robj
;
897 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
900 robj
= gem_to_radeon_bo(rfb
->obj
);
901 /* don't unpin kernel fb objects */
902 if (!radeon_fbdev_robj_is_fb(rdev
, robj
)) {
903 r
= radeon_bo_reserve(robj
, false);
905 radeon_bo_unpin(robj
);
906 radeon_bo_unreserve(robj
);
910 /* evict vram memory */
911 radeon_bo_evict_vram(rdev
);
913 mutex_lock(&rdev
->ring_lock
);
914 /* wait for gpu to finish processing current batch */
915 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++)
916 radeon_fence_wait_empty_locked(rdev
, i
);
917 mutex_unlock(&rdev
->ring_lock
);
919 radeon_save_bios_scratch_regs(rdev
);
921 radeon_pm_suspend(rdev
);
922 radeon_suspend(rdev
);
923 radeon_hpd_fini(rdev
);
924 /* evict remaining vram memory */
925 radeon_bo_evict_vram(rdev
);
927 radeon_agp_suspend(rdev
);
929 pci_save_state(dev
->pdev
);
930 if (state
.event
== PM_EVENT_SUSPEND
) {
931 /* Shut down the device */
932 pci_disable_device(dev
->pdev
);
933 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
936 radeon_fbdev_set_suspend(rdev
, 1);
941 int radeon_resume_kms(struct drm_device
*dev
)
943 struct drm_connector
*connector
;
944 struct radeon_device
*rdev
= dev
->dev_private
;
946 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
950 pci_set_power_state(dev
->pdev
, PCI_D0
);
951 pci_restore_state(dev
->pdev
);
952 if (pci_enable_device(dev
->pdev
)) {
956 /* resume AGP if in use */
957 radeon_agp_resume(rdev
);
959 radeon_pm_resume(rdev
);
960 radeon_restore_bios_scratch_regs(rdev
);
962 radeon_fbdev_set_suspend(rdev
, 0);
965 /* init dig PHYs, disp eng pll */
966 if (rdev
->is_atom_bios
) {
967 radeon_atom_encoder_init(rdev
);
968 radeon_atom_disp_eng_pll_init(rdev
);
970 /* reset hpd state */
971 radeon_hpd_init(rdev
);
972 /* blat the mode back in */
973 drm_helper_resume_force_mode(dev
);
974 /* turn on display hw */
975 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
976 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_ON
);
979 drm_kms_helper_poll_enable(dev
);
983 int radeon_gpu_reset(struct radeon_device
*rdev
)
988 radeon_save_bios_scratch_regs(rdev
);
990 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
991 radeon_suspend(rdev
);
993 r
= radeon_asic_reset(rdev
);
995 dev_info(rdev
->dev
, "GPU reset succeed\n");
997 radeon_restore_bios_scratch_regs(rdev
);
998 drm_helper_resume_force_mode(rdev
->ddev
);
999 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
1003 /* bad news, how to tell it to userspace ? */
1004 dev_info(rdev
->dev
, "GPU reset failed\n");
1014 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
1015 struct drm_info_list
*files
,
1020 for (i
= 0; i
< rdev
->debugfs_count
; i
++) {
1021 if (rdev
->debugfs
[i
].files
== files
) {
1022 /* Already registered */
1027 i
= rdev
->debugfs_count
+ 1;
1028 if (i
> RADEON_DEBUGFS_MAX_COMPONENTS
) {
1029 DRM_ERROR("Reached maximum number of debugfs components.\n");
1030 DRM_ERROR("Report so we increase "
1031 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1034 rdev
->debugfs
[rdev
->debugfs_count
].files
= files
;
1035 rdev
->debugfs
[rdev
->debugfs_count
].num_files
= nfiles
;
1036 rdev
->debugfs_count
= i
;
1037 #if defined(CONFIG_DEBUG_FS)
1038 drm_debugfs_create_files(files
, nfiles
,
1039 rdev
->ddev
->control
->debugfs_root
,
1040 rdev
->ddev
->control
);
1041 drm_debugfs_create_files(files
, nfiles
,
1042 rdev
->ddev
->primary
->debugfs_root
,
1043 rdev
->ddev
->primary
);
1048 static void radeon_debugfs_remove_files(struct radeon_device
*rdev
)
1050 #if defined(CONFIG_DEBUG_FS)
1053 for (i
= 0; i
< rdev
->debugfs_count
; i
++) {
1054 drm_debugfs_remove_files(rdev
->debugfs
[i
].files
,
1055 rdev
->debugfs
[i
].num_files
,
1056 rdev
->ddev
->control
);
1057 drm_debugfs_remove_files(rdev
->debugfs
[i
].files
,
1058 rdev
->debugfs
[i
].num_files
,
1059 rdev
->ddev
->primary
);
1064 #if defined(CONFIG_DEBUG_FS)
1065 int radeon_debugfs_init(struct drm_minor
*minor
)
1070 void radeon_debugfs_cleanup(struct drm_minor
*minor
)