2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include <linux/efi.h>
36 #include "radeon_reg.h"
40 static const char radeon_family_name
[][16] = {
106 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
107 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
109 struct radeon_px_quirk
{
117 static struct radeon_px_quirk radeon_px_quirk_list
[] = {
118 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
119 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
121 { PCI_VENDOR_ID_ATI
, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX
},
122 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
123 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
125 { PCI_VENDOR_ID_ATI
, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX
},
126 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
127 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
129 { PCI_VENDOR_ID_ATI
, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX
},
130 /* macbook pro 8.2 */
131 { PCI_VENDOR_ID_ATI
, 0x6741, PCI_VENDOR_ID_APPLE
, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP
},
135 bool radeon_is_px(struct drm_device
*dev
)
137 struct radeon_device
*rdev
= dev
->dev_private
;
139 if (rdev
->flags
& RADEON_IS_PX
)
144 static void radeon_device_handle_px_quirks(struct radeon_device
*rdev
)
146 struct radeon_px_quirk
*p
= radeon_px_quirk_list
;
148 /* Apply PX quirks */
149 while (p
&& p
->chip_device
!= 0) {
150 if (rdev
->pdev
->vendor
== p
->chip_vendor
&&
151 rdev
->pdev
->device
== p
->chip_device
&&
152 rdev
->pdev
->subsystem_vendor
== p
->subsys_vendor
&&
153 rdev
->pdev
->subsystem_device
== p
->subsys_device
) {
154 rdev
->px_quirk_flags
= p
->px_quirk_flags
;
160 if (rdev
->px_quirk_flags
& RADEON_PX_QUIRK_DISABLE_PX
)
161 rdev
->flags
&= ~RADEON_IS_PX
;
165 * radeon_program_register_sequence - program an array of registers.
167 * @rdev: radeon_device pointer
168 * @registers: pointer to the register array
169 * @array_size: size of the register array
171 * Programs an array or registers with and and or masks.
172 * This is a helper for setting golden registers.
174 void radeon_program_register_sequence(struct radeon_device
*rdev
,
175 const u32
*registers
,
176 const u32 array_size
)
178 u32 tmp
, reg
, and_mask
, or_mask
;
184 for (i
= 0; i
< array_size
; i
+=3) {
185 reg
= registers
[i
+ 0];
186 and_mask
= registers
[i
+ 1];
187 or_mask
= registers
[i
+ 2];
189 if (and_mask
== 0xffffffff) {
200 void radeon_pci_config_reset(struct radeon_device
*rdev
)
202 pci_write_config_dword(rdev
->pdev
, 0x7c, RADEON_ASIC_RESET_DATA
);
206 * radeon_surface_init - Clear GPU surface registers.
208 * @rdev: radeon_device pointer
210 * Clear GPU surface registers (r1xx-r5xx).
212 void radeon_surface_init(struct radeon_device
*rdev
)
214 /* FIXME: check this out */
215 if (rdev
->family
< CHIP_R600
) {
218 for (i
= 0; i
< RADEON_GEM_MAX_SURFACES
; i
++) {
219 if (rdev
->surface_regs
[i
].bo
)
220 radeon_bo_get_surface_reg(rdev
->surface_regs
[i
].bo
);
222 radeon_clear_surface_reg(rdev
, i
);
224 /* enable surfaces */
225 WREG32(RADEON_SURFACE_CNTL
, 0);
230 * GPU scratch registers helpers function.
233 * radeon_scratch_init - Init scratch register driver information.
235 * @rdev: radeon_device pointer
237 * Init CP scratch register driver information (r1xx-r5xx)
239 void radeon_scratch_init(struct radeon_device
*rdev
)
243 /* FIXME: check this out */
244 if (rdev
->family
< CHIP_R300
) {
245 rdev
->scratch
.num_reg
= 5;
247 rdev
->scratch
.num_reg
= 7;
249 rdev
->scratch
.reg_base
= RADEON_SCRATCH_REG0
;
250 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
251 rdev
->scratch
.free
[i
] = true;
252 rdev
->scratch
.reg
[i
] = rdev
->scratch
.reg_base
+ (i
* 4);
257 * radeon_scratch_get - Allocate a scratch register
259 * @rdev: radeon_device pointer
260 * @reg: scratch register mmio offset
262 * Allocate a CP scratch register for use by the driver (all asics).
263 * Returns 0 on success or -EINVAL on failure.
265 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
)
269 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
270 if (rdev
->scratch
.free
[i
]) {
271 rdev
->scratch
.free
[i
] = false;
272 *reg
= rdev
->scratch
.reg
[i
];
280 * radeon_scratch_free - Free a scratch register
282 * @rdev: radeon_device pointer
283 * @reg: scratch register mmio offset
285 * Free a CP scratch register allocated for use by the driver (all asics)
287 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
)
291 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
292 if (rdev
->scratch
.reg
[i
] == reg
) {
293 rdev
->scratch
.free
[i
] = true;
300 * GPU doorbell aperture helpers function.
303 * radeon_doorbell_init - Init doorbell driver information.
305 * @rdev: radeon_device pointer
307 * Init doorbell driver information (CIK)
308 * Returns 0 on success, error on failure.
310 static int radeon_doorbell_init(struct radeon_device
*rdev
)
312 /* doorbell bar mapping */
313 rdev
->doorbell
.base
= pci_resource_start(rdev
->pdev
, 2);
314 rdev
->doorbell
.size
= pci_resource_len(rdev
->pdev
, 2);
316 rdev
->doorbell
.num_doorbells
= min_t(u32
, rdev
->doorbell
.size
/ sizeof(u32
), RADEON_MAX_DOORBELLS
);
317 if (rdev
->doorbell
.num_doorbells
== 0)
320 rdev
->doorbell
.ptr
= ioremap(rdev
->doorbell
.base
, rdev
->doorbell
.num_doorbells
* sizeof(u32
));
321 if (rdev
->doorbell
.ptr
== NULL
) {
324 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev
->doorbell
.base
);
325 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev
->doorbell
.size
);
327 memset(&rdev
->doorbell
.used
, 0, sizeof(rdev
->doorbell
.used
));
333 * radeon_doorbell_fini - Tear down doorbell driver information.
335 * @rdev: radeon_device pointer
337 * Tear down doorbell driver information (CIK)
339 static void radeon_doorbell_fini(struct radeon_device
*rdev
)
341 iounmap(rdev
->doorbell
.ptr
);
342 rdev
->doorbell
.ptr
= NULL
;
346 * radeon_doorbell_get - Allocate a doorbell entry
348 * @rdev: radeon_device pointer
349 * @doorbell: doorbell index
351 * Allocate a doorbell for use by the driver (all asics).
352 * Returns 0 on success or -EINVAL on failure.
354 int radeon_doorbell_get(struct radeon_device
*rdev
, u32
*doorbell
)
356 unsigned long offset
= find_first_zero_bit(rdev
->doorbell
.used
, rdev
->doorbell
.num_doorbells
);
357 if (offset
< rdev
->doorbell
.num_doorbells
) {
358 __set_bit(offset
, rdev
->doorbell
.used
);
367 * radeon_doorbell_free - Free a doorbell entry
369 * @rdev: radeon_device pointer
370 * @doorbell: doorbell index
372 * Free a doorbell allocated for use by the driver (all asics)
374 void radeon_doorbell_free(struct radeon_device
*rdev
, u32 doorbell
)
376 if (doorbell
< rdev
->doorbell
.num_doorbells
)
377 __clear_bit(doorbell
, rdev
->doorbell
.used
);
381 * radeon_doorbell_get_kfd_info - Report doorbell configuration required to
384 * @rdev: radeon_device pointer
385 * @aperture_base: output returning doorbell aperture base physical address
386 * @aperture_size: output returning doorbell aperture size in bytes
387 * @start_offset: output returning # of doorbell bytes reserved for radeon.
389 * Radeon and the KFD share the doorbell aperture. Radeon sets it up,
390 * takes doorbells required for its own rings and reports the setup to KFD.
391 * Radeon reserved doorbells are at the start of the doorbell aperture.
393 void radeon_doorbell_get_kfd_info(struct radeon_device
*rdev
,
394 phys_addr_t
*aperture_base
,
395 size_t *aperture_size
,
396 size_t *start_offset
)
398 /* The first num_doorbells are used by radeon.
399 * KFD takes whatever's left in the aperture. */
400 if (rdev
->doorbell
.size
> rdev
->doorbell
.num_doorbells
* sizeof(u32
)) {
401 *aperture_base
= rdev
->doorbell
.base
;
402 *aperture_size
= rdev
->doorbell
.size
;
403 *start_offset
= rdev
->doorbell
.num_doorbells
* sizeof(u32
);
413 * Writeback is the the method by which the the GPU updates special pages
414 * in memory with the status of certain GPU events (fences, ring pointers,
419 * radeon_wb_disable - Disable Writeback
421 * @rdev: radeon_device pointer
423 * Disables Writeback (all asics). Used for suspend.
425 void radeon_wb_disable(struct radeon_device
*rdev
)
427 rdev
->wb
.enabled
= false;
431 * radeon_wb_fini - Disable Writeback and free memory
433 * @rdev: radeon_device pointer
435 * Disables Writeback and frees the Writeback memory (all asics).
436 * Used at driver shutdown.
438 void radeon_wb_fini(struct radeon_device
*rdev
)
440 radeon_wb_disable(rdev
);
441 if (rdev
->wb
.wb_obj
) {
442 if (!radeon_bo_reserve(rdev
->wb
.wb_obj
, false)) {
443 radeon_bo_kunmap(rdev
->wb
.wb_obj
);
444 radeon_bo_unpin(rdev
->wb
.wb_obj
);
445 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
447 radeon_bo_unref(&rdev
->wb
.wb_obj
);
449 rdev
->wb
.wb_obj
= NULL
;
454 * radeon_wb_init- Init Writeback driver info and allocate memory
456 * @rdev: radeon_device pointer
458 * Disables Writeback and frees the Writeback memory (all asics).
459 * Used at driver startup.
460 * Returns 0 on success or an -error on failure.
462 int radeon_wb_init(struct radeon_device
*rdev
)
466 if (rdev
->wb
.wb_obj
== NULL
) {
467 r
= radeon_bo_create(rdev
, RADEON_GPU_PAGE_SIZE
, PAGE_SIZE
, true,
468 RADEON_GEM_DOMAIN_GTT
, 0, NULL
, NULL
,
471 dev_warn(rdev
->dev
, "(%d) create WB bo failed\n", r
);
474 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
475 if (unlikely(r
!= 0)) {
476 radeon_wb_fini(rdev
);
479 r
= radeon_bo_pin(rdev
->wb
.wb_obj
, RADEON_GEM_DOMAIN_GTT
,
482 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
483 dev_warn(rdev
->dev
, "(%d) pin WB bo failed\n", r
);
484 radeon_wb_fini(rdev
);
487 r
= radeon_bo_kmap(rdev
->wb
.wb_obj
, (void **)&rdev
->wb
.wb
);
488 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
490 dev_warn(rdev
->dev
, "(%d) map WB bo failed\n", r
);
491 radeon_wb_fini(rdev
);
496 /* clear wb memory */
497 memset((char *)rdev
->wb
.wb
, 0, RADEON_GPU_PAGE_SIZE
);
498 /* disable event_write fences */
499 rdev
->wb
.use_event
= false;
500 /* disabled via module param */
501 if (radeon_no_wb
== 1) {
502 rdev
->wb
.enabled
= false;
504 if (rdev
->flags
& RADEON_IS_AGP
) {
505 /* often unreliable on AGP */
506 rdev
->wb
.enabled
= false;
507 } else if (rdev
->family
< CHIP_R300
) {
508 /* often unreliable on pre-r300 */
509 rdev
->wb
.enabled
= false;
511 rdev
->wb
.enabled
= true;
512 /* event_write fences are only available on r600+ */
513 if (rdev
->family
>= CHIP_R600
) {
514 rdev
->wb
.use_event
= true;
518 /* always use writeback/events on NI, APUs */
519 if (rdev
->family
>= CHIP_PALM
) {
520 rdev
->wb
.enabled
= true;
521 rdev
->wb
.use_event
= true;
524 dev_info(rdev
->dev
, "WB %sabled\n", rdev
->wb
.enabled
? "en" : "dis");
530 * radeon_vram_location - try to find VRAM location
531 * @rdev: radeon device structure holding all necessary informations
532 * @mc: memory controller structure holding memory informations
533 * @base: base address at which to put VRAM
535 * Function will place try to place VRAM at base address provided
536 * as parameter (which is so far either PCI aperture address or
537 * for IGP TOM base address).
539 * If there is not enough space to fit the unvisible VRAM in the 32bits
540 * address space then we limit the VRAM size to the aperture.
542 * If we are using AGP and if the AGP aperture doesn't allow us to have
543 * room for all the VRAM than we restrict the VRAM to the PCI aperture
544 * size and print a warning.
546 * This function will never fails, worst case are limiting VRAM.
548 * Note: GTT start, end, size should be initialized before calling this
549 * function on AGP platform.
551 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
552 * this shouldn't be a problem as we are using the PCI aperture as a reference.
553 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
556 * Note: we use mc_vram_size as on some board we need to program the mc to
557 * cover the whole aperture even if VRAM size is inferior to aperture size
558 * Novell bug 204882 + along with lots of ubuntu ones
560 * Note: when limiting vram it's safe to overwritte real_vram_size because
561 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
562 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
565 * Note: IGP TOM addr should be the same as the aperture addr, we don't
566 * explicitly check for that thought.
568 * FIXME: when reducing VRAM size align new size on power of 2.
570 void radeon_vram_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
, u64 base
)
572 uint64_t limit
= (uint64_t)radeon_vram_limit
<< 20;
574 mc
->vram_start
= base
;
575 if (mc
->mc_vram_size
> (rdev
->mc
.mc_mask
- base
+ 1)) {
576 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
577 mc
->real_vram_size
= mc
->aper_size
;
578 mc
->mc_vram_size
= mc
->aper_size
;
580 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
581 if (rdev
->flags
& RADEON_IS_AGP
&& mc
->vram_end
> mc
->gtt_start
&& mc
->vram_start
<= mc
->gtt_end
) {
582 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
583 mc
->real_vram_size
= mc
->aper_size
;
584 mc
->mc_vram_size
= mc
->aper_size
;
586 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
587 if (limit
&& limit
< mc
->real_vram_size
)
588 mc
->real_vram_size
= limit
;
589 dev_info(rdev
->dev
, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
590 mc
->mc_vram_size
>> 20, mc
->vram_start
,
591 mc
->vram_end
, mc
->real_vram_size
>> 20);
595 * radeon_gtt_location - try to find GTT location
596 * @rdev: radeon device structure holding all necessary informations
597 * @mc: memory controller structure holding memory informations
599 * Function will place try to place GTT before or after VRAM.
601 * If GTT size is bigger than space left then we ajust GTT size.
602 * Thus function will never fails.
604 * FIXME: when reducing GTT size align new size on power of 2.
606 void radeon_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
608 u64 size_af
, size_bf
;
610 size_af
= ((rdev
->mc
.mc_mask
- mc
->vram_end
) + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
611 size_bf
= mc
->vram_start
& ~mc
->gtt_base_align
;
612 if (size_bf
> size_af
) {
613 if (mc
->gtt_size
> size_bf
) {
614 dev_warn(rdev
->dev
, "limiting GTT\n");
615 mc
->gtt_size
= size_bf
;
617 mc
->gtt_start
= (mc
->vram_start
& ~mc
->gtt_base_align
) - mc
->gtt_size
;
619 if (mc
->gtt_size
> size_af
) {
620 dev_warn(rdev
->dev
, "limiting GTT\n");
621 mc
->gtt_size
= size_af
;
623 mc
->gtt_start
= (mc
->vram_end
+ 1 + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
625 mc
->gtt_end
= mc
->gtt_start
+ mc
->gtt_size
- 1;
626 dev_info(rdev
->dev
, "GTT: %lluM 0x%016llX - 0x%016llX\n",
627 mc
->gtt_size
>> 20, mc
->gtt_start
, mc
->gtt_end
);
631 * GPU helpers function.
635 * radeon_device_is_virtual - check if we are running is a virtual environment
637 * Check if the asic has been passed through to a VM (all asics).
638 * Used at driver startup.
639 * Returns true if virtual or false if not.
641 static bool radeon_device_is_virtual(void)
644 return boot_cpu_has(X86_FEATURE_HYPERVISOR
);
651 * radeon_card_posted - check if the hw has already been initialized
653 * @rdev: radeon_device pointer
655 * Check if the asic has been initialized (all asics).
656 * Used at driver startup.
657 * Returns true if initialized or false if not.
659 bool radeon_card_posted(struct radeon_device
*rdev
)
663 /* for pass through, always force asic_init */
664 if (radeon_device_is_virtual())
667 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
668 if (efi_enabled(EFI_BOOT
) &&
669 (rdev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
) &&
670 (rdev
->family
< CHIP_R600
))
673 if (ASIC_IS_NODCE(rdev
))
676 /* first check CRTCs */
677 if (ASIC_IS_DCE4(rdev
)) {
678 reg
= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) |
679 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
680 if (rdev
->num_crtc
>= 4) {
681 reg
|= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) |
682 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
684 if (rdev
->num_crtc
>= 6) {
685 reg
|= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) |
686 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
688 if (reg
& EVERGREEN_CRTC_MASTER_EN
)
690 } else if (ASIC_IS_AVIVO(rdev
)) {
691 reg
= RREG32(AVIVO_D1CRTC_CONTROL
) |
692 RREG32(AVIVO_D2CRTC_CONTROL
);
693 if (reg
& AVIVO_CRTC_EN
) {
697 reg
= RREG32(RADEON_CRTC_GEN_CNTL
) |
698 RREG32(RADEON_CRTC2_GEN_CNTL
);
699 if (reg
& RADEON_CRTC_EN
) {
705 /* then check MEM_SIZE, in case the crtcs are off */
706 if (rdev
->family
>= CHIP_R600
)
707 reg
= RREG32(R600_CONFIG_MEMSIZE
);
709 reg
= RREG32(RADEON_CONFIG_MEMSIZE
);
719 * radeon_update_bandwidth_info - update display bandwidth params
721 * @rdev: radeon_device pointer
723 * Used when sclk/mclk are switched or display modes are set.
724 * params are used to calculate display watermarks (all asics)
726 void radeon_update_bandwidth_info(struct radeon_device
*rdev
)
729 u32 sclk
= rdev
->pm
.current_sclk
;
730 u32 mclk
= rdev
->pm
.current_mclk
;
732 /* sclk/mclk in Mhz */
733 a
.full
= dfixed_const(100);
734 rdev
->pm
.sclk
.full
= dfixed_const(sclk
);
735 rdev
->pm
.sclk
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
736 rdev
->pm
.mclk
.full
= dfixed_const(mclk
);
737 rdev
->pm
.mclk
.full
= dfixed_div(rdev
->pm
.mclk
, a
);
739 if (rdev
->flags
& RADEON_IS_IGP
) {
740 a
.full
= dfixed_const(16);
741 /* core_bandwidth = sclk(Mhz) * 16 */
742 rdev
->pm
.core_bandwidth
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
747 * radeon_boot_test_post_card - check and possibly initialize the hw
749 * @rdev: radeon_device pointer
751 * Check if the asic is initialized and if not, attempt to initialize
753 * Returns true if initialized or false if not.
755 bool radeon_boot_test_post_card(struct radeon_device
*rdev
)
757 if (radeon_card_posted(rdev
))
761 DRM_INFO("GPU not posted. posting now...\n");
762 if (rdev
->is_atom_bios
)
763 atom_asic_init(rdev
->mode_info
.atom_context
);
765 radeon_combios_asic_init(rdev
->ddev
);
768 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
774 * radeon_dummy_page_init - init dummy page used by the driver
776 * @rdev: radeon_device pointer
778 * Allocate the dummy page used by the driver (all asics).
779 * This dummy page is used by the driver as a filler for gart entries
780 * when pages are taken out of the GART
781 * Returns 0 on sucess, -ENOMEM on failure.
783 int radeon_dummy_page_init(struct radeon_device
*rdev
)
785 if (rdev
->dummy_page
.page
)
787 rdev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
788 if (rdev
->dummy_page
.page
== NULL
)
790 rdev
->dummy_page
.addr
= pci_map_page(rdev
->pdev
, rdev
->dummy_page
.page
,
791 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
792 if (pci_dma_mapping_error(rdev
->pdev
, rdev
->dummy_page
.addr
)) {
793 dev_err(&rdev
->pdev
->dev
, "Failed to DMA MAP the dummy page\n");
794 __free_page(rdev
->dummy_page
.page
);
795 rdev
->dummy_page
.page
= NULL
;
798 rdev
->dummy_page
.entry
= radeon_gart_get_page_entry(rdev
->dummy_page
.addr
,
799 RADEON_GART_PAGE_DUMMY
);
804 * radeon_dummy_page_fini - free dummy page used by the driver
806 * @rdev: radeon_device pointer
808 * Frees the dummy page used by the driver (all asics).
810 void radeon_dummy_page_fini(struct radeon_device
*rdev
)
812 if (rdev
->dummy_page
.page
== NULL
)
814 pci_unmap_page(rdev
->pdev
, rdev
->dummy_page
.addr
,
815 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
816 __free_page(rdev
->dummy_page
.page
);
817 rdev
->dummy_page
.page
= NULL
;
821 /* ATOM accessor methods */
823 * ATOM is an interpreted byte code stored in tables in the vbios. The
824 * driver registers callbacks to access registers and the interpreter
825 * in the driver parses the tables and executes then to program specific
826 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
827 * atombios.h, and atom.c
831 * cail_pll_read - read PLL register
833 * @info: atom card_info pointer
834 * @reg: PLL register offset
836 * Provides a PLL register accessor for the atom interpreter (r4xx+).
837 * Returns the value of the PLL register.
839 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
841 struct radeon_device
*rdev
= info
->dev
->dev_private
;
844 r
= rdev
->pll_rreg(rdev
, reg
);
849 * cail_pll_write - write PLL register
851 * @info: atom card_info pointer
852 * @reg: PLL register offset
853 * @val: value to write to the pll register
855 * Provides a PLL register accessor for the atom interpreter (r4xx+).
857 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
859 struct radeon_device
*rdev
= info
->dev
->dev_private
;
861 rdev
->pll_wreg(rdev
, reg
, val
);
865 * cail_mc_read - read MC (Memory Controller) register
867 * @info: atom card_info pointer
868 * @reg: MC register offset
870 * Provides an MC register accessor for the atom interpreter (r4xx+).
871 * Returns the value of the MC register.
873 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
875 struct radeon_device
*rdev
= info
->dev
->dev_private
;
878 r
= rdev
->mc_rreg(rdev
, reg
);
883 * cail_mc_write - write MC (Memory Controller) register
885 * @info: atom card_info pointer
886 * @reg: MC register offset
887 * @val: value to write to the pll register
889 * Provides a MC register accessor for the atom interpreter (r4xx+).
891 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
893 struct radeon_device
*rdev
= info
->dev
->dev_private
;
895 rdev
->mc_wreg(rdev
, reg
, val
);
899 * cail_reg_write - write MMIO register
901 * @info: atom card_info pointer
902 * @reg: MMIO register offset
903 * @val: value to write to the pll register
905 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
907 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
909 struct radeon_device
*rdev
= info
->dev
->dev_private
;
915 * cail_reg_read - read MMIO register
917 * @info: atom card_info pointer
918 * @reg: MMIO register offset
920 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
921 * Returns the value of the MMIO register.
923 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
925 struct radeon_device
*rdev
= info
->dev
->dev_private
;
933 * cail_ioreg_write - write IO register
935 * @info: atom card_info pointer
936 * @reg: IO register offset
937 * @val: value to write to the pll register
939 * Provides a IO register accessor for the atom interpreter (r4xx+).
941 static void cail_ioreg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
943 struct radeon_device
*rdev
= info
->dev
->dev_private
;
945 WREG32_IO(reg
*4, val
);
949 * cail_ioreg_read - read IO register
951 * @info: atom card_info pointer
952 * @reg: IO register offset
954 * Provides an IO register accessor for the atom interpreter (r4xx+).
955 * Returns the value of the IO register.
957 static uint32_t cail_ioreg_read(struct card_info
*info
, uint32_t reg
)
959 struct radeon_device
*rdev
= info
->dev
->dev_private
;
962 r
= RREG32_IO(reg
*4);
967 * radeon_atombios_init - init the driver info and callbacks for atombios
969 * @rdev: radeon_device pointer
971 * Initializes the driver info and register access callbacks for the
972 * ATOM interpreter (r4xx+).
973 * Returns 0 on sucess, -ENOMEM on failure.
974 * Called at driver startup.
976 int radeon_atombios_init(struct radeon_device
*rdev
)
978 struct card_info
*atom_card_info
=
979 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
984 rdev
->mode_info
.atom_card_info
= atom_card_info
;
985 atom_card_info
->dev
= rdev
->ddev
;
986 atom_card_info
->reg_read
= cail_reg_read
;
987 atom_card_info
->reg_write
= cail_reg_write
;
988 /* needed for iio ops */
990 atom_card_info
->ioreg_read
= cail_ioreg_read
;
991 atom_card_info
->ioreg_write
= cail_ioreg_write
;
993 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
994 atom_card_info
->ioreg_read
= cail_reg_read
;
995 atom_card_info
->ioreg_write
= cail_reg_write
;
997 atom_card_info
->mc_read
= cail_mc_read
;
998 atom_card_info
->mc_write
= cail_mc_write
;
999 atom_card_info
->pll_read
= cail_pll_read
;
1000 atom_card_info
->pll_write
= cail_pll_write
;
1002 rdev
->mode_info
.atom_context
= atom_parse(atom_card_info
, rdev
->bios
);
1003 if (!rdev
->mode_info
.atom_context
) {
1004 radeon_atombios_fini(rdev
);
1008 mutex_init(&rdev
->mode_info
.atom_context
->mutex
);
1009 mutex_init(&rdev
->mode_info
.atom_context
->scratch_mutex
);
1010 radeon_atom_initialize_bios_scratch_regs(rdev
->ddev
);
1011 atom_allocate_fb_scratch(rdev
->mode_info
.atom_context
);
1016 * radeon_atombios_fini - free the driver info and callbacks for atombios
1018 * @rdev: radeon_device pointer
1020 * Frees the driver info and register access callbacks for the ATOM
1021 * interpreter (r4xx+).
1022 * Called at driver shutdown.
1024 void radeon_atombios_fini(struct radeon_device
*rdev
)
1026 if (rdev
->mode_info
.atom_context
) {
1027 kfree(rdev
->mode_info
.atom_context
->scratch
);
1029 kfree(rdev
->mode_info
.atom_context
);
1030 rdev
->mode_info
.atom_context
= NULL
;
1031 kfree(rdev
->mode_info
.atom_card_info
);
1032 rdev
->mode_info
.atom_card_info
= NULL
;
1037 * COMBIOS is the bios format prior to ATOM. It provides
1038 * command tables similar to ATOM, but doesn't have a unified
1039 * parser. See radeon_combios.c
1043 * radeon_combios_init - init the driver info for combios
1045 * @rdev: radeon_device pointer
1047 * Initializes the driver info for combios (r1xx-r3xx).
1048 * Returns 0 on sucess.
1049 * Called at driver startup.
1051 int radeon_combios_init(struct radeon_device
*rdev
)
1053 radeon_combios_initialize_bios_scratch_regs(rdev
->ddev
);
1058 * radeon_combios_fini - free the driver info for combios
1060 * @rdev: radeon_device pointer
1062 * Frees the driver info for combios (r1xx-r3xx).
1063 * Called at driver shutdown.
1065 void radeon_combios_fini(struct radeon_device
*rdev
)
1069 /* if we get transitioned to only one device, take VGA back */
1071 * radeon_vga_set_decode - enable/disable vga decode
1073 * @cookie: radeon_device pointer
1074 * @state: enable/disable vga decode
1076 * Enable/disable vga decode (all asics).
1077 * Returns VGA resource flags.
1079 static unsigned int radeon_vga_set_decode(void *cookie
, bool state
)
1081 struct radeon_device
*rdev
= cookie
;
1082 radeon_vga_set_state(rdev
, state
);
1084 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
1085 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1087 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1091 * radeon_check_pot_argument - check that argument is a power of two
1093 * @arg: value to check
1095 * Validates that a certain argument is a power of two (all asics).
1096 * Returns true if argument is valid.
1098 static bool radeon_check_pot_argument(int arg
)
1100 return (arg
& (arg
- 1)) == 0;
1104 * Determine a sensible default GART size according to ASIC family.
1106 * @family ASIC family name
1108 static int radeon_gart_size_auto(enum radeon_family family
)
1110 /* default to a larger gart size on newer asics */
1111 if (family
>= CHIP_TAHITI
)
1113 else if (family
>= CHIP_RV770
)
1120 * radeon_check_arguments - validate module params
1122 * @rdev: radeon_device pointer
1124 * Validates certain module parameters and updates
1125 * the associated values used by the driver (all asics).
1127 static void radeon_check_arguments(struct radeon_device
*rdev
)
1129 /* vramlimit must be a power of two */
1130 if (!radeon_check_pot_argument(radeon_vram_limit
)) {
1131 dev_warn(rdev
->dev
, "vram limit (%d) must be a power of 2\n",
1133 radeon_vram_limit
= 0;
1136 if (radeon_gart_size
== -1) {
1137 radeon_gart_size
= radeon_gart_size_auto(rdev
->family
);
1139 /* gtt size must be power of two and greater or equal to 32M */
1140 if (radeon_gart_size
< 32) {
1141 dev_warn(rdev
->dev
, "gart size (%d) too small\n",
1143 radeon_gart_size
= radeon_gart_size_auto(rdev
->family
);
1144 } else if (!radeon_check_pot_argument(radeon_gart_size
)) {
1145 dev_warn(rdev
->dev
, "gart size (%d) must be a power of 2\n",
1147 radeon_gart_size
= radeon_gart_size_auto(rdev
->family
);
1149 rdev
->mc
.gtt_size
= (uint64_t)radeon_gart_size
<< 20;
1151 /* AGP mode can only be -1, 1, 2, 4, 8 */
1152 switch (radeon_agpmode
) {
1161 dev_warn(rdev
->dev
, "invalid AGP mode %d (valid mode: "
1162 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode
);
1167 if (!radeon_check_pot_argument(radeon_vm_size
)) {
1168 dev_warn(rdev
->dev
, "VM size (%d) must be a power of 2\n",
1173 if (radeon_vm_size
< 1) {
1174 dev_warn(rdev
->dev
, "VM size (%d) too small, min is 1GB\n",
1180 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1182 if (radeon_vm_size
> 1024) {
1183 dev_warn(rdev
->dev
, "VM size (%d) too large, max is 1TB\n",
1188 /* defines number of bits in page table versus page directory,
1189 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1190 * page table and the remaining bits are in the page directory */
1191 if (radeon_vm_block_size
== -1) {
1193 /* Total bits covered by PD + PTs */
1194 unsigned bits
= ilog2(radeon_vm_size
) + 18;
1196 /* Make sure the PD is 4K in size up to 8GB address space.
1197 Above that split equal between PD and PTs */
1198 if (radeon_vm_size
<= 8)
1199 radeon_vm_block_size
= bits
- 9;
1201 radeon_vm_block_size
= (bits
+ 3) / 2;
1203 } else if (radeon_vm_block_size
< 9) {
1204 dev_warn(rdev
->dev
, "VM page table size (%d) too small\n",
1205 radeon_vm_block_size
);
1206 radeon_vm_block_size
= 9;
1209 if (radeon_vm_block_size
> 24 ||
1210 (radeon_vm_size
* 1024) < (1ull << radeon_vm_block_size
)) {
1211 dev_warn(rdev
->dev
, "VM page table size (%d) too large\n",
1212 radeon_vm_block_size
);
1213 radeon_vm_block_size
= 9;
1218 * radeon_switcheroo_set_state - set switcheroo state
1220 * @pdev: pci dev pointer
1221 * @state: vga_switcheroo state
1223 * Callback for the switcheroo driver. Suspends or resumes the
1224 * the asics before or after it is powered up using ACPI methods.
1226 static void radeon_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1228 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1229 struct radeon_device
*rdev
= dev
->dev_private
;
1231 if (radeon_is_px(dev
) && state
== VGA_SWITCHEROO_OFF
)
1234 if (state
== VGA_SWITCHEROO_ON
) {
1235 unsigned d3_delay
= dev
->pdev
->d3_delay
;
1237 printk(KERN_INFO
"radeon: switched on\n");
1238 /* don't suspend or resume card normally */
1239 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1241 if (d3_delay
< 20 && (rdev
->px_quirk_flags
& RADEON_PX_QUIRK_LONG_WAKEUP
))
1242 dev
->pdev
->d3_delay
= 20;
1244 radeon_resume_kms(dev
, true, true);
1246 dev
->pdev
->d3_delay
= d3_delay
;
1248 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1249 drm_kms_helper_poll_enable(dev
);
1251 printk(KERN_INFO
"radeon: switched off\n");
1252 drm_kms_helper_poll_disable(dev
);
1253 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1254 radeon_suspend_kms(dev
, true, true, false);
1255 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1260 * radeon_switcheroo_can_switch - see if switcheroo state can change
1262 * @pdev: pci dev pointer
1264 * Callback for the switcheroo driver. Check of the switcheroo
1265 * state can be changed.
1266 * Returns true if the state can be changed, false if not.
1268 static bool radeon_switcheroo_can_switch(struct pci_dev
*pdev
)
1270 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1273 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1274 * locking inversion with the driver load path. And the access here is
1275 * completely racy anyway. So don't bother with locking for now.
1277 return dev
->open_count
== 0;
1280 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops
= {
1281 .set_gpu_state
= radeon_switcheroo_set_state
,
1283 .can_switch
= radeon_switcheroo_can_switch
,
1287 * radeon_device_init - initialize the driver
1289 * @rdev: radeon_device pointer
1290 * @pdev: drm dev pointer
1291 * @pdev: pci dev pointer
1292 * @flags: driver flags
1294 * Initializes the driver info and hw (all asics).
1295 * Returns 0 for success or an error on failure.
1296 * Called at driver startup.
1298 int radeon_device_init(struct radeon_device
*rdev
,
1299 struct drm_device
*ddev
,
1300 struct pci_dev
*pdev
,
1305 bool runtime
= false;
1307 rdev
->shutdown
= false;
1308 rdev
->dev
= &pdev
->dev
;
1311 rdev
->flags
= flags
;
1312 rdev
->family
= flags
& RADEON_FAMILY_MASK
;
1313 rdev
->is_atom_bios
= false;
1314 rdev
->usec_timeout
= RADEON_MAX_USEC_TIMEOUT
;
1315 rdev
->mc
.gtt_size
= 512 * 1024 * 1024;
1316 rdev
->accel_working
= false;
1317 /* set up ring ids */
1318 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
1319 rdev
->ring
[i
].idx
= i
;
1321 rdev
->fence_context
= fence_context_alloc(RADEON_NUM_RINGS
);
1323 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1324 radeon_family_name
[rdev
->family
], pdev
->vendor
, pdev
->device
,
1325 pdev
->subsystem_vendor
, pdev
->subsystem_device
, pdev
->revision
);
1327 /* mutex initialization are all done here so we
1328 * can recall function without having locking issues */
1329 mutex_init(&rdev
->ring_lock
);
1330 mutex_init(&rdev
->dc_hw_i2c_mutex
);
1331 atomic_set(&rdev
->ih
.lock
, 0);
1332 mutex_init(&rdev
->gem
.mutex
);
1333 mutex_init(&rdev
->pm
.mutex
);
1334 mutex_init(&rdev
->gpu_clock_mutex
);
1335 mutex_init(&rdev
->srbm_mutex
);
1336 mutex_init(&rdev
->grbm_idx_mutex
);
1337 init_rwsem(&rdev
->pm
.mclk_lock
);
1338 init_rwsem(&rdev
->exclusive_lock
);
1339 init_waitqueue_head(&rdev
->irq
.vblank_queue
);
1340 mutex_init(&rdev
->mn_lock
);
1341 hash_init(rdev
->mn_hash
);
1342 r
= radeon_gem_init(rdev
);
1346 radeon_check_arguments(rdev
);
1347 /* Adjust VM size here.
1348 * Max GPUVM size for cayman+ is 40 bits.
1350 rdev
->vm_manager
.max_pfn
= radeon_vm_size
<< 18;
1352 /* Set asic functions */
1353 r
= radeon_asic_init(rdev
);
1357 /* all of the newer IGP chips have an internal gart
1358 * However some rs4xx report as AGP, so remove that here.
1360 if ((rdev
->family
>= CHIP_RS400
) &&
1361 (rdev
->flags
& RADEON_IS_IGP
)) {
1362 rdev
->flags
&= ~RADEON_IS_AGP
;
1365 if (rdev
->flags
& RADEON_IS_AGP
&& radeon_agpmode
== -1) {
1366 radeon_agp_disable(rdev
);
1369 /* Set the internal MC address mask
1370 * This is the max address of the GPU's
1371 * internal address space.
1373 if (rdev
->family
>= CHIP_CAYMAN
)
1374 rdev
->mc
.mc_mask
= 0xffffffffffULL
; /* 40 bit MC */
1375 else if (rdev
->family
>= CHIP_CEDAR
)
1376 rdev
->mc
.mc_mask
= 0xfffffffffULL
; /* 36 bit MC */
1378 rdev
->mc
.mc_mask
= 0xffffffffULL
; /* 32 bit MC */
1380 /* set DMA mask + need_dma32 flags.
1381 * PCIE - can handle 40-bits.
1382 * IGP - can handle 40-bits
1383 * AGP - generally dma32 is safest
1384 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1386 rdev
->need_dma32
= false;
1387 if (rdev
->flags
& RADEON_IS_AGP
)
1388 rdev
->need_dma32
= true;
1389 if ((rdev
->flags
& RADEON_IS_PCI
) &&
1390 (rdev
->family
<= CHIP_RS740
))
1391 rdev
->need_dma32
= true;
1393 dma_bits
= rdev
->need_dma32
? 32 : 40;
1394 r
= pci_set_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
1396 rdev
->need_dma32
= true;
1398 printk(KERN_WARNING
"radeon: No suitable DMA available.\n");
1400 r
= pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
1402 pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(32));
1403 printk(KERN_WARNING
"radeon: No coherent DMA available.\n");
1406 /* Registers mapping */
1407 /* TODO: block userspace mapping of io register */
1408 spin_lock_init(&rdev
->mmio_idx_lock
);
1409 spin_lock_init(&rdev
->smc_idx_lock
);
1410 spin_lock_init(&rdev
->pll_idx_lock
);
1411 spin_lock_init(&rdev
->mc_idx_lock
);
1412 spin_lock_init(&rdev
->pcie_idx_lock
);
1413 spin_lock_init(&rdev
->pciep_idx_lock
);
1414 spin_lock_init(&rdev
->pif_idx_lock
);
1415 spin_lock_init(&rdev
->cg_idx_lock
);
1416 spin_lock_init(&rdev
->uvd_idx_lock
);
1417 spin_lock_init(&rdev
->rcu_idx_lock
);
1418 spin_lock_init(&rdev
->didt_idx_lock
);
1419 spin_lock_init(&rdev
->end_idx_lock
);
1420 if (rdev
->family
>= CHIP_BONAIRE
) {
1421 rdev
->rmmio_base
= pci_resource_start(rdev
->pdev
, 5);
1422 rdev
->rmmio_size
= pci_resource_len(rdev
->pdev
, 5);
1424 rdev
->rmmio_base
= pci_resource_start(rdev
->pdev
, 2);
1425 rdev
->rmmio_size
= pci_resource_len(rdev
->pdev
, 2);
1427 rdev
->rmmio
= ioremap(rdev
->rmmio_base
, rdev
->rmmio_size
);
1428 if (rdev
->rmmio
== NULL
) {
1431 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev
->rmmio_base
);
1432 DRM_INFO("register mmio size: %u\n", (unsigned)rdev
->rmmio_size
);
1434 /* doorbell bar mapping */
1435 if (rdev
->family
>= CHIP_BONAIRE
)
1436 radeon_doorbell_init(rdev
);
1438 /* io port mapping */
1439 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1440 if (pci_resource_flags(rdev
->pdev
, i
) & IORESOURCE_IO
) {
1441 rdev
->rio_mem_size
= pci_resource_len(rdev
->pdev
, i
);
1442 rdev
->rio_mem
= pci_iomap(rdev
->pdev
, i
, rdev
->rio_mem_size
);
1446 if (rdev
->rio_mem
== NULL
)
1447 DRM_ERROR("Unable to find PCI I/O BAR\n");
1449 if (rdev
->flags
& RADEON_IS_PX
)
1450 radeon_device_handle_px_quirks(rdev
);
1452 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1453 /* this will fail for cards that aren't VGA class devices, just
1455 vga_client_register(rdev
->pdev
, rdev
, NULL
, radeon_vga_set_decode
);
1457 if (rdev
->flags
& RADEON_IS_PX
)
1459 vga_switcheroo_register_client(rdev
->pdev
, &radeon_switcheroo_ops
, runtime
);
1461 vga_switcheroo_init_domain_pm_ops(rdev
->dev
, &rdev
->vga_pm_domain
);
1463 r
= radeon_init(rdev
);
1467 r
= radeon_gem_debugfs_init(rdev
);
1469 DRM_ERROR("registering gem debugfs failed (%d).\n", r
);
1472 r
= radeon_mst_debugfs_init(rdev
);
1474 DRM_ERROR("registering mst debugfs failed (%d).\n", r
);
1477 if (rdev
->flags
& RADEON_IS_AGP
&& !rdev
->accel_working
) {
1478 /* Acceleration not working on AGP card try again
1479 * with fallback to PCI or PCIE GART
1481 radeon_asic_reset(rdev
);
1483 radeon_agp_disable(rdev
);
1484 r
= radeon_init(rdev
);
1489 r
= radeon_ib_ring_tests(rdev
);
1491 DRM_ERROR("ib ring test failed (%d).\n", r
);
1494 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted
1495 * after the CP ring have chew one packet at least. Hence here we stop
1496 * and restart DPM after the radeon_ib_ring_tests().
1498 if (rdev
->pm
.dpm_enabled
&&
1499 (rdev
->pm
.pm_method
== PM_METHOD_DPM
) &&
1500 (rdev
->family
== CHIP_TURKS
) &&
1501 (rdev
->flags
& RADEON_IS_MOBILITY
)) {
1502 mutex_lock(&rdev
->pm
.mutex
);
1503 radeon_dpm_disable(rdev
);
1504 radeon_dpm_enable(rdev
);
1505 mutex_unlock(&rdev
->pm
.mutex
);
1508 if ((radeon_testing
& 1)) {
1509 if (rdev
->accel_working
)
1510 radeon_test_moves(rdev
);
1512 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1514 if ((radeon_testing
& 2)) {
1515 if (rdev
->accel_working
)
1516 radeon_test_syncing(rdev
);
1518 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1520 if (radeon_benchmarking
) {
1521 if (rdev
->accel_working
)
1522 radeon_benchmark(rdev
, radeon_benchmarking
);
1524 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1530 vga_switcheroo_fini_domain_pm_ops(rdev
->dev
);
1534 static void radeon_debugfs_remove_files(struct radeon_device
*rdev
);
1537 * radeon_device_fini - tear down the driver
1539 * @rdev: radeon_device pointer
1541 * Tear down the driver info (all asics).
1542 * Called at driver shutdown.
1544 void radeon_device_fini(struct radeon_device
*rdev
)
1546 DRM_INFO("radeon: finishing device.\n");
1547 rdev
->shutdown
= true;
1548 /* evict vram memory */
1549 radeon_bo_evict_vram(rdev
);
1551 vga_switcheroo_unregister_client(rdev
->pdev
);
1552 if (rdev
->flags
& RADEON_IS_PX
)
1553 vga_switcheroo_fini_domain_pm_ops(rdev
->dev
);
1554 vga_client_register(rdev
->pdev
, NULL
, NULL
, NULL
);
1556 pci_iounmap(rdev
->pdev
, rdev
->rio_mem
);
1557 rdev
->rio_mem
= NULL
;
1558 iounmap(rdev
->rmmio
);
1560 if (rdev
->family
>= CHIP_BONAIRE
)
1561 radeon_doorbell_fini(rdev
);
1562 radeon_debugfs_remove_files(rdev
);
1570 * radeon_suspend_kms - initiate device suspend
1572 * @pdev: drm dev pointer
1573 * @state: suspend state
1575 * Puts the hw in the suspend state (all asics).
1576 * Returns 0 for success or an error on failure.
1577 * Called at driver suspend.
1579 int radeon_suspend_kms(struct drm_device
*dev
, bool suspend
,
1580 bool fbcon
, bool freeze
)
1582 struct radeon_device
*rdev
;
1583 struct drm_crtc
*crtc
;
1584 struct drm_connector
*connector
;
1587 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
1591 rdev
= dev
->dev_private
;
1593 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1596 drm_kms_helper_poll_disable(dev
);
1598 drm_modeset_lock_all(dev
);
1599 /* turn off display hw */
1600 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1601 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_OFF
);
1603 drm_modeset_unlock_all(dev
);
1605 /* unpin the front buffers and cursors */
1606 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1607 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1608 struct radeon_framebuffer
*rfb
= to_radeon_framebuffer(crtc
->primary
->fb
);
1609 struct radeon_bo
*robj
;
1611 if (radeon_crtc
->cursor_bo
) {
1612 struct radeon_bo
*robj
= gem_to_radeon_bo(radeon_crtc
->cursor_bo
);
1613 r
= radeon_bo_reserve(robj
, false);
1615 radeon_bo_unpin(robj
);
1616 radeon_bo_unreserve(robj
);
1620 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
1623 robj
= gem_to_radeon_bo(rfb
->obj
);
1624 /* don't unpin kernel fb objects */
1625 if (!radeon_fbdev_robj_is_fb(rdev
, robj
)) {
1626 r
= radeon_bo_reserve(robj
, false);
1628 radeon_bo_unpin(robj
);
1629 radeon_bo_unreserve(robj
);
1633 /* evict vram memory */
1634 radeon_bo_evict_vram(rdev
);
1636 /* wait for gpu to finish processing current batch */
1637 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
1638 r
= radeon_fence_wait_empty(rdev
, i
);
1640 /* delay GPU reset to resume */
1641 radeon_fence_driver_force_completion(rdev
, i
);
1645 radeon_save_bios_scratch_regs(rdev
);
1647 radeon_suspend(rdev
);
1648 radeon_hpd_fini(rdev
);
1649 /* evict remaining vram memory */
1650 radeon_bo_evict_vram(rdev
);
1652 radeon_agp_suspend(rdev
);
1654 pci_save_state(dev
->pdev
);
1655 if (freeze
&& rdev
->family
>= CHIP_CEDAR
) {
1656 rdev
->asic
->asic_reset(rdev
, true);
1657 pci_restore_state(dev
->pdev
);
1658 } else if (suspend
) {
1659 /* Shut down the device */
1660 pci_disable_device(dev
->pdev
);
1661 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
1666 radeon_fbdev_set_suspend(rdev
, 1);
1673 * radeon_resume_kms - initiate device resume
1675 * @pdev: drm dev pointer
1677 * Bring the hw back to operating state (all asics).
1678 * Returns 0 for success or an error on failure.
1679 * Called at driver resume.
1681 int radeon_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
)
1683 struct drm_connector
*connector
;
1684 struct radeon_device
*rdev
= dev
->dev_private
;
1685 struct drm_crtc
*crtc
;
1688 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1695 pci_set_power_state(dev
->pdev
, PCI_D0
);
1696 pci_restore_state(dev
->pdev
);
1697 if (pci_enable_device(dev
->pdev
)) {
1703 /* resume AGP if in use */
1704 radeon_agp_resume(rdev
);
1705 radeon_resume(rdev
);
1707 r
= radeon_ib_ring_tests(rdev
);
1709 DRM_ERROR("ib ring test failed (%d).\n", r
);
1711 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
) {
1712 /* do dpm late init */
1713 r
= radeon_pm_late_init(rdev
);
1715 rdev
->pm
.dpm_enabled
= false;
1716 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1719 /* resume old pm late */
1720 radeon_pm_resume(rdev
);
1723 radeon_restore_bios_scratch_regs(rdev
);
1726 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1727 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1729 if (radeon_crtc
->cursor_bo
) {
1730 struct radeon_bo
*robj
= gem_to_radeon_bo(radeon_crtc
->cursor_bo
);
1731 r
= radeon_bo_reserve(robj
, false);
1733 /* Only 27 bit offset for legacy cursor */
1734 r
= radeon_bo_pin_restricted(robj
,
1735 RADEON_GEM_DOMAIN_VRAM
,
1736 ASIC_IS_AVIVO(rdev
) ?
1738 &radeon_crtc
->cursor_addr
);
1740 DRM_ERROR("Failed to pin cursor BO (%d)\n", r
);
1741 radeon_bo_unreserve(robj
);
1746 /* init dig PHYs, disp eng pll */
1747 if (rdev
->is_atom_bios
) {
1748 radeon_atom_encoder_init(rdev
);
1749 radeon_atom_disp_eng_pll_init(rdev
);
1750 /* turn on the BL */
1751 if (rdev
->mode_info
.bl_encoder
) {
1752 u8 bl_level
= radeon_get_backlight_level(rdev
,
1753 rdev
->mode_info
.bl_encoder
);
1754 radeon_set_backlight_level(rdev
, rdev
->mode_info
.bl_encoder
,
1758 /* reset hpd state */
1759 radeon_hpd_init(rdev
);
1760 /* blat the mode back in */
1762 drm_helper_resume_force_mode(dev
);
1763 /* turn on display hw */
1764 drm_modeset_lock_all(dev
);
1765 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1766 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_ON
);
1768 drm_modeset_unlock_all(dev
);
1771 drm_kms_helper_poll_enable(dev
);
1773 /* set the power state here in case we are a PX system or headless */
1774 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
)
1775 radeon_pm_compute_clocks(rdev
);
1778 radeon_fbdev_set_suspend(rdev
, 0);
1786 * radeon_gpu_reset - reset the asic
1788 * @rdev: radeon device pointer
1790 * Attempt the reset the GPU if it has hung (all asics).
1791 * Returns 0 for success or an error on failure.
1793 int radeon_gpu_reset(struct radeon_device
*rdev
)
1795 unsigned ring_sizes
[RADEON_NUM_RINGS
];
1796 uint32_t *ring_data
[RADEON_NUM_RINGS
];
1803 down_write(&rdev
->exclusive_lock
);
1805 if (!rdev
->needs_reset
) {
1806 up_write(&rdev
->exclusive_lock
);
1810 atomic_inc(&rdev
->gpu_reset_counter
);
1812 radeon_save_bios_scratch_regs(rdev
);
1814 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
1815 radeon_suspend(rdev
);
1816 radeon_hpd_fini(rdev
);
1818 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1819 ring_sizes
[i
] = radeon_ring_backup(rdev
, &rdev
->ring
[i
],
1821 if (ring_sizes
[i
]) {
1823 dev_info(rdev
->dev
, "Saved %d dwords of commands "
1824 "on ring %d.\n", ring_sizes
[i
], i
);
1828 r
= radeon_asic_reset(rdev
);
1830 dev_info(rdev
->dev
, "GPU reset succeeded, trying to resume\n");
1831 radeon_resume(rdev
);
1834 radeon_restore_bios_scratch_regs(rdev
);
1836 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1837 if (!r
&& ring_data
[i
]) {
1838 radeon_ring_restore(rdev
, &rdev
->ring
[i
],
1839 ring_sizes
[i
], ring_data
[i
]);
1841 radeon_fence_driver_force_completion(rdev
, i
);
1842 kfree(ring_data
[i
]);
1846 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
) {
1847 /* do dpm late init */
1848 r
= radeon_pm_late_init(rdev
);
1850 rdev
->pm
.dpm_enabled
= false;
1851 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1854 /* resume old pm late */
1855 radeon_pm_resume(rdev
);
1858 /* init dig PHYs, disp eng pll */
1859 if (rdev
->is_atom_bios
) {
1860 radeon_atom_encoder_init(rdev
);
1861 radeon_atom_disp_eng_pll_init(rdev
);
1862 /* turn on the BL */
1863 if (rdev
->mode_info
.bl_encoder
) {
1864 u8 bl_level
= radeon_get_backlight_level(rdev
,
1865 rdev
->mode_info
.bl_encoder
);
1866 radeon_set_backlight_level(rdev
, rdev
->mode_info
.bl_encoder
,
1870 /* reset hpd state */
1871 radeon_hpd_init(rdev
);
1873 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
1875 rdev
->in_reset
= true;
1876 rdev
->needs_reset
= false;
1878 downgrade_write(&rdev
->exclusive_lock
);
1880 drm_helper_resume_force_mode(rdev
->ddev
);
1882 /* set the power state here in case we are a PX system or headless */
1883 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
)
1884 radeon_pm_compute_clocks(rdev
);
1887 r
= radeon_ib_ring_tests(rdev
);
1891 /* bad news, how to tell it to userspace ? */
1892 dev_info(rdev
->dev
, "GPU reset failed\n");
1895 rdev
->needs_reset
= r
== -EAGAIN
;
1896 rdev
->in_reset
= false;
1898 up_read(&rdev
->exclusive_lock
);
1906 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
1907 struct drm_info_list
*files
,
1912 for (i
= 0; i
< rdev
->debugfs_count
; i
++) {
1913 if (rdev
->debugfs
[i
].files
== files
) {
1914 /* Already registered */
1919 i
= rdev
->debugfs_count
+ 1;
1920 if (i
> RADEON_DEBUGFS_MAX_COMPONENTS
) {
1921 DRM_ERROR("Reached maximum number of debugfs components.\n");
1922 DRM_ERROR("Report so we increase "
1923 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1926 rdev
->debugfs
[rdev
->debugfs_count
].files
= files
;
1927 rdev
->debugfs
[rdev
->debugfs_count
].num_files
= nfiles
;
1928 rdev
->debugfs_count
= i
;
1929 #if defined(CONFIG_DEBUG_FS)
1930 drm_debugfs_create_files(files
, nfiles
,
1931 rdev
->ddev
->control
->debugfs_root
,
1932 rdev
->ddev
->control
);
1933 drm_debugfs_create_files(files
, nfiles
,
1934 rdev
->ddev
->primary
->debugfs_root
,
1935 rdev
->ddev
->primary
);
1940 static void radeon_debugfs_remove_files(struct radeon_device
*rdev
)
1942 #if defined(CONFIG_DEBUG_FS)
1945 for (i
= 0; i
< rdev
->debugfs_count
; i
++) {
1946 drm_debugfs_remove_files(rdev
->debugfs
[i
].files
,
1947 rdev
->debugfs
[i
].num_files
,
1948 rdev
->ddev
->control
);
1949 drm_debugfs_remove_files(rdev
->debugfs
[i
].files
,
1950 rdev
->debugfs
[i
].num_files
,
1951 rdev
->ddev
->primary
);
1956 #if defined(CONFIG_DEBUG_FS)
1957 int radeon_debugfs_init(struct drm_minor
*minor
)
1962 void radeon_debugfs_cleanup(struct drm_minor
*minor
)