drivers/gpu/drm/radeon/radeon_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <linux/efi.h>
  36 #include "radeon_reg.h"
  37 #include "radeon.h"
  38 #include "atom.h"
  39
  40 static const char radeon_family_name[][16] = {
  41         "R100",
  42         "RV100",
  43         "RS100",
  44         "RV200",
  45         "RS200",
  46         "R200",
  47         "RV250",
  48         "RS300",
  49         "RV280",
  50         "R300",
  51         "R350",
  52         "RV350",
  53         "RV380",
  54         "R420",
  55         "R423",
  56         "RV410",
  57         "RS400",
  58         "RS480",
  59         "RS600",
  60         "RS690",
  61         "RS740",
  62         "RV515",
  63         "R520",
  64         "RV530",
  65         "RV560",
  66         "RV570",
  67         "R580",
  68         "R600",
  69         "RV610",
  70         "RV630",
  71         "RV670",
  72         "RV620",
  73         "RV635",
  74         "RS780",
  75         "RS880",
  76         "RV770",
  77         "RV730",
  78         "RV710",
  79         "RV740",
  80         "CEDAR",
  81         "REDWOOD",
  82         "JUNIPER",
  83         "CYPRESS",
  84         "HEMLOCK",
  85         "PALM",
  86         "SUMO",
  87         "SUMO2",
  88         "BARTS",
  89         "TURKS",
  90         "CAICOS",
  91         "CAYMAN",
  92         "ARUBA",
  93         "TAHITI",
  94         "PITCAIRN",
  95         "VERDE",
  96         "LAST",
  97 };
  98
  99 /**
 100  * radeon_surface_init - Clear GPU surface registers.
 101  *
 102  * @rdev: radeon_device pointer
 103  *
 104  * Clear GPU surface registers (r1xx-r5xx).
 105  */
 106 void radeon_surface_init(struct radeon_device *rdev)
 107 {
 108         /* FIXME: check this out */
 109         if (rdev->family < CHIP_R600) {
 110                 int i;
 111
 112                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 113                         if (rdev->surface_regs[i].bo)
 114                                 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
 115                         else
 116                                 radeon_clear_surface_reg(rdev, i);
 117                 }
 118                 /* enable surfaces */
 119                 WREG32(RADEON_SURFACE_CNTL, 0);
 120         }
 121 }
 122
 123 /*
 124  * GPU scratch registers helpers function.
 125  */
 126 /**
 127  * radeon_scratch_init - Init scratch register driver information.
 128  *
 129  * @rdev: radeon_device pointer
 130  *
 131  * Init CP scratch register driver information (r1xx-r5xx)
 132  */
 133 void radeon_scratch_init(struct radeon_device *rdev)
 134 {
 135         int i;
 136
 137         /* FIXME: check this out */
 138         if (rdev->family < CHIP_R300) {
 139                 rdev->scratch.num_reg = 5;
 140         } else {
 141                 rdev->scratch.num_reg = 7;
 142         }
 143         rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
 144         for (i = 0; i < rdev->scratch.num_reg; i++) {
 145                 rdev->scratch.free[i] = true;
 146                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
 147         }
 148 }
 149
 150 /**
 151  * radeon_scratch_get - Allocate a scratch register
 152  *
 153  * @rdev: radeon_device pointer
 154  * @reg: scratch register mmio offset
 155  *
 156  * Allocate a CP scratch register for use by the driver (all asics).
 157  * Returns 0 on success or -EINVAL on failure.
 158  */
 159 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
 160 {
 161         int i;
 162
 163         for (i = 0; i < rdev->scratch.num_reg; i++) {
 164                 if (rdev->scratch.free[i]) {
 165                         rdev->scratch.free[i] = false;
 166                         *reg = rdev->scratch.reg[i];
 167                         return 0;
 168                 }
 169         }
 170         return -EINVAL;
 171 }
 172
 173 /**
 174  * radeon_scratch_free - Free a scratch register
 175  *
 176  * @rdev: radeon_device pointer
 177  * @reg: scratch register mmio offset
 178  *
 179  * Free a CP scratch register allocated for use by the driver (all asics)
 180  */
 181 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
 182 {
 183         int i;
 184
 185         for (i = 0; i < rdev->scratch.num_reg; i++) {
 186                 if (rdev->scratch.reg[i] == reg) {
 187                         rdev->scratch.free[i] = true;
 188                         return;
 189                 }
 190         }
 191 }
 192
 193 /*
 194  * radeon_wb_*()
 195  * Writeback is the the method by which the the GPU updates special pages
 196  * in memory with the status of certain GPU events (fences, ring pointers,
 197  * etc.).
 198  */
 199
 200 /**
 201  * radeon_wb_disable - Disable Writeback
 202  *
 203  * @rdev: radeon_device pointer
 204  *
 205  * Disables Writeback (all asics).  Used for suspend.
 206  */
 207 void radeon_wb_disable(struct radeon_device *rdev)
 208 {
 209         int r;
 210
 211         if (rdev->wb.wb_obj) {
 212                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 213                 if (unlikely(r != 0))
 214                         return;
 215                 radeon_bo_kunmap(rdev->wb.wb_obj);
 216                 radeon_bo_unpin(rdev->wb.wb_obj);
 217                 radeon_bo_unreserve(rdev->wb.wb_obj);
 218         }
 219         rdev->wb.enabled = false;
 220 }
 221
 222 /**
 223  * radeon_wb_fini - Disable Writeback and free memory
 224  *
 225  * @rdev: radeon_device pointer
 226  *
 227  * Disables Writeback and frees the Writeback memory (all asics).
 228  * Used at driver shutdown.
 229  */
 230 void radeon_wb_fini(struct radeon_device *rdev)
 231 {
 232         radeon_wb_disable(rdev);
 233         if (rdev->wb.wb_obj) {
 234                 radeon_bo_unref(&rdev->wb.wb_obj);
 235                 rdev->wb.wb = NULL;
 236                 rdev->wb.wb_obj = NULL;
 237         }
 238 }
 239
 240 /**
 241  * radeon_wb_init- Init Writeback driver info and allocate memory
 242  *
 243  * @rdev: radeon_device pointer
 244  *
 245  * Disables Writeback and frees the Writeback memory (all asics).
 246  * Used at driver startup.
 247  * Returns 0 on success or an -error on failure.
 248  */
 249 int radeon_wb_init(struct radeon_device *rdev)
 250 {
 251         int r;
 252
 253         if (rdev->wb.wb_obj == NULL) {
 254                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
 255                                      RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
 256                 if (r) {
 257                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
 258                         return r;
 259                 }
 260         }
 261         r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 262         if (unlikely(r != 0)) {
 263                 radeon_wb_fini(rdev);
 264                 return r;
 265         }
 266         r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 267                           &rdev->wb.gpu_addr);
 268         if (r) {
 269                 radeon_bo_unreserve(rdev->wb.wb_obj);
 270                 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
 271                 radeon_wb_fini(rdev);
 272                 return r;
 273         }
 274         r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 275         radeon_bo_unreserve(rdev->wb.wb_obj);
 276         if (r) {
 277                 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
 278                 radeon_wb_fini(rdev);
 279                 return r;
 280         }
 281
 282         /* clear wb memory */
 283         memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
 284         /* disable event_write fences */
 285         rdev->wb.use_event = false;
 286         /* disabled via module param */
 287         if (radeon_no_wb == 1) {
 288                 rdev->wb.enabled = false;
 289         } else {
 290                 if (rdev->flags & RADEON_IS_AGP) {
 291                         /* often unreliable on AGP */
 292                         rdev->wb.enabled = false;
 293                 } else if (rdev->family < CHIP_R300) {
 294                         /* often unreliable on pre-r300 */
 295                         rdev->wb.enabled = false;
 296                 } else {
 297                         rdev->wb.enabled = true;
 298                         /* event_write fences are only available on r600+ */
 299                         if (rdev->family >= CHIP_R600) {
 300                                 rdev->wb.use_event = true;
 301                         }
 302                 }
 303         }
 304         /* always use writeback/events on NI, APUs */
 305         if (rdev->family >= CHIP_PALM) {
 306                 rdev->wb.enabled = true;
 307                 rdev->wb.use_event = true;
 308         }
 309
 310         dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
 311
 312         return 0;
 313 }
 314
 315 /**
 316  * radeon_vram_location - try to find VRAM location
 317  * @rdev: radeon device structure holding all necessary informations
 318  * @mc: memory controller structure holding memory informations
 319  * @base: base address at which to put VRAM
 320  *
 321  * Function will place try to place VRAM at base address provided
 322  * as parameter (which is so far either PCI aperture address or
 323  * for IGP TOM base address).
 324  *
 325  * If there is not enough space to fit the unvisible VRAM in the 32bits
 326  * address space then we limit the VRAM size to the aperture.
 327  *
 328  * If we are using AGP and if the AGP aperture doesn't allow us to have
 329  * room for all the VRAM than we restrict the VRAM to the PCI aperture
 330  * size and print a warning.
 331  *
 332  * This function will never fails, worst case are limiting VRAM.
 333  *
 334  * Note: GTT start, end, size should be initialized before calling this
 335  * function on AGP platform.
 336  *
 337  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 338  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 339  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 340  * not IGP.
 341  *
 342  * Note: we use mc_vram_size as on some board we need to program the mc to
 343  * cover the whole aperture even if VRAM size is inferior to aperture size
 344  * Novell bug 204882 + along with lots of ubuntu ones
 345  *
 346  * Note: when limiting vram it's safe to overwritte real_vram_size because
 347  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 348  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 349  * ones)
 350  *
 351  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 352  * explicitly check for that thought.
 353  *
 354  * FIXME: when reducing VRAM size align new size on power of 2.
 355  */
 356 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
 357 {
 358         uint64_t limit = (uint64_t)radeon_vram_limit << 20;
 359
 360         mc->vram_start = base;
 361         if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
 362                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 363                 mc->real_vram_size = mc->aper_size;
 364                 mc->mc_vram_size = mc->aper_size;
 365         }
 366         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 367         if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
 368                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 369                 mc->real_vram_size = mc->aper_size;
 370                 mc->mc_vram_size = mc->aper_size;
 371         }
 372         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 373         if (limit && limit < mc->real_vram_size)
 374                 mc->real_vram_size = limit;
 375         dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 376                         mc->mc_vram_size >> 20, mc->vram_start,
 377                         mc->vram_end, mc->real_vram_size >> 20);
 378 }
 379
 380 /**
 381  * radeon_gtt_location - try to find GTT location
 382  * @rdev: radeon device structure holding all necessary informations
 383  * @mc: memory controller structure holding memory informations
 384  *
 385  * Function will place try to place GTT before or after VRAM.
 386  *
 387  * If GTT size is bigger than space left then we ajust GTT size.
 388  * Thus function will never fails.
 389  *
 390  * FIXME: when reducing GTT size align new size on power of 2.
 391  */
 392 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 393 {
 394         u64 size_af, size_bf;
 395
 396         size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 397         size_bf = mc->vram_start & ~mc->gtt_base_align;
 398         if (size_bf > size_af) {
 399                 if (mc->gtt_size > size_bf) {
 400                         dev_warn(rdev->dev, "limiting GTT\n");
 401                         mc->gtt_size = size_bf;
 402                 }
 403                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 404         } else {
 405                 if (mc->gtt_size > size_af) {
 406                         dev_warn(rdev->dev, "limiting GTT\n");
 407                         mc->gtt_size = size_af;
 408                 }
 409                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 410         }
 411         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 412         dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 413                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 414 }
 415
 416 /*
 417  * GPU helpers function.
 418  */
 419 /**
 420  * radeon_card_posted - check if the hw has already been initialized
 421  *
 422  * @rdev: radeon_device pointer
 423  *
 424  * Check if the asic has been initialized (all asics).
 425  * Used at driver startup.
 426  * Returns true if initialized or false if not.
 427  */
 428 bool radeon_card_posted(struct radeon_device *rdev)
 429 {
 430         uint32_t reg;
 431
 432         if (efi_enabled && rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)
 433                 return false;
 434
 435         /* first check CRTCs */
 436         if (ASIC_IS_DCE41(rdev)) {
 437                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 438                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 439                 if (reg & EVERGREEN_CRTC_MASTER_EN)
 440                         return true;
 441         } else if (ASIC_IS_DCE4(rdev)) {
 442                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 443                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
 444                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
 445                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
 446                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
 447                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 448                 if (reg & EVERGREEN_CRTC_MASTER_EN)
 449                         return true;
 450         } else if (ASIC_IS_AVIVO(rdev)) {
 451                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 452                       RREG32(AVIVO_D2CRTC_CONTROL);
 453                 if (reg & AVIVO_CRTC_EN) {
 454                         return true;
 455                 }
 456         } else {
 457                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 458                       RREG32(RADEON_CRTC2_GEN_CNTL);
 459                 if (reg & RADEON_CRTC_EN) {
 460                         return true;
 461                 }
 462         }
 463
 464         /* then check MEM_SIZE, in case the crtcs are off */
 465         if (rdev->family >= CHIP_R600)
 466                 reg = RREG32(R600_CONFIG_MEMSIZE);
 467         else
 468                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
 469
 470         if (reg)
 471                 return true;
 472
 473         return false;
 474
 475 }
 476
 477 /**
 478  * radeon_update_bandwidth_info - update display bandwidth params
 479  *
 480  * @rdev: radeon_device pointer
 481  *
 482  * Used when sclk/mclk are switched or display modes are set.
 483  * params are used to calculate display watermarks (all asics)
 484  */
 485 void radeon_update_bandwidth_info(struct radeon_device *rdev)
 486 {
 487         fixed20_12 a;
 488         u32 sclk = rdev->pm.current_sclk;
 489         u32 mclk = rdev->pm.current_mclk;
 490
 491         /* sclk/mclk in Mhz */
 492         a.full = dfixed_const(100);
 493         rdev->pm.sclk.full = dfixed_const(sclk);
 494         rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
 495         rdev->pm.mclk.full = dfixed_const(mclk);
 496         rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 497
 498         if (rdev->flags & RADEON_IS_IGP) {
 499                 a.full = dfixed_const(16);
 500                 /* core_bandwidth = sclk(Mhz) * 16 */
 501                 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
 502         }
 503 }
 504
 505 /**
 506  * radeon_boot_test_post_card - check and possibly initialize the hw
 507  *
 508  * @rdev: radeon_device pointer
 509  *
 510  * Check if the asic is initialized and if not, attempt to initialize
 511  * it (all asics).
 512  * Returns true if initialized or false if not.
 513  */
 514 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 515 {
 516         if (radeon_card_posted(rdev))
 517                 return true;
 518
 519         if (rdev->bios) {
 520                 DRM_INFO("GPU not posted. posting now...\n");
 521                 if (rdev->is_atom_bios)
 522                         atom_asic_init(rdev->mode_info.atom_context);
 523                 else
 524                         radeon_combios_asic_init(rdev->ddev);
 525                 return true;
 526         } else {
 527                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 528                 return false;
 529         }
 530 }
 531
 532 /**
 533  * radeon_dummy_page_init - init dummy page used by the driver
 534  *
 535  * @rdev: radeon_device pointer
 536  *
 537  * Allocate the dummy page used by the driver (all asics).
 538  * This dummy page is used by the driver as a filler for gart entries
 539  * when pages are taken out of the GART
 540  * Returns 0 on sucess, -ENOMEM on failure.
 541  */
 542 int radeon_dummy_page_init(struct radeon_device *rdev)
 543 {
 544         if (rdev->dummy_page.page)
 545                 return 0;
 546         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 547         if (rdev->dummy_page.page == NULL)
 548                 return -ENOMEM;
 549         rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 550                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 551         if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
 552                 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 553                 __free_page(rdev->dummy_page.page);
 554                 rdev->dummy_page.page = NULL;
 555                 return -ENOMEM;
 556         }
 557         return 0;
 558 }
 559
 560 /**
 561  * radeon_dummy_page_fini - free dummy page used by the driver
 562  *
 563  * @rdev: radeon_device pointer
 564  *
 565  * Frees the dummy page used by the driver (all asics).
 566  */
 567 void radeon_dummy_page_fini(struct radeon_device *rdev)
 568 {
 569         if (rdev->dummy_page.page == NULL)
 570                 return;
 571         pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 572                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 573         __free_page(rdev->dummy_page.page);
 574         rdev->dummy_page.page = NULL;
 575 }
 576
 577
 578 /* ATOM accessor methods */
 579 /*
 580  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 581  * driver registers callbacks to access registers and the interpreter
 582  * in the driver parses the tables and executes then to program specific
 583  * actions (set display modes, asic init, etc.).  See radeon_atombios.c,
 584  * atombios.h, and atom.c
 585  */
 586
 587 /**
 588  * cail_pll_read - read PLL register
 589  *
 590  * @info: atom card_info pointer
 591  * @reg: PLL register offset
 592  *
 593  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 594  * Returns the value of the PLL register.
 595  */
 596 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 597 {
 598         struct radeon_device *rdev = info->dev->dev_private;
 599         uint32_t r;
 600
 601         r = rdev->pll_rreg(rdev, reg);
 602         return r;
 603 }
 604
 605 /**
 606  * cail_pll_write - write PLL register
 607  *
 608  * @info: atom card_info pointer
 609  * @reg: PLL register offset
 610  * @val: value to write to the pll register
 611  *
 612  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 613  */
 614 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 615 {
 616         struct radeon_device *rdev = info->dev->dev_private;
 617
 618         rdev->pll_wreg(rdev, reg, val);
 619 }
 620
 621 /**
 622  * cail_mc_read - read MC (Memory Controller) register
 623  *
 624  * @info: atom card_info pointer
 625  * @reg: MC register offset
 626  *
 627  * Provides an MC register accessor for the atom interpreter (r4xx+).
 628  * Returns the value of the MC register.
 629  */
 630 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 631 {
 632         struct radeon_device *rdev = info->dev->dev_private;
 633         uint32_t r;
 634
 635         r = rdev->mc_rreg(rdev, reg);
 636         return r;
 637 }
 638
 639 /**
 640  * cail_mc_write - write MC (Memory Controller) register
 641  *
 642  * @info: atom card_info pointer
 643  * @reg: MC register offset
 644  * @val: value to write to the pll register
 645  *
 646  * Provides a MC register accessor for the atom interpreter (r4xx+).
 647  */
 648 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 649 {
 650         struct radeon_device *rdev = info->dev->dev_private;
 651
 652         rdev->mc_wreg(rdev, reg, val);
 653 }
 654
 655 /**
 656  * cail_reg_write - write MMIO register
 657  *
 658  * @info: atom card_info pointer
 659  * @reg: MMIO register offset
 660  * @val: value to write to the pll register
 661  *
 662  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 663  */
 664 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 665 {
 666         struct radeon_device *rdev = info->dev->dev_private;
 667
 668         WREG32(reg*4, val);
 669 }
 670
 671 /**
 672  * cail_reg_read - read MMIO register
 673  *
 674  * @info: atom card_info pointer
 675  * @reg: MMIO register offset
 676  *
 677  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 678  * Returns the value of the MMIO register.
 679  */
 680 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 681 {
 682         struct radeon_device *rdev = info->dev->dev_private;
 683         uint32_t r;
 684
 685         r = RREG32(reg*4);
 686         return r;
 687 }
 688
 689 /**
 690  * cail_ioreg_write - write IO register
 691  *
 692  * @info: atom card_info pointer
 693  * @reg: IO register offset
 694  * @val: value to write to the pll register
 695  *
 696  * Provides a IO register accessor for the atom interpreter (r4xx+).
 697  */
 698 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 699 {
 700         struct radeon_device *rdev = info->dev->dev_private;
 701
 702         WREG32_IO(reg*4, val);
 703 }
 704
 705 /**
 706  * cail_ioreg_read - read IO register
 707  *
 708  * @info: atom card_info pointer
 709  * @reg: IO register offset
 710  *
 711  * Provides an IO register accessor for the atom interpreter (r4xx+).
 712  * Returns the value of the IO register.
 713  */
 714 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 715 {
 716         struct radeon_device *rdev = info->dev->dev_private;
 717         uint32_t r;
 718
 719         r = RREG32_IO(reg*4);
 720         return r;
 721 }
 722
 723 /**
 724  * radeon_atombios_init - init the driver info and callbacks for atombios
 725  *
 726  * @rdev: radeon_device pointer
 727  *
 728  * Initializes the driver info and register access callbacks for the
 729  * ATOM interpreter (r4xx+).
 730  * Returns 0 on sucess, -ENOMEM on failure.
 731  * Called at driver startup.
 732  */
 733 int radeon_atombios_init(struct radeon_device *rdev)
 734 {
 735         struct card_info *atom_card_info =
 736             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 737
 738         if (!atom_card_info)
 739                 return -ENOMEM;
 740
 741         rdev->mode_info.atom_card_info = atom_card_info;
 742         atom_card_info->dev = rdev->ddev;
 743         atom_card_info->reg_read = cail_reg_read;
 744         atom_card_info->reg_write = cail_reg_write;
 745         /* needed for iio ops */
 746         if (rdev->rio_mem) {
 747                 atom_card_info->ioreg_read = cail_ioreg_read;
 748                 atom_card_info->ioreg_write = cail_ioreg_write;
 749         } else {
 750                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 751                 atom_card_info->ioreg_read = cail_reg_read;
 752                 atom_card_info->ioreg_write = cail_reg_write;
 753         }
 754         atom_card_info->mc_read = cail_mc_read;
 755         atom_card_info->mc_write = cail_mc_write;
 756         atom_card_info->pll_read = cail_pll_read;
 757         atom_card_info->pll_write = cail_pll_write;
 758
 759         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 760         mutex_init(&rdev->mode_info.atom_context->mutex);
 761         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 762         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
 763         return 0;
 764 }
 765
 766 /**
 767  * radeon_atombios_fini - free the driver info and callbacks for atombios
 768  *
 769  * @rdev: radeon_device pointer
 770  *
 771  * Frees the driver info and register access callbacks for the ATOM
 772  * interpreter (r4xx+).
 773  * Called at driver shutdown.
 774  */
 775 void radeon_atombios_fini(struct radeon_device *rdev)
 776 {
 777         if (rdev->mode_info.atom_context) {
 778                 kfree(rdev->mode_info.atom_context->scratch);
 779                 kfree(rdev->mode_info.atom_context);
 780         }
 781         kfree(rdev->mode_info.atom_card_info);
 782 }
 783
 784 /* COMBIOS */
 785 /*
 786  * COMBIOS is the bios format prior to ATOM. It provides
 787  * command tables similar to ATOM, but doesn't have a unified
 788  * parser.  See radeon_combios.c
 789  */
 790
 791 /**
 792  * radeon_combios_init - init the driver info for combios
 793  *
 794  * @rdev: radeon_device pointer
 795  *
 796  * Initializes the driver info for combios (r1xx-r3xx).
 797  * Returns 0 on sucess.
 798  * Called at driver startup.
 799  */
 800 int radeon_combios_init(struct radeon_device *rdev)
 801 {
 802         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
 803         return 0;
 804 }
 805
 806 /**
 807  * radeon_combios_fini - free the driver info for combios
 808  *
 809  * @rdev: radeon_device pointer
 810  *
 811  * Frees the driver info for combios (r1xx-r3xx).
 812  * Called at driver shutdown.
 813  */
 814 void radeon_combios_fini(struct radeon_device *rdev)
 815 {
 816 }
 817
 818 /* if we get transitioned to only one device, take VGA back */
 819 /**
 820  * radeon_vga_set_decode - enable/disable vga decode
 821  *
 822  * @cookie: radeon_device pointer
 823  * @state: enable/disable vga decode
 824  *
 825  * Enable/disable vga decode (all asics).
 826  * Returns VGA resource flags.
 827  */
 828 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
 829 {
 830         struct radeon_device *rdev = cookie;
 831         radeon_vga_set_state(rdev, state);
 832         if (state)
 833                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 834                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 835         else
 836                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 837 }
 838
 839 /**
 840  * radeon_check_pot_argument - check that argument is a power of two
 841  *
 842  * @arg: value to check
 843  *
 844  * Validates that a certain argument is a power of two (all asics).
 845  * Returns true if argument is valid.
 846  */
 847 static bool radeon_check_pot_argument(int arg)
 848 {
 849         return (arg & (arg - 1)) == 0;
 850 }
 851
 852 /**
 853  * radeon_check_arguments - validate module params
 854  *
 855  * @rdev: radeon_device pointer
 856  *
 857  * Validates certain module parameters and updates
 858  * the associated values used by the driver (all asics).
 859  */
 860 static void radeon_check_arguments(struct radeon_device *rdev)
 861 {
 862         /* vramlimit must be a power of two */
 863         if (!radeon_check_pot_argument(radeon_vram_limit)) {
 864                 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
 865                                 radeon_vram_limit);
 866                 radeon_vram_limit = 0;
 867         }
 868
 869         /* gtt size must be power of two and greater or equal to 32M */
 870         if (radeon_gart_size < 32) {
 871                 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
 872                                 radeon_gart_size);
 873                 radeon_gart_size = 512;
 874
 875         } else if (!radeon_check_pot_argument(radeon_gart_size)) {
 876                 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
 877                                 radeon_gart_size);
 878                 radeon_gart_size = 512;
 879         }
 880         rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
 881
 882         /* AGP mode can only be -1, 1, 2, 4, 8 */
 883         switch (radeon_agpmode) {
 884         case -1:
 885         case 0:
 886         case 1:
 887         case 2:
 888         case 4:
 889         case 8:
 890                 break;
 891         default:
 892                 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
 893                                 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
 894                 radeon_agpmode = 0;
 895                 break;
 896         }
 897 }
 898
 899 /**
 900  * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
 901  * needed for waking up.
 902  *
 903  * @pdev: pci dev pointer
 904  */
 905 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
 906 {
 907
 908         /* 6600m in a macbook pro */
 909         if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
 910             pdev->subsystem_device == 0x00e2) {
 911                 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
 912                 return true;
 913         }
 914
 915         return false;
 916 }
 917
 918 /**
 919  * radeon_switcheroo_set_state - set switcheroo state
 920  *
 921  * @pdev: pci dev pointer
 922  * @state: vga switcheroo state
 923  *
 924  * Callback for the switcheroo driver.  Suspends or resumes the
 925  * the asics before or after it is powered up using ACPI methods.
 926  */
 927 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 928 {
 929         struct drm_device *dev = pci_get_drvdata(pdev);
 930         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 931         if (state == VGA_SWITCHEROO_ON) {
 932                 unsigned d3_delay = dev->pdev->d3_delay;
 933
 934                 printk(KERN_INFO "radeon: switched on\n");
 935                 /* don't suspend or resume card normally */
 936                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 937
 938                 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
 939                         dev->pdev->d3_delay = 20;
 940
 941                 radeon_resume_kms(dev);
 942
 943                 dev->pdev->d3_delay = d3_delay;
 944
 945                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 946                 drm_kms_helper_poll_enable(dev);
 947         } else {
 948                 printk(KERN_INFO "radeon: switched off\n");
 949                 drm_kms_helper_poll_disable(dev);
 950                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 951                 radeon_suspend_kms(dev, pmm);
 952                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 953         }
 954 }
 955
 956 /**
 957  * radeon_switcheroo_can_switch - see if switcheroo state can change
 958  *
 959  * @pdev: pci dev pointer
 960  *
 961  * Callback for the switcheroo driver.  Check of the switcheroo
 962  * state can be changed.
 963  * Returns true if the state can be changed, false if not.
 964  */
 965 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
 966 {
 967         struct drm_device *dev = pci_get_drvdata(pdev);
 968         bool can_switch;
 969
 970         spin_lock(&dev->count_lock);
 971         can_switch = (dev->open_count == 0);
 972         spin_unlock(&dev->count_lock);
 973         return can_switch;
 974 }
 975
 976 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
 977         .set_gpu_state = radeon_switcheroo_set_state,
 978         .reprobe = NULL,
 979         .can_switch = radeon_switcheroo_can_switch,
 980 };
 981
 982 /**
 983  * radeon_device_init - initialize the driver
 984  *
 985  * @rdev: radeon_device pointer
 986  * @pdev: drm dev pointer
 987  * @pdev: pci dev pointer
 988  * @flags: driver flags
 989  *
 990  * Initializes the driver info and hw (all asics).
 991  * Returns 0 for success or an error on failure.
 992  * Called at driver startup.
 993  */
 994 int radeon_device_init(struct radeon_device *rdev,
 995                        struct drm_device *ddev,
 996                        struct pci_dev *pdev,
 997                        uint32_t flags)
 998 {
 999         int r, i;
1000         int dma_bits;
1001
1002         rdev->shutdown = false;
1003         rdev->dev = &pdev->dev;
1004         rdev->ddev = ddev;
1005         rdev->pdev = pdev;
1006         rdev->flags = flags;
1007         rdev->family = flags & RADEON_FAMILY_MASK;
1008         rdev->is_atom_bios = false;
1009         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1010         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
1011         rdev->accel_working = false;
1012         /* set up ring ids */
1013         for (i = 0; i < RADEON_NUM_RINGS; i++) {
1014                 rdev->ring[i].idx = i;
1015         }
1016
1017         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1018                 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1019                 pdev->subsystem_vendor, pdev->subsystem_device);
1020
1021         /* mutex initialization are all done here so we
1022          * can recall function without having locking issues */
1023         mutex_init(&rdev->ring_lock);
1024         mutex_init(&rdev->dc_hw_i2c_mutex);
1025         atomic_set(&rdev->ih.lock, 0);
1026         mutex_init(&rdev->gem.mutex);
1027         mutex_init(&rdev->pm.mutex);
1028         mutex_init(&rdev->gpu_clock_mutex);
1029         init_rwsem(&rdev->pm.mclk_lock);
1030         init_rwsem(&rdev->exclusive_lock);
1031         init_waitqueue_head(&rdev->irq.vblank_queue);
1032         r = radeon_gem_init(rdev);
1033         if (r)
1034                 return r;
1035         /* initialize vm here */
1036         mutex_init(&rdev->vm_manager.lock);
1037         /* Adjust VM size here.
1038          * Currently set to 4GB ((1 << 20) 4k pages).
1039          * Max GPUVM size for cayman and SI is 40 bits.
1040          */
1041         rdev->vm_manager.max_pfn = 1 << 20;
1042         INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1043
1044         /* Set asic functions */
1045         r = radeon_asic_init(rdev);
1046         if (r)
1047                 return r;
1048         radeon_check_arguments(rdev);
1049
1050         /* all of the newer IGP chips have an internal gart
1051          * However some rs4xx report as AGP, so remove that here.
1052          */
1053         if ((rdev->family >= CHIP_RS400) &&
1054             (rdev->flags & RADEON_IS_IGP)) {
1055                 rdev->flags &= ~RADEON_IS_AGP;
1056         }
1057
1058         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1059                 radeon_agp_disable(rdev);
1060         }
1061
1062         /* set DMA mask + need_dma32 flags.
1063          * PCIE - can handle 40-bits.
1064          * IGP - can handle 40-bits
1065          * AGP - generally dma32 is safest
1066          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1067          */
1068         rdev->need_dma32 = false;
1069         if (rdev->flags & RADEON_IS_AGP)
1070                 rdev->need_dma32 = true;
1071         if ((rdev->flags & RADEON_IS_PCI) &&
1072             (rdev->family <= CHIP_RS740))
1073                 rdev->need_dma32 = true;
1074
1075         dma_bits = rdev->need_dma32 ? 32 : 40;
1076         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1077         if (r) {
1078                 rdev->need_dma32 = true;
1079                 dma_bits = 32;
1080                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1081         }
1082         r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1083         if (r) {
1084                 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1085                 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1086         }
1087
1088         /* Registers mapping */
1089         /* TODO: block userspace mapping of io register */
1090         spin_lock_init(&rdev->mmio_idx_lock);
1091         rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1092         rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1093         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1094         if (rdev->rmmio == NULL) {
1095                 return -ENOMEM;
1096         }
1097         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1098         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1099
1100         /* io port mapping */
1101         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1102                 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1103                         rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1104                         rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1105                         break;
1106                 }
1107         }
1108         if (rdev->rio_mem == NULL)
1109                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1110
1111         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1112         /* this will fail for cards that aren't VGA class devices, just
1113          * ignore it */
1114         vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1115         vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops);
1116
1117         r = radeon_init(rdev);
1118         if (r)
1119                 return r;
1120
1121         r = radeon_ib_ring_tests(rdev);
1122         if (r)
1123                 DRM_ERROR("ib ring test failed (%d).\n", r);
1124
1125         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1126                 /* Acceleration not working on AGP card try again
1127                  * with fallback to PCI or PCIE GART
1128                  */
1129                 radeon_asic_reset(rdev);
1130                 radeon_fini(rdev);
1131                 radeon_agp_disable(rdev);
1132                 r = radeon_init(rdev);
1133                 if (r)
1134                         return r;
1135         }
1136         if ((radeon_testing & 1)) {
1137                 radeon_test_moves(rdev);
1138         }
1139         if ((radeon_testing & 2)) {
1140                 radeon_test_syncing(rdev);
1141         }
1142         if (radeon_benchmarking) {
1143                 radeon_benchmark(rdev, radeon_benchmarking);
1144         }
1145         return 0;
1146 }
1147
1148 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1149
1150 /**
1151  * radeon_device_fini - tear down the driver
1152  *
1153  * @rdev: radeon_device pointer
1154  *
1155  * Tear down the driver info (all asics).
1156  * Called at driver shutdown.
1157  */
1158 void radeon_device_fini(struct radeon_device *rdev)
1159 {
1160         DRM_INFO("radeon: finishing device.\n");
1161         rdev->shutdown = true;
1162         /* evict vram memory */
1163         radeon_bo_evict_vram(rdev);
1164         radeon_fini(rdev);
1165         vga_switcheroo_unregister_client(rdev->pdev);
1166         vga_client_register(rdev->pdev, NULL, NULL, NULL);
1167         if (rdev->rio_mem)
1168                 pci_iounmap(rdev->pdev, rdev->rio_mem);
1169         rdev->rio_mem = NULL;
1170         iounmap(rdev->rmmio);
1171         rdev->rmmio = NULL;
1172         radeon_debugfs_remove_files(rdev);
1173 }
1174
1175
1176 /*
1177  * Suspend & resume.
1178  */
1179 /**
1180  * radeon_suspend_kms - initiate device suspend
1181  *
1182  * @pdev: drm dev pointer
1183  * @state: suspend state
1184  *
1185  * Puts the hw in the suspend state (all asics).
1186  * Returns 0 for success or an error on failure.
1187  * Called at driver suspend.
1188  */
1189 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
1190 {
1191         struct radeon_device *rdev;
1192         struct drm_crtc *crtc;
1193         struct drm_connector *connector;
1194         int i, r;
1195         bool force_completion = false;
1196
1197         if (dev == NULL || dev->dev_private == NULL) {
1198                 return -ENODEV;
1199         }
1200         if (state.event == PM_EVENT_PRETHAW) {
1201                 return 0;
1202         }
1203         rdev = dev->dev_private;
1204
1205         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1206                 return 0;
1207
1208         drm_kms_helper_poll_disable(dev);
1209
1210         /* turn off display hw */
1211         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1212                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1213         }
1214
1215         /* unpin the front buffers */
1216         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1217                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
1218                 struct radeon_bo *robj;
1219
1220                 if (rfb == NULL || rfb->obj == NULL) {
1221                         continue;
1222                 }
1223                 robj = gem_to_radeon_bo(rfb->obj);
1224                 /* don't unpin kernel fb objects */
1225                 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1226                         r = radeon_bo_reserve(robj, false);
1227                         if (r == 0) {
1228                                 radeon_bo_unpin(robj);
1229                                 radeon_bo_unreserve(robj);
1230                         }
1231                 }
1232         }
1233         /* evict vram memory */
1234         radeon_bo_evict_vram(rdev);
1235
1236         mutex_lock(&rdev->ring_lock);
1237         /* wait for gpu to finish processing current batch */
1238         for (i = 0; i < RADEON_NUM_RINGS; i++) {
1239                 r = radeon_fence_wait_empty_locked(rdev, i);
1240                 if (r) {
1241                         /* delay GPU reset to resume */
1242                         force_completion = true;
1243                 }
1244         }
1245         if (force_completion) {
1246                 radeon_fence_driver_force_completion(rdev);
1247         }
1248         mutex_unlock(&rdev->ring_lock);
1249
1250         radeon_save_bios_scratch_regs(rdev);
1251
1252         radeon_pm_suspend(rdev);
1253         radeon_suspend(rdev);
1254         radeon_hpd_fini(rdev);
1255         /* evict remaining vram memory */
1256         radeon_bo_evict_vram(rdev);
1257
1258         radeon_agp_suspend(rdev);
1259
1260         pci_save_state(dev->pdev);
1261         if (state.event == PM_EVENT_SUSPEND) {
1262                 /* Shut down the device */
1263                 pci_disable_device(dev->pdev);
1264                 pci_set_power_state(dev->pdev, PCI_D3hot);
1265         }
1266         console_lock();
1267         radeon_fbdev_set_suspend(rdev, 1);
1268         console_unlock();
1269         return 0;
1270 }
1271
1272 /**
1273  * radeon_resume_kms - initiate device resume
1274  *
1275  * @pdev: drm dev pointer
1276  *
1277  * Bring the hw back to operating state (all asics).
1278  * Returns 0 for success or an error on failure.
1279  * Called at driver resume.
1280  */
1281 int radeon_resume_kms(struct drm_device *dev)
1282 {
1283         struct drm_connector *connector;
1284         struct radeon_device *rdev = dev->dev_private;
1285         int r;
1286
1287         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1288                 return 0;
1289
1290         console_lock();
1291         pci_set_power_state(dev->pdev, PCI_D0);
1292         pci_restore_state(dev->pdev);
1293         if (pci_enable_device(dev->pdev)) {
1294                 console_unlock();
1295                 return -1;
1296         }
1297         /* resume AGP if in use */
1298         radeon_agp_resume(rdev);
1299         radeon_resume(rdev);
1300
1301         r = radeon_ib_ring_tests(rdev);
1302         if (r)
1303                 DRM_ERROR("ib ring test failed (%d).\n", r);
1304
1305         radeon_pm_resume(rdev);
1306         radeon_restore_bios_scratch_regs(rdev);
1307
1308         radeon_fbdev_set_suspend(rdev, 0);
1309         console_unlock();
1310
1311         /* init dig PHYs, disp eng pll */
1312         if (rdev->is_atom_bios) {
1313                 radeon_atom_encoder_init(rdev);
1314                 radeon_atom_disp_eng_pll_init(rdev);
1315                 /* turn on the BL */
1316                 if (rdev->mode_info.bl_encoder) {
1317                         u8 bl_level = radeon_get_backlight_level(rdev,
1318                                                                  rdev->mode_info.bl_encoder);
1319                         radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1320                                                    bl_level);
1321                 }
1322         }
1323         /* reset hpd state */
1324         radeon_hpd_init(rdev);
1325         /* blat the mode back in */
1326         drm_helper_resume_force_mode(dev);
1327         /* turn on display hw */
1328         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1329                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1330         }
1331
1332         drm_kms_helper_poll_enable(dev);
1333         return 0;
1334 }
1335
1336 /**
1337  * radeon_gpu_reset - reset the asic
1338  *
1339  * @rdev: radeon device pointer
1340  *
1341  * Attempt the reset the GPU if it has hung (all asics).
1342  * Returns 0 for success or an error on failure.
1343  */
1344 int radeon_gpu_reset(struct radeon_device *rdev)
1345 {
1346         unsigned ring_sizes[RADEON_NUM_RINGS];
1347         uint32_t *ring_data[RADEON_NUM_RINGS];
1348
1349         bool saved = false;
1350
1351         int i, r;
1352         int resched;
1353
1354         down_write(&rdev->exclusive_lock);
1355         radeon_save_bios_scratch_regs(rdev);
1356         /* block TTM */
1357         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1358         radeon_suspend(rdev);
1359
1360         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1361                 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1362                                                    &ring_data[i]);
1363                 if (ring_sizes[i]) {
1364                         saved = true;
1365                         dev_info(rdev->dev, "Saved %d dwords of commands "
1366                                  "on ring %d.\n", ring_sizes[i], i);
1367                 }
1368         }
1369
1370 retry:
1371         r = radeon_asic_reset(rdev);
1372         if (!r) {
1373                 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1374                 radeon_resume(rdev);
1375         }
1376
1377         radeon_restore_bios_scratch_regs(rdev);
1378
1379         if (!r) {
1380                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1381                         radeon_ring_restore(rdev, &rdev->ring[i],
1382                                             ring_sizes[i], ring_data[i]);
1383                         ring_sizes[i] = 0;
1384                         ring_data[i] = NULL;
1385                 }
1386
1387                 r = radeon_ib_ring_tests(rdev);
1388                 if (r) {
1389                         dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1390                         if (saved) {
1391                                 saved = false;
1392                                 radeon_suspend(rdev);
1393                                 goto retry;
1394                         }
1395                 }
1396         } else {
1397                 radeon_fence_driver_force_completion(rdev);
1398                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1399                         kfree(ring_data[i]);
1400                 }
1401         }
1402
1403         drm_helper_resume_force_mode(rdev->ddev);
1404
1405         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1406         if (r) {
1407                 /* bad news, how to tell it to userspace ? */
1408                 dev_info(rdev->dev, "GPU reset failed\n");
1409         }
1410
1411         up_write(&rdev->exclusive_lock);
1412         return r;
1413 }
1414
1415
1416 /*
1417  * Debugfs
1418  */
1419 int radeon_debugfs_add_files(struct radeon_device *rdev,
1420                              struct drm_info_list *files,
1421                              unsigned nfiles)
1422 {
1423         unsigned i;
1424
1425         for (i = 0; i < rdev->debugfs_count; i++) {
1426                 if (rdev->debugfs[i].files == files) {
1427                         /* Already registered */
1428                         return 0;
1429                 }
1430         }
1431
1432         i = rdev->debugfs_count + 1;
1433         if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1434                 DRM_ERROR("Reached maximum number of debugfs components.\n");
1435                 DRM_ERROR("Report so we increase "
1436                           "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1437                 return -EINVAL;
1438         }
1439         rdev->debugfs[rdev->debugfs_count].files = files;
1440         rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1441         rdev->debugfs_count = i;
1442 #if defined(CONFIG_DEBUG_FS)
1443         drm_debugfs_create_files(files, nfiles,
1444                                  rdev->ddev->control->debugfs_root,
1445                                  rdev->ddev->control);
1446         drm_debugfs_create_files(files, nfiles,
1447                                  rdev->ddev->primary->debugfs_root,
1448                                  rdev->ddev->primary);
1449 #endif
1450         return 0;
1451 }
1452
1453 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1454 {
1455 #if defined(CONFIG_DEBUG_FS)
1456         unsigned i;
1457
1458         for (i = 0; i < rdev->debugfs_count; i++) {
1459                 drm_debugfs_remove_files(rdev->debugfs[i].files,
1460                                          rdev->debugfs[i].num_files,
1461                                          rdev->ddev->control);
1462                 drm_debugfs_remove_files(rdev->debugfs[i].files,
1463                                          rdev->debugfs[i].num_files,
1464                                          rdev->ddev->primary);
1465         }
1466 #endif
1467 }
1468
1469 #if defined(CONFIG_DEBUG_FS)
1470 int radeon_debugfs_init(struct drm_minor *minor)
1471 {
1472         return 0;
1473 }
1474
1475 void radeon_debugfs_cleanup(struct drm_minor *minor)
1476 {
1477 }
1478 #endif