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drm/radeon: separate vblank and pflip crtc handling
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_display.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include <linux/pm_runtime.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_edid.h>
36
37 #include <linux/gcd.h>
38
39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
40 {
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
44 int i;
45
46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
48
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
52
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
56
57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
58 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
60
61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
62 for (i = 0; i < 256; i++) {
63 WREG32(AVIVO_DC_LUT_30_COLOR,
64 (radeon_crtc->lut_r[i] << 20) |
65 (radeon_crtc->lut_g[i] << 10) |
66 (radeon_crtc->lut_b[i] << 0));
67 }
68
69 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
70 }
71
72 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
73 {
74 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
75 struct drm_device *dev = crtc->dev;
76 struct radeon_device *rdev = dev->dev_private;
77 int i;
78
79 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
80 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
81
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
85
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
89
90 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
91 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
92
93 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
94 for (i = 0; i < 256; i++) {
95 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
96 (radeon_crtc->lut_r[i] << 20) |
97 (radeon_crtc->lut_g[i] << 10) |
98 (radeon_crtc->lut_b[i] << 0));
99 }
100 }
101
102 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
103 {
104 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
105 struct drm_device *dev = crtc->dev;
106 struct radeon_device *rdev = dev->dev_private;
107 int i;
108
109 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
110
111 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
112 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
113 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
114 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
115 NI_GRPH_PRESCALE_BYPASS);
116 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
117 NI_OVL_PRESCALE_BYPASS);
118 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
119 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
120 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
121
122 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
123
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
127
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
131
132 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
133 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
134
135 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
136 for (i = 0; i < 256; i++) {
137 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
138 (radeon_crtc->lut_r[i] << 20) |
139 (radeon_crtc->lut_g[i] << 10) |
140 (radeon_crtc->lut_b[i] << 0));
141 }
142
143 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
144 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
145 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
148 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
149 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
150 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
151 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
152 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
153 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
154 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
155 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
156 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
157 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
158 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
159 if (ASIC_IS_DCE8(rdev)) {
160 /* XXX this only needs to be programmed once per crtc at startup,
161 * not sure where the best place for it is
162 */
163 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
164 CIK_CURSOR_ALPHA_BLND_ENA);
165 }
166 }
167
168 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
169 {
170 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
171 struct drm_device *dev = crtc->dev;
172 struct radeon_device *rdev = dev->dev_private;
173 int i;
174 uint32_t dac2_cntl;
175
176 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
177 if (radeon_crtc->crtc_id == 0)
178 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
179 else
180 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
181 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
182
183 WREG8(RADEON_PALETTE_INDEX, 0);
184 for (i = 0; i < 256; i++) {
185 WREG32(RADEON_PALETTE_30_DATA,
186 (radeon_crtc->lut_r[i] << 20) |
187 (radeon_crtc->lut_g[i] << 10) |
188 (radeon_crtc->lut_b[i] << 0));
189 }
190 }
191
192 void radeon_crtc_load_lut(struct drm_crtc *crtc)
193 {
194 struct drm_device *dev = crtc->dev;
195 struct radeon_device *rdev = dev->dev_private;
196
197 if (!crtc->enabled)
198 return;
199
200 if (ASIC_IS_DCE5(rdev))
201 dce5_crtc_load_lut(crtc);
202 else if (ASIC_IS_DCE4(rdev))
203 dce4_crtc_load_lut(crtc);
204 else if (ASIC_IS_AVIVO(rdev))
205 avivo_crtc_load_lut(crtc);
206 else
207 legacy_crtc_load_lut(crtc);
208 }
209
210 /** Sets the color ramps on behalf of fbcon */
211 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
212 u16 blue, int regno)
213 {
214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
215
216 radeon_crtc->lut_r[regno] = red >> 6;
217 radeon_crtc->lut_g[regno] = green >> 6;
218 radeon_crtc->lut_b[regno] = blue >> 6;
219 }
220
221 /** Gets the color ramps on behalf of fbcon */
222 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
223 u16 *blue, int regno)
224 {
225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
226
227 *red = radeon_crtc->lut_r[regno] << 6;
228 *green = radeon_crtc->lut_g[regno] << 6;
229 *blue = radeon_crtc->lut_b[regno] << 6;
230 }
231
232 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
233 u16 *blue, uint32_t start, uint32_t size)
234 {
235 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
236 int end = (start + size > 256) ? 256 : start + size, i;
237
238 /* userspace palettes are always correct as is */
239 for (i = start; i < end; i++) {
240 radeon_crtc->lut_r[i] = red[i] >> 6;
241 radeon_crtc->lut_g[i] = green[i] >> 6;
242 radeon_crtc->lut_b[i] = blue[i] >> 6;
243 }
244 radeon_crtc_load_lut(crtc);
245 }
246
247 static void radeon_crtc_destroy(struct drm_crtc *crtc)
248 {
249 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
250
251 drm_crtc_cleanup(crtc);
252 kfree(radeon_crtc);
253 }
254
255 /*
256 * Handle unpin events outside the interrupt handler proper.
257 */
258 static void radeon_unpin_work_func(struct work_struct *__work)
259 {
260 struct radeon_unpin_work *work =
261 container_of(__work, struct radeon_unpin_work, work);
262 int r;
263
264 /* unpin of the old buffer */
265 r = radeon_bo_reserve(work->old_rbo, false);
266 if (likely(r == 0)) {
267 r = radeon_bo_unpin(work->old_rbo);
268 if (unlikely(r != 0)) {
269 DRM_ERROR("failed to unpin buffer after flip\n");
270 }
271 radeon_bo_unreserve(work->old_rbo);
272 } else
273 DRM_ERROR("failed to reserve buffer after flip\n");
274
275 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
276 kfree(work);
277 }
278
279 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
280 {
281 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
282 struct radeon_unpin_work *work;
283 unsigned long flags;
284 u32 update_pending;
285 int vpos, hpos;
286
287 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
288 work = radeon_crtc->unpin_work;
289 if (work == NULL ||
290 (work->fence && !radeon_fence_signaled(work->fence))) {
291 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
292 return;
293 }
294 /* New pageflip, or just completion of a previous one? */
295 if (!radeon_crtc->deferred_flip_completion) {
296 /* do the flip (mmio) */
297 radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
298 update_pending = radeon_page_flip_pending(rdev, crtc_id);
299 } else {
300 /* This is just a completion of a flip queued in crtc
301 * at last invocation. Make sure we go directly to
302 * completion routine.
303 */
304 update_pending = 0;
305 }
306
307 /* Has the pageflip already completed in crtc, or is it certain
308 * to complete in this vblank?
309 */
310 if (update_pending &&
311 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
312 &vpos, &hpos, NULL, NULL)) &&
313 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
314 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
315 /* crtc didn't flip in this target vblank interval,
316 * but flip is pending in crtc. Based on the current
317 * scanout position we know that the current frame is
318 * (nearly) complete and the flip will (likely)
319 * complete before the start of the next frame.
320 */
321 update_pending = 0;
322 }
323 if (update_pending) {
324 /* crtc didn't flip in this target vblank interval,
325 * but flip is pending in crtc. It will complete it
326 * in next vblank interval, so complete the flip at
327 * next vblank irq.
328 */
329 radeon_crtc->deferred_flip_completion = 1;
330 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
331 return;
332 } else {
333 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
334 radeon_crtc_handle_flip(rdev, crtc_id);
335 }
336 }
337
338 /**
339 * radeon_crtc_handle_flip - page flip completed
340 *
341 * @rdev: radeon device pointer
342 * @crtc_id: crtc number this event is for
343 *
344 * Called when we are sure that a page flip for this crtc is completed.
345 */
346 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
347 {
348 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
349 struct radeon_unpin_work *work;
350 unsigned long flags;
351
352 /* this can happen at init */
353 if (radeon_crtc == NULL)
354 return;
355
356 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
357 work = radeon_crtc->unpin_work;
358 if (work == NULL) {
359 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
360 return;
361 }
362
363 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
364 radeon_crtc->unpin_work = NULL;
365 radeon_crtc->deferred_flip_completion = 0;
366
367 /* wakeup userspace */
368 if (work->event)
369 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
370
371 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
372
373 radeon_fence_unref(&work->fence);
374 radeon_irq_kms_pflip_irq_get(rdev, work->crtc_id);
375 schedule_work(&work->work);
376 }
377
378 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
379 struct drm_framebuffer *fb,
380 struct drm_pending_vblank_event *event,
381 uint32_t page_flip_flags)
382 {
383 struct drm_device *dev = crtc->dev;
384 struct radeon_device *rdev = dev->dev_private;
385 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
386 struct radeon_framebuffer *old_radeon_fb;
387 struct radeon_framebuffer *new_radeon_fb;
388 struct drm_gem_object *obj;
389 struct radeon_bo *rbo;
390 struct radeon_unpin_work *work;
391 unsigned long flags;
392 u32 tiling_flags, pitch_pixels;
393 u64 base;
394 int r;
395
396 work = kzalloc(sizeof *work, GFP_KERNEL);
397 if (work == NULL)
398 return -ENOMEM;
399
400 work->event = event;
401 work->rdev = rdev;
402 work->crtc_id = radeon_crtc->crtc_id;
403 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
404 new_radeon_fb = to_radeon_framebuffer(fb);
405 /* schedule unpin of the old buffer */
406 obj = old_radeon_fb->obj;
407 /* take a reference to the old object */
408 drm_gem_object_reference(obj);
409 rbo = gem_to_radeon_bo(obj);
410 work->old_rbo = rbo;
411 obj = new_radeon_fb->obj;
412 rbo = gem_to_radeon_bo(obj);
413
414 spin_lock(&rbo->tbo.bdev->fence_lock);
415 if (rbo->tbo.sync_obj)
416 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
417 spin_unlock(&rbo->tbo.bdev->fence_lock);
418
419 INIT_WORK(&work->work, radeon_unpin_work_func);
420
421 /* We borrow the event spin lock for protecting unpin_work */
422 spin_lock_irqsave(&dev->event_lock, flags);
423 if (radeon_crtc->unpin_work) {
424 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
425 r = -EBUSY;
426 goto unlock_free;
427 }
428 radeon_crtc->unpin_work = work;
429 radeon_crtc->deferred_flip_completion = 0;
430 spin_unlock_irqrestore(&dev->event_lock, flags);
431
432 /* pin the new buffer */
433 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
434 work->old_rbo, rbo);
435
436 r = radeon_bo_reserve(rbo, false);
437 if (unlikely(r != 0)) {
438 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
439 goto pflip_cleanup;
440 }
441 /* Only 27 bit offset for legacy CRTC */
442 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
443 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
444 if (unlikely(r != 0)) {
445 radeon_bo_unreserve(rbo);
446 r = -EINVAL;
447 DRM_ERROR("failed to pin new rbo buffer before flip\n");
448 goto pflip_cleanup;
449 }
450 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
451 radeon_bo_unreserve(rbo);
452
453 if (!ASIC_IS_AVIVO(rdev)) {
454 /* crtc offset is from display base addr not FB location */
455 base -= radeon_crtc->legacy_display_base_addr;
456 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
457
458 if (tiling_flags & RADEON_TILING_MACRO) {
459 if (ASIC_IS_R300(rdev)) {
460 base &= ~0x7ff;
461 } else {
462 int byteshift = fb->bits_per_pixel >> 4;
463 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
464 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
465 }
466 } else {
467 int offset = crtc->y * pitch_pixels + crtc->x;
468 switch (fb->bits_per_pixel) {
469 case 8:
470 default:
471 offset *= 1;
472 break;
473 case 15:
474 case 16:
475 offset *= 2;
476 break;
477 case 24:
478 offset *= 3;
479 break;
480 case 32:
481 offset *= 4;
482 break;
483 }
484 base += offset;
485 }
486 base &= ~7;
487 }
488
489 spin_lock_irqsave(&dev->event_lock, flags);
490 work->new_crtc_base = base;
491 spin_unlock_irqrestore(&dev->event_lock, flags);
492
493 /* update crtc fb */
494 crtc->primary->fb = fb;
495
496 /* set the proper interrupt */
497 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
498
499 return 0;
500
501 pflip_cleanup:
502 spin_lock_irqsave(&dev->event_lock, flags);
503 radeon_crtc->unpin_work = NULL;
504 unlock_free:
505 spin_unlock_irqrestore(&dev->event_lock, flags);
506 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
507 radeon_fence_unref(&work->fence);
508 kfree(work);
509
510 return r;
511 }
512
513 static int
514 radeon_crtc_set_config(struct drm_mode_set *set)
515 {
516 struct drm_device *dev;
517 struct radeon_device *rdev;
518 struct drm_crtc *crtc;
519 bool active = false;
520 int ret;
521
522 if (!set || !set->crtc)
523 return -EINVAL;
524
525 dev = set->crtc->dev;
526
527 ret = pm_runtime_get_sync(dev->dev);
528 if (ret < 0)
529 return ret;
530
531 ret = drm_crtc_helper_set_config(set);
532
533 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
534 if (crtc->enabled)
535 active = true;
536
537 pm_runtime_mark_last_busy(dev->dev);
538
539 rdev = dev->dev_private;
540 /* if we have active crtcs and we don't have a power ref,
541 take the current one */
542 if (active && !rdev->have_disp_power_ref) {
543 rdev->have_disp_power_ref = true;
544 return ret;
545 }
546 /* if we have no active crtcs, then drop the power ref
547 we got before */
548 if (!active && rdev->have_disp_power_ref) {
549 pm_runtime_put_autosuspend(dev->dev);
550 rdev->have_disp_power_ref = false;
551 }
552
553 /* drop the power reference we got coming in here */
554 pm_runtime_put_autosuspend(dev->dev);
555 return ret;
556 }
557 static const struct drm_crtc_funcs radeon_crtc_funcs = {
558 .cursor_set = radeon_crtc_cursor_set,
559 .cursor_move = radeon_crtc_cursor_move,
560 .gamma_set = radeon_crtc_gamma_set,
561 .set_config = radeon_crtc_set_config,
562 .destroy = radeon_crtc_destroy,
563 .page_flip = radeon_crtc_page_flip,
564 };
565
566 static void radeon_crtc_init(struct drm_device *dev, int index)
567 {
568 struct radeon_device *rdev = dev->dev_private;
569 struct radeon_crtc *radeon_crtc;
570 int i;
571
572 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
573 if (radeon_crtc == NULL)
574 return;
575
576 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
577
578 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
579 radeon_crtc->crtc_id = index;
580 rdev->mode_info.crtcs[index] = radeon_crtc;
581
582 if (rdev->family >= CHIP_BONAIRE) {
583 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
584 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
585 } else {
586 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
587 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
588 }
589 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
590 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
591
592 #if 0
593 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
594 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
595 radeon_crtc->mode_set.num_connectors = 0;
596 #endif
597
598 for (i = 0; i < 256; i++) {
599 radeon_crtc->lut_r[i] = i << 2;
600 radeon_crtc->lut_g[i] = i << 2;
601 radeon_crtc->lut_b[i] = i << 2;
602 }
603
604 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
605 radeon_atombios_init_crtc(dev, radeon_crtc);
606 else
607 radeon_legacy_init_crtc(dev, radeon_crtc);
608 }
609
610 static const char *encoder_names[38] = {
611 "NONE",
612 "INTERNAL_LVDS",
613 "INTERNAL_TMDS1",
614 "INTERNAL_TMDS2",
615 "INTERNAL_DAC1",
616 "INTERNAL_DAC2",
617 "INTERNAL_SDVOA",
618 "INTERNAL_SDVOB",
619 "SI170B",
620 "CH7303",
621 "CH7301",
622 "INTERNAL_DVO1",
623 "EXTERNAL_SDVOA",
624 "EXTERNAL_SDVOB",
625 "TITFP513",
626 "INTERNAL_LVTM1",
627 "VT1623",
628 "HDMI_SI1930",
629 "HDMI_INTERNAL",
630 "INTERNAL_KLDSCP_TMDS1",
631 "INTERNAL_KLDSCP_DVO1",
632 "INTERNAL_KLDSCP_DAC1",
633 "INTERNAL_KLDSCP_DAC2",
634 "SI178",
635 "MVPU_FPGA",
636 "INTERNAL_DDI",
637 "VT1625",
638 "HDMI_SI1932",
639 "DP_AN9801",
640 "DP_DP501",
641 "INTERNAL_UNIPHY",
642 "INTERNAL_KLDSCP_LVTMA",
643 "INTERNAL_UNIPHY1",
644 "INTERNAL_UNIPHY2",
645 "NUTMEG",
646 "TRAVIS",
647 "INTERNAL_VCE",
648 "INTERNAL_UNIPHY3",
649 };
650
651 static const char *hpd_names[6] = {
652 "HPD1",
653 "HPD2",
654 "HPD3",
655 "HPD4",
656 "HPD5",
657 "HPD6",
658 };
659
660 static void radeon_print_display_setup(struct drm_device *dev)
661 {
662 struct drm_connector *connector;
663 struct radeon_connector *radeon_connector;
664 struct drm_encoder *encoder;
665 struct radeon_encoder *radeon_encoder;
666 uint32_t devices;
667 int i = 0;
668
669 DRM_INFO("Radeon Display Connectors\n");
670 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
671 radeon_connector = to_radeon_connector(connector);
672 DRM_INFO("Connector %d:\n", i);
673 DRM_INFO(" %s\n", drm_get_connector_name(connector));
674 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
675 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
676 if (radeon_connector->ddc_bus) {
677 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
678 radeon_connector->ddc_bus->rec.mask_clk_reg,
679 radeon_connector->ddc_bus->rec.mask_data_reg,
680 radeon_connector->ddc_bus->rec.a_clk_reg,
681 radeon_connector->ddc_bus->rec.a_data_reg,
682 radeon_connector->ddc_bus->rec.en_clk_reg,
683 radeon_connector->ddc_bus->rec.en_data_reg,
684 radeon_connector->ddc_bus->rec.y_clk_reg,
685 radeon_connector->ddc_bus->rec.y_data_reg);
686 if (radeon_connector->router.ddc_valid)
687 DRM_INFO(" DDC Router 0x%x/0x%x\n",
688 radeon_connector->router.ddc_mux_control_pin,
689 radeon_connector->router.ddc_mux_state);
690 if (radeon_connector->router.cd_valid)
691 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
692 radeon_connector->router.cd_mux_control_pin,
693 radeon_connector->router.cd_mux_state);
694 } else {
695 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
696 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
697 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
698 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
699 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
700 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
701 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
702 }
703 DRM_INFO(" Encoders:\n");
704 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
705 radeon_encoder = to_radeon_encoder(encoder);
706 devices = radeon_encoder->devices & radeon_connector->devices;
707 if (devices) {
708 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
709 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
710 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
711 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
712 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
713 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
714 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
715 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
716 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
717 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
718 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
719 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
720 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
721 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
722 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
723 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
724 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
725 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
726 if (devices & ATOM_DEVICE_TV1_SUPPORT)
727 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
728 if (devices & ATOM_DEVICE_CV_SUPPORT)
729 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
730 }
731 }
732 i++;
733 }
734 }
735
736 static bool radeon_setup_enc_conn(struct drm_device *dev)
737 {
738 struct radeon_device *rdev = dev->dev_private;
739 bool ret = false;
740
741 if (rdev->bios) {
742 if (rdev->is_atom_bios) {
743 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
744 if (ret == false)
745 ret = radeon_get_atom_connector_info_from_object_table(dev);
746 } else {
747 ret = radeon_get_legacy_connector_info_from_bios(dev);
748 if (ret == false)
749 ret = radeon_get_legacy_connector_info_from_table(dev);
750 }
751 } else {
752 if (!ASIC_IS_AVIVO(rdev))
753 ret = radeon_get_legacy_connector_info_from_table(dev);
754 }
755 if (ret) {
756 radeon_setup_encoder_clones(dev);
757 radeon_print_display_setup(dev);
758 }
759
760 return ret;
761 }
762
763 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
764 {
765 struct drm_device *dev = radeon_connector->base.dev;
766 struct radeon_device *rdev = dev->dev_private;
767 int ret = 0;
768
769 /* on hw with routers, select right port */
770 if (radeon_connector->router.ddc_valid)
771 radeon_router_select_ddc_port(radeon_connector);
772
773 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
774 ENCODER_OBJECT_ID_NONE) {
775 if (radeon_connector->ddc_bus->has_aux)
776 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
777 &radeon_connector->ddc_bus->aux.ddc);
778 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
779 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
780 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
781
782 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
783 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
784 radeon_connector->ddc_bus->has_aux)
785 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
786 &radeon_connector->ddc_bus->aux.ddc);
787 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
788 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
789 &radeon_connector->ddc_bus->adapter);
790 } else {
791 if (radeon_connector->ddc_bus && !radeon_connector->edid)
792 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
793 &radeon_connector->ddc_bus->adapter);
794 }
795
796 if (!radeon_connector->edid) {
797 if (rdev->is_atom_bios) {
798 /* some laptops provide a hardcoded edid in rom for LCDs */
799 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
800 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
801 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
802 } else
803 /* some servers provide a hardcoded edid in rom for KVMs */
804 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
805 }
806 if (radeon_connector->edid) {
807 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
808 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
809 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
810 return ret;
811 }
812 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
813 return 0;
814 }
815
816 /* avivo */
817
818 /**
819 * avivo_reduce_ratio - fractional number reduction
820 *
821 * @nom: nominator
822 * @den: denominator
823 * @nom_min: minimum value for nominator
824 * @den_min: minimum value for denominator
825 *
826 * Find the greatest common divisor and apply it on both nominator and
827 * denominator, but make nominator and denominator are at least as large
828 * as their minimum values.
829 */
830 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
831 unsigned nom_min, unsigned den_min)
832 {
833 unsigned tmp;
834
835 /* reduce the numbers to a simpler ratio */
836 tmp = gcd(*nom, *den);
837 *nom /= tmp;
838 *den /= tmp;
839
840 /* make sure nominator is large enough */
841 if (*nom < nom_min) {
842 tmp = (nom_min + *nom - 1) / *nom;
843 *nom *= tmp;
844 *den *= tmp;
845 }
846
847 /* make sure the denominator is large enough */
848 if (*den < den_min) {
849 tmp = (den_min + *den - 1) / *den;
850 *nom *= tmp;
851 *den *= tmp;
852 }
853 }
854
855 /**
856 * avivo_get_fb_ref_div - feedback and ref divider calculation
857 *
858 * @nom: nominator
859 * @den: denominator
860 * @post_div: post divider
861 * @fb_div_max: feedback divider maximum
862 * @ref_div_max: reference divider maximum
863 * @fb_div: resulting feedback divider
864 * @ref_div: resulting reference divider
865 *
866 * Calculate feedback and reference divider for a given post divider. Makes
867 * sure we stay within the limits.
868 */
869 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
870 unsigned fb_div_max, unsigned ref_div_max,
871 unsigned *fb_div, unsigned *ref_div)
872 {
873 /* limit reference * post divider to a maximum */
874 ref_div_max = min(210 / post_div, ref_div_max);
875
876 /* get matching reference and feedback divider */
877 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
878 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
879
880 /* limit fb divider to its maximum */
881 if (*fb_div > fb_div_max) {
882 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
883 *fb_div = fb_div_max;
884 }
885 }
886
887 /**
888 * radeon_compute_pll_avivo - compute PLL paramaters
889 *
890 * @pll: information about the PLL
891 * @dot_clock_p: resulting pixel clock
892 * fb_div_p: resulting feedback divider
893 * frac_fb_div_p: fractional part of the feedback divider
894 * ref_div_p: resulting reference divider
895 * post_div_p: resulting reference divider
896 *
897 * Try to calculate the PLL parameters to generate the given frequency:
898 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
899 */
900 void radeon_compute_pll_avivo(struct radeon_pll *pll,
901 u32 freq,
902 u32 *dot_clock_p,
903 u32 *fb_div_p,
904 u32 *frac_fb_div_p,
905 u32 *ref_div_p,
906 u32 *post_div_p)
907 {
908 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
909 freq : freq / 10;
910
911 unsigned fb_div_min, fb_div_max, fb_div;
912 unsigned post_div_min, post_div_max, post_div;
913 unsigned ref_div_min, ref_div_max, ref_div;
914 unsigned post_div_best, diff_best;
915 unsigned nom, den;
916
917 /* determine allowed feedback divider range */
918 fb_div_min = pll->min_feedback_div;
919 fb_div_max = pll->max_feedback_div;
920
921 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
922 fb_div_min *= 10;
923 fb_div_max *= 10;
924 }
925
926 /* determine allowed ref divider range */
927 if (pll->flags & RADEON_PLL_USE_REF_DIV)
928 ref_div_min = pll->reference_div;
929 else
930 ref_div_min = pll->min_ref_div;
931
932 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
933 pll->flags & RADEON_PLL_USE_REF_DIV)
934 ref_div_max = pll->reference_div;
935 else
936 ref_div_max = pll->max_ref_div;
937
938 /* determine allowed post divider range */
939 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
940 post_div_min = pll->post_div;
941 post_div_max = pll->post_div;
942 } else {
943 unsigned vco_min, vco_max;
944
945 if (pll->flags & RADEON_PLL_IS_LCD) {
946 vco_min = pll->lcd_pll_out_min;
947 vco_max = pll->lcd_pll_out_max;
948 } else {
949 vco_min = pll->pll_out_min;
950 vco_max = pll->pll_out_max;
951 }
952
953 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
954 vco_min *= 10;
955 vco_max *= 10;
956 }
957
958 post_div_min = vco_min / target_clock;
959 if ((target_clock * post_div_min) < vco_min)
960 ++post_div_min;
961 if (post_div_min < pll->min_post_div)
962 post_div_min = pll->min_post_div;
963
964 post_div_max = vco_max / target_clock;
965 if ((target_clock * post_div_max) > vco_max)
966 --post_div_max;
967 if (post_div_max > pll->max_post_div)
968 post_div_max = pll->max_post_div;
969 }
970
971 /* represent the searched ratio as fractional number */
972 nom = target_clock;
973 den = pll->reference_freq;
974
975 /* reduce the numbers to a simpler ratio */
976 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
977
978 /* now search for a post divider */
979 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
980 post_div_best = post_div_min;
981 else
982 post_div_best = post_div_max;
983 diff_best = ~0;
984
985 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
986 unsigned diff;
987 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
988 ref_div_max, &fb_div, &ref_div);
989 diff = abs(target_clock - (pll->reference_freq * fb_div) /
990 (ref_div * post_div));
991
992 if (diff < diff_best || (diff == diff_best &&
993 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
994
995 post_div_best = post_div;
996 diff_best = diff;
997 }
998 }
999 post_div = post_div_best;
1000
1001 /* get the feedback and reference divider for the optimal value */
1002 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1003 &fb_div, &ref_div);
1004
1005 /* reduce the numbers to a simpler ratio once more */
1006 /* this also makes sure that the reference divider is large enough */
1007 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1008
1009 /* and finally save the result */
1010 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1011 *fb_div_p = fb_div / 10;
1012 *frac_fb_div_p = fb_div % 10;
1013 } else {
1014 *fb_div_p = fb_div;
1015 *frac_fb_div_p = 0;
1016 }
1017
1018 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1019 (pll->reference_freq * *frac_fb_div_p)) /
1020 (ref_div * post_div * 10);
1021 *ref_div_p = ref_div;
1022 *post_div_p = post_div;
1023
1024 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1025 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1026 ref_div, post_div);
1027 }
1028
1029 /* pre-avivo */
1030 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1031 {
1032 uint64_t mod;
1033
1034 n += d / 2;
1035
1036 mod = do_div(n, d);
1037 return n;
1038 }
1039
1040 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1041 uint64_t freq,
1042 uint32_t *dot_clock_p,
1043 uint32_t *fb_div_p,
1044 uint32_t *frac_fb_div_p,
1045 uint32_t *ref_div_p,
1046 uint32_t *post_div_p)
1047 {
1048 uint32_t min_ref_div = pll->min_ref_div;
1049 uint32_t max_ref_div = pll->max_ref_div;
1050 uint32_t min_post_div = pll->min_post_div;
1051 uint32_t max_post_div = pll->max_post_div;
1052 uint32_t min_fractional_feed_div = 0;
1053 uint32_t max_fractional_feed_div = 0;
1054 uint32_t best_vco = pll->best_vco;
1055 uint32_t best_post_div = 1;
1056 uint32_t best_ref_div = 1;
1057 uint32_t best_feedback_div = 1;
1058 uint32_t best_frac_feedback_div = 0;
1059 uint32_t best_freq = -1;
1060 uint32_t best_error = 0xffffffff;
1061 uint32_t best_vco_diff = 1;
1062 uint32_t post_div;
1063 u32 pll_out_min, pll_out_max;
1064
1065 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1066 freq = freq * 1000;
1067
1068 if (pll->flags & RADEON_PLL_IS_LCD) {
1069 pll_out_min = pll->lcd_pll_out_min;
1070 pll_out_max = pll->lcd_pll_out_max;
1071 } else {
1072 pll_out_min = pll->pll_out_min;
1073 pll_out_max = pll->pll_out_max;
1074 }
1075
1076 if (pll_out_min > 64800)
1077 pll_out_min = 64800;
1078
1079 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1080 min_ref_div = max_ref_div = pll->reference_div;
1081 else {
1082 while (min_ref_div < max_ref_div-1) {
1083 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1084 uint32_t pll_in = pll->reference_freq / mid;
1085 if (pll_in < pll->pll_in_min)
1086 max_ref_div = mid;
1087 else if (pll_in > pll->pll_in_max)
1088 min_ref_div = mid;
1089 else
1090 break;
1091 }
1092 }
1093
1094 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1095 min_post_div = max_post_div = pll->post_div;
1096
1097 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1098 min_fractional_feed_div = pll->min_frac_feedback_div;
1099 max_fractional_feed_div = pll->max_frac_feedback_div;
1100 }
1101
1102 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1103 uint32_t ref_div;
1104
1105 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1106 continue;
1107
1108 /* legacy radeons only have a few post_divs */
1109 if (pll->flags & RADEON_PLL_LEGACY) {
1110 if ((post_div == 5) ||
1111 (post_div == 7) ||
1112 (post_div == 9) ||
1113 (post_div == 10) ||
1114 (post_div == 11) ||
1115 (post_div == 13) ||
1116 (post_div == 14) ||
1117 (post_div == 15))
1118 continue;
1119 }
1120
1121 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1122 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1123 uint32_t pll_in = pll->reference_freq / ref_div;
1124 uint32_t min_feed_div = pll->min_feedback_div;
1125 uint32_t max_feed_div = pll->max_feedback_div + 1;
1126
1127 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1128 continue;
1129
1130 while (min_feed_div < max_feed_div) {
1131 uint32_t vco;
1132 uint32_t min_frac_feed_div = min_fractional_feed_div;
1133 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1134 uint32_t frac_feedback_div;
1135 uint64_t tmp;
1136
1137 feedback_div = (min_feed_div + max_feed_div) / 2;
1138
1139 tmp = (uint64_t)pll->reference_freq * feedback_div;
1140 vco = radeon_div(tmp, ref_div);
1141
1142 if (vco < pll_out_min) {
1143 min_feed_div = feedback_div + 1;
1144 continue;
1145 } else if (vco > pll_out_max) {
1146 max_feed_div = feedback_div;
1147 continue;
1148 }
1149
1150 while (min_frac_feed_div < max_frac_feed_div) {
1151 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1152 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1153 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1154 current_freq = radeon_div(tmp, ref_div * post_div);
1155
1156 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1157 if (freq < current_freq)
1158 error = 0xffffffff;
1159 else
1160 error = freq - current_freq;
1161 } else
1162 error = abs(current_freq - freq);
1163 vco_diff = abs(vco - best_vco);
1164
1165 if ((best_vco == 0 && error < best_error) ||
1166 (best_vco != 0 &&
1167 ((best_error > 100 && error < best_error - 100) ||
1168 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1169 best_post_div = post_div;
1170 best_ref_div = ref_div;
1171 best_feedback_div = feedback_div;
1172 best_frac_feedback_div = frac_feedback_div;
1173 best_freq = current_freq;
1174 best_error = error;
1175 best_vco_diff = vco_diff;
1176 } else if (current_freq == freq) {
1177 if (best_freq == -1) {
1178 best_post_div = post_div;
1179 best_ref_div = ref_div;
1180 best_feedback_div = feedback_div;
1181 best_frac_feedback_div = frac_feedback_div;
1182 best_freq = current_freq;
1183 best_error = error;
1184 best_vco_diff = vco_diff;
1185 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1186 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1187 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1188 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1189 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1190 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1191 best_post_div = post_div;
1192 best_ref_div = ref_div;
1193 best_feedback_div = feedback_div;
1194 best_frac_feedback_div = frac_feedback_div;
1195 best_freq = current_freq;
1196 best_error = error;
1197 best_vco_diff = vco_diff;
1198 }
1199 }
1200 if (current_freq < freq)
1201 min_frac_feed_div = frac_feedback_div + 1;
1202 else
1203 max_frac_feed_div = frac_feedback_div;
1204 }
1205 if (current_freq < freq)
1206 min_feed_div = feedback_div + 1;
1207 else
1208 max_feed_div = feedback_div;
1209 }
1210 }
1211 }
1212
1213 *dot_clock_p = best_freq / 10000;
1214 *fb_div_p = best_feedback_div;
1215 *frac_fb_div_p = best_frac_feedback_div;
1216 *ref_div_p = best_ref_div;
1217 *post_div_p = best_post_div;
1218 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1219 (long long)freq,
1220 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1221 best_ref_div, best_post_div);
1222
1223 }
1224
1225 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1226 {
1227 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1228
1229 if (radeon_fb->obj) {
1230 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1231 }
1232 drm_framebuffer_cleanup(fb);
1233 kfree(radeon_fb);
1234 }
1235
1236 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1237 struct drm_file *file_priv,
1238 unsigned int *handle)
1239 {
1240 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1241
1242 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1243 }
1244
1245 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1246 .destroy = radeon_user_framebuffer_destroy,
1247 .create_handle = radeon_user_framebuffer_create_handle,
1248 };
1249
1250 int
1251 radeon_framebuffer_init(struct drm_device *dev,
1252 struct radeon_framebuffer *rfb,
1253 struct drm_mode_fb_cmd2 *mode_cmd,
1254 struct drm_gem_object *obj)
1255 {
1256 int ret;
1257 rfb->obj = obj;
1258 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1259 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1260 if (ret) {
1261 rfb->obj = NULL;
1262 return ret;
1263 }
1264 return 0;
1265 }
1266
1267 static struct drm_framebuffer *
1268 radeon_user_framebuffer_create(struct drm_device *dev,
1269 struct drm_file *file_priv,
1270 struct drm_mode_fb_cmd2 *mode_cmd)
1271 {
1272 struct drm_gem_object *obj;
1273 struct radeon_framebuffer *radeon_fb;
1274 int ret;
1275
1276 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1277 if (obj == NULL) {
1278 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1279 "can't create framebuffer\n", mode_cmd->handles[0]);
1280 return ERR_PTR(-ENOENT);
1281 }
1282
1283 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1284 if (radeon_fb == NULL) {
1285 drm_gem_object_unreference_unlocked(obj);
1286 return ERR_PTR(-ENOMEM);
1287 }
1288
1289 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1290 if (ret) {
1291 kfree(radeon_fb);
1292 drm_gem_object_unreference_unlocked(obj);
1293 return ERR_PTR(ret);
1294 }
1295
1296 return &radeon_fb->base;
1297 }
1298
1299 static void radeon_output_poll_changed(struct drm_device *dev)
1300 {
1301 struct radeon_device *rdev = dev->dev_private;
1302 radeon_fb_output_poll_changed(rdev);
1303 }
1304
1305 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1306 .fb_create = radeon_user_framebuffer_create,
1307 .output_poll_changed = radeon_output_poll_changed
1308 };
1309
1310 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1311 { { 0, "driver" },
1312 { 1, "bios" },
1313 };
1314
1315 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1316 { { TV_STD_NTSC, "ntsc" },
1317 { TV_STD_PAL, "pal" },
1318 { TV_STD_PAL_M, "pal-m" },
1319 { TV_STD_PAL_60, "pal-60" },
1320 { TV_STD_NTSC_J, "ntsc-j" },
1321 { TV_STD_SCART_PAL, "scart-pal" },
1322 { TV_STD_PAL_CN, "pal-cn" },
1323 { TV_STD_SECAM, "secam" },
1324 };
1325
1326 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1327 { { UNDERSCAN_OFF, "off" },
1328 { UNDERSCAN_ON, "on" },
1329 { UNDERSCAN_AUTO, "auto" },
1330 };
1331
1332 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1333 { { RADEON_AUDIO_DISABLE, "off" },
1334 { RADEON_AUDIO_ENABLE, "on" },
1335 { RADEON_AUDIO_AUTO, "auto" },
1336 };
1337
1338 /* XXX support different dither options? spatial, temporal, both, etc. */
1339 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1340 { { RADEON_FMT_DITHER_DISABLE, "off" },
1341 { RADEON_FMT_DITHER_ENABLE, "on" },
1342 };
1343
1344 static int radeon_modeset_create_props(struct radeon_device *rdev)
1345 {
1346 int sz;
1347
1348 if (rdev->is_atom_bios) {
1349 rdev->mode_info.coherent_mode_property =
1350 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1351 if (!rdev->mode_info.coherent_mode_property)
1352 return -ENOMEM;
1353 }
1354
1355 if (!ASIC_IS_AVIVO(rdev)) {
1356 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1357 rdev->mode_info.tmds_pll_property =
1358 drm_property_create_enum(rdev->ddev, 0,
1359 "tmds_pll",
1360 radeon_tmds_pll_enum_list, sz);
1361 }
1362
1363 rdev->mode_info.load_detect_property =
1364 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1365 if (!rdev->mode_info.load_detect_property)
1366 return -ENOMEM;
1367
1368 drm_mode_create_scaling_mode_property(rdev->ddev);
1369
1370 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1371 rdev->mode_info.tv_std_property =
1372 drm_property_create_enum(rdev->ddev, 0,
1373 "tv standard",
1374 radeon_tv_std_enum_list, sz);
1375
1376 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1377 rdev->mode_info.underscan_property =
1378 drm_property_create_enum(rdev->ddev, 0,
1379 "underscan",
1380 radeon_underscan_enum_list, sz);
1381
1382 rdev->mode_info.underscan_hborder_property =
1383 drm_property_create_range(rdev->ddev, 0,
1384 "underscan hborder", 0, 128);
1385 if (!rdev->mode_info.underscan_hborder_property)
1386 return -ENOMEM;
1387
1388 rdev->mode_info.underscan_vborder_property =
1389 drm_property_create_range(rdev->ddev, 0,
1390 "underscan vborder", 0, 128);
1391 if (!rdev->mode_info.underscan_vborder_property)
1392 return -ENOMEM;
1393
1394 sz = ARRAY_SIZE(radeon_audio_enum_list);
1395 rdev->mode_info.audio_property =
1396 drm_property_create_enum(rdev->ddev, 0,
1397 "audio",
1398 radeon_audio_enum_list, sz);
1399
1400 sz = ARRAY_SIZE(radeon_dither_enum_list);
1401 rdev->mode_info.dither_property =
1402 drm_property_create_enum(rdev->ddev, 0,
1403 "dither",
1404 radeon_dither_enum_list, sz);
1405
1406 return 0;
1407 }
1408
1409 void radeon_update_display_priority(struct radeon_device *rdev)
1410 {
1411 /* adjustment options for the display watermarks */
1412 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1413 /* set display priority to high for r3xx, rv515 chips
1414 * this avoids flickering due to underflow to the
1415 * display controllers during heavy acceleration.
1416 * Don't force high on rs4xx igp chips as it seems to
1417 * affect the sound card. See kernel bug 15982.
1418 */
1419 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1420 !(rdev->flags & RADEON_IS_IGP))
1421 rdev->disp_priority = 2;
1422 else
1423 rdev->disp_priority = 0;
1424 } else
1425 rdev->disp_priority = radeon_disp_priority;
1426
1427 }
1428
1429 /*
1430 * Allocate hdmi structs and determine register offsets
1431 */
1432 static void radeon_afmt_init(struct radeon_device *rdev)
1433 {
1434 int i;
1435
1436 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1437 rdev->mode_info.afmt[i] = NULL;
1438
1439 if (ASIC_IS_NODCE(rdev)) {
1440 /* nothing to do */
1441 } else if (ASIC_IS_DCE4(rdev)) {
1442 static uint32_t eg_offsets[] = {
1443 EVERGREEN_CRTC0_REGISTER_OFFSET,
1444 EVERGREEN_CRTC1_REGISTER_OFFSET,
1445 EVERGREEN_CRTC2_REGISTER_OFFSET,
1446 EVERGREEN_CRTC3_REGISTER_OFFSET,
1447 EVERGREEN_CRTC4_REGISTER_OFFSET,
1448 EVERGREEN_CRTC5_REGISTER_OFFSET,
1449 0x13830 - 0x7030,
1450 };
1451 int num_afmt;
1452
1453 /* DCE8 has 7 audio blocks tied to DIG encoders */
1454 /* DCE6 has 6 audio blocks tied to DIG encoders */
1455 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1456 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1457 if (ASIC_IS_DCE8(rdev))
1458 num_afmt = 7;
1459 else if (ASIC_IS_DCE6(rdev))
1460 num_afmt = 6;
1461 else if (ASIC_IS_DCE5(rdev))
1462 num_afmt = 6;
1463 else if (ASIC_IS_DCE41(rdev))
1464 num_afmt = 2;
1465 else /* DCE4 */
1466 num_afmt = 6;
1467
1468 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1469 for (i = 0; i < num_afmt; i++) {
1470 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1471 if (rdev->mode_info.afmt[i]) {
1472 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1473 rdev->mode_info.afmt[i]->id = i;
1474 }
1475 }
1476 } else if (ASIC_IS_DCE3(rdev)) {
1477 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1478 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1479 if (rdev->mode_info.afmt[0]) {
1480 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1481 rdev->mode_info.afmt[0]->id = 0;
1482 }
1483 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1484 if (rdev->mode_info.afmt[1]) {
1485 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1486 rdev->mode_info.afmt[1]->id = 1;
1487 }
1488 } else if (ASIC_IS_DCE2(rdev)) {
1489 /* DCE2 has at least 1 routable audio block */
1490 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1491 if (rdev->mode_info.afmt[0]) {
1492 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1493 rdev->mode_info.afmt[0]->id = 0;
1494 }
1495 /* r6xx has 2 routable audio blocks */
1496 if (rdev->family >= CHIP_R600) {
1497 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1498 if (rdev->mode_info.afmt[1]) {
1499 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1500 rdev->mode_info.afmt[1]->id = 1;
1501 }
1502 }
1503 }
1504 }
1505
1506 static void radeon_afmt_fini(struct radeon_device *rdev)
1507 {
1508 int i;
1509
1510 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1511 kfree(rdev->mode_info.afmt[i]);
1512 rdev->mode_info.afmt[i] = NULL;
1513 }
1514 }
1515
1516 int radeon_modeset_init(struct radeon_device *rdev)
1517 {
1518 int i;
1519 int ret;
1520
1521 drm_mode_config_init(rdev->ddev);
1522 rdev->mode_info.mode_config_initialized = true;
1523
1524 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1525
1526 if (ASIC_IS_DCE5(rdev)) {
1527 rdev->ddev->mode_config.max_width = 16384;
1528 rdev->ddev->mode_config.max_height = 16384;
1529 } else if (ASIC_IS_AVIVO(rdev)) {
1530 rdev->ddev->mode_config.max_width = 8192;
1531 rdev->ddev->mode_config.max_height = 8192;
1532 } else {
1533 rdev->ddev->mode_config.max_width = 4096;
1534 rdev->ddev->mode_config.max_height = 4096;
1535 }
1536
1537 rdev->ddev->mode_config.preferred_depth = 24;
1538 rdev->ddev->mode_config.prefer_shadow = 1;
1539
1540 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1541
1542 ret = radeon_modeset_create_props(rdev);
1543 if (ret) {
1544 return ret;
1545 }
1546
1547 /* init i2c buses */
1548 radeon_i2c_init(rdev);
1549
1550 /* check combios for a valid hardcoded EDID - Sun servers */
1551 if (!rdev->is_atom_bios) {
1552 /* check for hardcoded EDID in BIOS */
1553 radeon_combios_check_hardcoded_edid(rdev);
1554 }
1555
1556 /* allocate crtcs */
1557 for (i = 0; i < rdev->num_crtc; i++) {
1558 radeon_crtc_init(rdev->ddev, i);
1559 }
1560
1561 /* okay we should have all the bios connectors */
1562 ret = radeon_setup_enc_conn(rdev->ddev);
1563 if (!ret) {
1564 return ret;
1565 }
1566
1567 /* init dig PHYs, disp eng pll */
1568 if (rdev->is_atom_bios) {
1569 radeon_atom_encoder_init(rdev);
1570 radeon_atom_disp_eng_pll_init(rdev);
1571 }
1572
1573 /* initialize hpd */
1574 radeon_hpd_init(rdev);
1575
1576 /* setup afmt */
1577 radeon_afmt_init(rdev);
1578
1579 radeon_fbdev_init(rdev);
1580 drm_kms_helper_poll_init(rdev->ddev);
1581
1582 if (rdev->pm.dpm_enabled) {
1583 /* do dpm late init */
1584 ret = radeon_pm_late_init(rdev);
1585 if (ret) {
1586 rdev->pm.dpm_enabled = false;
1587 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1588 }
1589 /* set the dpm state for PX since there won't be
1590 * a modeset to call this.
1591 */
1592 radeon_pm_compute_clocks(rdev);
1593 }
1594
1595 return 0;
1596 }
1597
1598 void radeon_modeset_fini(struct radeon_device *rdev)
1599 {
1600 radeon_fbdev_fini(rdev);
1601 kfree(rdev->mode_info.bios_hardcoded_edid);
1602
1603 if (rdev->mode_info.mode_config_initialized) {
1604 radeon_afmt_fini(rdev);
1605 drm_kms_helper_poll_fini(rdev->ddev);
1606 radeon_hpd_fini(rdev);
1607 drm_mode_config_cleanup(rdev->ddev);
1608 rdev->mode_info.mode_config_initialized = false;
1609 }
1610 /* free i2c buses */
1611 radeon_i2c_fini(rdev);
1612 }
1613
1614 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1615 {
1616 /* try and guess if this is a tv or a monitor */
1617 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1618 (mode->vdisplay == 576) || /* 576p */
1619 (mode->vdisplay == 720) || /* 720p */
1620 (mode->vdisplay == 1080)) /* 1080p */
1621 return true;
1622 else
1623 return false;
1624 }
1625
1626 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1627 const struct drm_display_mode *mode,
1628 struct drm_display_mode *adjusted_mode)
1629 {
1630 struct drm_device *dev = crtc->dev;
1631 struct radeon_device *rdev = dev->dev_private;
1632 struct drm_encoder *encoder;
1633 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1634 struct radeon_encoder *radeon_encoder;
1635 struct drm_connector *connector;
1636 struct radeon_connector *radeon_connector;
1637 bool first = true;
1638 u32 src_v = 1, dst_v = 1;
1639 u32 src_h = 1, dst_h = 1;
1640
1641 radeon_crtc->h_border = 0;
1642 radeon_crtc->v_border = 0;
1643
1644 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1645 if (encoder->crtc != crtc)
1646 continue;
1647 radeon_encoder = to_radeon_encoder(encoder);
1648 connector = radeon_get_connector_for_encoder(encoder);
1649 radeon_connector = to_radeon_connector(connector);
1650
1651 if (first) {
1652 /* set scaling */
1653 if (radeon_encoder->rmx_type == RMX_OFF)
1654 radeon_crtc->rmx_type = RMX_OFF;
1655 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1656 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1657 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1658 else
1659 radeon_crtc->rmx_type = RMX_OFF;
1660 /* copy native mode */
1661 memcpy(&radeon_crtc->native_mode,
1662 &radeon_encoder->native_mode,
1663 sizeof(struct drm_display_mode));
1664 src_v = crtc->mode.vdisplay;
1665 dst_v = radeon_crtc->native_mode.vdisplay;
1666 src_h = crtc->mode.hdisplay;
1667 dst_h = radeon_crtc->native_mode.hdisplay;
1668
1669 /* fix up for overscan on hdmi */
1670 if (ASIC_IS_AVIVO(rdev) &&
1671 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1672 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1673 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1674 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1675 is_hdtv_mode(mode)))) {
1676 if (radeon_encoder->underscan_hborder != 0)
1677 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1678 else
1679 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1680 if (radeon_encoder->underscan_vborder != 0)
1681 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1682 else
1683 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1684 radeon_crtc->rmx_type = RMX_FULL;
1685 src_v = crtc->mode.vdisplay;
1686 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1687 src_h = crtc->mode.hdisplay;
1688 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1689 }
1690 first = false;
1691 } else {
1692 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1693 /* WARNING: Right now this can't happen but
1694 * in the future we need to check that scaling
1695 * are consistent across different encoder
1696 * (ie all encoder can work with the same
1697 * scaling).
1698 */
1699 DRM_ERROR("Scaling not consistent across encoder.\n");
1700 return false;
1701 }
1702 }
1703 }
1704 if (radeon_crtc->rmx_type != RMX_OFF) {
1705 fixed20_12 a, b;
1706 a.full = dfixed_const(src_v);
1707 b.full = dfixed_const(dst_v);
1708 radeon_crtc->vsc.full = dfixed_div(a, b);
1709 a.full = dfixed_const(src_h);
1710 b.full = dfixed_const(dst_h);
1711 radeon_crtc->hsc.full = dfixed_div(a, b);
1712 } else {
1713 radeon_crtc->vsc.full = dfixed_const(1);
1714 radeon_crtc->hsc.full = dfixed_const(1);
1715 }
1716 return true;
1717 }
1718
1719 /*
1720 * Retrieve current video scanout position of crtc on a given gpu, and
1721 * an optional accurate timestamp of when query happened.
1722 *
1723 * \param dev Device to query.
1724 * \param crtc Crtc to query.
1725 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1726 * \param *vpos Location where vertical scanout position should be stored.
1727 * \param *hpos Location where horizontal scanout position should go.
1728 * \param *stime Target location for timestamp taken immediately before
1729 * scanout position query. Can be NULL to skip timestamp.
1730 * \param *etime Target location for timestamp taken immediately after
1731 * scanout position query. Can be NULL to skip timestamp.
1732 *
1733 * Returns vpos as a positive number while in active scanout area.
1734 * Returns vpos as a negative number inside vblank, counting the number
1735 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1736 * until start of active scanout / end of vblank."
1737 *
1738 * \return Flags, or'ed together as follows:
1739 *
1740 * DRM_SCANOUTPOS_VALID = Query successful.
1741 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1742 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1743 * this flag means that returned position may be offset by a constant but
1744 * unknown small number of scanlines wrt. real scanout position.
1745 *
1746 */
1747 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1748 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1749 {
1750 u32 stat_crtc = 0, vbl = 0, position = 0;
1751 int vbl_start, vbl_end, vtotal, ret = 0;
1752 bool in_vbl = true;
1753
1754 struct radeon_device *rdev = dev->dev_private;
1755
1756 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1757
1758 /* Get optional system timestamp before query. */
1759 if (stime)
1760 *stime = ktime_get();
1761
1762 if (ASIC_IS_DCE4(rdev)) {
1763 if (crtc == 0) {
1764 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1765 EVERGREEN_CRTC0_REGISTER_OFFSET);
1766 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1767 EVERGREEN_CRTC0_REGISTER_OFFSET);
1768 ret |= DRM_SCANOUTPOS_VALID;
1769 }
1770 if (crtc == 1) {
1771 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1772 EVERGREEN_CRTC1_REGISTER_OFFSET);
1773 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1774 EVERGREEN_CRTC1_REGISTER_OFFSET);
1775 ret |= DRM_SCANOUTPOS_VALID;
1776 }
1777 if (crtc == 2) {
1778 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1779 EVERGREEN_CRTC2_REGISTER_OFFSET);
1780 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1781 EVERGREEN_CRTC2_REGISTER_OFFSET);
1782 ret |= DRM_SCANOUTPOS_VALID;
1783 }
1784 if (crtc == 3) {
1785 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1786 EVERGREEN_CRTC3_REGISTER_OFFSET);
1787 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1788 EVERGREEN_CRTC3_REGISTER_OFFSET);
1789 ret |= DRM_SCANOUTPOS_VALID;
1790 }
1791 if (crtc == 4) {
1792 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1793 EVERGREEN_CRTC4_REGISTER_OFFSET);
1794 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1795 EVERGREEN_CRTC4_REGISTER_OFFSET);
1796 ret |= DRM_SCANOUTPOS_VALID;
1797 }
1798 if (crtc == 5) {
1799 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1800 EVERGREEN_CRTC5_REGISTER_OFFSET);
1801 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1802 EVERGREEN_CRTC5_REGISTER_OFFSET);
1803 ret |= DRM_SCANOUTPOS_VALID;
1804 }
1805 } else if (ASIC_IS_AVIVO(rdev)) {
1806 if (crtc == 0) {
1807 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1808 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1809 ret |= DRM_SCANOUTPOS_VALID;
1810 }
1811 if (crtc == 1) {
1812 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1813 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1814 ret |= DRM_SCANOUTPOS_VALID;
1815 }
1816 } else {
1817 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1818 if (crtc == 0) {
1819 /* Assume vbl_end == 0, get vbl_start from
1820 * upper 16 bits.
1821 */
1822 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1823 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1824 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1825 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1826 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1827 if (!(stat_crtc & 1))
1828 in_vbl = false;
1829
1830 ret |= DRM_SCANOUTPOS_VALID;
1831 }
1832 if (crtc == 1) {
1833 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1834 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1835 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1836 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1837 if (!(stat_crtc & 1))
1838 in_vbl = false;
1839
1840 ret |= DRM_SCANOUTPOS_VALID;
1841 }
1842 }
1843
1844 /* Get optional system timestamp after query. */
1845 if (etime)
1846 *etime = ktime_get();
1847
1848 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1849
1850 /* Decode into vertical and horizontal scanout position. */
1851 *vpos = position & 0x1fff;
1852 *hpos = (position >> 16) & 0x1fff;
1853
1854 /* Valid vblank area boundaries from gpu retrieved? */
1855 if (vbl > 0) {
1856 /* Yes: Decode. */
1857 ret |= DRM_SCANOUTPOS_ACCURATE;
1858 vbl_start = vbl & 0x1fff;
1859 vbl_end = (vbl >> 16) & 0x1fff;
1860 }
1861 else {
1862 /* No: Fake something reasonable which gives at least ok results. */
1863 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1864 vbl_end = 0;
1865 }
1866
1867 /* Test scanout position against vblank region. */
1868 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1869 in_vbl = false;
1870
1871 /* Check if inside vblank area and apply corrective offsets:
1872 * vpos will then be >=0 in video scanout area, but negative
1873 * within vblank area, counting down the number of lines until
1874 * start of scanout.
1875 */
1876
1877 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1878 if (in_vbl && (*vpos >= vbl_start)) {
1879 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1880 *vpos = *vpos - vtotal;
1881 }
1882
1883 /* Correct for shifted end of vbl at vbl_end. */
1884 *vpos = *vpos - vbl_end;
1885
1886 /* In vblank? */
1887 if (in_vbl)
1888 ret |= DRM_SCANOUTPOS_INVBL;
1889
1890 /* Is vpos outside nominal vblank area, but less than
1891 * 1/100 of a frame height away from start of vblank?
1892 * If so, assume this isn't a massively delayed vblank
1893 * interrupt, but a vblank interrupt that fired a few
1894 * microseconds before true start of vblank. Compensate
1895 * by adding a full frame duration to the final timestamp.
1896 * Happens, e.g., on ATI R500, R600.
1897 *
1898 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1899 */
1900 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1901 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1902 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1903
1904 if (vbl_start - *vpos < vtotal / 100) {
1905 *vpos -= vtotal;
1906
1907 /* Signal this correction as "applied". */
1908 ret |= 0x8;
1909 }
1910 }
1911
1912 return ret;
1913 }
Linux kernel - Deliverables
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