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drm/ttm: flip the switch, and convert to dma_fence
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_display.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include <linux/pm_runtime.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_edid.h>
36
37 #include <linux/gcd.h>
38
39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
40 {
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
44 int i;
45
46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
48
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
52
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
56
57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
58 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
60
61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
62 for (i = 0; i < 256; i++) {
63 WREG32(AVIVO_DC_LUT_30_COLOR,
64 (radeon_crtc->lut_r[i] << 20) |
65 (radeon_crtc->lut_g[i] << 10) |
66 (radeon_crtc->lut_b[i] << 0));
67 }
68
69 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
70 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
71 }
72
73 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
74 {
75 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
76 struct drm_device *dev = crtc->dev;
77 struct radeon_device *rdev = dev->dev_private;
78 int i;
79
80 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
81 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
82
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
86
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
90
91 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
92 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
93
94 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
95 for (i = 0; i < 256; i++) {
96 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
97 (radeon_crtc->lut_r[i] << 20) |
98 (radeon_crtc->lut_g[i] << 10) |
99 (radeon_crtc->lut_b[i] << 0));
100 }
101 }
102
103 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
104 {
105 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
106 struct drm_device *dev = crtc->dev;
107 struct radeon_device *rdev = dev->dev_private;
108 int i;
109
110 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
111
112 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
113 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
114 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
115 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
116 NI_GRPH_PRESCALE_BYPASS);
117 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
118 NI_OVL_PRESCALE_BYPASS);
119 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
120 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
121 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
122
123 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
124
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
128
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
132
133 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
134 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
135
136 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
137 for (i = 0; i < 256; i++) {
138 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
139 (radeon_crtc->lut_r[i] << 20) |
140 (radeon_crtc->lut_g[i] << 10) |
141 (radeon_crtc->lut_b[i] << 0));
142 }
143
144 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
145 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
148 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
149 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
150 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
151 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
152 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
153 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
154 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
155 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
156 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
157 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
158 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
159 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
160 if (ASIC_IS_DCE8(rdev)) {
161 /* XXX this only needs to be programmed once per crtc at startup,
162 * not sure where the best place for it is
163 */
164 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
165 CIK_CURSOR_ALPHA_BLND_ENA);
166 }
167 }
168
169 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
170 {
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int i;
175 uint32_t dac2_cntl;
176
177 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
178 if (radeon_crtc->crtc_id == 0)
179 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
180 else
181 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
182 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
183
184 WREG8(RADEON_PALETTE_INDEX, 0);
185 for (i = 0; i < 256; i++) {
186 WREG32(RADEON_PALETTE_30_DATA,
187 (radeon_crtc->lut_r[i] << 20) |
188 (radeon_crtc->lut_g[i] << 10) |
189 (radeon_crtc->lut_b[i] << 0));
190 }
191 }
192
193 void radeon_crtc_load_lut(struct drm_crtc *crtc)
194 {
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
197
198 if (!crtc->enabled)
199 return;
200
201 if (ASIC_IS_DCE5(rdev))
202 dce5_crtc_load_lut(crtc);
203 else if (ASIC_IS_DCE4(rdev))
204 dce4_crtc_load_lut(crtc);
205 else if (ASIC_IS_AVIVO(rdev))
206 avivo_crtc_load_lut(crtc);
207 else
208 legacy_crtc_load_lut(crtc);
209 }
210
211 /** Sets the color ramps on behalf of fbcon */
212 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
213 u16 blue, int regno)
214 {
215 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
216
217 radeon_crtc->lut_r[regno] = red >> 6;
218 radeon_crtc->lut_g[regno] = green >> 6;
219 radeon_crtc->lut_b[regno] = blue >> 6;
220 }
221
222 /** Gets the color ramps on behalf of fbcon */
223 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
224 u16 *blue, int regno)
225 {
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227
228 *red = radeon_crtc->lut_r[regno] << 6;
229 *green = radeon_crtc->lut_g[regno] << 6;
230 *blue = radeon_crtc->lut_b[regno] << 6;
231 }
232
233 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
234 u16 *blue, uint32_t start, uint32_t size)
235 {
236 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
237 int end = (start + size > 256) ? 256 : start + size, i;
238
239 /* userspace palettes are always correct as is */
240 for (i = start; i < end; i++) {
241 radeon_crtc->lut_r[i] = red[i] >> 6;
242 radeon_crtc->lut_g[i] = green[i] >> 6;
243 radeon_crtc->lut_b[i] = blue[i] >> 6;
244 }
245 radeon_crtc_load_lut(crtc);
246 }
247
248 static void radeon_crtc_destroy(struct drm_crtc *crtc)
249 {
250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
251
252 drm_crtc_cleanup(crtc);
253 destroy_workqueue(radeon_crtc->flip_queue);
254 kfree(radeon_crtc);
255 }
256
257 /**
258 * radeon_unpin_work_func - unpin old buffer object
259 *
260 * @__work - kernel work item
261 *
262 * Unpin the old frame buffer object outside of the interrupt handler
263 */
264 static void radeon_unpin_work_func(struct work_struct *__work)
265 {
266 struct radeon_flip_work *work =
267 container_of(__work, struct radeon_flip_work, unpin_work);
268 int r;
269
270 /* unpin of the old buffer */
271 r = radeon_bo_reserve(work->old_rbo, false);
272 if (likely(r == 0)) {
273 r = radeon_bo_unpin(work->old_rbo);
274 if (unlikely(r != 0)) {
275 DRM_ERROR("failed to unpin buffer after flip\n");
276 }
277 radeon_bo_unreserve(work->old_rbo);
278 } else
279 DRM_ERROR("failed to reserve buffer after flip\n");
280
281 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
282 kfree(work);
283 }
284
285 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
286 {
287 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
288 unsigned long flags;
289 u32 update_pending;
290 int vpos, hpos;
291
292 /* can happen during initialization */
293 if (radeon_crtc == NULL)
294 return;
295
296 /* Skip the pageflip completion check below (based on polling) on
297 * asics which reliably support hw pageflip completion irqs. pflip
298 * irqs are a reliable and race-free method of handling pageflip
299 * completion detection. A use_pflipirq module parameter < 2 allows
300 * to override this in case of asics with faulty pflip irqs.
301 * A module parameter of 0 would only use this polling based path,
302 * a parameter of 1 would use pflip irq only as a backup to this
303 * path, as in Linux 3.16.
304 */
305 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
306 return;
307
308 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
309 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
310 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
311 "RADEON_FLIP_SUBMITTED(%d)\n",
312 radeon_crtc->flip_status,
313 RADEON_FLIP_SUBMITTED);
314 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
315 return;
316 }
317
318 update_pending = radeon_page_flip_pending(rdev, crtc_id);
319
320 /* Has the pageflip already completed in crtc, or is it certain
321 * to complete in this vblank?
322 */
323 if (update_pending &&
324 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
325 &vpos, &hpos, NULL, NULL)) &&
326 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
327 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
328 /* crtc didn't flip in this target vblank interval,
329 * but flip is pending in crtc. Based on the current
330 * scanout position we know that the current frame is
331 * (nearly) complete and the flip will (likely)
332 * complete before the start of the next frame.
333 */
334 update_pending = 0;
335 }
336 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
337 if (!update_pending)
338 radeon_crtc_handle_flip(rdev, crtc_id);
339 }
340
341 /**
342 * radeon_crtc_handle_flip - page flip completed
343 *
344 * @rdev: radeon device pointer
345 * @crtc_id: crtc number this event is for
346 *
347 * Called when we are sure that a page flip for this crtc is completed.
348 */
349 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
350 {
351 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
352 struct radeon_flip_work *work;
353 unsigned long flags;
354
355 /* this can happen at init */
356 if (radeon_crtc == NULL)
357 return;
358
359 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
360 work = radeon_crtc->flip_work;
361 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
362 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
363 "RADEON_FLIP_SUBMITTED(%d)\n",
364 radeon_crtc->flip_status,
365 RADEON_FLIP_SUBMITTED);
366 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
367 return;
368 }
369
370 /* Pageflip completed. Clean up. */
371 radeon_crtc->flip_status = RADEON_FLIP_NONE;
372 radeon_crtc->flip_work = NULL;
373
374 /* wakeup userspace */
375 if (work->event)
376 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
377
378 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
379
380 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
381 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
382 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
383 }
384
385 /**
386 * radeon_flip_work_func - page flip framebuffer
387 *
388 * @work - kernel work item
389 *
390 * Wait for the buffer object to become idle and do the actual page flip
391 */
392 static void radeon_flip_work_func(struct work_struct *__work)
393 {
394 struct radeon_flip_work *work =
395 container_of(__work, struct radeon_flip_work, flip_work);
396 struct radeon_device *rdev = work->rdev;
397 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
398
399 struct drm_crtc *crtc = &radeon_crtc->base;
400 unsigned long flags;
401 int r;
402
403 down_read(&rdev->exclusive_lock);
404 if (work->fence) {
405 r = radeon_fence_wait(work->fence, false);
406 if (r == -EDEADLK) {
407 up_read(&rdev->exclusive_lock);
408 do {
409 r = radeon_gpu_reset(rdev);
410 } while (r == -EAGAIN);
411 down_read(&rdev->exclusive_lock);
412 }
413 if (r)
414 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
415
416 /* We continue with the page flip even if we failed to wait on
417 * the fence, otherwise the DRM core and userspace will be
418 * confused about which BO the CRTC is scanning out
419 */
420
421 radeon_fence_unref(&work->fence);
422 }
423
424 /* We borrow the event spin lock for protecting flip_status */
425 spin_lock_irqsave(&crtc->dev->event_lock, flags);
426
427 /* set the proper interrupt */
428 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
429
430 /* do the flip (mmio) */
431 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base);
432
433 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
434 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
435 up_read(&rdev->exclusive_lock);
436 }
437
438 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
439 struct drm_framebuffer *fb,
440 struct drm_pending_vblank_event *event,
441 uint32_t page_flip_flags)
442 {
443 struct drm_device *dev = crtc->dev;
444 struct radeon_device *rdev = dev->dev_private;
445 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
446 struct radeon_framebuffer *old_radeon_fb;
447 struct radeon_framebuffer *new_radeon_fb;
448 struct drm_gem_object *obj;
449 struct radeon_flip_work *work;
450 struct radeon_bo *new_rbo;
451 uint32_t tiling_flags, pitch_pixels;
452 uint64_t base;
453 unsigned long flags;
454 int r;
455
456 work = kzalloc(sizeof *work, GFP_KERNEL);
457 if (work == NULL)
458 return -ENOMEM;
459
460 INIT_WORK(&work->flip_work, radeon_flip_work_func);
461 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
462
463 work->rdev = rdev;
464 work->crtc_id = radeon_crtc->crtc_id;
465 work->event = event;
466
467 /* schedule unpin of the old buffer */
468 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
469 obj = old_radeon_fb->obj;
470
471 /* take a reference to the old object */
472 drm_gem_object_reference(obj);
473 work->old_rbo = gem_to_radeon_bo(obj);
474
475 new_radeon_fb = to_radeon_framebuffer(fb);
476 obj = new_radeon_fb->obj;
477 new_rbo = gem_to_radeon_bo(obj);
478
479 /* pin the new buffer */
480 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
481 work->old_rbo, new_rbo);
482
483 r = radeon_bo_reserve(new_rbo, false);
484 if (unlikely(r != 0)) {
485 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
486 goto cleanup;
487 }
488 /* Only 27 bit offset for legacy CRTC */
489 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
490 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
491 if (unlikely(r != 0)) {
492 radeon_bo_unreserve(new_rbo);
493 r = -EINVAL;
494 DRM_ERROR("failed to pin new rbo buffer before flip\n");
495 goto cleanup;
496 }
497 work->fence = (struct radeon_fence *)fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
498 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
499 radeon_bo_unreserve(new_rbo);
500
501 if (!ASIC_IS_AVIVO(rdev)) {
502 /* crtc offset is from display base addr not FB location */
503 base -= radeon_crtc->legacy_display_base_addr;
504 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
505
506 if (tiling_flags & RADEON_TILING_MACRO) {
507 if (ASIC_IS_R300(rdev)) {
508 base &= ~0x7ff;
509 } else {
510 int byteshift = fb->bits_per_pixel >> 4;
511 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
512 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
513 }
514 } else {
515 int offset = crtc->y * pitch_pixels + crtc->x;
516 switch (fb->bits_per_pixel) {
517 case 8:
518 default:
519 offset *= 1;
520 break;
521 case 15:
522 case 16:
523 offset *= 2;
524 break;
525 case 24:
526 offset *= 3;
527 break;
528 case 32:
529 offset *= 4;
530 break;
531 }
532 base += offset;
533 }
534 base &= ~7;
535 }
536 work->base = base;
537
538 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id);
539 if (r) {
540 DRM_ERROR("failed to get vblank before flip\n");
541 goto pflip_cleanup;
542 }
543
544 /* We borrow the event spin lock for protecting flip_work */
545 spin_lock_irqsave(&crtc->dev->event_lock, flags);
546
547 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
548 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
549 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
550 r = -EBUSY;
551 goto vblank_cleanup;
552 }
553 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
554 radeon_crtc->flip_work = work;
555
556 /* update crtc fb */
557 crtc->primary->fb = fb;
558
559 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
560
561 queue_work(radeon_crtc->flip_queue, &work->flip_work);
562 return 0;
563
564 vblank_cleanup:
565 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id);
566
567 pflip_cleanup:
568 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
569 DRM_ERROR("failed to reserve new rbo in error path\n");
570 goto cleanup;
571 }
572 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
573 DRM_ERROR("failed to unpin new rbo in error path\n");
574 }
575 radeon_bo_unreserve(new_rbo);
576
577 cleanup:
578 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
579 radeon_fence_unref(&work->fence);
580 kfree(work);
581 return r;
582 }
583
584 static int
585 radeon_crtc_set_config(struct drm_mode_set *set)
586 {
587 struct drm_device *dev;
588 struct radeon_device *rdev;
589 struct drm_crtc *crtc;
590 bool active = false;
591 int ret;
592
593 if (!set || !set->crtc)
594 return -EINVAL;
595
596 dev = set->crtc->dev;
597
598 ret = pm_runtime_get_sync(dev->dev);
599 if (ret < 0)
600 return ret;
601
602 ret = drm_crtc_helper_set_config(set);
603
604 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
605 if (crtc->enabled)
606 active = true;
607
608 pm_runtime_mark_last_busy(dev->dev);
609
610 rdev = dev->dev_private;
611 /* if we have active crtcs and we don't have a power ref,
612 take the current one */
613 if (active && !rdev->have_disp_power_ref) {
614 rdev->have_disp_power_ref = true;
615 return ret;
616 }
617 /* if we have no active crtcs, then drop the power ref
618 we got before */
619 if (!active && rdev->have_disp_power_ref) {
620 pm_runtime_put_autosuspend(dev->dev);
621 rdev->have_disp_power_ref = false;
622 }
623
624 /* drop the power reference we got coming in here */
625 pm_runtime_put_autosuspend(dev->dev);
626 return ret;
627 }
628 static const struct drm_crtc_funcs radeon_crtc_funcs = {
629 .cursor_set = radeon_crtc_cursor_set,
630 .cursor_move = radeon_crtc_cursor_move,
631 .gamma_set = radeon_crtc_gamma_set,
632 .set_config = radeon_crtc_set_config,
633 .destroy = radeon_crtc_destroy,
634 .page_flip = radeon_crtc_page_flip,
635 };
636
637 static void radeon_crtc_init(struct drm_device *dev, int index)
638 {
639 struct radeon_device *rdev = dev->dev_private;
640 struct radeon_crtc *radeon_crtc;
641 int i;
642
643 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
644 if (radeon_crtc == NULL)
645 return;
646
647 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
648
649 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
650 radeon_crtc->crtc_id = index;
651 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc");
652 rdev->mode_info.crtcs[index] = radeon_crtc;
653
654 if (rdev->family >= CHIP_BONAIRE) {
655 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
656 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
657 } else {
658 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
659 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
660 }
661 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
662 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
663
664 #if 0
665 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
666 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
667 radeon_crtc->mode_set.num_connectors = 0;
668 #endif
669
670 for (i = 0; i < 256; i++) {
671 radeon_crtc->lut_r[i] = i << 2;
672 radeon_crtc->lut_g[i] = i << 2;
673 radeon_crtc->lut_b[i] = i << 2;
674 }
675
676 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
677 radeon_atombios_init_crtc(dev, radeon_crtc);
678 else
679 radeon_legacy_init_crtc(dev, radeon_crtc);
680 }
681
682 static const char *encoder_names[38] = {
683 "NONE",
684 "INTERNAL_LVDS",
685 "INTERNAL_TMDS1",
686 "INTERNAL_TMDS2",
687 "INTERNAL_DAC1",
688 "INTERNAL_DAC2",
689 "INTERNAL_SDVOA",
690 "INTERNAL_SDVOB",
691 "SI170B",
692 "CH7303",
693 "CH7301",
694 "INTERNAL_DVO1",
695 "EXTERNAL_SDVOA",
696 "EXTERNAL_SDVOB",
697 "TITFP513",
698 "INTERNAL_LVTM1",
699 "VT1623",
700 "HDMI_SI1930",
701 "HDMI_INTERNAL",
702 "INTERNAL_KLDSCP_TMDS1",
703 "INTERNAL_KLDSCP_DVO1",
704 "INTERNAL_KLDSCP_DAC1",
705 "INTERNAL_KLDSCP_DAC2",
706 "SI178",
707 "MVPU_FPGA",
708 "INTERNAL_DDI",
709 "VT1625",
710 "HDMI_SI1932",
711 "DP_AN9801",
712 "DP_DP501",
713 "INTERNAL_UNIPHY",
714 "INTERNAL_KLDSCP_LVTMA",
715 "INTERNAL_UNIPHY1",
716 "INTERNAL_UNIPHY2",
717 "NUTMEG",
718 "TRAVIS",
719 "INTERNAL_VCE",
720 "INTERNAL_UNIPHY3",
721 };
722
723 static const char *hpd_names[6] = {
724 "HPD1",
725 "HPD2",
726 "HPD3",
727 "HPD4",
728 "HPD5",
729 "HPD6",
730 };
731
732 static void radeon_print_display_setup(struct drm_device *dev)
733 {
734 struct drm_connector *connector;
735 struct radeon_connector *radeon_connector;
736 struct drm_encoder *encoder;
737 struct radeon_encoder *radeon_encoder;
738 uint32_t devices;
739 int i = 0;
740
741 DRM_INFO("Radeon Display Connectors\n");
742 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
743 radeon_connector = to_radeon_connector(connector);
744 DRM_INFO("Connector %d:\n", i);
745 DRM_INFO(" %s\n", connector->name);
746 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
747 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
748 if (radeon_connector->ddc_bus) {
749 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
750 radeon_connector->ddc_bus->rec.mask_clk_reg,
751 radeon_connector->ddc_bus->rec.mask_data_reg,
752 radeon_connector->ddc_bus->rec.a_clk_reg,
753 radeon_connector->ddc_bus->rec.a_data_reg,
754 radeon_connector->ddc_bus->rec.en_clk_reg,
755 radeon_connector->ddc_bus->rec.en_data_reg,
756 radeon_connector->ddc_bus->rec.y_clk_reg,
757 radeon_connector->ddc_bus->rec.y_data_reg);
758 if (radeon_connector->router.ddc_valid)
759 DRM_INFO(" DDC Router 0x%x/0x%x\n",
760 radeon_connector->router.ddc_mux_control_pin,
761 radeon_connector->router.ddc_mux_state);
762 if (radeon_connector->router.cd_valid)
763 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
764 radeon_connector->router.cd_mux_control_pin,
765 radeon_connector->router.cd_mux_state);
766 } else {
767 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
768 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
769 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
770 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
771 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
772 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
773 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
774 }
775 DRM_INFO(" Encoders:\n");
776 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
777 radeon_encoder = to_radeon_encoder(encoder);
778 devices = radeon_encoder->devices & radeon_connector->devices;
779 if (devices) {
780 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
781 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
782 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
783 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
784 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
785 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
786 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
787 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
788 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
789 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
790 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
791 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
792 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
793 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
794 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
795 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
796 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
797 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
798 if (devices & ATOM_DEVICE_TV1_SUPPORT)
799 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
800 if (devices & ATOM_DEVICE_CV_SUPPORT)
801 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
802 }
803 }
804 i++;
805 }
806 }
807
808 static bool radeon_setup_enc_conn(struct drm_device *dev)
809 {
810 struct radeon_device *rdev = dev->dev_private;
811 bool ret = false;
812
813 if (rdev->bios) {
814 if (rdev->is_atom_bios) {
815 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
816 if (ret == false)
817 ret = radeon_get_atom_connector_info_from_object_table(dev);
818 } else {
819 ret = radeon_get_legacy_connector_info_from_bios(dev);
820 if (ret == false)
821 ret = radeon_get_legacy_connector_info_from_table(dev);
822 }
823 } else {
824 if (!ASIC_IS_AVIVO(rdev))
825 ret = radeon_get_legacy_connector_info_from_table(dev);
826 }
827 if (ret) {
828 radeon_setup_encoder_clones(dev);
829 radeon_print_display_setup(dev);
830 }
831
832 return ret;
833 }
834
835 /* avivo */
836
837 /**
838 * avivo_reduce_ratio - fractional number reduction
839 *
840 * @nom: nominator
841 * @den: denominator
842 * @nom_min: minimum value for nominator
843 * @den_min: minimum value for denominator
844 *
845 * Find the greatest common divisor and apply it on both nominator and
846 * denominator, but make nominator and denominator are at least as large
847 * as their minimum values.
848 */
849 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
850 unsigned nom_min, unsigned den_min)
851 {
852 unsigned tmp;
853
854 /* reduce the numbers to a simpler ratio */
855 tmp = gcd(*nom, *den);
856 *nom /= tmp;
857 *den /= tmp;
858
859 /* make sure nominator is large enough */
860 if (*nom < nom_min) {
861 tmp = DIV_ROUND_UP(nom_min, *nom);
862 *nom *= tmp;
863 *den *= tmp;
864 }
865
866 /* make sure the denominator is large enough */
867 if (*den < den_min) {
868 tmp = DIV_ROUND_UP(den_min, *den);
869 *nom *= tmp;
870 *den *= tmp;
871 }
872 }
873
874 /**
875 * avivo_get_fb_ref_div - feedback and ref divider calculation
876 *
877 * @nom: nominator
878 * @den: denominator
879 * @post_div: post divider
880 * @fb_div_max: feedback divider maximum
881 * @ref_div_max: reference divider maximum
882 * @fb_div: resulting feedback divider
883 * @ref_div: resulting reference divider
884 *
885 * Calculate feedback and reference divider for a given post divider. Makes
886 * sure we stay within the limits.
887 */
888 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
889 unsigned fb_div_max, unsigned ref_div_max,
890 unsigned *fb_div, unsigned *ref_div)
891 {
892 /* limit reference * post divider to a maximum */
893 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
894
895 /* get matching reference and feedback divider */
896 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
897 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
898
899 /* limit fb divider to its maximum */
900 if (*fb_div > fb_div_max) {
901 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
902 *fb_div = fb_div_max;
903 }
904 }
905
906 /**
907 * radeon_compute_pll_avivo - compute PLL paramaters
908 *
909 * @pll: information about the PLL
910 * @dot_clock_p: resulting pixel clock
911 * fb_div_p: resulting feedback divider
912 * frac_fb_div_p: fractional part of the feedback divider
913 * ref_div_p: resulting reference divider
914 * post_div_p: resulting reference divider
915 *
916 * Try to calculate the PLL parameters to generate the given frequency:
917 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
918 */
919 void radeon_compute_pll_avivo(struct radeon_pll *pll,
920 u32 freq,
921 u32 *dot_clock_p,
922 u32 *fb_div_p,
923 u32 *frac_fb_div_p,
924 u32 *ref_div_p,
925 u32 *post_div_p)
926 {
927 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
928 freq : freq / 10;
929
930 unsigned fb_div_min, fb_div_max, fb_div;
931 unsigned post_div_min, post_div_max, post_div;
932 unsigned ref_div_min, ref_div_max, ref_div;
933 unsigned post_div_best, diff_best;
934 unsigned nom, den;
935
936 /* determine allowed feedback divider range */
937 fb_div_min = pll->min_feedback_div;
938 fb_div_max = pll->max_feedback_div;
939
940 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
941 fb_div_min *= 10;
942 fb_div_max *= 10;
943 }
944
945 /* determine allowed ref divider range */
946 if (pll->flags & RADEON_PLL_USE_REF_DIV)
947 ref_div_min = pll->reference_div;
948 else
949 ref_div_min = pll->min_ref_div;
950
951 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
952 pll->flags & RADEON_PLL_USE_REF_DIV)
953 ref_div_max = pll->reference_div;
954 else
955 ref_div_max = pll->max_ref_div;
956
957 /* determine allowed post divider range */
958 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
959 post_div_min = pll->post_div;
960 post_div_max = pll->post_div;
961 } else {
962 unsigned vco_min, vco_max;
963
964 if (pll->flags & RADEON_PLL_IS_LCD) {
965 vco_min = pll->lcd_pll_out_min;
966 vco_max = pll->lcd_pll_out_max;
967 } else {
968 vco_min = pll->pll_out_min;
969 vco_max = pll->pll_out_max;
970 }
971
972 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
973 vco_min *= 10;
974 vco_max *= 10;
975 }
976
977 post_div_min = vco_min / target_clock;
978 if ((target_clock * post_div_min) < vco_min)
979 ++post_div_min;
980 if (post_div_min < pll->min_post_div)
981 post_div_min = pll->min_post_div;
982
983 post_div_max = vco_max / target_clock;
984 if ((target_clock * post_div_max) > vco_max)
985 --post_div_max;
986 if (post_div_max > pll->max_post_div)
987 post_div_max = pll->max_post_div;
988 }
989
990 /* represent the searched ratio as fractional number */
991 nom = target_clock;
992 den = pll->reference_freq;
993
994 /* reduce the numbers to a simpler ratio */
995 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
996
997 /* now search for a post divider */
998 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
999 post_div_best = post_div_min;
1000 else
1001 post_div_best = post_div_max;
1002 diff_best = ~0;
1003
1004 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1005 unsigned diff;
1006 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1007 ref_div_max, &fb_div, &ref_div);
1008 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1009 (ref_div * post_div));
1010
1011 if (diff < diff_best || (diff == diff_best &&
1012 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1013
1014 post_div_best = post_div;
1015 diff_best = diff;
1016 }
1017 }
1018 post_div = post_div_best;
1019
1020 /* get the feedback and reference divider for the optimal value */
1021 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1022 &fb_div, &ref_div);
1023
1024 /* reduce the numbers to a simpler ratio once more */
1025 /* this also makes sure that the reference divider is large enough */
1026 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1027
1028 /* avoid high jitter with small fractional dividers */
1029 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1030 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1031 if (fb_div < fb_div_min) {
1032 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1033 fb_div *= tmp;
1034 ref_div *= tmp;
1035 }
1036 }
1037
1038 /* and finally save the result */
1039 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1040 *fb_div_p = fb_div / 10;
1041 *frac_fb_div_p = fb_div % 10;
1042 } else {
1043 *fb_div_p = fb_div;
1044 *frac_fb_div_p = 0;
1045 }
1046
1047 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1048 (pll->reference_freq * *frac_fb_div_p)) /
1049 (ref_div * post_div * 10);
1050 *ref_div_p = ref_div;
1051 *post_div_p = post_div;
1052
1053 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1054 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1055 ref_div, post_div);
1056 }
1057
1058 /* pre-avivo */
1059 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1060 {
1061 uint64_t mod;
1062
1063 n += d / 2;
1064
1065 mod = do_div(n, d);
1066 return n;
1067 }
1068
1069 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1070 uint64_t freq,
1071 uint32_t *dot_clock_p,
1072 uint32_t *fb_div_p,
1073 uint32_t *frac_fb_div_p,
1074 uint32_t *ref_div_p,
1075 uint32_t *post_div_p)
1076 {
1077 uint32_t min_ref_div = pll->min_ref_div;
1078 uint32_t max_ref_div = pll->max_ref_div;
1079 uint32_t min_post_div = pll->min_post_div;
1080 uint32_t max_post_div = pll->max_post_div;
1081 uint32_t min_fractional_feed_div = 0;
1082 uint32_t max_fractional_feed_div = 0;
1083 uint32_t best_vco = pll->best_vco;
1084 uint32_t best_post_div = 1;
1085 uint32_t best_ref_div = 1;
1086 uint32_t best_feedback_div = 1;
1087 uint32_t best_frac_feedback_div = 0;
1088 uint32_t best_freq = -1;
1089 uint32_t best_error = 0xffffffff;
1090 uint32_t best_vco_diff = 1;
1091 uint32_t post_div;
1092 u32 pll_out_min, pll_out_max;
1093
1094 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1095 freq = freq * 1000;
1096
1097 if (pll->flags & RADEON_PLL_IS_LCD) {
1098 pll_out_min = pll->lcd_pll_out_min;
1099 pll_out_max = pll->lcd_pll_out_max;
1100 } else {
1101 pll_out_min = pll->pll_out_min;
1102 pll_out_max = pll->pll_out_max;
1103 }
1104
1105 if (pll_out_min > 64800)
1106 pll_out_min = 64800;
1107
1108 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1109 min_ref_div = max_ref_div = pll->reference_div;
1110 else {
1111 while (min_ref_div < max_ref_div-1) {
1112 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1113 uint32_t pll_in = pll->reference_freq / mid;
1114 if (pll_in < pll->pll_in_min)
1115 max_ref_div = mid;
1116 else if (pll_in > pll->pll_in_max)
1117 min_ref_div = mid;
1118 else
1119 break;
1120 }
1121 }
1122
1123 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1124 min_post_div = max_post_div = pll->post_div;
1125
1126 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1127 min_fractional_feed_div = pll->min_frac_feedback_div;
1128 max_fractional_feed_div = pll->max_frac_feedback_div;
1129 }
1130
1131 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1132 uint32_t ref_div;
1133
1134 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1135 continue;
1136
1137 /* legacy radeons only have a few post_divs */
1138 if (pll->flags & RADEON_PLL_LEGACY) {
1139 if ((post_div == 5) ||
1140 (post_div == 7) ||
1141 (post_div == 9) ||
1142 (post_div == 10) ||
1143 (post_div == 11) ||
1144 (post_div == 13) ||
1145 (post_div == 14) ||
1146 (post_div == 15))
1147 continue;
1148 }
1149
1150 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1151 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1152 uint32_t pll_in = pll->reference_freq / ref_div;
1153 uint32_t min_feed_div = pll->min_feedback_div;
1154 uint32_t max_feed_div = pll->max_feedback_div + 1;
1155
1156 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1157 continue;
1158
1159 while (min_feed_div < max_feed_div) {
1160 uint32_t vco;
1161 uint32_t min_frac_feed_div = min_fractional_feed_div;
1162 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1163 uint32_t frac_feedback_div;
1164 uint64_t tmp;
1165
1166 feedback_div = (min_feed_div + max_feed_div) / 2;
1167
1168 tmp = (uint64_t)pll->reference_freq * feedback_div;
1169 vco = radeon_div(tmp, ref_div);
1170
1171 if (vco < pll_out_min) {
1172 min_feed_div = feedback_div + 1;
1173 continue;
1174 } else if (vco > pll_out_max) {
1175 max_feed_div = feedback_div;
1176 continue;
1177 }
1178
1179 while (min_frac_feed_div < max_frac_feed_div) {
1180 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1181 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1182 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1183 current_freq = radeon_div(tmp, ref_div * post_div);
1184
1185 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1186 if (freq < current_freq)
1187 error = 0xffffffff;
1188 else
1189 error = freq - current_freq;
1190 } else
1191 error = abs(current_freq - freq);
1192 vco_diff = abs(vco - best_vco);
1193
1194 if ((best_vco == 0 && error < best_error) ||
1195 (best_vco != 0 &&
1196 ((best_error > 100 && error < best_error - 100) ||
1197 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1198 best_post_div = post_div;
1199 best_ref_div = ref_div;
1200 best_feedback_div = feedback_div;
1201 best_frac_feedback_div = frac_feedback_div;
1202 best_freq = current_freq;
1203 best_error = error;
1204 best_vco_diff = vco_diff;
1205 } else if (current_freq == freq) {
1206 if (best_freq == -1) {
1207 best_post_div = post_div;
1208 best_ref_div = ref_div;
1209 best_feedback_div = feedback_div;
1210 best_frac_feedback_div = frac_feedback_div;
1211 best_freq = current_freq;
1212 best_error = error;
1213 best_vco_diff = vco_diff;
1214 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1215 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1216 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1217 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1218 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1219 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1220 best_post_div = post_div;
1221 best_ref_div = ref_div;
1222 best_feedback_div = feedback_div;
1223 best_frac_feedback_div = frac_feedback_div;
1224 best_freq = current_freq;
1225 best_error = error;
1226 best_vco_diff = vco_diff;
1227 }
1228 }
1229 if (current_freq < freq)
1230 min_frac_feed_div = frac_feedback_div + 1;
1231 else
1232 max_frac_feed_div = frac_feedback_div;
1233 }
1234 if (current_freq < freq)
1235 min_feed_div = feedback_div + 1;
1236 else
1237 max_feed_div = feedback_div;
1238 }
1239 }
1240 }
1241
1242 *dot_clock_p = best_freq / 10000;
1243 *fb_div_p = best_feedback_div;
1244 *frac_fb_div_p = best_frac_feedback_div;
1245 *ref_div_p = best_ref_div;
1246 *post_div_p = best_post_div;
1247 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1248 (long long)freq,
1249 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1250 best_ref_div, best_post_div);
1251
1252 }
1253
1254 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1255 {
1256 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1257
1258 if (radeon_fb->obj) {
1259 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1260 }
1261 drm_framebuffer_cleanup(fb);
1262 kfree(radeon_fb);
1263 }
1264
1265 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1266 struct drm_file *file_priv,
1267 unsigned int *handle)
1268 {
1269 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1270
1271 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1272 }
1273
1274 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1275 .destroy = radeon_user_framebuffer_destroy,
1276 .create_handle = radeon_user_framebuffer_create_handle,
1277 };
1278
1279 int
1280 radeon_framebuffer_init(struct drm_device *dev,
1281 struct radeon_framebuffer *rfb,
1282 struct drm_mode_fb_cmd2 *mode_cmd,
1283 struct drm_gem_object *obj)
1284 {
1285 int ret;
1286 rfb->obj = obj;
1287 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1288 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1289 if (ret) {
1290 rfb->obj = NULL;
1291 return ret;
1292 }
1293 return 0;
1294 }
1295
1296 static struct drm_framebuffer *
1297 radeon_user_framebuffer_create(struct drm_device *dev,
1298 struct drm_file *file_priv,
1299 struct drm_mode_fb_cmd2 *mode_cmd)
1300 {
1301 struct drm_gem_object *obj;
1302 struct radeon_framebuffer *radeon_fb;
1303 int ret;
1304
1305 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1306 if (obj == NULL) {
1307 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1308 "can't create framebuffer\n", mode_cmd->handles[0]);
1309 return ERR_PTR(-ENOENT);
1310 }
1311
1312 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1313 if (radeon_fb == NULL) {
1314 drm_gem_object_unreference_unlocked(obj);
1315 return ERR_PTR(-ENOMEM);
1316 }
1317
1318 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1319 if (ret) {
1320 kfree(radeon_fb);
1321 drm_gem_object_unreference_unlocked(obj);
1322 return ERR_PTR(ret);
1323 }
1324
1325 return &radeon_fb->base;
1326 }
1327
1328 static void radeon_output_poll_changed(struct drm_device *dev)
1329 {
1330 struct radeon_device *rdev = dev->dev_private;
1331 radeon_fb_output_poll_changed(rdev);
1332 }
1333
1334 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1335 .fb_create = radeon_user_framebuffer_create,
1336 .output_poll_changed = radeon_output_poll_changed
1337 };
1338
1339 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1340 { { 0, "driver" },
1341 { 1, "bios" },
1342 };
1343
1344 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1345 { { TV_STD_NTSC, "ntsc" },
1346 { TV_STD_PAL, "pal" },
1347 { TV_STD_PAL_M, "pal-m" },
1348 { TV_STD_PAL_60, "pal-60" },
1349 { TV_STD_NTSC_J, "ntsc-j" },
1350 { TV_STD_SCART_PAL, "scart-pal" },
1351 { TV_STD_PAL_CN, "pal-cn" },
1352 { TV_STD_SECAM, "secam" },
1353 };
1354
1355 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1356 { { UNDERSCAN_OFF, "off" },
1357 { UNDERSCAN_ON, "on" },
1358 { UNDERSCAN_AUTO, "auto" },
1359 };
1360
1361 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1362 { { RADEON_AUDIO_DISABLE, "off" },
1363 { RADEON_AUDIO_ENABLE, "on" },
1364 { RADEON_AUDIO_AUTO, "auto" },
1365 };
1366
1367 /* XXX support different dither options? spatial, temporal, both, etc. */
1368 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1369 { { RADEON_FMT_DITHER_DISABLE, "off" },
1370 { RADEON_FMT_DITHER_ENABLE, "on" },
1371 };
1372
1373 static int radeon_modeset_create_props(struct radeon_device *rdev)
1374 {
1375 int sz;
1376
1377 if (rdev->is_atom_bios) {
1378 rdev->mode_info.coherent_mode_property =
1379 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1380 if (!rdev->mode_info.coherent_mode_property)
1381 return -ENOMEM;
1382 }
1383
1384 if (!ASIC_IS_AVIVO(rdev)) {
1385 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1386 rdev->mode_info.tmds_pll_property =
1387 drm_property_create_enum(rdev->ddev, 0,
1388 "tmds_pll",
1389 radeon_tmds_pll_enum_list, sz);
1390 }
1391
1392 rdev->mode_info.load_detect_property =
1393 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1394 if (!rdev->mode_info.load_detect_property)
1395 return -ENOMEM;
1396
1397 drm_mode_create_scaling_mode_property(rdev->ddev);
1398
1399 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1400 rdev->mode_info.tv_std_property =
1401 drm_property_create_enum(rdev->ddev, 0,
1402 "tv standard",
1403 radeon_tv_std_enum_list, sz);
1404
1405 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1406 rdev->mode_info.underscan_property =
1407 drm_property_create_enum(rdev->ddev, 0,
1408 "underscan",
1409 radeon_underscan_enum_list, sz);
1410
1411 rdev->mode_info.underscan_hborder_property =
1412 drm_property_create_range(rdev->ddev, 0,
1413 "underscan hborder", 0, 128);
1414 if (!rdev->mode_info.underscan_hborder_property)
1415 return -ENOMEM;
1416
1417 rdev->mode_info.underscan_vborder_property =
1418 drm_property_create_range(rdev->ddev, 0,
1419 "underscan vborder", 0, 128);
1420 if (!rdev->mode_info.underscan_vborder_property)
1421 return -ENOMEM;
1422
1423 sz = ARRAY_SIZE(radeon_audio_enum_list);
1424 rdev->mode_info.audio_property =
1425 drm_property_create_enum(rdev->ddev, 0,
1426 "audio",
1427 radeon_audio_enum_list, sz);
1428
1429 sz = ARRAY_SIZE(radeon_dither_enum_list);
1430 rdev->mode_info.dither_property =
1431 drm_property_create_enum(rdev->ddev, 0,
1432 "dither",
1433 radeon_dither_enum_list, sz);
1434
1435 return 0;
1436 }
1437
1438 void radeon_update_display_priority(struct radeon_device *rdev)
1439 {
1440 /* adjustment options for the display watermarks */
1441 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1442 /* set display priority to high for r3xx, rv515 chips
1443 * this avoids flickering due to underflow to the
1444 * display controllers during heavy acceleration.
1445 * Don't force high on rs4xx igp chips as it seems to
1446 * affect the sound card. See kernel bug 15982.
1447 */
1448 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1449 !(rdev->flags & RADEON_IS_IGP))
1450 rdev->disp_priority = 2;
1451 else
1452 rdev->disp_priority = 0;
1453 } else
1454 rdev->disp_priority = radeon_disp_priority;
1455
1456 }
1457
1458 /*
1459 * Allocate hdmi structs and determine register offsets
1460 */
1461 static void radeon_afmt_init(struct radeon_device *rdev)
1462 {
1463 int i;
1464
1465 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1466 rdev->mode_info.afmt[i] = NULL;
1467
1468 if (ASIC_IS_NODCE(rdev)) {
1469 /* nothing to do */
1470 } else if (ASIC_IS_DCE4(rdev)) {
1471 static uint32_t eg_offsets[] = {
1472 EVERGREEN_CRTC0_REGISTER_OFFSET,
1473 EVERGREEN_CRTC1_REGISTER_OFFSET,
1474 EVERGREEN_CRTC2_REGISTER_OFFSET,
1475 EVERGREEN_CRTC3_REGISTER_OFFSET,
1476 EVERGREEN_CRTC4_REGISTER_OFFSET,
1477 EVERGREEN_CRTC5_REGISTER_OFFSET,
1478 0x13830 - 0x7030,
1479 };
1480 int num_afmt;
1481
1482 /* DCE8 has 7 audio blocks tied to DIG encoders */
1483 /* DCE6 has 6 audio blocks tied to DIG encoders */
1484 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1485 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1486 if (ASIC_IS_DCE8(rdev))
1487 num_afmt = 7;
1488 else if (ASIC_IS_DCE6(rdev))
1489 num_afmt = 6;
1490 else if (ASIC_IS_DCE5(rdev))
1491 num_afmt = 6;
1492 else if (ASIC_IS_DCE41(rdev))
1493 num_afmt = 2;
1494 else /* DCE4 */
1495 num_afmt = 6;
1496
1497 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1498 for (i = 0; i < num_afmt; i++) {
1499 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1500 if (rdev->mode_info.afmt[i]) {
1501 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1502 rdev->mode_info.afmt[i]->id = i;
1503 }
1504 }
1505 } else if (ASIC_IS_DCE3(rdev)) {
1506 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1507 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1508 if (rdev->mode_info.afmt[0]) {
1509 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1510 rdev->mode_info.afmt[0]->id = 0;
1511 }
1512 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1513 if (rdev->mode_info.afmt[1]) {
1514 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1515 rdev->mode_info.afmt[1]->id = 1;
1516 }
1517 } else if (ASIC_IS_DCE2(rdev)) {
1518 /* DCE2 has at least 1 routable audio block */
1519 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1520 if (rdev->mode_info.afmt[0]) {
1521 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1522 rdev->mode_info.afmt[0]->id = 0;
1523 }
1524 /* r6xx has 2 routable audio blocks */
1525 if (rdev->family >= CHIP_R600) {
1526 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1527 if (rdev->mode_info.afmt[1]) {
1528 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1529 rdev->mode_info.afmt[1]->id = 1;
1530 }
1531 }
1532 }
1533 }
1534
1535 static void radeon_afmt_fini(struct radeon_device *rdev)
1536 {
1537 int i;
1538
1539 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1540 kfree(rdev->mode_info.afmt[i]);
1541 rdev->mode_info.afmt[i] = NULL;
1542 }
1543 }
1544
1545 int radeon_modeset_init(struct radeon_device *rdev)
1546 {
1547 int i;
1548 int ret;
1549
1550 drm_mode_config_init(rdev->ddev);
1551 rdev->mode_info.mode_config_initialized = true;
1552
1553 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1554
1555 if (ASIC_IS_DCE5(rdev)) {
1556 rdev->ddev->mode_config.max_width = 16384;
1557 rdev->ddev->mode_config.max_height = 16384;
1558 } else if (ASIC_IS_AVIVO(rdev)) {
1559 rdev->ddev->mode_config.max_width = 8192;
1560 rdev->ddev->mode_config.max_height = 8192;
1561 } else {
1562 rdev->ddev->mode_config.max_width = 4096;
1563 rdev->ddev->mode_config.max_height = 4096;
1564 }
1565
1566 rdev->ddev->mode_config.preferred_depth = 24;
1567 rdev->ddev->mode_config.prefer_shadow = 1;
1568
1569 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1570
1571 ret = radeon_modeset_create_props(rdev);
1572 if (ret) {
1573 return ret;
1574 }
1575
1576 /* init i2c buses */
1577 radeon_i2c_init(rdev);
1578
1579 /* check combios for a valid hardcoded EDID - Sun servers */
1580 if (!rdev->is_atom_bios) {
1581 /* check for hardcoded EDID in BIOS */
1582 radeon_combios_check_hardcoded_edid(rdev);
1583 }
1584
1585 /* allocate crtcs */
1586 for (i = 0; i < rdev->num_crtc; i++) {
1587 radeon_crtc_init(rdev->ddev, i);
1588 }
1589
1590 /* okay we should have all the bios connectors */
1591 ret = radeon_setup_enc_conn(rdev->ddev);
1592 if (!ret) {
1593 return ret;
1594 }
1595
1596 /* init dig PHYs, disp eng pll */
1597 if (rdev->is_atom_bios) {
1598 radeon_atom_encoder_init(rdev);
1599 radeon_atom_disp_eng_pll_init(rdev);
1600 }
1601
1602 /* initialize hpd */
1603 radeon_hpd_init(rdev);
1604
1605 /* setup afmt */
1606 radeon_afmt_init(rdev);
1607
1608 radeon_fbdev_init(rdev);
1609 drm_kms_helper_poll_init(rdev->ddev);
1610
1611 if (rdev->pm.dpm_enabled) {
1612 /* do dpm late init */
1613 ret = radeon_pm_late_init(rdev);
1614 if (ret) {
1615 rdev->pm.dpm_enabled = false;
1616 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1617 }
1618 /* set the dpm state for PX since there won't be
1619 * a modeset to call this.
1620 */
1621 radeon_pm_compute_clocks(rdev);
1622 }
1623
1624 return 0;
1625 }
1626
1627 void radeon_modeset_fini(struct radeon_device *rdev)
1628 {
1629 radeon_fbdev_fini(rdev);
1630 kfree(rdev->mode_info.bios_hardcoded_edid);
1631
1632 if (rdev->mode_info.mode_config_initialized) {
1633 radeon_afmt_fini(rdev);
1634 drm_kms_helper_poll_fini(rdev->ddev);
1635 radeon_hpd_fini(rdev);
1636 drm_mode_config_cleanup(rdev->ddev);
1637 rdev->mode_info.mode_config_initialized = false;
1638 }
1639 /* free i2c buses */
1640 radeon_i2c_fini(rdev);
1641 }
1642
1643 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1644 {
1645 /* try and guess if this is a tv or a monitor */
1646 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1647 (mode->vdisplay == 576) || /* 576p */
1648 (mode->vdisplay == 720) || /* 720p */
1649 (mode->vdisplay == 1080)) /* 1080p */
1650 return true;
1651 else
1652 return false;
1653 }
1654
1655 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1656 const struct drm_display_mode *mode,
1657 struct drm_display_mode *adjusted_mode)
1658 {
1659 struct drm_device *dev = crtc->dev;
1660 struct radeon_device *rdev = dev->dev_private;
1661 struct drm_encoder *encoder;
1662 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1663 struct radeon_encoder *radeon_encoder;
1664 struct drm_connector *connector;
1665 struct radeon_connector *radeon_connector;
1666 bool first = true;
1667 u32 src_v = 1, dst_v = 1;
1668 u32 src_h = 1, dst_h = 1;
1669
1670 radeon_crtc->h_border = 0;
1671 radeon_crtc->v_border = 0;
1672
1673 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1674 if (encoder->crtc != crtc)
1675 continue;
1676 radeon_encoder = to_radeon_encoder(encoder);
1677 connector = radeon_get_connector_for_encoder(encoder);
1678 radeon_connector = to_radeon_connector(connector);
1679
1680 if (first) {
1681 /* set scaling */
1682 if (radeon_encoder->rmx_type == RMX_OFF)
1683 radeon_crtc->rmx_type = RMX_OFF;
1684 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1685 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1686 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1687 else
1688 radeon_crtc->rmx_type = RMX_OFF;
1689 /* copy native mode */
1690 memcpy(&radeon_crtc->native_mode,
1691 &radeon_encoder->native_mode,
1692 sizeof(struct drm_display_mode));
1693 src_v = crtc->mode.vdisplay;
1694 dst_v = radeon_crtc->native_mode.vdisplay;
1695 src_h = crtc->mode.hdisplay;
1696 dst_h = radeon_crtc->native_mode.hdisplay;
1697
1698 /* fix up for overscan on hdmi */
1699 if (ASIC_IS_AVIVO(rdev) &&
1700 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1701 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1702 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1703 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1704 is_hdtv_mode(mode)))) {
1705 if (radeon_encoder->underscan_hborder != 0)
1706 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1707 else
1708 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1709 if (radeon_encoder->underscan_vborder != 0)
1710 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1711 else
1712 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1713 radeon_crtc->rmx_type = RMX_FULL;
1714 src_v = crtc->mode.vdisplay;
1715 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1716 src_h = crtc->mode.hdisplay;
1717 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1718 }
1719 first = false;
1720 } else {
1721 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1722 /* WARNING: Right now this can't happen but
1723 * in the future we need to check that scaling
1724 * are consistent across different encoder
1725 * (ie all encoder can work with the same
1726 * scaling).
1727 */
1728 DRM_ERROR("Scaling not consistent across encoder.\n");
1729 return false;
1730 }
1731 }
1732 }
1733 if (radeon_crtc->rmx_type != RMX_OFF) {
1734 fixed20_12 a, b;
1735 a.full = dfixed_const(src_v);
1736 b.full = dfixed_const(dst_v);
1737 radeon_crtc->vsc.full = dfixed_div(a, b);
1738 a.full = dfixed_const(src_h);
1739 b.full = dfixed_const(dst_h);
1740 radeon_crtc->hsc.full = dfixed_div(a, b);
1741 } else {
1742 radeon_crtc->vsc.full = dfixed_const(1);
1743 radeon_crtc->hsc.full = dfixed_const(1);
1744 }
1745 return true;
1746 }
1747
1748 /*
1749 * Retrieve current video scanout position of crtc on a given gpu, and
1750 * an optional accurate timestamp of when query happened.
1751 *
1752 * \param dev Device to query.
1753 * \param crtc Crtc to query.
1754 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1755 * \param *vpos Location where vertical scanout position should be stored.
1756 * \param *hpos Location where horizontal scanout position should go.
1757 * \param *stime Target location for timestamp taken immediately before
1758 * scanout position query. Can be NULL to skip timestamp.
1759 * \param *etime Target location for timestamp taken immediately after
1760 * scanout position query. Can be NULL to skip timestamp.
1761 *
1762 * Returns vpos as a positive number while in active scanout area.
1763 * Returns vpos as a negative number inside vblank, counting the number
1764 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1765 * until start of active scanout / end of vblank."
1766 *
1767 * \return Flags, or'ed together as follows:
1768 *
1769 * DRM_SCANOUTPOS_VALID = Query successful.
1770 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1771 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1772 * this flag means that returned position may be offset by a constant but
1773 * unknown small number of scanlines wrt. real scanout position.
1774 *
1775 */
1776 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1777 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1778 {
1779 u32 stat_crtc = 0, vbl = 0, position = 0;
1780 int vbl_start, vbl_end, vtotal, ret = 0;
1781 bool in_vbl = true;
1782
1783 struct radeon_device *rdev = dev->dev_private;
1784
1785 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1786
1787 /* Get optional system timestamp before query. */
1788 if (stime)
1789 *stime = ktime_get();
1790
1791 if (ASIC_IS_DCE4(rdev)) {
1792 if (crtc == 0) {
1793 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1794 EVERGREEN_CRTC0_REGISTER_OFFSET);
1795 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1796 EVERGREEN_CRTC0_REGISTER_OFFSET);
1797 ret |= DRM_SCANOUTPOS_VALID;
1798 }
1799 if (crtc == 1) {
1800 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1801 EVERGREEN_CRTC1_REGISTER_OFFSET);
1802 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1803 EVERGREEN_CRTC1_REGISTER_OFFSET);
1804 ret |= DRM_SCANOUTPOS_VALID;
1805 }
1806 if (crtc == 2) {
1807 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1808 EVERGREEN_CRTC2_REGISTER_OFFSET);
1809 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1810 EVERGREEN_CRTC2_REGISTER_OFFSET);
1811 ret |= DRM_SCANOUTPOS_VALID;
1812 }
1813 if (crtc == 3) {
1814 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1815 EVERGREEN_CRTC3_REGISTER_OFFSET);
1816 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1817 EVERGREEN_CRTC3_REGISTER_OFFSET);
1818 ret |= DRM_SCANOUTPOS_VALID;
1819 }
1820 if (crtc == 4) {
1821 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1822 EVERGREEN_CRTC4_REGISTER_OFFSET);
1823 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1824 EVERGREEN_CRTC4_REGISTER_OFFSET);
1825 ret |= DRM_SCANOUTPOS_VALID;
1826 }
1827 if (crtc == 5) {
1828 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1829 EVERGREEN_CRTC5_REGISTER_OFFSET);
1830 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1831 EVERGREEN_CRTC5_REGISTER_OFFSET);
1832 ret |= DRM_SCANOUTPOS_VALID;
1833 }
1834 } else if (ASIC_IS_AVIVO(rdev)) {
1835 if (crtc == 0) {
1836 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1837 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1838 ret |= DRM_SCANOUTPOS_VALID;
1839 }
1840 if (crtc == 1) {
1841 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1842 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1843 ret |= DRM_SCANOUTPOS_VALID;
1844 }
1845 } else {
1846 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1847 if (crtc == 0) {
1848 /* Assume vbl_end == 0, get vbl_start from
1849 * upper 16 bits.
1850 */
1851 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1852 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1853 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1854 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1855 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1856 if (!(stat_crtc & 1))
1857 in_vbl = false;
1858
1859 ret |= DRM_SCANOUTPOS_VALID;
1860 }
1861 if (crtc == 1) {
1862 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1863 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1864 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1865 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1866 if (!(stat_crtc & 1))
1867 in_vbl = false;
1868
1869 ret |= DRM_SCANOUTPOS_VALID;
1870 }
1871 }
1872
1873 /* Get optional system timestamp after query. */
1874 if (etime)
1875 *etime = ktime_get();
1876
1877 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1878
1879 /* Decode into vertical and horizontal scanout position. */
1880 *vpos = position & 0x1fff;
1881 *hpos = (position >> 16) & 0x1fff;
1882
1883 /* Valid vblank area boundaries from gpu retrieved? */
1884 if (vbl > 0) {
1885 /* Yes: Decode. */
1886 ret |= DRM_SCANOUTPOS_ACCURATE;
1887 vbl_start = vbl & 0x1fff;
1888 vbl_end = (vbl >> 16) & 0x1fff;
1889 }
1890 else {
1891 /* No: Fake something reasonable which gives at least ok results. */
1892 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1893 vbl_end = 0;
1894 }
1895
1896 /* Test scanout position against vblank region. */
1897 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1898 in_vbl = false;
1899
1900 /* Check if inside vblank area and apply corrective offsets:
1901 * vpos will then be >=0 in video scanout area, but negative
1902 * within vblank area, counting down the number of lines until
1903 * start of scanout.
1904 */
1905
1906 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1907 if (in_vbl && (*vpos >= vbl_start)) {
1908 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1909 *vpos = *vpos - vtotal;
1910 }
1911
1912 /* Correct for shifted end of vbl at vbl_end. */
1913 *vpos = *vpos - vbl_end;
1914
1915 /* In vblank? */
1916 if (in_vbl)
1917 ret |= DRM_SCANOUTPOS_INVBL;
1918
1919 /* Is vpos outside nominal vblank area, but less than
1920 * 1/100 of a frame height away from start of vblank?
1921 * If so, assume this isn't a massively delayed vblank
1922 * interrupt, but a vblank interrupt that fired a few
1923 * microseconds before true start of vblank. Compensate
1924 * by adding a full frame duration to the final timestamp.
1925 * Happens, e.g., on ATI R500, R600.
1926 *
1927 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1928 */
1929 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1930 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1931 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1932
1933 if (vbl_start - *vpos < vtotal / 100) {
1934 *vpos -= vtotal;
1935
1936 /* Signal this correction as "applied". */
1937 ret |= 0x8;
1938 }
1939 }
1940
1941 return ret;
1942 }
Linux kernel - Deliverables
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