2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include <asm/div64.h>
33 #include "drm_crtc_helper.h"
36 static int radeon_ddc_dump(struct drm_connector
*connector
);
38 static void avivo_crtc_load_lut(struct drm_crtc
*crtc
)
40 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
41 struct drm_device
*dev
= crtc
->dev
;
42 struct radeon_device
*rdev
= dev
->dev_private
;
45 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
46 WREG32(AVIVO_DC_LUTA_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
56 WREG32(AVIVO_DC_LUT_RW_SELECT
, radeon_crtc
->crtc_id
);
57 WREG32(AVIVO_DC_LUT_RW_MODE
, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK
, 0x0000003f);
60 WREG8(AVIVO_DC_LUT_RW_INDEX
, 0);
61 for (i
= 0; i
< 256; i
++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR
,
63 (radeon_crtc
->lut_r
[i
] << 20) |
64 (radeon_crtc
->lut_g
[i
] << 10) |
65 (radeon_crtc
->lut_b
[i
] << 0));
68 WREG32(AVIVO_D1GRPH_LUT_SEL
+ radeon_crtc
->crtc_offset
, radeon_crtc
->crtc_id
);
71 static void dce4_crtc_load_lut(struct drm_crtc
*crtc
)
73 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
74 struct drm_device
*dev
= crtc
->dev
;
75 struct radeon_device
*rdev
= dev
->dev_private
;
78 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
79 WREG32(EVERGREEN_DC_LUT_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_RW_MODE
+ radeon_crtc
->crtc_offset
, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK
+ radeon_crtc
->crtc_offset
, 0x00000007);
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX
+ radeon_crtc
->crtc_offset
, 0);
93 for (i
= 0; i
< 256; i
++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR
+ radeon_crtc
->crtc_offset
,
95 (radeon_crtc
->lut_r
[i
] << 20) |
96 (radeon_crtc
->lut_g
[i
] << 10) |
97 (radeon_crtc
->lut_b
[i
] << 0));
101 static void dce5_crtc_load_lut(struct drm_crtc
*crtc
)
103 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
104 struct drm_device
*dev
= crtc
->dev
;
105 struct radeon_device
*rdev
= dev
->dev_private
;
108 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
110 WREG32(NI_INPUT_CSC_CONTROL
+ radeon_crtc
->crtc_offset
,
111 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS
) |
112 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS
)));
113 WREG32(NI_PRESCALE_GRPH_CONTROL
+ radeon_crtc
->crtc_offset
,
114 NI_GRPH_PRESCALE_BYPASS
);
115 WREG32(NI_PRESCALE_OVL_CONTROL
+ radeon_crtc
->crtc_offset
,
116 NI_OVL_PRESCALE_BYPASS
);
117 WREG32(NI_INPUT_GAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
118 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT
) |
119 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT
)));
121 WREG32(EVERGREEN_DC_LUT_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
131 WREG32(EVERGREEN_DC_LUT_RW_MODE
+ radeon_crtc
->crtc_offset
, 0);
132 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK
+ radeon_crtc
->crtc_offset
, 0x00000007);
134 WREG32(EVERGREEN_DC_LUT_RW_INDEX
+ radeon_crtc
->crtc_offset
, 0);
135 for (i
= 0; i
< 256; i
++) {
136 WREG32(EVERGREEN_DC_LUT_30_COLOR
+ radeon_crtc
->crtc_offset
,
137 (radeon_crtc
->lut_r
[i
] << 20) |
138 (radeon_crtc
->lut_g
[i
] << 10) |
139 (radeon_crtc
->lut_b
[i
] << 0));
142 WREG32(NI_DEGAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
143 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
144 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
145 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
146 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
)));
147 WREG32(NI_GAMUT_REMAP_CONTROL
+ radeon_crtc
->crtc_offset
,
148 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS
) |
149 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS
)));
150 WREG32(NI_REGAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
151 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS
) |
152 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS
)));
153 WREG32(NI_OUTPUT_CSC_CONTROL
+ radeon_crtc
->crtc_offset
,
154 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS
) |
155 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS
)));
156 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
157 WREG32(0x6940 + radeon_crtc
->crtc_offset
, 0);
161 static void legacy_crtc_load_lut(struct drm_crtc
*crtc
)
163 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
164 struct drm_device
*dev
= crtc
->dev
;
165 struct radeon_device
*rdev
= dev
->dev_private
;
169 dac2_cntl
= RREG32(RADEON_DAC_CNTL2
);
170 if (radeon_crtc
->crtc_id
== 0)
171 dac2_cntl
&= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL
;
173 dac2_cntl
|= RADEON_DAC2_PALETTE_ACC_CTL
;
174 WREG32(RADEON_DAC_CNTL2
, dac2_cntl
);
176 WREG8(RADEON_PALETTE_INDEX
, 0);
177 for (i
= 0; i
< 256; i
++) {
178 WREG32(RADEON_PALETTE_30_DATA
,
179 (radeon_crtc
->lut_r
[i
] << 20) |
180 (radeon_crtc
->lut_g
[i
] << 10) |
181 (radeon_crtc
->lut_b
[i
] << 0));
185 void radeon_crtc_load_lut(struct drm_crtc
*crtc
)
187 struct drm_device
*dev
= crtc
->dev
;
188 struct radeon_device
*rdev
= dev
->dev_private
;
193 if (ASIC_IS_DCE5(rdev
))
194 dce5_crtc_load_lut(crtc
);
195 else if (ASIC_IS_DCE4(rdev
))
196 dce4_crtc_load_lut(crtc
);
197 else if (ASIC_IS_AVIVO(rdev
))
198 avivo_crtc_load_lut(crtc
);
200 legacy_crtc_load_lut(crtc
);
203 /** Sets the color ramps on behalf of fbcon */
204 void radeon_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
207 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
209 radeon_crtc
->lut_r
[regno
] = red
>> 6;
210 radeon_crtc
->lut_g
[regno
] = green
>> 6;
211 radeon_crtc
->lut_b
[regno
] = blue
>> 6;
214 /** Gets the color ramps on behalf of fbcon */
215 void radeon_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
216 u16
*blue
, int regno
)
218 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
220 *red
= radeon_crtc
->lut_r
[regno
] << 6;
221 *green
= radeon_crtc
->lut_g
[regno
] << 6;
222 *blue
= radeon_crtc
->lut_b
[regno
] << 6;
225 static void radeon_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
226 u16
*blue
, uint32_t start
, uint32_t size
)
228 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
229 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
231 /* userspace palettes are always correct as is */
232 for (i
= start
; i
< end
; i
++) {
233 radeon_crtc
->lut_r
[i
] = red
[i
] >> 6;
234 radeon_crtc
->lut_g
[i
] = green
[i
] >> 6;
235 radeon_crtc
->lut_b
[i
] = blue
[i
] >> 6;
237 radeon_crtc_load_lut(crtc
);
240 static void radeon_crtc_destroy(struct drm_crtc
*crtc
)
242 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
244 drm_crtc_cleanup(crtc
);
249 * Handle unpin events outside the interrupt handler proper.
251 static void radeon_unpin_work_func(struct work_struct
*__work
)
253 struct radeon_unpin_work
*work
=
254 container_of(__work
, struct radeon_unpin_work
, work
);
257 /* unpin of the old buffer */
258 r
= radeon_bo_reserve(work
->old_rbo
, false);
259 if (likely(r
== 0)) {
260 r
= radeon_bo_unpin(work
->old_rbo
);
261 if (unlikely(r
!= 0)) {
262 DRM_ERROR("failed to unpin buffer after flip\n");
264 radeon_bo_unreserve(work
->old_rbo
);
266 DRM_ERROR("failed to reserve buffer after flip\n");
270 void radeon_crtc_handle_flip(struct radeon_device
*rdev
, int crtc_id
)
272 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc_id
];
273 struct radeon_unpin_work
*work
;
274 struct drm_pending_vblank_event
*e
;
280 spin_lock_irqsave(&rdev
->ddev
->event_lock
, flags
);
281 work
= radeon_crtc
->unpin_work
;
283 !radeon_fence_signaled(work
->fence
)) {
284 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
287 /* New pageflip, or just completion of a previous one? */
288 if (!radeon_crtc
->deferred_flip_completion
) {
289 /* do the flip (mmio) */
290 update_pending
= radeon_page_flip(rdev
, crtc_id
, work
->new_crtc_base
);
292 /* This is just a completion of a flip queued in crtc
293 * at last invocation. Make sure we go directly to
294 * completion routine.
297 radeon_crtc
->deferred_flip_completion
= 0;
300 /* Has the pageflip already completed in crtc, or is it certain
301 * to complete in this vblank?
303 if (update_pending
&&
304 (DRM_SCANOUTPOS_VALID
& radeon_get_crtc_scanoutpos(rdev
->ddev
, crtc_id
,
307 (vpos
< (99 * rdev
->mode_info
.crtcs
[crtc_id
]->base
.hwmode
.crtc_vdisplay
)/100)) {
308 /* crtc didn't flip in this target vblank interval,
309 * but flip is pending in crtc. It will complete it
310 * in next vblank interval, so complete the flip at
313 radeon_crtc
->deferred_flip_completion
= 1;
314 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
318 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
319 radeon_crtc
->unpin_work
= NULL
;
321 /* wakeup userspace */
324 e
->event
.sequence
= drm_vblank_count_and_time(rdev
->ddev
, crtc_id
, &now
);
325 e
->event
.tv_sec
= now
.tv_sec
;
326 e
->event
.tv_usec
= now
.tv_usec
;
327 list_add_tail(&e
->base
.link
, &e
->base
.file_priv
->event_list
);
328 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
330 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
332 drm_vblank_put(rdev
->ddev
, radeon_crtc
->crtc_id
);
333 radeon_fence_unref(&work
->fence
);
334 radeon_post_page_flip(work
->rdev
, work
->crtc_id
);
335 schedule_work(&work
->work
);
338 static int radeon_crtc_page_flip(struct drm_crtc
*crtc
,
339 struct drm_framebuffer
*fb
,
340 struct drm_pending_vblank_event
*event
)
342 struct drm_device
*dev
= crtc
->dev
;
343 struct radeon_device
*rdev
= dev
->dev_private
;
344 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
345 struct radeon_framebuffer
*old_radeon_fb
;
346 struct radeon_framebuffer
*new_radeon_fb
;
347 struct drm_gem_object
*obj
;
348 struct radeon_bo
*rbo
;
349 struct radeon_fence
*fence
;
350 struct radeon_unpin_work
*work
;
352 u32 tiling_flags
, pitch_pixels
;
356 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
360 r
= radeon_fence_create(rdev
, &fence
);
361 if (unlikely(r
!= 0)) {
363 DRM_ERROR("flip queue: failed to create fence.\n");
368 work
->crtc_id
= radeon_crtc
->crtc_id
;
369 work
->fence
= radeon_fence_ref(fence
);
370 old_radeon_fb
= to_radeon_framebuffer(crtc
->fb
);
371 new_radeon_fb
= to_radeon_framebuffer(fb
);
372 /* schedule unpin of the old buffer */
373 obj
= old_radeon_fb
->obj
;
374 rbo
= obj
->driver_private
;
376 INIT_WORK(&work
->work
, radeon_unpin_work_func
);
378 /* We borrow the event spin lock for protecting unpin_work */
379 spin_lock_irqsave(&dev
->event_lock
, flags
);
380 if (radeon_crtc
->unpin_work
) {
381 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
383 radeon_fence_unref(&fence
);
385 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
388 radeon_crtc
->unpin_work
= work
;
389 radeon_crtc
->deferred_flip_completion
= 0;
390 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
392 /* pin the new buffer */
393 obj
= new_radeon_fb
->obj
;
394 rbo
= obj
->driver_private
;
396 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
399 r
= radeon_bo_reserve(rbo
, false);
400 if (unlikely(r
!= 0)) {
401 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
404 r
= radeon_bo_pin(rbo
, RADEON_GEM_DOMAIN_VRAM
, &base
);
405 if (unlikely(r
!= 0)) {
406 radeon_bo_unreserve(rbo
);
408 DRM_ERROR("failed to pin new rbo buffer before flip\n");
411 radeon_bo_get_tiling_flags(rbo
, &tiling_flags
, NULL
);
412 radeon_bo_unreserve(rbo
);
414 if (!ASIC_IS_AVIVO(rdev
)) {
415 /* crtc offset is from display base addr not FB location */
416 base
-= radeon_crtc
->legacy_display_base_addr
;
417 pitch_pixels
= fb
->pitch
/ (fb
->bits_per_pixel
/ 8);
419 if (tiling_flags
& RADEON_TILING_MACRO
) {
420 if (ASIC_IS_R300(rdev
)) {
423 int byteshift
= fb
->bits_per_pixel
>> 4;
424 int tile_addr
= (((crtc
->y
>> 3) * pitch_pixels
+ crtc
->x
) >> (8 - byteshift
)) << 11;
425 base
+= tile_addr
+ ((crtc
->x
<< byteshift
) % 256) + ((crtc
->y
% 8) << 8);
428 int offset
= crtc
->y
* pitch_pixels
+ crtc
->x
;
429 switch (fb
->bits_per_pixel
) {
450 spin_lock_irqsave(&dev
->event_lock
, flags
);
451 work
->new_crtc_base
= base
;
452 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
457 r
= drm_vblank_get(dev
, radeon_crtc
->crtc_id
);
459 DRM_ERROR("failed to get vblank before flip\n");
463 /* 32 ought to cover us */
464 r
= radeon_ring_lock(rdev
, 32);
466 DRM_ERROR("failed to lock the ring before flip\n");
471 radeon_fence_emit(rdev
, fence
);
472 /* set the proper interrupt */
473 radeon_pre_page_flip(rdev
, radeon_crtc
->crtc_id
);
475 radeon_ring_unlock_commit(rdev
);
480 drm_vblank_put(dev
, radeon_crtc
->crtc_id
);
483 r
= radeon_bo_reserve(rbo
, false);
484 if (unlikely(r
!= 0)) {
485 DRM_ERROR("failed to reserve new rbo in error path\n");
488 r
= radeon_bo_unpin(rbo
);
489 if (unlikely(r
!= 0)) {
490 radeon_bo_unreserve(rbo
);
492 DRM_ERROR("failed to unpin new rbo in error path\n");
495 radeon_bo_unreserve(rbo
);
498 spin_lock_irqsave(&dev
->event_lock
, flags
);
499 radeon_crtc
->unpin_work
= NULL
;
500 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
501 radeon_fence_unref(&fence
);
507 static const struct drm_crtc_funcs radeon_crtc_funcs
= {
508 .cursor_set
= radeon_crtc_cursor_set
,
509 .cursor_move
= radeon_crtc_cursor_move
,
510 .gamma_set
= radeon_crtc_gamma_set
,
511 .set_config
= drm_crtc_helper_set_config
,
512 .destroy
= radeon_crtc_destroy
,
513 .page_flip
= radeon_crtc_page_flip
,
516 static void radeon_crtc_init(struct drm_device
*dev
, int index
)
518 struct radeon_device
*rdev
= dev
->dev_private
;
519 struct radeon_crtc
*radeon_crtc
;
522 radeon_crtc
= kzalloc(sizeof(struct radeon_crtc
) + (RADEONFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
523 if (radeon_crtc
== NULL
)
526 drm_crtc_init(dev
, &radeon_crtc
->base
, &radeon_crtc_funcs
);
528 drm_mode_crtc_set_gamma_size(&radeon_crtc
->base
, 256);
529 radeon_crtc
->crtc_id
= index
;
530 rdev
->mode_info
.crtcs
[index
] = radeon_crtc
;
533 radeon_crtc
->mode_set
.crtc
= &radeon_crtc
->base
;
534 radeon_crtc
->mode_set
.connectors
= (struct drm_connector
**)(radeon_crtc
+ 1);
535 radeon_crtc
->mode_set
.num_connectors
= 0;
538 for (i
= 0; i
< 256; i
++) {
539 radeon_crtc
->lut_r
[i
] = i
<< 2;
540 radeon_crtc
->lut_g
[i
] = i
<< 2;
541 radeon_crtc
->lut_b
[i
] = i
<< 2;
544 if (rdev
->is_atom_bios
&& (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
))
545 radeon_atombios_init_crtc(dev
, radeon_crtc
);
547 radeon_legacy_init_crtc(dev
, radeon_crtc
);
550 static const char *encoder_names
[36] = {
570 "INTERNAL_KLDSCP_TMDS1",
571 "INTERNAL_KLDSCP_DVO1",
572 "INTERNAL_KLDSCP_DAC1",
573 "INTERNAL_KLDSCP_DAC2",
582 "INTERNAL_KLDSCP_LVTMA",
589 static const char *connector_names
[15] = {
607 static const char *hpd_names
[6] = {
616 static void radeon_print_display_setup(struct drm_device
*dev
)
618 struct drm_connector
*connector
;
619 struct radeon_connector
*radeon_connector
;
620 struct drm_encoder
*encoder
;
621 struct radeon_encoder
*radeon_encoder
;
625 DRM_INFO("Radeon Display Connectors\n");
626 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
627 radeon_connector
= to_radeon_connector(connector
);
628 DRM_INFO("Connector %d:\n", i
);
629 DRM_INFO(" %s\n", connector_names
[connector
->connector_type
]);
630 if (radeon_connector
->hpd
.hpd
!= RADEON_HPD_NONE
)
631 DRM_INFO(" %s\n", hpd_names
[radeon_connector
->hpd
.hpd
]);
632 if (radeon_connector
->ddc_bus
) {
633 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
634 radeon_connector
->ddc_bus
->rec
.mask_clk_reg
,
635 radeon_connector
->ddc_bus
->rec
.mask_data_reg
,
636 radeon_connector
->ddc_bus
->rec
.a_clk_reg
,
637 radeon_connector
->ddc_bus
->rec
.a_data_reg
,
638 radeon_connector
->ddc_bus
->rec
.en_clk_reg
,
639 radeon_connector
->ddc_bus
->rec
.en_data_reg
,
640 radeon_connector
->ddc_bus
->rec
.y_clk_reg
,
641 radeon_connector
->ddc_bus
->rec
.y_data_reg
);
642 if (radeon_connector
->router
.ddc_valid
)
643 DRM_INFO(" DDC Router 0x%x/0x%x\n",
644 radeon_connector
->router
.ddc_mux_control_pin
,
645 radeon_connector
->router
.ddc_mux_state
);
646 if (radeon_connector
->router
.cd_valid
)
647 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
648 radeon_connector
->router
.cd_mux_control_pin
,
649 radeon_connector
->router
.cd_mux_state
);
651 if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
||
652 connector
->connector_type
== DRM_MODE_CONNECTOR_DVII
||
653 connector
->connector_type
== DRM_MODE_CONNECTOR_DVID
||
654 connector
->connector_type
== DRM_MODE_CONNECTOR_DVIA
||
655 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIA
||
656 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIB
)
657 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
659 DRM_INFO(" Encoders:\n");
660 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
661 radeon_encoder
= to_radeon_encoder(encoder
);
662 devices
= radeon_encoder
->devices
& radeon_connector
->devices
;
664 if (devices
& ATOM_DEVICE_CRT1_SUPPORT
)
665 DRM_INFO(" CRT1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
666 if (devices
& ATOM_DEVICE_CRT2_SUPPORT
)
667 DRM_INFO(" CRT2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
668 if (devices
& ATOM_DEVICE_LCD1_SUPPORT
)
669 DRM_INFO(" LCD1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
670 if (devices
& ATOM_DEVICE_DFP1_SUPPORT
)
671 DRM_INFO(" DFP1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
672 if (devices
& ATOM_DEVICE_DFP2_SUPPORT
)
673 DRM_INFO(" DFP2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
674 if (devices
& ATOM_DEVICE_DFP3_SUPPORT
)
675 DRM_INFO(" DFP3: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
676 if (devices
& ATOM_DEVICE_DFP4_SUPPORT
)
677 DRM_INFO(" DFP4: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
678 if (devices
& ATOM_DEVICE_DFP5_SUPPORT
)
679 DRM_INFO(" DFP5: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
680 if (devices
& ATOM_DEVICE_DFP6_SUPPORT
)
681 DRM_INFO(" DFP6: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
682 if (devices
& ATOM_DEVICE_TV1_SUPPORT
)
683 DRM_INFO(" TV1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
684 if (devices
& ATOM_DEVICE_CV_SUPPORT
)
685 DRM_INFO(" CV: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
692 static bool radeon_setup_enc_conn(struct drm_device
*dev
)
694 struct radeon_device
*rdev
= dev
->dev_private
;
695 struct drm_connector
*drm_connector
;
699 if (rdev
->is_atom_bios
) {
700 ret
= radeon_get_atom_connector_info_from_supported_devices_table(dev
);
702 ret
= radeon_get_atom_connector_info_from_object_table(dev
);
704 ret
= radeon_get_legacy_connector_info_from_bios(dev
);
706 ret
= radeon_get_legacy_connector_info_from_table(dev
);
709 if (!ASIC_IS_AVIVO(rdev
))
710 ret
= radeon_get_legacy_connector_info_from_table(dev
);
713 radeon_setup_encoder_clones(dev
);
714 radeon_print_display_setup(dev
);
715 list_for_each_entry(drm_connector
, &dev
->mode_config
.connector_list
, head
)
716 radeon_ddc_dump(drm_connector
);
722 int radeon_ddc_get_modes(struct radeon_connector
*radeon_connector
)
724 struct drm_device
*dev
= radeon_connector
->base
.dev
;
725 struct radeon_device
*rdev
= dev
->dev_private
;
728 /* on hw with routers, select right port */
729 if (radeon_connector
->router
.ddc_valid
)
730 radeon_router_select_ddc_port(radeon_connector
);
732 if ((radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_DisplayPort
) ||
733 (radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_eDP
)) {
734 struct radeon_connector_atom_dig
*dig
= radeon_connector
->con_priv
;
735 if ((dig
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
||
736 dig
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
) && dig
->dp_i2c_bus
)
737 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
, &dig
->dp_i2c_bus
->adapter
);
739 if (!radeon_connector
->ddc_bus
)
741 if (!radeon_connector
->edid
) {
742 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
, &radeon_connector
->ddc_bus
->adapter
);
745 if (!radeon_connector
->edid
) {
746 if (rdev
->is_atom_bios
) {
747 /* some laptops provide a hardcoded edid in rom for LCDs */
748 if (((radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_LVDS
) ||
749 (radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_eDP
)))
750 radeon_connector
->edid
= radeon_bios_get_hardcoded_edid(rdev
);
752 /* some servers provide a hardcoded edid in rom for KVMs */
753 radeon_connector
->edid
= radeon_bios_get_hardcoded_edid(rdev
);
755 if (radeon_connector
->edid
) {
756 drm_mode_connector_update_edid_property(&radeon_connector
->base
, radeon_connector
->edid
);
757 ret
= drm_add_edid_modes(&radeon_connector
->base
, radeon_connector
->edid
);
760 drm_mode_connector_update_edid_property(&radeon_connector
->base
, NULL
);
764 static int radeon_ddc_dump(struct drm_connector
*connector
)
767 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
770 /* on hw with routers, select right port */
771 if (radeon_connector
->router
.ddc_valid
)
772 radeon_router_select_ddc_port(radeon_connector
);
774 if (!radeon_connector
->ddc_bus
)
776 edid
= drm_get_edid(connector
, &radeon_connector
->ddc_bus
->adapter
);
783 static inline uint32_t radeon_div(uint64_t n
, uint32_t d
)
793 void radeon_compute_pll(struct radeon_pll
*pll
,
795 uint32_t *dot_clock_p
,
797 uint32_t *frac_fb_div_p
,
799 uint32_t *post_div_p
)
801 uint32_t min_ref_div
= pll
->min_ref_div
;
802 uint32_t max_ref_div
= pll
->max_ref_div
;
803 uint32_t min_post_div
= pll
->min_post_div
;
804 uint32_t max_post_div
= pll
->max_post_div
;
805 uint32_t min_fractional_feed_div
= 0;
806 uint32_t max_fractional_feed_div
= 0;
807 uint32_t best_vco
= pll
->best_vco
;
808 uint32_t best_post_div
= 1;
809 uint32_t best_ref_div
= 1;
810 uint32_t best_feedback_div
= 1;
811 uint32_t best_frac_feedback_div
= 0;
812 uint32_t best_freq
= -1;
813 uint32_t best_error
= 0xffffffff;
814 uint32_t best_vco_diff
= 1;
816 u32 pll_out_min
, pll_out_max
;
818 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq
, pll
->min_ref_div
, pll
->max_ref_div
);
821 if (pll
->flags
& RADEON_PLL_IS_LCD
) {
822 pll_out_min
= pll
->lcd_pll_out_min
;
823 pll_out_max
= pll
->lcd_pll_out_max
;
825 pll_out_min
= pll
->pll_out_min
;
826 pll_out_max
= pll
->pll_out_max
;
829 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
)
830 min_ref_div
= max_ref_div
= pll
->reference_div
;
832 while (min_ref_div
< max_ref_div
-1) {
833 uint32_t mid
= (min_ref_div
+ max_ref_div
) / 2;
834 uint32_t pll_in
= pll
->reference_freq
/ mid
;
835 if (pll_in
< pll
->pll_in_min
)
837 else if (pll_in
> pll
->pll_in_max
)
844 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
)
845 min_post_div
= max_post_div
= pll
->post_div
;
847 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
848 min_fractional_feed_div
= pll
->min_frac_feedback_div
;
849 max_fractional_feed_div
= pll
->max_frac_feedback_div
;
852 for (post_div
= max_post_div
; post_div
>= min_post_div
; --post_div
) {
855 if ((pll
->flags
& RADEON_PLL_NO_ODD_POST_DIV
) && (post_div
& 1))
858 /* legacy radeons only have a few post_divs */
859 if (pll
->flags
& RADEON_PLL_LEGACY
) {
860 if ((post_div
== 5) ||
871 for (ref_div
= min_ref_div
; ref_div
<= max_ref_div
; ++ref_div
) {
872 uint32_t feedback_div
, current_freq
= 0, error
, vco_diff
;
873 uint32_t pll_in
= pll
->reference_freq
/ ref_div
;
874 uint32_t min_feed_div
= pll
->min_feedback_div
;
875 uint32_t max_feed_div
= pll
->max_feedback_div
+ 1;
877 if (pll_in
< pll
->pll_in_min
|| pll_in
> pll
->pll_in_max
)
880 while (min_feed_div
< max_feed_div
) {
882 uint32_t min_frac_feed_div
= min_fractional_feed_div
;
883 uint32_t max_frac_feed_div
= max_fractional_feed_div
+ 1;
884 uint32_t frac_feedback_div
;
887 feedback_div
= (min_feed_div
+ max_feed_div
) / 2;
889 tmp
= (uint64_t)pll
->reference_freq
* feedback_div
;
890 vco
= radeon_div(tmp
, ref_div
);
892 if (vco
< pll_out_min
) {
893 min_feed_div
= feedback_div
+ 1;
895 } else if (vco
> pll_out_max
) {
896 max_feed_div
= feedback_div
;
900 while (min_frac_feed_div
< max_frac_feed_div
) {
901 frac_feedback_div
= (min_frac_feed_div
+ max_frac_feed_div
) / 2;
902 tmp
= (uint64_t)pll
->reference_freq
* 10000 * feedback_div
;
903 tmp
+= (uint64_t)pll
->reference_freq
* 1000 * frac_feedback_div
;
904 current_freq
= radeon_div(tmp
, ref_div
* post_div
);
906 if (pll
->flags
& RADEON_PLL_PREFER_CLOSEST_LOWER
) {
907 if (freq
< current_freq
)
910 error
= freq
- current_freq
;
912 error
= abs(current_freq
- freq
);
913 vco_diff
= abs(vco
- best_vco
);
915 if ((best_vco
== 0 && error
< best_error
) ||
917 ((best_error
> 100 && error
< best_error
- 100) ||
918 (abs(error
- best_error
) < 100 && vco_diff
< best_vco_diff
)))) {
919 best_post_div
= post_div
;
920 best_ref_div
= ref_div
;
921 best_feedback_div
= feedback_div
;
922 best_frac_feedback_div
= frac_feedback_div
;
923 best_freq
= current_freq
;
925 best_vco_diff
= vco_diff
;
926 } else if (current_freq
== freq
) {
927 if (best_freq
== -1) {
928 best_post_div
= post_div
;
929 best_ref_div
= ref_div
;
930 best_feedback_div
= feedback_div
;
931 best_frac_feedback_div
= frac_feedback_div
;
932 best_freq
= current_freq
;
934 best_vco_diff
= vco_diff
;
935 } else if (((pll
->flags
& RADEON_PLL_PREFER_LOW_REF_DIV
) && (ref_div
< best_ref_div
)) ||
936 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_REF_DIV
) && (ref_div
> best_ref_div
)) ||
937 ((pll
->flags
& RADEON_PLL_PREFER_LOW_FB_DIV
) && (feedback_div
< best_feedback_div
)) ||
938 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_FB_DIV
) && (feedback_div
> best_feedback_div
)) ||
939 ((pll
->flags
& RADEON_PLL_PREFER_LOW_POST_DIV
) && (post_div
< best_post_div
)) ||
940 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_POST_DIV
) && (post_div
> best_post_div
))) {
941 best_post_div
= post_div
;
942 best_ref_div
= ref_div
;
943 best_feedback_div
= feedback_div
;
944 best_frac_feedback_div
= frac_feedback_div
;
945 best_freq
= current_freq
;
947 best_vco_diff
= vco_diff
;
950 if (current_freq
< freq
)
951 min_frac_feed_div
= frac_feedback_div
+ 1;
953 max_frac_feed_div
= frac_feedback_div
;
955 if (current_freq
< freq
)
956 min_feed_div
= feedback_div
+ 1;
958 max_feed_div
= feedback_div
;
963 *dot_clock_p
= best_freq
/ 10000;
964 *fb_div_p
= best_feedback_div
;
965 *frac_fb_div_p
= best_frac_feedback_div
;
966 *ref_div_p
= best_ref_div
;
967 *post_div_p
= best_post_div
;
970 static void radeon_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
972 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
974 if (radeon_fb
->obj
) {
975 drm_gem_object_unreference_unlocked(radeon_fb
->obj
);
977 drm_framebuffer_cleanup(fb
);
981 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
982 struct drm_file
*file_priv
,
983 unsigned int *handle
)
985 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
987 return drm_gem_handle_create(file_priv
, radeon_fb
->obj
, handle
);
990 static const struct drm_framebuffer_funcs radeon_fb_funcs
= {
991 .destroy
= radeon_user_framebuffer_destroy
,
992 .create_handle
= radeon_user_framebuffer_create_handle
,
996 radeon_framebuffer_init(struct drm_device
*dev
,
997 struct radeon_framebuffer
*rfb
,
998 struct drm_mode_fb_cmd
*mode_cmd
,
999 struct drm_gem_object
*obj
)
1002 drm_framebuffer_init(dev
, &rfb
->base
, &radeon_fb_funcs
);
1003 drm_helper_mode_fill_fb_struct(&rfb
->base
, mode_cmd
);
1006 static struct drm_framebuffer
*
1007 radeon_user_framebuffer_create(struct drm_device
*dev
,
1008 struct drm_file
*file_priv
,
1009 struct drm_mode_fb_cmd
*mode_cmd
)
1011 struct drm_gem_object
*obj
;
1012 struct radeon_framebuffer
*radeon_fb
;
1014 obj
= drm_gem_object_lookup(dev
, file_priv
, mode_cmd
->handle
);
1016 dev_err(&dev
->pdev
->dev
, "No GEM object associated to handle 0x%08X, "
1017 "can't create framebuffer\n", mode_cmd
->handle
);
1018 return ERR_PTR(-ENOENT
);
1021 radeon_fb
= kzalloc(sizeof(*radeon_fb
), GFP_KERNEL
);
1022 if (radeon_fb
== NULL
)
1023 return ERR_PTR(-ENOMEM
);
1025 radeon_framebuffer_init(dev
, radeon_fb
, mode_cmd
, obj
);
1027 return &radeon_fb
->base
;
1030 static void radeon_output_poll_changed(struct drm_device
*dev
)
1032 struct radeon_device
*rdev
= dev
->dev_private
;
1033 radeon_fb_output_poll_changed(rdev
);
1036 static const struct drm_mode_config_funcs radeon_mode_funcs
= {
1037 .fb_create
= radeon_user_framebuffer_create
,
1038 .output_poll_changed
= radeon_output_poll_changed
1041 struct drm_prop_enum_list
{
1046 static struct drm_prop_enum_list radeon_tmds_pll_enum_list
[] =
1051 static struct drm_prop_enum_list radeon_tv_std_enum_list
[] =
1052 { { TV_STD_NTSC
, "ntsc" },
1053 { TV_STD_PAL
, "pal" },
1054 { TV_STD_PAL_M
, "pal-m" },
1055 { TV_STD_PAL_60
, "pal-60" },
1056 { TV_STD_NTSC_J
, "ntsc-j" },
1057 { TV_STD_SCART_PAL
, "scart-pal" },
1058 { TV_STD_PAL_CN
, "pal-cn" },
1059 { TV_STD_SECAM
, "secam" },
1062 static struct drm_prop_enum_list radeon_underscan_enum_list
[] =
1063 { { UNDERSCAN_OFF
, "off" },
1064 { UNDERSCAN_ON
, "on" },
1065 { UNDERSCAN_AUTO
, "auto" },
1068 static int radeon_modeset_create_props(struct radeon_device
*rdev
)
1072 if (rdev
->is_atom_bios
) {
1073 rdev
->mode_info
.coherent_mode_property
=
1074 drm_property_create(rdev
->ddev
,
1075 DRM_MODE_PROP_RANGE
,
1077 if (!rdev
->mode_info
.coherent_mode_property
)
1080 rdev
->mode_info
.coherent_mode_property
->values
[0] = 0;
1081 rdev
->mode_info
.coherent_mode_property
->values
[1] = 1;
1084 if (!ASIC_IS_AVIVO(rdev
)) {
1085 sz
= ARRAY_SIZE(radeon_tmds_pll_enum_list
);
1086 rdev
->mode_info
.tmds_pll_property
=
1087 drm_property_create(rdev
->ddev
,
1090 for (i
= 0; i
< sz
; i
++) {
1091 drm_property_add_enum(rdev
->mode_info
.tmds_pll_property
,
1093 radeon_tmds_pll_enum_list
[i
].type
,
1094 radeon_tmds_pll_enum_list
[i
].name
);
1098 rdev
->mode_info
.load_detect_property
=
1099 drm_property_create(rdev
->ddev
,
1100 DRM_MODE_PROP_RANGE
,
1101 "load detection", 2);
1102 if (!rdev
->mode_info
.load_detect_property
)
1104 rdev
->mode_info
.load_detect_property
->values
[0] = 0;
1105 rdev
->mode_info
.load_detect_property
->values
[1] = 1;
1107 drm_mode_create_scaling_mode_property(rdev
->ddev
);
1109 sz
= ARRAY_SIZE(radeon_tv_std_enum_list
);
1110 rdev
->mode_info
.tv_std_property
=
1111 drm_property_create(rdev
->ddev
,
1114 for (i
= 0; i
< sz
; i
++) {
1115 drm_property_add_enum(rdev
->mode_info
.tv_std_property
,
1117 radeon_tv_std_enum_list
[i
].type
,
1118 radeon_tv_std_enum_list
[i
].name
);
1121 sz
= ARRAY_SIZE(radeon_underscan_enum_list
);
1122 rdev
->mode_info
.underscan_property
=
1123 drm_property_create(rdev
->ddev
,
1126 for (i
= 0; i
< sz
; i
++) {
1127 drm_property_add_enum(rdev
->mode_info
.underscan_property
,
1129 radeon_underscan_enum_list
[i
].type
,
1130 radeon_underscan_enum_list
[i
].name
);
1133 rdev
->mode_info
.underscan_hborder_property
=
1134 drm_property_create(rdev
->ddev
,
1135 DRM_MODE_PROP_RANGE
,
1136 "underscan hborder", 2);
1137 if (!rdev
->mode_info
.underscan_hborder_property
)
1139 rdev
->mode_info
.underscan_hborder_property
->values
[0] = 0;
1140 rdev
->mode_info
.underscan_hborder_property
->values
[1] = 128;
1142 rdev
->mode_info
.underscan_vborder_property
=
1143 drm_property_create(rdev
->ddev
,
1144 DRM_MODE_PROP_RANGE
,
1145 "underscan vborder", 2);
1146 if (!rdev
->mode_info
.underscan_vborder_property
)
1148 rdev
->mode_info
.underscan_vborder_property
->values
[0] = 0;
1149 rdev
->mode_info
.underscan_vborder_property
->values
[1] = 128;
1154 void radeon_update_display_priority(struct radeon_device
*rdev
)
1156 /* adjustment options for the display watermarks */
1157 if ((radeon_disp_priority
== 0) || (radeon_disp_priority
> 2)) {
1158 /* set display priority to high for r3xx, rv515 chips
1159 * this avoids flickering due to underflow to the
1160 * display controllers during heavy acceleration.
1161 * Don't force high on rs4xx igp chips as it seems to
1162 * affect the sound card. See kernel bug 15982.
1164 if ((ASIC_IS_R300(rdev
) || (rdev
->family
== CHIP_RV515
)) &&
1165 !(rdev
->flags
& RADEON_IS_IGP
))
1166 rdev
->disp_priority
= 2;
1168 rdev
->disp_priority
= 0;
1170 rdev
->disp_priority
= radeon_disp_priority
;
1174 int radeon_modeset_init(struct radeon_device
*rdev
)
1179 drm_mode_config_init(rdev
->ddev
);
1180 rdev
->mode_info
.mode_config_initialized
= true;
1182 rdev
->ddev
->mode_config
.funcs
= (void *)&radeon_mode_funcs
;
1184 if (ASIC_IS_DCE5(rdev
)) {
1185 rdev
->ddev
->mode_config
.max_width
= 16384;
1186 rdev
->ddev
->mode_config
.max_height
= 16384;
1187 } else if (ASIC_IS_AVIVO(rdev
)) {
1188 rdev
->ddev
->mode_config
.max_width
= 8192;
1189 rdev
->ddev
->mode_config
.max_height
= 8192;
1191 rdev
->ddev
->mode_config
.max_width
= 4096;
1192 rdev
->ddev
->mode_config
.max_height
= 4096;
1195 rdev
->ddev
->mode_config
.fb_base
= rdev
->mc
.aper_base
;
1197 ret
= radeon_modeset_create_props(rdev
);
1202 /* init i2c buses */
1203 radeon_i2c_init(rdev
);
1205 /* check combios for a valid hardcoded EDID - Sun servers */
1206 if (!rdev
->is_atom_bios
) {
1207 /* check for hardcoded EDID in BIOS */
1208 radeon_combios_check_hardcoded_edid(rdev
);
1211 /* allocate crtcs */
1212 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1213 radeon_crtc_init(rdev
->ddev
, i
);
1216 /* okay we should have all the bios connectors */
1217 ret
= radeon_setup_enc_conn(rdev
->ddev
);
1221 /* initialize hpd */
1222 radeon_hpd_init(rdev
);
1224 /* Initialize power management */
1225 radeon_pm_init(rdev
);
1227 radeon_fbdev_init(rdev
);
1228 drm_kms_helper_poll_init(rdev
->ddev
);
1233 void radeon_modeset_fini(struct radeon_device
*rdev
)
1235 radeon_fbdev_fini(rdev
);
1236 kfree(rdev
->mode_info
.bios_hardcoded_edid
);
1237 radeon_pm_fini(rdev
);
1239 if (rdev
->mode_info
.mode_config_initialized
) {
1240 drm_kms_helper_poll_fini(rdev
->ddev
);
1241 radeon_hpd_fini(rdev
);
1242 drm_mode_config_cleanup(rdev
->ddev
);
1243 rdev
->mode_info
.mode_config_initialized
= false;
1245 /* free i2c buses */
1246 radeon_i2c_fini(rdev
);
1249 static bool is_hdtv_mode(struct drm_display_mode
*mode
)
1251 /* try and guess if this is a tv or a monitor */
1252 if ((mode
->vdisplay
== 480 && mode
->hdisplay
== 720) || /* 480p */
1253 (mode
->vdisplay
== 576) || /* 576p */
1254 (mode
->vdisplay
== 720) || /* 720p */
1255 (mode
->vdisplay
== 1080)) /* 1080p */
1261 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc
*crtc
,
1262 struct drm_display_mode
*mode
,
1263 struct drm_display_mode
*adjusted_mode
)
1265 struct drm_device
*dev
= crtc
->dev
;
1266 struct radeon_device
*rdev
= dev
->dev_private
;
1267 struct drm_encoder
*encoder
;
1268 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1269 struct radeon_encoder
*radeon_encoder
;
1270 struct drm_connector
*connector
;
1271 struct radeon_connector
*radeon_connector
;
1273 u32 src_v
= 1, dst_v
= 1;
1274 u32 src_h
= 1, dst_h
= 1;
1276 radeon_crtc
->h_border
= 0;
1277 radeon_crtc
->v_border
= 0;
1279 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1280 if (encoder
->crtc
!= crtc
)
1282 radeon_encoder
= to_radeon_encoder(encoder
);
1283 connector
= radeon_get_connector_for_encoder(encoder
);
1284 radeon_connector
= to_radeon_connector(connector
);
1288 if (radeon_encoder
->rmx_type
== RMX_OFF
)
1289 radeon_crtc
->rmx_type
= RMX_OFF
;
1290 else if (mode
->hdisplay
< radeon_encoder
->native_mode
.hdisplay
||
1291 mode
->vdisplay
< radeon_encoder
->native_mode
.vdisplay
)
1292 radeon_crtc
->rmx_type
= radeon_encoder
->rmx_type
;
1294 radeon_crtc
->rmx_type
= RMX_OFF
;
1295 /* copy native mode */
1296 memcpy(&radeon_crtc
->native_mode
,
1297 &radeon_encoder
->native_mode
,
1298 sizeof(struct drm_display_mode
));
1299 src_v
= crtc
->mode
.vdisplay
;
1300 dst_v
= radeon_crtc
->native_mode
.vdisplay
;
1301 src_h
= crtc
->mode
.hdisplay
;
1302 dst_h
= radeon_crtc
->native_mode
.hdisplay
;
1304 /* fix up for overscan on hdmi */
1305 if (ASIC_IS_AVIVO(rdev
) &&
1306 (!(mode
->flags
& DRM_MODE_FLAG_INTERLACE
)) &&
1307 ((radeon_encoder
->underscan_type
== UNDERSCAN_ON
) ||
1308 ((radeon_encoder
->underscan_type
== UNDERSCAN_AUTO
) &&
1309 drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
1310 is_hdtv_mode(mode
)))) {
1311 if (radeon_encoder
->underscan_hborder
!= 0)
1312 radeon_crtc
->h_border
= radeon_encoder
->underscan_hborder
;
1314 radeon_crtc
->h_border
= (mode
->hdisplay
>> 5) + 16;
1315 if (radeon_encoder
->underscan_vborder
!= 0)
1316 radeon_crtc
->v_border
= radeon_encoder
->underscan_vborder
;
1318 radeon_crtc
->v_border
= (mode
->vdisplay
>> 5) + 16;
1319 radeon_crtc
->rmx_type
= RMX_FULL
;
1320 src_v
= crtc
->mode
.vdisplay
;
1321 dst_v
= crtc
->mode
.vdisplay
- (radeon_crtc
->v_border
* 2);
1322 src_h
= crtc
->mode
.hdisplay
;
1323 dst_h
= crtc
->mode
.hdisplay
- (radeon_crtc
->h_border
* 2);
1327 if (radeon_crtc
->rmx_type
!= radeon_encoder
->rmx_type
) {
1328 /* WARNING: Right now this can't happen but
1329 * in the future we need to check that scaling
1330 * are consistent across different encoder
1331 * (ie all encoder can work with the same
1334 DRM_ERROR("Scaling not consistent across encoder.\n");
1339 if (radeon_crtc
->rmx_type
!= RMX_OFF
) {
1341 a
.full
= dfixed_const(src_v
);
1342 b
.full
= dfixed_const(dst_v
);
1343 radeon_crtc
->vsc
.full
= dfixed_div(a
, b
);
1344 a
.full
= dfixed_const(src_h
);
1345 b
.full
= dfixed_const(dst_h
);
1346 radeon_crtc
->hsc
.full
= dfixed_div(a
, b
);
1348 radeon_crtc
->vsc
.full
= dfixed_const(1);
1349 radeon_crtc
->hsc
.full
= dfixed_const(1);
1355 * Retrieve current video scanout position of crtc on a given gpu.
1357 * \param dev Device to query.
1358 * \param crtc Crtc to query.
1359 * \param *vpos Location where vertical scanout position should be stored.
1360 * \param *hpos Location where horizontal scanout position should go.
1362 * Returns vpos as a positive number while in active scanout area.
1363 * Returns vpos as a negative number inside vblank, counting the number
1364 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1365 * until start of active scanout / end of vblank."
1367 * \return Flags, or'ed together as follows:
1369 * DRM_SCANOUTPOS_VALID = Query successfull.
1370 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1371 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1372 * this flag means that returned position may be offset by a constant but
1373 * unknown small number of scanlines wrt. real scanout position.
1376 int radeon_get_crtc_scanoutpos(struct drm_device
*dev
, int crtc
, int *vpos
, int *hpos
)
1378 u32 stat_crtc
= 0, vbl
= 0, position
= 0;
1379 int vbl_start
, vbl_end
, vtotal
, ret
= 0;
1382 struct radeon_device
*rdev
= dev
->dev_private
;
1384 if (ASIC_IS_DCE4(rdev
)) {
1386 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1387 EVERGREEN_CRTC0_REGISTER_OFFSET
);
1388 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1389 EVERGREEN_CRTC0_REGISTER_OFFSET
);
1390 ret
|= DRM_SCANOUTPOS_VALID
;
1393 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1394 EVERGREEN_CRTC1_REGISTER_OFFSET
);
1395 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1396 EVERGREEN_CRTC1_REGISTER_OFFSET
);
1397 ret
|= DRM_SCANOUTPOS_VALID
;
1400 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1401 EVERGREEN_CRTC2_REGISTER_OFFSET
);
1402 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1403 EVERGREEN_CRTC2_REGISTER_OFFSET
);
1404 ret
|= DRM_SCANOUTPOS_VALID
;
1407 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1408 EVERGREEN_CRTC3_REGISTER_OFFSET
);
1409 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1410 EVERGREEN_CRTC3_REGISTER_OFFSET
);
1411 ret
|= DRM_SCANOUTPOS_VALID
;
1414 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1415 EVERGREEN_CRTC4_REGISTER_OFFSET
);
1416 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1417 EVERGREEN_CRTC4_REGISTER_OFFSET
);
1418 ret
|= DRM_SCANOUTPOS_VALID
;
1421 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1422 EVERGREEN_CRTC5_REGISTER_OFFSET
);
1423 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1424 EVERGREEN_CRTC5_REGISTER_OFFSET
);
1425 ret
|= DRM_SCANOUTPOS_VALID
;
1427 } else if (ASIC_IS_AVIVO(rdev
)) {
1429 vbl
= RREG32(AVIVO_D1CRTC_V_BLANK_START_END
);
1430 position
= RREG32(AVIVO_D1CRTC_STATUS_POSITION
);
1431 ret
|= DRM_SCANOUTPOS_VALID
;
1434 vbl
= RREG32(AVIVO_D2CRTC_V_BLANK_START_END
);
1435 position
= RREG32(AVIVO_D2CRTC_STATUS_POSITION
);
1436 ret
|= DRM_SCANOUTPOS_VALID
;
1439 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1441 /* Assume vbl_end == 0, get vbl_start from
1444 vbl
= (RREG32(RADEON_CRTC_V_TOTAL_DISP
) &
1445 RADEON_CRTC_V_DISP
) >> RADEON_CRTC_V_DISP_SHIFT
;
1446 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1447 position
= (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE
) >> 16) & RADEON_CRTC_V_TOTAL
;
1448 stat_crtc
= RREG32(RADEON_CRTC_STATUS
);
1449 if (!(stat_crtc
& 1))
1452 ret
|= DRM_SCANOUTPOS_VALID
;
1455 vbl
= (RREG32(RADEON_CRTC2_V_TOTAL_DISP
) &
1456 RADEON_CRTC_V_DISP
) >> RADEON_CRTC_V_DISP_SHIFT
;
1457 position
= (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE
) >> 16) & RADEON_CRTC_V_TOTAL
;
1458 stat_crtc
= RREG32(RADEON_CRTC2_STATUS
);
1459 if (!(stat_crtc
& 1))
1462 ret
|= DRM_SCANOUTPOS_VALID
;
1466 /* Decode into vertical and horizontal scanout position. */
1467 *vpos
= position
& 0x1fff;
1468 *hpos
= (position
>> 16) & 0x1fff;
1470 /* Valid vblank area boundaries from gpu retrieved? */
1473 ret
|= DRM_SCANOUTPOS_ACCURATE
;
1474 vbl_start
= vbl
& 0x1fff;
1475 vbl_end
= (vbl
>> 16) & 0x1fff;
1478 /* No: Fake something reasonable which gives at least ok results. */
1479 vbl_start
= rdev
->mode_info
.crtcs
[crtc
]->base
.hwmode
.crtc_vdisplay
;
1483 /* Test scanout position against vblank region. */
1484 if ((*vpos
< vbl_start
) && (*vpos
>= vbl_end
))
1487 /* Check if inside vblank area and apply corrective offsets:
1488 * vpos will then be >=0 in video scanout area, but negative
1489 * within vblank area, counting down the number of lines until
1493 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1494 if (in_vbl
&& (*vpos
>= vbl_start
)) {
1495 vtotal
= rdev
->mode_info
.crtcs
[crtc
]->base
.hwmode
.crtc_vtotal
;
1496 *vpos
= *vpos
- vtotal
;
1499 /* Correct for shifted end of vbl at vbl_end. */
1500 *vpos
= *vpos
- vbl_end
;
1504 ret
|= DRM_SCANOUTPOS_INVBL
;