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drm/radeon: remove drm_vblank_get|put from pflip handling
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_display.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include <linux/pm_runtime.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_edid.h>
36
37 #include <linux/gcd.h>
38
39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
40 {
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
44 int i;
45
46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
48
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
52
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
56
57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
58 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
60
61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
62 for (i = 0; i < 256; i++) {
63 WREG32(AVIVO_DC_LUT_30_COLOR,
64 (radeon_crtc->lut_r[i] << 20) |
65 (radeon_crtc->lut_g[i] << 10) |
66 (radeon_crtc->lut_b[i] << 0));
67 }
68
69 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
70 }
71
72 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
73 {
74 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
75 struct drm_device *dev = crtc->dev;
76 struct radeon_device *rdev = dev->dev_private;
77 int i;
78
79 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
80 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
81
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
85
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
89
90 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
91 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
92
93 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
94 for (i = 0; i < 256; i++) {
95 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
96 (radeon_crtc->lut_r[i] << 20) |
97 (radeon_crtc->lut_g[i] << 10) |
98 (radeon_crtc->lut_b[i] << 0));
99 }
100 }
101
102 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
103 {
104 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
105 struct drm_device *dev = crtc->dev;
106 struct radeon_device *rdev = dev->dev_private;
107 int i;
108
109 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
110
111 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
112 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
113 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
114 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
115 NI_GRPH_PRESCALE_BYPASS);
116 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
117 NI_OVL_PRESCALE_BYPASS);
118 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
119 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
120 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
121
122 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
123
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
127
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
131
132 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
133 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
134
135 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
136 for (i = 0; i < 256; i++) {
137 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
138 (radeon_crtc->lut_r[i] << 20) |
139 (radeon_crtc->lut_g[i] << 10) |
140 (radeon_crtc->lut_b[i] << 0));
141 }
142
143 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
144 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
145 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
148 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
149 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
150 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
151 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
152 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
153 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
154 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
155 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
156 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
157 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
158 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
159 if (ASIC_IS_DCE8(rdev)) {
160 /* XXX this only needs to be programmed once per crtc at startup,
161 * not sure where the best place for it is
162 */
163 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
164 CIK_CURSOR_ALPHA_BLND_ENA);
165 }
166 }
167
168 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
169 {
170 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
171 struct drm_device *dev = crtc->dev;
172 struct radeon_device *rdev = dev->dev_private;
173 int i;
174 uint32_t dac2_cntl;
175
176 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
177 if (radeon_crtc->crtc_id == 0)
178 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
179 else
180 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
181 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
182
183 WREG8(RADEON_PALETTE_INDEX, 0);
184 for (i = 0; i < 256; i++) {
185 WREG32(RADEON_PALETTE_30_DATA,
186 (radeon_crtc->lut_r[i] << 20) |
187 (radeon_crtc->lut_g[i] << 10) |
188 (radeon_crtc->lut_b[i] << 0));
189 }
190 }
191
192 void radeon_crtc_load_lut(struct drm_crtc *crtc)
193 {
194 struct drm_device *dev = crtc->dev;
195 struct radeon_device *rdev = dev->dev_private;
196
197 if (!crtc->enabled)
198 return;
199
200 if (ASIC_IS_DCE5(rdev))
201 dce5_crtc_load_lut(crtc);
202 else if (ASIC_IS_DCE4(rdev))
203 dce4_crtc_load_lut(crtc);
204 else if (ASIC_IS_AVIVO(rdev))
205 avivo_crtc_load_lut(crtc);
206 else
207 legacy_crtc_load_lut(crtc);
208 }
209
210 /** Sets the color ramps on behalf of fbcon */
211 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
212 u16 blue, int regno)
213 {
214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
215
216 radeon_crtc->lut_r[regno] = red >> 6;
217 radeon_crtc->lut_g[regno] = green >> 6;
218 radeon_crtc->lut_b[regno] = blue >> 6;
219 }
220
221 /** Gets the color ramps on behalf of fbcon */
222 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
223 u16 *blue, int regno)
224 {
225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
226
227 *red = radeon_crtc->lut_r[regno] << 6;
228 *green = radeon_crtc->lut_g[regno] << 6;
229 *blue = radeon_crtc->lut_b[regno] << 6;
230 }
231
232 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
233 u16 *blue, uint32_t start, uint32_t size)
234 {
235 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
236 int end = (start + size > 256) ? 256 : start + size, i;
237
238 /* userspace palettes are always correct as is */
239 for (i = start; i < end; i++) {
240 radeon_crtc->lut_r[i] = red[i] >> 6;
241 radeon_crtc->lut_g[i] = green[i] >> 6;
242 radeon_crtc->lut_b[i] = blue[i] >> 6;
243 }
244 radeon_crtc_load_lut(crtc);
245 }
246
247 static void radeon_crtc_destroy(struct drm_crtc *crtc)
248 {
249 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
250
251 drm_crtc_cleanup(crtc);
252 kfree(radeon_crtc);
253 }
254
255 /*
256 * Handle unpin events outside the interrupt handler proper.
257 */
258 static void radeon_unpin_work_func(struct work_struct *__work)
259 {
260 struct radeon_unpin_work *work =
261 container_of(__work, struct radeon_unpin_work, work);
262 int r;
263
264 /* unpin of the old buffer */
265 r = radeon_bo_reserve(work->old_rbo, false);
266 if (likely(r == 0)) {
267 r = radeon_bo_unpin(work->old_rbo);
268 if (unlikely(r != 0)) {
269 DRM_ERROR("failed to unpin buffer after flip\n");
270 }
271 radeon_bo_unreserve(work->old_rbo);
272 } else
273 DRM_ERROR("failed to reserve buffer after flip\n");
274
275 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
276 kfree(work);
277 }
278
279 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
280 {
281 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
282 struct radeon_unpin_work *work;
283 unsigned long flags;
284 u32 update_pending;
285 int vpos, hpos;
286
287 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
288 work = radeon_crtc->unpin_work;
289 if (work == NULL ||
290 (work->fence && !radeon_fence_signaled(work->fence))) {
291 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
292 return;
293 }
294 /* New pageflip, or just completion of a previous one? */
295 if (!radeon_crtc->deferred_flip_completion) {
296 /* do the flip (mmio) */
297 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
298 } else {
299 /* This is just a completion of a flip queued in crtc
300 * at last invocation. Make sure we go directly to
301 * completion routine.
302 */
303 update_pending = 0;
304 radeon_crtc->deferred_flip_completion = 0;
305 }
306
307 /* Has the pageflip already completed in crtc, or is it certain
308 * to complete in this vblank?
309 */
310 if (update_pending &&
311 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
312 &vpos, &hpos, NULL, NULL)) &&
313 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
314 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
315 /* crtc didn't flip in this target vblank interval,
316 * but flip is pending in crtc. Based on the current
317 * scanout position we know that the current frame is
318 * (nearly) complete and the flip will (likely)
319 * complete before the start of the next frame.
320 */
321 update_pending = 0;
322 }
323 if (update_pending) {
324 /* crtc didn't flip in this target vblank interval,
325 * but flip is pending in crtc. It will complete it
326 * in next vblank interval, so complete the flip at
327 * next vblank irq.
328 */
329 radeon_crtc->deferred_flip_completion = 1;
330 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
331 return;
332 }
333
334 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
335 radeon_crtc->unpin_work = NULL;
336
337 /* wakeup userspace */
338 if (work->event)
339 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
340
341 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
342
343 radeon_fence_unref(&work->fence);
344 radeon_irq_kms_pflip_irq_get(rdev, work->crtc_id);
345 schedule_work(&work->work);
346 }
347
348 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
349 struct drm_framebuffer *fb,
350 struct drm_pending_vblank_event *event,
351 uint32_t page_flip_flags)
352 {
353 struct drm_device *dev = crtc->dev;
354 struct radeon_device *rdev = dev->dev_private;
355 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
356 struct radeon_framebuffer *old_radeon_fb;
357 struct radeon_framebuffer *new_radeon_fb;
358 struct drm_gem_object *obj;
359 struct radeon_bo *rbo;
360 struct radeon_unpin_work *work;
361 unsigned long flags;
362 u32 tiling_flags, pitch_pixels;
363 u64 base;
364 int r;
365
366 work = kzalloc(sizeof *work, GFP_KERNEL);
367 if (work == NULL)
368 return -ENOMEM;
369
370 work->event = event;
371 work->rdev = rdev;
372 work->crtc_id = radeon_crtc->crtc_id;
373 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
374 new_radeon_fb = to_radeon_framebuffer(fb);
375 /* schedule unpin of the old buffer */
376 obj = old_radeon_fb->obj;
377 /* take a reference to the old object */
378 drm_gem_object_reference(obj);
379 rbo = gem_to_radeon_bo(obj);
380 work->old_rbo = rbo;
381 obj = new_radeon_fb->obj;
382 rbo = gem_to_radeon_bo(obj);
383
384 spin_lock(&rbo->tbo.bdev->fence_lock);
385 if (rbo->tbo.sync_obj)
386 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
387 spin_unlock(&rbo->tbo.bdev->fence_lock);
388
389 INIT_WORK(&work->work, radeon_unpin_work_func);
390
391 /* We borrow the event spin lock for protecting unpin_work */
392 spin_lock_irqsave(&dev->event_lock, flags);
393 if (radeon_crtc->unpin_work) {
394 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
395 r = -EBUSY;
396 goto unlock_free;
397 }
398 radeon_crtc->unpin_work = work;
399 radeon_crtc->deferred_flip_completion = 0;
400 spin_unlock_irqrestore(&dev->event_lock, flags);
401
402 /* pin the new buffer */
403 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
404 work->old_rbo, rbo);
405
406 r = radeon_bo_reserve(rbo, false);
407 if (unlikely(r != 0)) {
408 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
409 goto pflip_cleanup;
410 }
411 /* Only 27 bit offset for legacy CRTC */
412 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
413 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
414 if (unlikely(r != 0)) {
415 radeon_bo_unreserve(rbo);
416 r = -EINVAL;
417 DRM_ERROR("failed to pin new rbo buffer before flip\n");
418 goto pflip_cleanup;
419 }
420 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
421 radeon_bo_unreserve(rbo);
422
423 if (!ASIC_IS_AVIVO(rdev)) {
424 /* crtc offset is from display base addr not FB location */
425 base -= radeon_crtc->legacy_display_base_addr;
426 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
427
428 if (tiling_flags & RADEON_TILING_MACRO) {
429 if (ASIC_IS_R300(rdev)) {
430 base &= ~0x7ff;
431 } else {
432 int byteshift = fb->bits_per_pixel >> 4;
433 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
434 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
435 }
436 } else {
437 int offset = crtc->y * pitch_pixels + crtc->x;
438 switch (fb->bits_per_pixel) {
439 case 8:
440 default:
441 offset *= 1;
442 break;
443 case 15:
444 case 16:
445 offset *= 2;
446 break;
447 case 24:
448 offset *= 3;
449 break;
450 case 32:
451 offset *= 4;
452 break;
453 }
454 base += offset;
455 }
456 base &= ~7;
457 }
458
459 spin_lock_irqsave(&dev->event_lock, flags);
460 work->new_crtc_base = base;
461 spin_unlock_irqrestore(&dev->event_lock, flags);
462
463 /* update crtc fb */
464 crtc->primary->fb = fb;
465
466 /* set the proper interrupt */
467 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
468
469 return 0;
470
471 pflip_cleanup:
472 spin_lock_irqsave(&dev->event_lock, flags);
473 radeon_crtc->unpin_work = NULL;
474 unlock_free:
475 spin_unlock_irqrestore(&dev->event_lock, flags);
476 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
477 radeon_fence_unref(&work->fence);
478 kfree(work);
479
480 return r;
481 }
482
483 static int
484 radeon_crtc_set_config(struct drm_mode_set *set)
485 {
486 struct drm_device *dev;
487 struct radeon_device *rdev;
488 struct drm_crtc *crtc;
489 bool active = false;
490 int ret;
491
492 if (!set || !set->crtc)
493 return -EINVAL;
494
495 dev = set->crtc->dev;
496
497 ret = pm_runtime_get_sync(dev->dev);
498 if (ret < 0)
499 return ret;
500
501 ret = drm_crtc_helper_set_config(set);
502
503 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
504 if (crtc->enabled)
505 active = true;
506
507 pm_runtime_mark_last_busy(dev->dev);
508
509 rdev = dev->dev_private;
510 /* if we have active crtcs and we don't have a power ref,
511 take the current one */
512 if (active && !rdev->have_disp_power_ref) {
513 rdev->have_disp_power_ref = true;
514 return ret;
515 }
516 /* if we have no active crtcs, then drop the power ref
517 we got before */
518 if (!active && rdev->have_disp_power_ref) {
519 pm_runtime_put_autosuspend(dev->dev);
520 rdev->have_disp_power_ref = false;
521 }
522
523 /* drop the power reference we got coming in here */
524 pm_runtime_put_autosuspend(dev->dev);
525 return ret;
526 }
527 static const struct drm_crtc_funcs radeon_crtc_funcs = {
528 .cursor_set = radeon_crtc_cursor_set,
529 .cursor_move = radeon_crtc_cursor_move,
530 .gamma_set = radeon_crtc_gamma_set,
531 .set_config = radeon_crtc_set_config,
532 .destroy = radeon_crtc_destroy,
533 .page_flip = radeon_crtc_page_flip,
534 };
535
536 static void radeon_crtc_init(struct drm_device *dev, int index)
537 {
538 struct radeon_device *rdev = dev->dev_private;
539 struct radeon_crtc *radeon_crtc;
540 int i;
541
542 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
543 if (radeon_crtc == NULL)
544 return;
545
546 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
547
548 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
549 radeon_crtc->crtc_id = index;
550 rdev->mode_info.crtcs[index] = radeon_crtc;
551
552 if (rdev->family >= CHIP_BONAIRE) {
553 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
554 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
555 } else {
556 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
557 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
558 }
559 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
560 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
561
562 #if 0
563 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
564 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
565 radeon_crtc->mode_set.num_connectors = 0;
566 #endif
567
568 for (i = 0; i < 256; i++) {
569 radeon_crtc->lut_r[i] = i << 2;
570 radeon_crtc->lut_g[i] = i << 2;
571 radeon_crtc->lut_b[i] = i << 2;
572 }
573
574 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
575 radeon_atombios_init_crtc(dev, radeon_crtc);
576 else
577 radeon_legacy_init_crtc(dev, radeon_crtc);
578 }
579
580 static const char *encoder_names[38] = {
581 "NONE",
582 "INTERNAL_LVDS",
583 "INTERNAL_TMDS1",
584 "INTERNAL_TMDS2",
585 "INTERNAL_DAC1",
586 "INTERNAL_DAC2",
587 "INTERNAL_SDVOA",
588 "INTERNAL_SDVOB",
589 "SI170B",
590 "CH7303",
591 "CH7301",
592 "INTERNAL_DVO1",
593 "EXTERNAL_SDVOA",
594 "EXTERNAL_SDVOB",
595 "TITFP513",
596 "INTERNAL_LVTM1",
597 "VT1623",
598 "HDMI_SI1930",
599 "HDMI_INTERNAL",
600 "INTERNAL_KLDSCP_TMDS1",
601 "INTERNAL_KLDSCP_DVO1",
602 "INTERNAL_KLDSCP_DAC1",
603 "INTERNAL_KLDSCP_DAC2",
604 "SI178",
605 "MVPU_FPGA",
606 "INTERNAL_DDI",
607 "VT1625",
608 "HDMI_SI1932",
609 "DP_AN9801",
610 "DP_DP501",
611 "INTERNAL_UNIPHY",
612 "INTERNAL_KLDSCP_LVTMA",
613 "INTERNAL_UNIPHY1",
614 "INTERNAL_UNIPHY2",
615 "NUTMEG",
616 "TRAVIS",
617 "INTERNAL_VCE",
618 "INTERNAL_UNIPHY3",
619 };
620
621 static const char *hpd_names[6] = {
622 "HPD1",
623 "HPD2",
624 "HPD3",
625 "HPD4",
626 "HPD5",
627 "HPD6",
628 };
629
630 static void radeon_print_display_setup(struct drm_device *dev)
631 {
632 struct drm_connector *connector;
633 struct radeon_connector *radeon_connector;
634 struct drm_encoder *encoder;
635 struct radeon_encoder *radeon_encoder;
636 uint32_t devices;
637 int i = 0;
638
639 DRM_INFO("Radeon Display Connectors\n");
640 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
641 radeon_connector = to_radeon_connector(connector);
642 DRM_INFO("Connector %d:\n", i);
643 DRM_INFO(" %s\n", drm_get_connector_name(connector));
644 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
645 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
646 if (radeon_connector->ddc_bus) {
647 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
648 radeon_connector->ddc_bus->rec.mask_clk_reg,
649 radeon_connector->ddc_bus->rec.mask_data_reg,
650 radeon_connector->ddc_bus->rec.a_clk_reg,
651 radeon_connector->ddc_bus->rec.a_data_reg,
652 radeon_connector->ddc_bus->rec.en_clk_reg,
653 radeon_connector->ddc_bus->rec.en_data_reg,
654 radeon_connector->ddc_bus->rec.y_clk_reg,
655 radeon_connector->ddc_bus->rec.y_data_reg);
656 if (radeon_connector->router.ddc_valid)
657 DRM_INFO(" DDC Router 0x%x/0x%x\n",
658 radeon_connector->router.ddc_mux_control_pin,
659 radeon_connector->router.ddc_mux_state);
660 if (radeon_connector->router.cd_valid)
661 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
662 radeon_connector->router.cd_mux_control_pin,
663 radeon_connector->router.cd_mux_state);
664 } else {
665 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
666 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
667 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
668 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
669 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
670 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
671 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
672 }
673 DRM_INFO(" Encoders:\n");
674 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
675 radeon_encoder = to_radeon_encoder(encoder);
676 devices = radeon_encoder->devices & radeon_connector->devices;
677 if (devices) {
678 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
679 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
680 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
681 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
682 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
683 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
684 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
685 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
686 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
687 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
688 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
689 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
690 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
691 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
692 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
693 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
694 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
695 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
696 if (devices & ATOM_DEVICE_TV1_SUPPORT)
697 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
698 if (devices & ATOM_DEVICE_CV_SUPPORT)
699 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
700 }
701 }
702 i++;
703 }
704 }
705
706 static bool radeon_setup_enc_conn(struct drm_device *dev)
707 {
708 struct radeon_device *rdev = dev->dev_private;
709 bool ret = false;
710
711 if (rdev->bios) {
712 if (rdev->is_atom_bios) {
713 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
714 if (ret == false)
715 ret = radeon_get_atom_connector_info_from_object_table(dev);
716 } else {
717 ret = radeon_get_legacy_connector_info_from_bios(dev);
718 if (ret == false)
719 ret = radeon_get_legacy_connector_info_from_table(dev);
720 }
721 } else {
722 if (!ASIC_IS_AVIVO(rdev))
723 ret = radeon_get_legacy_connector_info_from_table(dev);
724 }
725 if (ret) {
726 radeon_setup_encoder_clones(dev);
727 radeon_print_display_setup(dev);
728 }
729
730 return ret;
731 }
732
733 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
734 {
735 struct drm_device *dev = radeon_connector->base.dev;
736 struct radeon_device *rdev = dev->dev_private;
737 int ret = 0;
738
739 /* on hw with routers, select right port */
740 if (radeon_connector->router.ddc_valid)
741 radeon_router_select_ddc_port(radeon_connector);
742
743 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
744 ENCODER_OBJECT_ID_NONE) {
745 if (radeon_connector->ddc_bus->has_aux)
746 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
747 &radeon_connector->ddc_bus->aux.ddc);
748 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
749 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
750 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
751
752 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
753 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
754 radeon_connector->ddc_bus->has_aux)
755 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
756 &radeon_connector->ddc_bus->aux.ddc);
757 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
758 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
759 &radeon_connector->ddc_bus->adapter);
760 } else {
761 if (radeon_connector->ddc_bus && !radeon_connector->edid)
762 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
763 &radeon_connector->ddc_bus->adapter);
764 }
765
766 if (!radeon_connector->edid) {
767 if (rdev->is_atom_bios) {
768 /* some laptops provide a hardcoded edid in rom for LCDs */
769 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
770 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
771 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
772 } else
773 /* some servers provide a hardcoded edid in rom for KVMs */
774 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
775 }
776 if (radeon_connector->edid) {
777 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
778 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
779 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
780 return ret;
781 }
782 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
783 return 0;
784 }
785
786 /* avivo */
787
788 /**
789 * avivo_reduce_ratio - fractional number reduction
790 *
791 * @nom: nominator
792 * @den: denominator
793 * @nom_min: minimum value for nominator
794 * @den_min: minimum value for denominator
795 *
796 * Find the greatest common divisor and apply it on both nominator and
797 * denominator, but make nominator and denominator are at least as large
798 * as their minimum values.
799 */
800 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
801 unsigned nom_min, unsigned den_min)
802 {
803 unsigned tmp;
804
805 /* reduce the numbers to a simpler ratio */
806 tmp = gcd(*nom, *den);
807 *nom /= tmp;
808 *den /= tmp;
809
810 /* make sure nominator is large enough */
811 if (*nom < nom_min) {
812 tmp = (nom_min + *nom - 1) / *nom;
813 *nom *= tmp;
814 *den *= tmp;
815 }
816
817 /* make sure the denominator is large enough */
818 if (*den < den_min) {
819 tmp = (den_min + *den - 1) / *den;
820 *nom *= tmp;
821 *den *= tmp;
822 }
823 }
824
825 /**
826 * avivo_get_fb_ref_div - feedback and ref divider calculation
827 *
828 * @nom: nominator
829 * @den: denominator
830 * @post_div: post divider
831 * @fb_div_max: feedback divider maximum
832 * @ref_div_max: reference divider maximum
833 * @fb_div: resulting feedback divider
834 * @ref_div: resulting reference divider
835 *
836 * Calculate feedback and reference divider for a given post divider. Makes
837 * sure we stay within the limits.
838 */
839 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
840 unsigned fb_div_max, unsigned ref_div_max,
841 unsigned *fb_div, unsigned *ref_div)
842 {
843 /* limit reference * post divider to a maximum */
844 ref_div_max = min(210 / post_div, ref_div_max);
845
846 /* get matching reference and feedback divider */
847 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
848 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
849
850 /* limit fb divider to its maximum */
851 if (*fb_div > fb_div_max) {
852 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
853 *fb_div = fb_div_max;
854 }
855 }
856
857 /**
858 * radeon_compute_pll_avivo - compute PLL paramaters
859 *
860 * @pll: information about the PLL
861 * @dot_clock_p: resulting pixel clock
862 * fb_div_p: resulting feedback divider
863 * frac_fb_div_p: fractional part of the feedback divider
864 * ref_div_p: resulting reference divider
865 * post_div_p: resulting reference divider
866 *
867 * Try to calculate the PLL parameters to generate the given frequency:
868 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
869 */
870 void radeon_compute_pll_avivo(struct radeon_pll *pll,
871 u32 freq,
872 u32 *dot_clock_p,
873 u32 *fb_div_p,
874 u32 *frac_fb_div_p,
875 u32 *ref_div_p,
876 u32 *post_div_p)
877 {
878 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
879 freq : freq / 10;
880
881 unsigned fb_div_min, fb_div_max, fb_div;
882 unsigned post_div_min, post_div_max, post_div;
883 unsigned ref_div_min, ref_div_max, ref_div;
884 unsigned post_div_best, diff_best;
885 unsigned nom, den;
886
887 /* determine allowed feedback divider range */
888 fb_div_min = pll->min_feedback_div;
889 fb_div_max = pll->max_feedback_div;
890
891 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
892 fb_div_min *= 10;
893 fb_div_max *= 10;
894 }
895
896 /* determine allowed ref divider range */
897 if (pll->flags & RADEON_PLL_USE_REF_DIV)
898 ref_div_min = pll->reference_div;
899 else
900 ref_div_min = pll->min_ref_div;
901
902 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
903 pll->flags & RADEON_PLL_USE_REF_DIV)
904 ref_div_max = pll->reference_div;
905 else
906 ref_div_max = pll->max_ref_div;
907
908 /* determine allowed post divider range */
909 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
910 post_div_min = pll->post_div;
911 post_div_max = pll->post_div;
912 } else {
913 unsigned vco_min, vco_max;
914
915 if (pll->flags & RADEON_PLL_IS_LCD) {
916 vco_min = pll->lcd_pll_out_min;
917 vco_max = pll->lcd_pll_out_max;
918 } else {
919 vco_min = pll->pll_out_min;
920 vco_max = pll->pll_out_max;
921 }
922
923 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
924 vco_min *= 10;
925 vco_max *= 10;
926 }
927
928 post_div_min = vco_min / target_clock;
929 if ((target_clock * post_div_min) < vco_min)
930 ++post_div_min;
931 if (post_div_min < pll->min_post_div)
932 post_div_min = pll->min_post_div;
933
934 post_div_max = vco_max / target_clock;
935 if ((target_clock * post_div_max) > vco_max)
936 --post_div_max;
937 if (post_div_max > pll->max_post_div)
938 post_div_max = pll->max_post_div;
939 }
940
941 /* represent the searched ratio as fractional number */
942 nom = target_clock;
943 den = pll->reference_freq;
944
945 /* reduce the numbers to a simpler ratio */
946 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
947
948 /* now search for a post divider */
949 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
950 post_div_best = post_div_min;
951 else
952 post_div_best = post_div_max;
953 diff_best = ~0;
954
955 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
956 unsigned diff;
957 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
958 ref_div_max, &fb_div, &ref_div);
959 diff = abs(target_clock - (pll->reference_freq * fb_div) /
960 (ref_div * post_div));
961
962 if (diff < diff_best || (diff == diff_best &&
963 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
964
965 post_div_best = post_div;
966 diff_best = diff;
967 }
968 }
969 post_div = post_div_best;
970
971 /* get the feedback and reference divider for the optimal value */
972 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
973 &fb_div, &ref_div);
974
975 /* reduce the numbers to a simpler ratio once more */
976 /* this also makes sure that the reference divider is large enough */
977 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
978
979 /* and finally save the result */
980 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
981 *fb_div_p = fb_div / 10;
982 *frac_fb_div_p = fb_div % 10;
983 } else {
984 *fb_div_p = fb_div;
985 *frac_fb_div_p = 0;
986 }
987
988 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
989 (pll->reference_freq * *frac_fb_div_p)) /
990 (ref_div * post_div * 10);
991 *ref_div_p = ref_div;
992 *post_div_p = post_div;
993
994 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
995 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
996 ref_div, post_div);
997 }
998
999 /* pre-avivo */
1000 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1001 {
1002 uint64_t mod;
1003
1004 n += d / 2;
1005
1006 mod = do_div(n, d);
1007 return n;
1008 }
1009
1010 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1011 uint64_t freq,
1012 uint32_t *dot_clock_p,
1013 uint32_t *fb_div_p,
1014 uint32_t *frac_fb_div_p,
1015 uint32_t *ref_div_p,
1016 uint32_t *post_div_p)
1017 {
1018 uint32_t min_ref_div = pll->min_ref_div;
1019 uint32_t max_ref_div = pll->max_ref_div;
1020 uint32_t min_post_div = pll->min_post_div;
1021 uint32_t max_post_div = pll->max_post_div;
1022 uint32_t min_fractional_feed_div = 0;
1023 uint32_t max_fractional_feed_div = 0;
1024 uint32_t best_vco = pll->best_vco;
1025 uint32_t best_post_div = 1;
1026 uint32_t best_ref_div = 1;
1027 uint32_t best_feedback_div = 1;
1028 uint32_t best_frac_feedback_div = 0;
1029 uint32_t best_freq = -1;
1030 uint32_t best_error = 0xffffffff;
1031 uint32_t best_vco_diff = 1;
1032 uint32_t post_div;
1033 u32 pll_out_min, pll_out_max;
1034
1035 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1036 freq = freq * 1000;
1037
1038 if (pll->flags & RADEON_PLL_IS_LCD) {
1039 pll_out_min = pll->lcd_pll_out_min;
1040 pll_out_max = pll->lcd_pll_out_max;
1041 } else {
1042 pll_out_min = pll->pll_out_min;
1043 pll_out_max = pll->pll_out_max;
1044 }
1045
1046 if (pll_out_min > 64800)
1047 pll_out_min = 64800;
1048
1049 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1050 min_ref_div = max_ref_div = pll->reference_div;
1051 else {
1052 while (min_ref_div < max_ref_div-1) {
1053 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1054 uint32_t pll_in = pll->reference_freq / mid;
1055 if (pll_in < pll->pll_in_min)
1056 max_ref_div = mid;
1057 else if (pll_in > pll->pll_in_max)
1058 min_ref_div = mid;
1059 else
1060 break;
1061 }
1062 }
1063
1064 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1065 min_post_div = max_post_div = pll->post_div;
1066
1067 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1068 min_fractional_feed_div = pll->min_frac_feedback_div;
1069 max_fractional_feed_div = pll->max_frac_feedback_div;
1070 }
1071
1072 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1073 uint32_t ref_div;
1074
1075 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1076 continue;
1077
1078 /* legacy radeons only have a few post_divs */
1079 if (pll->flags & RADEON_PLL_LEGACY) {
1080 if ((post_div == 5) ||
1081 (post_div == 7) ||
1082 (post_div == 9) ||
1083 (post_div == 10) ||
1084 (post_div == 11) ||
1085 (post_div == 13) ||
1086 (post_div == 14) ||
1087 (post_div == 15))
1088 continue;
1089 }
1090
1091 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1092 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1093 uint32_t pll_in = pll->reference_freq / ref_div;
1094 uint32_t min_feed_div = pll->min_feedback_div;
1095 uint32_t max_feed_div = pll->max_feedback_div + 1;
1096
1097 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1098 continue;
1099
1100 while (min_feed_div < max_feed_div) {
1101 uint32_t vco;
1102 uint32_t min_frac_feed_div = min_fractional_feed_div;
1103 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1104 uint32_t frac_feedback_div;
1105 uint64_t tmp;
1106
1107 feedback_div = (min_feed_div + max_feed_div) / 2;
1108
1109 tmp = (uint64_t)pll->reference_freq * feedback_div;
1110 vco = radeon_div(tmp, ref_div);
1111
1112 if (vco < pll_out_min) {
1113 min_feed_div = feedback_div + 1;
1114 continue;
1115 } else if (vco > pll_out_max) {
1116 max_feed_div = feedback_div;
1117 continue;
1118 }
1119
1120 while (min_frac_feed_div < max_frac_feed_div) {
1121 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1122 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1123 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1124 current_freq = radeon_div(tmp, ref_div * post_div);
1125
1126 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1127 if (freq < current_freq)
1128 error = 0xffffffff;
1129 else
1130 error = freq - current_freq;
1131 } else
1132 error = abs(current_freq - freq);
1133 vco_diff = abs(vco - best_vco);
1134
1135 if ((best_vco == 0 && error < best_error) ||
1136 (best_vco != 0 &&
1137 ((best_error > 100 && error < best_error - 100) ||
1138 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1139 best_post_div = post_div;
1140 best_ref_div = ref_div;
1141 best_feedback_div = feedback_div;
1142 best_frac_feedback_div = frac_feedback_div;
1143 best_freq = current_freq;
1144 best_error = error;
1145 best_vco_diff = vco_diff;
1146 } else if (current_freq == freq) {
1147 if (best_freq == -1) {
1148 best_post_div = post_div;
1149 best_ref_div = ref_div;
1150 best_feedback_div = feedback_div;
1151 best_frac_feedback_div = frac_feedback_div;
1152 best_freq = current_freq;
1153 best_error = error;
1154 best_vco_diff = vco_diff;
1155 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1156 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1157 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1158 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1159 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1160 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1161 best_post_div = post_div;
1162 best_ref_div = ref_div;
1163 best_feedback_div = feedback_div;
1164 best_frac_feedback_div = frac_feedback_div;
1165 best_freq = current_freq;
1166 best_error = error;
1167 best_vco_diff = vco_diff;
1168 }
1169 }
1170 if (current_freq < freq)
1171 min_frac_feed_div = frac_feedback_div + 1;
1172 else
1173 max_frac_feed_div = frac_feedback_div;
1174 }
1175 if (current_freq < freq)
1176 min_feed_div = feedback_div + 1;
1177 else
1178 max_feed_div = feedback_div;
1179 }
1180 }
1181 }
1182
1183 *dot_clock_p = best_freq / 10000;
1184 *fb_div_p = best_feedback_div;
1185 *frac_fb_div_p = best_frac_feedback_div;
1186 *ref_div_p = best_ref_div;
1187 *post_div_p = best_post_div;
1188 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1189 (long long)freq,
1190 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1191 best_ref_div, best_post_div);
1192
1193 }
1194
1195 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1196 {
1197 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1198
1199 if (radeon_fb->obj) {
1200 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1201 }
1202 drm_framebuffer_cleanup(fb);
1203 kfree(radeon_fb);
1204 }
1205
1206 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1207 struct drm_file *file_priv,
1208 unsigned int *handle)
1209 {
1210 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1211
1212 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1213 }
1214
1215 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1216 .destroy = radeon_user_framebuffer_destroy,
1217 .create_handle = radeon_user_framebuffer_create_handle,
1218 };
1219
1220 int
1221 radeon_framebuffer_init(struct drm_device *dev,
1222 struct radeon_framebuffer *rfb,
1223 struct drm_mode_fb_cmd2 *mode_cmd,
1224 struct drm_gem_object *obj)
1225 {
1226 int ret;
1227 rfb->obj = obj;
1228 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1229 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1230 if (ret) {
1231 rfb->obj = NULL;
1232 return ret;
1233 }
1234 return 0;
1235 }
1236
1237 static struct drm_framebuffer *
1238 radeon_user_framebuffer_create(struct drm_device *dev,
1239 struct drm_file *file_priv,
1240 struct drm_mode_fb_cmd2 *mode_cmd)
1241 {
1242 struct drm_gem_object *obj;
1243 struct radeon_framebuffer *radeon_fb;
1244 int ret;
1245
1246 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1247 if (obj == NULL) {
1248 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1249 "can't create framebuffer\n", mode_cmd->handles[0]);
1250 return ERR_PTR(-ENOENT);
1251 }
1252
1253 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1254 if (radeon_fb == NULL) {
1255 drm_gem_object_unreference_unlocked(obj);
1256 return ERR_PTR(-ENOMEM);
1257 }
1258
1259 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1260 if (ret) {
1261 kfree(radeon_fb);
1262 drm_gem_object_unreference_unlocked(obj);
1263 return ERR_PTR(ret);
1264 }
1265
1266 return &radeon_fb->base;
1267 }
1268
1269 static void radeon_output_poll_changed(struct drm_device *dev)
1270 {
1271 struct radeon_device *rdev = dev->dev_private;
1272 radeon_fb_output_poll_changed(rdev);
1273 }
1274
1275 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1276 .fb_create = radeon_user_framebuffer_create,
1277 .output_poll_changed = radeon_output_poll_changed
1278 };
1279
1280 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1281 { { 0, "driver" },
1282 { 1, "bios" },
1283 };
1284
1285 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1286 { { TV_STD_NTSC, "ntsc" },
1287 { TV_STD_PAL, "pal" },
1288 { TV_STD_PAL_M, "pal-m" },
1289 { TV_STD_PAL_60, "pal-60" },
1290 { TV_STD_NTSC_J, "ntsc-j" },
1291 { TV_STD_SCART_PAL, "scart-pal" },
1292 { TV_STD_PAL_CN, "pal-cn" },
1293 { TV_STD_SECAM, "secam" },
1294 };
1295
1296 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1297 { { UNDERSCAN_OFF, "off" },
1298 { UNDERSCAN_ON, "on" },
1299 { UNDERSCAN_AUTO, "auto" },
1300 };
1301
1302 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1303 { { RADEON_AUDIO_DISABLE, "off" },
1304 { RADEON_AUDIO_ENABLE, "on" },
1305 { RADEON_AUDIO_AUTO, "auto" },
1306 };
1307
1308 /* XXX support different dither options? spatial, temporal, both, etc. */
1309 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1310 { { RADEON_FMT_DITHER_DISABLE, "off" },
1311 { RADEON_FMT_DITHER_ENABLE, "on" },
1312 };
1313
1314 static int radeon_modeset_create_props(struct radeon_device *rdev)
1315 {
1316 int sz;
1317
1318 if (rdev->is_atom_bios) {
1319 rdev->mode_info.coherent_mode_property =
1320 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1321 if (!rdev->mode_info.coherent_mode_property)
1322 return -ENOMEM;
1323 }
1324
1325 if (!ASIC_IS_AVIVO(rdev)) {
1326 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1327 rdev->mode_info.tmds_pll_property =
1328 drm_property_create_enum(rdev->ddev, 0,
1329 "tmds_pll",
1330 radeon_tmds_pll_enum_list, sz);
1331 }
1332
1333 rdev->mode_info.load_detect_property =
1334 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1335 if (!rdev->mode_info.load_detect_property)
1336 return -ENOMEM;
1337
1338 drm_mode_create_scaling_mode_property(rdev->ddev);
1339
1340 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1341 rdev->mode_info.tv_std_property =
1342 drm_property_create_enum(rdev->ddev, 0,
1343 "tv standard",
1344 radeon_tv_std_enum_list, sz);
1345
1346 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1347 rdev->mode_info.underscan_property =
1348 drm_property_create_enum(rdev->ddev, 0,
1349 "underscan",
1350 radeon_underscan_enum_list, sz);
1351
1352 rdev->mode_info.underscan_hborder_property =
1353 drm_property_create_range(rdev->ddev, 0,
1354 "underscan hborder", 0, 128);
1355 if (!rdev->mode_info.underscan_hborder_property)
1356 return -ENOMEM;
1357
1358 rdev->mode_info.underscan_vborder_property =
1359 drm_property_create_range(rdev->ddev, 0,
1360 "underscan vborder", 0, 128);
1361 if (!rdev->mode_info.underscan_vborder_property)
1362 return -ENOMEM;
1363
1364 sz = ARRAY_SIZE(radeon_audio_enum_list);
1365 rdev->mode_info.audio_property =
1366 drm_property_create_enum(rdev->ddev, 0,
1367 "audio",
1368 radeon_audio_enum_list, sz);
1369
1370 sz = ARRAY_SIZE(radeon_dither_enum_list);
1371 rdev->mode_info.dither_property =
1372 drm_property_create_enum(rdev->ddev, 0,
1373 "dither",
1374 radeon_dither_enum_list, sz);
1375
1376 return 0;
1377 }
1378
1379 void radeon_update_display_priority(struct radeon_device *rdev)
1380 {
1381 /* adjustment options for the display watermarks */
1382 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1383 /* set display priority to high for r3xx, rv515 chips
1384 * this avoids flickering due to underflow to the
1385 * display controllers during heavy acceleration.
1386 * Don't force high on rs4xx igp chips as it seems to
1387 * affect the sound card. See kernel bug 15982.
1388 */
1389 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1390 !(rdev->flags & RADEON_IS_IGP))
1391 rdev->disp_priority = 2;
1392 else
1393 rdev->disp_priority = 0;
1394 } else
1395 rdev->disp_priority = radeon_disp_priority;
1396
1397 }
1398
1399 /*
1400 * Allocate hdmi structs and determine register offsets
1401 */
1402 static void radeon_afmt_init(struct radeon_device *rdev)
1403 {
1404 int i;
1405
1406 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1407 rdev->mode_info.afmt[i] = NULL;
1408
1409 if (ASIC_IS_NODCE(rdev)) {
1410 /* nothing to do */
1411 } else if (ASIC_IS_DCE4(rdev)) {
1412 static uint32_t eg_offsets[] = {
1413 EVERGREEN_CRTC0_REGISTER_OFFSET,
1414 EVERGREEN_CRTC1_REGISTER_OFFSET,
1415 EVERGREEN_CRTC2_REGISTER_OFFSET,
1416 EVERGREEN_CRTC3_REGISTER_OFFSET,
1417 EVERGREEN_CRTC4_REGISTER_OFFSET,
1418 EVERGREEN_CRTC5_REGISTER_OFFSET,
1419 0x13830 - 0x7030,
1420 };
1421 int num_afmt;
1422
1423 /* DCE8 has 7 audio blocks tied to DIG encoders */
1424 /* DCE6 has 6 audio blocks tied to DIG encoders */
1425 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1426 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1427 if (ASIC_IS_DCE8(rdev))
1428 num_afmt = 7;
1429 else if (ASIC_IS_DCE6(rdev))
1430 num_afmt = 6;
1431 else if (ASIC_IS_DCE5(rdev))
1432 num_afmt = 6;
1433 else if (ASIC_IS_DCE41(rdev))
1434 num_afmt = 2;
1435 else /* DCE4 */
1436 num_afmt = 6;
1437
1438 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1439 for (i = 0; i < num_afmt; i++) {
1440 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1441 if (rdev->mode_info.afmt[i]) {
1442 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1443 rdev->mode_info.afmt[i]->id = i;
1444 }
1445 }
1446 } else if (ASIC_IS_DCE3(rdev)) {
1447 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1448 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1449 if (rdev->mode_info.afmt[0]) {
1450 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1451 rdev->mode_info.afmt[0]->id = 0;
1452 }
1453 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1454 if (rdev->mode_info.afmt[1]) {
1455 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1456 rdev->mode_info.afmt[1]->id = 1;
1457 }
1458 } else if (ASIC_IS_DCE2(rdev)) {
1459 /* DCE2 has at least 1 routable audio block */
1460 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1461 if (rdev->mode_info.afmt[0]) {
1462 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1463 rdev->mode_info.afmt[0]->id = 0;
1464 }
1465 /* r6xx has 2 routable audio blocks */
1466 if (rdev->family >= CHIP_R600) {
1467 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1468 if (rdev->mode_info.afmt[1]) {
1469 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1470 rdev->mode_info.afmt[1]->id = 1;
1471 }
1472 }
1473 }
1474 }
1475
1476 static void radeon_afmt_fini(struct radeon_device *rdev)
1477 {
1478 int i;
1479
1480 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1481 kfree(rdev->mode_info.afmt[i]);
1482 rdev->mode_info.afmt[i] = NULL;
1483 }
1484 }
1485
1486 int radeon_modeset_init(struct radeon_device *rdev)
1487 {
1488 int i;
1489 int ret;
1490
1491 drm_mode_config_init(rdev->ddev);
1492 rdev->mode_info.mode_config_initialized = true;
1493
1494 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1495
1496 if (ASIC_IS_DCE5(rdev)) {
1497 rdev->ddev->mode_config.max_width = 16384;
1498 rdev->ddev->mode_config.max_height = 16384;
1499 } else if (ASIC_IS_AVIVO(rdev)) {
1500 rdev->ddev->mode_config.max_width = 8192;
1501 rdev->ddev->mode_config.max_height = 8192;
1502 } else {
1503 rdev->ddev->mode_config.max_width = 4096;
1504 rdev->ddev->mode_config.max_height = 4096;
1505 }
1506
1507 rdev->ddev->mode_config.preferred_depth = 24;
1508 rdev->ddev->mode_config.prefer_shadow = 1;
1509
1510 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1511
1512 ret = radeon_modeset_create_props(rdev);
1513 if (ret) {
1514 return ret;
1515 }
1516
1517 /* init i2c buses */
1518 radeon_i2c_init(rdev);
1519
1520 /* check combios for a valid hardcoded EDID - Sun servers */
1521 if (!rdev->is_atom_bios) {
1522 /* check for hardcoded EDID in BIOS */
1523 radeon_combios_check_hardcoded_edid(rdev);
1524 }
1525
1526 /* allocate crtcs */
1527 for (i = 0; i < rdev->num_crtc; i++) {
1528 radeon_crtc_init(rdev->ddev, i);
1529 }
1530
1531 /* okay we should have all the bios connectors */
1532 ret = radeon_setup_enc_conn(rdev->ddev);
1533 if (!ret) {
1534 return ret;
1535 }
1536
1537 /* init dig PHYs, disp eng pll */
1538 if (rdev->is_atom_bios) {
1539 radeon_atom_encoder_init(rdev);
1540 radeon_atom_disp_eng_pll_init(rdev);
1541 }
1542
1543 /* initialize hpd */
1544 radeon_hpd_init(rdev);
1545
1546 /* setup afmt */
1547 radeon_afmt_init(rdev);
1548
1549 radeon_fbdev_init(rdev);
1550 drm_kms_helper_poll_init(rdev->ddev);
1551
1552 if (rdev->pm.dpm_enabled) {
1553 /* do dpm late init */
1554 ret = radeon_pm_late_init(rdev);
1555 if (ret) {
1556 rdev->pm.dpm_enabled = false;
1557 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1558 }
1559 /* set the dpm state for PX since there won't be
1560 * a modeset to call this.
1561 */
1562 radeon_pm_compute_clocks(rdev);
1563 }
1564
1565 return 0;
1566 }
1567
1568 void radeon_modeset_fini(struct radeon_device *rdev)
1569 {
1570 radeon_fbdev_fini(rdev);
1571 kfree(rdev->mode_info.bios_hardcoded_edid);
1572
1573 if (rdev->mode_info.mode_config_initialized) {
1574 radeon_afmt_fini(rdev);
1575 drm_kms_helper_poll_fini(rdev->ddev);
1576 radeon_hpd_fini(rdev);
1577 drm_mode_config_cleanup(rdev->ddev);
1578 rdev->mode_info.mode_config_initialized = false;
1579 }
1580 /* free i2c buses */
1581 radeon_i2c_fini(rdev);
1582 }
1583
1584 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1585 {
1586 /* try and guess if this is a tv or a monitor */
1587 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1588 (mode->vdisplay == 576) || /* 576p */
1589 (mode->vdisplay == 720) || /* 720p */
1590 (mode->vdisplay == 1080)) /* 1080p */
1591 return true;
1592 else
1593 return false;
1594 }
1595
1596 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1597 const struct drm_display_mode *mode,
1598 struct drm_display_mode *adjusted_mode)
1599 {
1600 struct drm_device *dev = crtc->dev;
1601 struct radeon_device *rdev = dev->dev_private;
1602 struct drm_encoder *encoder;
1603 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1604 struct radeon_encoder *radeon_encoder;
1605 struct drm_connector *connector;
1606 struct radeon_connector *radeon_connector;
1607 bool first = true;
1608 u32 src_v = 1, dst_v = 1;
1609 u32 src_h = 1, dst_h = 1;
1610
1611 radeon_crtc->h_border = 0;
1612 radeon_crtc->v_border = 0;
1613
1614 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1615 if (encoder->crtc != crtc)
1616 continue;
1617 radeon_encoder = to_radeon_encoder(encoder);
1618 connector = radeon_get_connector_for_encoder(encoder);
1619 radeon_connector = to_radeon_connector(connector);
1620
1621 if (first) {
1622 /* set scaling */
1623 if (radeon_encoder->rmx_type == RMX_OFF)
1624 radeon_crtc->rmx_type = RMX_OFF;
1625 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1626 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1627 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1628 else
1629 radeon_crtc->rmx_type = RMX_OFF;
1630 /* copy native mode */
1631 memcpy(&radeon_crtc->native_mode,
1632 &radeon_encoder->native_mode,
1633 sizeof(struct drm_display_mode));
1634 src_v = crtc->mode.vdisplay;
1635 dst_v = radeon_crtc->native_mode.vdisplay;
1636 src_h = crtc->mode.hdisplay;
1637 dst_h = radeon_crtc->native_mode.hdisplay;
1638
1639 /* fix up for overscan on hdmi */
1640 if (ASIC_IS_AVIVO(rdev) &&
1641 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1642 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1643 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1644 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1645 is_hdtv_mode(mode)))) {
1646 if (radeon_encoder->underscan_hborder != 0)
1647 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1648 else
1649 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1650 if (radeon_encoder->underscan_vborder != 0)
1651 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1652 else
1653 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1654 radeon_crtc->rmx_type = RMX_FULL;
1655 src_v = crtc->mode.vdisplay;
1656 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1657 src_h = crtc->mode.hdisplay;
1658 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1659 }
1660 first = false;
1661 } else {
1662 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1663 /* WARNING: Right now this can't happen but
1664 * in the future we need to check that scaling
1665 * are consistent across different encoder
1666 * (ie all encoder can work with the same
1667 * scaling).
1668 */
1669 DRM_ERROR("Scaling not consistent across encoder.\n");
1670 return false;
1671 }
1672 }
1673 }
1674 if (radeon_crtc->rmx_type != RMX_OFF) {
1675 fixed20_12 a, b;
1676 a.full = dfixed_const(src_v);
1677 b.full = dfixed_const(dst_v);
1678 radeon_crtc->vsc.full = dfixed_div(a, b);
1679 a.full = dfixed_const(src_h);
1680 b.full = dfixed_const(dst_h);
1681 radeon_crtc->hsc.full = dfixed_div(a, b);
1682 } else {
1683 radeon_crtc->vsc.full = dfixed_const(1);
1684 radeon_crtc->hsc.full = dfixed_const(1);
1685 }
1686 return true;
1687 }
1688
1689 /*
1690 * Retrieve current video scanout position of crtc on a given gpu, and
1691 * an optional accurate timestamp of when query happened.
1692 *
1693 * \param dev Device to query.
1694 * \param crtc Crtc to query.
1695 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1696 * \param *vpos Location where vertical scanout position should be stored.
1697 * \param *hpos Location where horizontal scanout position should go.
1698 * \param *stime Target location for timestamp taken immediately before
1699 * scanout position query. Can be NULL to skip timestamp.
1700 * \param *etime Target location for timestamp taken immediately after
1701 * scanout position query. Can be NULL to skip timestamp.
1702 *
1703 * Returns vpos as a positive number while in active scanout area.
1704 * Returns vpos as a negative number inside vblank, counting the number
1705 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1706 * until start of active scanout / end of vblank."
1707 *
1708 * \return Flags, or'ed together as follows:
1709 *
1710 * DRM_SCANOUTPOS_VALID = Query successful.
1711 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1712 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1713 * this flag means that returned position may be offset by a constant but
1714 * unknown small number of scanlines wrt. real scanout position.
1715 *
1716 */
1717 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1718 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1719 {
1720 u32 stat_crtc = 0, vbl = 0, position = 0;
1721 int vbl_start, vbl_end, vtotal, ret = 0;
1722 bool in_vbl = true;
1723
1724 struct radeon_device *rdev = dev->dev_private;
1725
1726 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1727
1728 /* Get optional system timestamp before query. */
1729 if (stime)
1730 *stime = ktime_get();
1731
1732 if (ASIC_IS_DCE4(rdev)) {
1733 if (crtc == 0) {
1734 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1735 EVERGREEN_CRTC0_REGISTER_OFFSET);
1736 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1737 EVERGREEN_CRTC0_REGISTER_OFFSET);
1738 ret |= DRM_SCANOUTPOS_VALID;
1739 }
1740 if (crtc == 1) {
1741 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1742 EVERGREEN_CRTC1_REGISTER_OFFSET);
1743 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1744 EVERGREEN_CRTC1_REGISTER_OFFSET);
1745 ret |= DRM_SCANOUTPOS_VALID;
1746 }
1747 if (crtc == 2) {
1748 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1749 EVERGREEN_CRTC2_REGISTER_OFFSET);
1750 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1751 EVERGREEN_CRTC2_REGISTER_OFFSET);
1752 ret |= DRM_SCANOUTPOS_VALID;
1753 }
1754 if (crtc == 3) {
1755 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1756 EVERGREEN_CRTC3_REGISTER_OFFSET);
1757 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1758 EVERGREEN_CRTC3_REGISTER_OFFSET);
1759 ret |= DRM_SCANOUTPOS_VALID;
1760 }
1761 if (crtc == 4) {
1762 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1763 EVERGREEN_CRTC4_REGISTER_OFFSET);
1764 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1765 EVERGREEN_CRTC4_REGISTER_OFFSET);
1766 ret |= DRM_SCANOUTPOS_VALID;
1767 }
1768 if (crtc == 5) {
1769 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1770 EVERGREEN_CRTC5_REGISTER_OFFSET);
1771 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1772 EVERGREEN_CRTC5_REGISTER_OFFSET);
1773 ret |= DRM_SCANOUTPOS_VALID;
1774 }
1775 } else if (ASIC_IS_AVIVO(rdev)) {
1776 if (crtc == 0) {
1777 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1778 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1779 ret |= DRM_SCANOUTPOS_VALID;
1780 }
1781 if (crtc == 1) {
1782 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1783 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1784 ret |= DRM_SCANOUTPOS_VALID;
1785 }
1786 } else {
1787 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1788 if (crtc == 0) {
1789 /* Assume vbl_end == 0, get vbl_start from
1790 * upper 16 bits.
1791 */
1792 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1793 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1794 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1795 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1796 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1797 if (!(stat_crtc & 1))
1798 in_vbl = false;
1799
1800 ret |= DRM_SCANOUTPOS_VALID;
1801 }
1802 if (crtc == 1) {
1803 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1804 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1805 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1806 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1807 if (!(stat_crtc & 1))
1808 in_vbl = false;
1809
1810 ret |= DRM_SCANOUTPOS_VALID;
1811 }
1812 }
1813
1814 /* Get optional system timestamp after query. */
1815 if (etime)
1816 *etime = ktime_get();
1817
1818 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1819
1820 /* Decode into vertical and horizontal scanout position. */
1821 *vpos = position & 0x1fff;
1822 *hpos = (position >> 16) & 0x1fff;
1823
1824 /* Valid vblank area boundaries from gpu retrieved? */
1825 if (vbl > 0) {
1826 /* Yes: Decode. */
1827 ret |= DRM_SCANOUTPOS_ACCURATE;
1828 vbl_start = vbl & 0x1fff;
1829 vbl_end = (vbl >> 16) & 0x1fff;
1830 }
1831 else {
1832 /* No: Fake something reasonable which gives at least ok results. */
1833 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1834 vbl_end = 0;
1835 }
1836
1837 /* Test scanout position against vblank region. */
1838 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1839 in_vbl = false;
1840
1841 /* Check if inside vblank area and apply corrective offsets:
1842 * vpos will then be >=0 in video scanout area, but negative
1843 * within vblank area, counting down the number of lines until
1844 * start of scanout.
1845 */
1846
1847 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1848 if (in_vbl && (*vpos >= vbl_start)) {
1849 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1850 *vpos = *vpos - vtotal;
1851 }
1852
1853 /* Correct for shifted end of vbl at vbl_end. */
1854 *vpos = *vpos - vbl_end;
1855
1856 /* In vblank? */
1857 if (in_vbl)
1858 ret |= DRM_SCANOUTPOS_INVBL;
1859
1860 /* Is vpos outside nominal vblank area, but less than
1861 * 1/100 of a frame height away from start of vblank?
1862 * If so, assume this isn't a massively delayed vblank
1863 * interrupt, but a vblank interrupt that fired a few
1864 * microseconds before true start of vblank. Compensate
1865 * by adding a full frame duration to the final timestamp.
1866 * Happens, e.g., on ATI R500, R600.
1867 *
1868 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1869 */
1870 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1871 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1872 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1873
1874 if (vbl_start - *vpos < vtotal / 100) {
1875 *vpos -= vtotal;
1876
1877 /* Signal this correction as "applied". */
1878 ret |= 0x8;
1879 }
1880 }
1881
1882 return ret;
1883 }
Linux kernel - Deliverables
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