2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include <asm/div64.h>
33 #include "drm_crtc_helper.h"
36 static int radeon_ddc_dump(struct drm_connector
*connector
);
38 static void avivo_crtc_load_lut(struct drm_crtc
*crtc
)
40 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
41 struct drm_device
*dev
= crtc
->dev
;
42 struct radeon_device
*rdev
= dev
->dev_private
;
45 DRM_DEBUG("%d\n", radeon_crtc
->crtc_id
);
46 WREG32(AVIVO_DC_LUTA_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
56 WREG32(AVIVO_DC_LUT_RW_SELECT
, radeon_crtc
->crtc_id
);
57 WREG32(AVIVO_DC_LUT_RW_MODE
, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK
, 0x0000003f);
60 WREG8(AVIVO_DC_LUT_RW_INDEX
, 0);
61 for (i
= 0; i
< 256; i
++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR
,
63 (radeon_crtc
->lut_r
[i
] << 20) |
64 (radeon_crtc
->lut_g
[i
] << 10) |
65 (radeon_crtc
->lut_b
[i
] << 0));
68 WREG32(AVIVO_D1GRPH_LUT_SEL
+ radeon_crtc
->crtc_offset
, radeon_crtc
->crtc_id
);
71 static void legacy_crtc_load_lut(struct drm_crtc
*crtc
)
73 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
74 struct drm_device
*dev
= crtc
->dev
;
75 struct radeon_device
*rdev
= dev
->dev_private
;
79 dac2_cntl
= RREG32(RADEON_DAC_CNTL2
);
80 if (radeon_crtc
->crtc_id
== 0)
81 dac2_cntl
&= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL
;
83 dac2_cntl
|= RADEON_DAC2_PALETTE_ACC_CTL
;
84 WREG32(RADEON_DAC_CNTL2
, dac2_cntl
);
86 WREG8(RADEON_PALETTE_INDEX
, 0);
87 for (i
= 0; i
< 256; i
++) {
88 WREG32(RADEON_PALETTE_30_DATA
,
89 (radeon_crtc
->lut_r
[i
] << 20) |
90 (radeon_crtc
->lut_g
[i
] << 10) |
91 (radeon_crtc
->lut_b
[i
] << 0));
95 void radeon_crtc_load_lut(struct drm_crtc
*crtc
)
97 struct drm_device
*dev
= crtc
->dev
;
98 struct radeon_device
*rdev
= dev
->dev_private
;
103 if (ASIC_IS_AVIVO(rdev
))
104 avivo_crtc_load_lut(crtc
);
106 legacy_crtc_load_lut(crtc
);
109 /** Sets the color ramps on behalf of fbcon */
110 void radeon_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
113 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
115 radeon_crtc
->lut_r
[regno
] = red
>> 6;
116 radeon_crtc
->lut_g
[regno
] = green
>> 6;
117 radeon_crtc
->lut_b
[regno
] = blue
>> 6;
120 /** Gets the color ramps on behalf of fbcon */
121 void radeon_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
122 u16
*blue
, int regno
)
124 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
126 *red
= radeon_crtc
->lut_r
[regno
] << 6;
127 *green
= radeon_crtc
->lut_g
[regno
] << 6;
128 *blue
= radeon_crtc
->lut_b
[regno
] << 6;
131 static void radeon_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
132 u16
*blue
, uint32_t size
)
134 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
141 /* userspace palettes are always correct as is */
142 for (i
= 0; i
< 256; i
++) {
143 radeon_crtc
->lut_r
[i
] = red
[i
] >> 6;
144 radeon_crtc
->lut_g
[i
] = green
[i
] >> 6;
145 radeon_crtc
->lut_b
[i
] = blue
[i
] >> 6;
147 radeon_crtc_load_lut(crtc
);
150 static void radeon_crtc_destroy(struct drm_crtc
*crtc
)
152 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
154 drm_crtc_cleanup(crtc
);
158 static const struct drm_crtc_funcs radeon_crtc_funcs
= {
159 .cursor_set
= radeon_crtc_cursor_set
,
160 .cursor_move
= radeon_crtc_cursor_move
,
161 .gamma_set
= radeon_crtc_gamma_set
,
162 .set_config
= drm_crtc_helper_set_config
,
163 .destroy
= radeon_crtc_destroy
,
166 static void radeon_crtc_init(struct drm_device
*dev
, int index
)
168 struct radeon_device
*rdev
= dev
->dev_private
;
169 struct radeon_crtc
*radeon_crtc
;
172 radeon_crtc
= kzalloc(sizeof(struct radeon_crtc
) + (RADEONFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
173 if (radeon_crtc
== NULL
)
176 drm_crtc_init(dev
, &radeon_crtc
->base
, &radeon_crtc_funcs
);
178 drm_mode_crtc_set_gamma_size(&radeon_crtc
->base
, 256);
179 radeon_crtc
->crtc_id
= index
;
180 rdev
->mode_info
.crtcs
[index
] = radeon_crtc
;
183 radeon_crtc
->mode_set
.crtc
= &radeon_crtc
->base
;
184 radeon_crtc
->mode_set
.connectors
= (struct drm_connector
**)(radeon_crtc
+ 1);
185 radeon_crtc
->mode_set
.num_connectors
= 0;
188 for (i
= 0; i
< 256; i
++) {
189 radeon_crtc
->lut_r
[i
] = i
<< 2;
190 radeon_crtc
->lut_g
[i
] = i
<< 2;
191 radeon_crtc
->lut_b
[i
] = i
<< 2;
194 if (rdev
->is_atom_bios
&& (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
))
195 radeon_atombios_init_crtc(dev
, radeon_crtc
);
197 radeon_legacy_init_crtc(dev
, radeon_crtc
);
200 static const char *encoder_names
[34] = {
220 "INTERNAL_KLDSCP_TMDS1",
221 "INTERNAL_KLDSCP_DVO1",
222 "INTERNAL_KLDSCP_DAC1",
223 "INTERNAL_KLDSCP_DAC2",
232 "INTERNAL_KLDSCP_LVTMA",
237 static const char *connector_names
[13] = {
253 static void radeon_print_display_setup(struct drm_device
*dev
)
255 struct drm_connector
*connector
;
256 struct radeon_connector
*radeon_connector
;
257 struct drm_encoder
*encoder
;
258 struct radeon_encoder
*radeon_encoder
;
262 DRM_INFO("Radeon Display Connectors\n");
263 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
264 radeon_connector
= to_radeon_connector(connector
);
265 DRM_INFO("Connector %d:\n", i
);
266 DRM_INFO(" %s\n", connector_names
[connector
->connector_type
]);
267 if (radeon_connector
->ddc_bus
)
268 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
269 radeon_connector
->ddc_bus
->rec
.mask_clk_reg
,
270 radeon_connector
->ddc_bus
->rec
.mask_data_reg
,
271 radeon_connector
->ddc_bus
->rec
.a_clk_reg
,
272 radeon_connector
->ddc_bus
->rec
.a_data_reg
,
273 radeon_connector
->ddc_bus
->rec
.en_clk_reg
,
274 radeon_connector
->ddc_bus
->rec
.en_data_reg
,
275 radeon_connector
->ddc_bus
->rec
.y_clk_reg
,
276 radeon_connector
->ddc_bus
->rec
.y_data_reg
);
277 DRM_INFO(" Encoders:\n");
278 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
279 radeon_encoder
= to_radeon_encoder(encoder
);
280 devices
= radeon_encoder
->devices
& radeon_connector
->devices
;
282 if (devices
& ATOM_DEVICE_CRT1_SUPPORT
)
283 DRM_INFO(" CRT1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
284 if (devices
& ATOM_DEVICE_CRT2_SUPPORT
)
285 DRM_INFO(" CRT2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
286 if (devices
& ATOM_DEVICE_LCD1_SUPPORT
)
287 DRM_INFO(" LCD1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
288 if (devices
& ATOM_DEVICE_DFP1_SUPPORT
)
289 DRM_INFO(" DFP1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
290 if (devices
& ATOM_DEVICE_DFP2_SUPPORT
)
291 DRM_INFO(" DFP2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
292 if (devices
& ATOM_DEVICE_DFP3_SUPPORT
)
293 DRM_INFO(" DFP3: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
294 if (devices
& ATOM_DEVICE_DFP4_SUPPORT
)
295 DRM_INFO(" DFP4: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
296 if (devices
& ATOM_DEVICE_DFP5_SUPPORT
)
297 DRM_INFO(" DFP5: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
298 if (devices
& ATOM_DEVICE_TV1_SUPPORT
)
299 DRM_INFO(" TV1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
300 if (devices
& ATOM_DEVICE_CV_SUPPORT
)
301 DRM_INFO(" CV: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
308 static bool radeon_setup_enc_conn(struct drm_device
*dev
)
310 struct radeon_device
*rdev
= dev
->dev_private
;
311 struct drm_connector
*drm_connector
;
315 if (rdev
->is_atom_bios
) {
316 if (rdev
->family
>= CHIP_R600
)
317 ret
= radeon_get_atom_connector_info_from_object_table(dev
);
319 ret
= radeon_get_atom_connector_info_from_supported_devices_table(dev
);
321 ret
= radeon_get_legacy_connector_info_from_bios(dev
);
323 if (!ASIC_IS_AVIVO(rdev
))
324 ret
= radeon_get_legacy_connector_info_from_table(dev
);
327 radeon_setup_encoder_clones(dev
);
328 radeon_print_display_setup(dev
);
329 list_for_each_entry(drm_connector
, &dev
->mode_config
.connector_list
, head
)
330 radeon_ddc_dump(drm_connector
);
336 int radeon_ddc_get_modes(struct radeon_connector
*radeon_connector
)
340 if (!radeon_connector
->ddc_bus
)
342 if (!radeon_connector
->edid
) {
343 radeon_i2c_do_lock(radeon_connector
->ddc_bus
, 1);
344 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
, &radeon_connector
->ddc_bus
->adapter
);
345 radeon_i2c_do_lock(radeon_connector
->ddc_bus
, 0);
348 if (radeon_connector
->edid
) {
349 drm_mode_connector_update_edid_property(&radeon_connector
->base
, radeon_connector
->edid
);
350 ret
= drm_add_edid_modes(&radeon_connector
->base
, radeon_connector
->edid
);
353 drm_mode_connector_update_edid_property(&radeon_connector
->base
, NULL
);
357 static int radeon_ddc_dump(struct drm_connector
*connector
)
360 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
363 if (!radeon_connector
->ddc_bus
)
365 radeon_i2c_do_lock(radeon_connector
->ddc_bus
, 1);
366 edid
= drm_get_edid(connector
, &radeon_connector
->ddc_bus
->adapter
);
367 radeon_i2c_do_lock(radeon_connector
->ddc_bus
, 0);
374 static inline uint32_t radeon_div(uint64_t n
, uint32_t d
)
384 void radeon_compute_pll(struct radeon_pll
*pll
,
386 uint32_t *dot_clock_p
,
388 uint32_t *frac_fb_div_p
,
390 uint32_t *post_div_p
,
393 uint32_t min_ref_div
= pll
->min_ref_div
;
394 uint32_t max_ref_div
= pll
->max_ref_div
;
395 uint32_t min_fractional_feed_div
= 0;
396 uint32_t max_fractional_feed_div
= 0;
397 uint32_t best_vco
= pll
->best_vco
;
398 uint32_t best_post_div
= 1;
399 uint32_t best_ref_div
= 1;
400 uint32_t best_feedback_div
= 1;
401 uint32_t best_frac_feedback_div
= 0;
402 uint32_t best_freq
= -1;
403 uint32_t best_error
= 0xffffffff;
404 uint32_t best_vco_diff
= 1;
407 DRM_DEBUG("PLL freq %llu %u %u\n", freq
, pll
->min_ref_div
, pll
->max_ref_div
);
410 if (flags
& RADEON_PLL_USE_REF_DIV
)
411 min_ref_div
= max_ref_div
= pll
->reference_div
;
413 while (min_ref_div
< max_ref_div
-1) {
414 uint32_t mid
= (min_ref_div
+ max_ref_div
) / 2;
415 uint32_t pll_in
= pll
->reference_freq
/ mid
;
416 if (pll_in
< pll
->pll_in_min
)
418 else if (pll_in
> pll
->pll_in_max
)
425 if (flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
426 min_fractional_feed_div
= pll
->min_frac_feedback_div
;
427 max_fractional_feed_div
= pll
->max_frac_feedback_div
;
430 for (post_div
= pll
->min_post_div
; post_div
<= pll
->max_post_div
; ++post_div
) {
433 if ((flags
& RADEON_PLL_NO_ODD_POST_DIV
) && (post_div
& 1))
436 /* legacy radeons only have a few post_divs */
437 if (flags
& RADEON_PLL_LEGACY
) {
438 if ((post_div
== 5) ||
449 for (ref_div
= min_ref_div
; ref_div
<= max_ref_div
; ++ref_div
) {
450 uint32_t feedback_div
, current_freq
= 0, error
, vco_diff
;
451 uint32_t pll_in
= pll
->reference_freq
/ ref_div
;
452 uint32_t min_feed_div
= pll
->min_feedback_div
;
453 uint32_t max_feed_div
= pll
->max_feedback_div
+ 1;
455 if (pll_in
< pll
->pll_in_min
|| pll_in
> pll
->pll_in_max
)
458 while (min_feed_div
< max_feed_div
) {
460 uint32_t min_frac_feed_div
= min_fractional_feed_div
;
461 uint32_t max_frac_feed_div
= max_fractional_feed_div
+ 1;
462 uint32_t frac_feedback_div
;
465 feedback_div
= (min_feed_div
+ max_feed_div
) / 2;
467 tmp
= (uint64_t)pll
->reference_freq
* feedback_div
;
468 vco
= radeon_div(tmp
, ref_div
);
470 if (vco
< pll
->pll_out_min
) {
471 min_feed_div
= feedback_div
+ 1;
473 } else if (vco
> pll
->pll_out_max
) {
474 max_feed_div
= feedback_div
;
478 while (min_frac_feed_div
< max_frac_feed_div
) {
479 frac_feedback_div
= (min_frac_feed_div
+ max_frac_feed_div
) / 2;
480 tmp
= (uint64_t)pll
->reference_freq
* 10000 * feedback_div
;
481 tmp
+= (uint64_t)pll
->reference_freq
* 1000 * frac_feedback_div
;
482 current_freq
= radeon_div(tmp
, ref_div
* post_div
);
484 if (flags
& RADEON_PLL_PREFER_CLOSEST_LOWER
) {
485 error
= freq
- current_freq
;
486 error
= error
< 0 ? 0xffffffff : error
;
488 error
= abs(current_freq
- freq
);
489 vco_diff
= abs(vco
- best_vco
);
491 if ((best_vco
== 0 && error
< best_error
) ||
493 (error
< best_error
- 100 ||
494 (abs(error
- best_error
) < 100 && vco_diff
< best_vco_diff
)))) {
495 best_post_div
= post_div
;
496 best_ref_div
= ref_div
;
497 best_feedback_div
= feedback_div
;
498 best_frac_feedback_div
= frac_feedback_div
;
499 best_freq
= current_freq
;
501 best_vco_diff
= vco_diff
;
502 } else if (current_freq
== freq
) {
503 if (best_freq
== -1) {
504 best_post_div
= post_div
;
505 best_ref_div
= ref_div
;
506 best_feedback_div
= feedback_div
;
507 best_frac_feedback_div
= frac_feedback_div
;
508 best_freq
= current_freq
;
510 best_vco_diff
= vco_diff
;
511 } else if (((flags
& RADEON_PLL_PREFER_LOW_REF_DIV
) && (ref_div
< best_ref_div
)) ||
512 ((flags
& RADEON_PLL_PREFER_HIGH_REF_DIV
) && (ref_div
> best_ref_div
)) ||
513 ((flags
& RADEON_PLL_PREFER_LOW_FB_DIV
) && (feedback_div
< best_feedback_div
)) ||
514 ((flags
& RADEON_PLL_PREFER_HIGH_FB_DIV
) && (feedback_div
> best_feedback_div
)) ||
515 ((flags
& RADEON_PLL_PREFER_LOW_POST_DIV
) && (post_div
< best_post_div
)) ||
516 ((flags
& RADEON_PLL_PREFER_HIGH_POST_DIV
) && (post_div
> best_post_div
))) {
517 best_post_div
= post_div
;
518 best_ref_div
= ref_div
;
519 best_feedback_div
= feedback_div
;
520 best_frac_feedback_div
= frac_feedback_div
;
521 best_freq
= current_freq
;
523 best_vco_diff
= vco_diff
;
526 if (current_freq
< freq
)
527 min_frac_feed_div
= frac_feedback_div
+ 1;
529 max_frac_feed_div
= frac_feedback_div
;
531 if (current_freq
< freq
)
532 min_feed_div
= feedback_div
+ 1;
534 max_feed_div
= feedback_div
;
539 *dot_clock_p
= best_freq
/ 10000;
540 *fb_div_p
= best_feedback_div
;
541 *frac_fb_div_p
= best_frac_feedback_div
;
542 *ref_div_p
= best_ref_div
;
543 *post_div_p
= best_post_div
;
546 static void radeon_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
548 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
549 struct drm_device
*dev
= fb
->dev
;
552 radeonfb_remove(dev
, fb
);
554 if (radeon_fb
->obj
) {
555 radeon_gem_object_unpin(radeon_fb
->obj
);
556 mutex_lock(&dev
->struct_mutex
);
557 drm_gem_object_unreference(radeon_fb
->obj
);
558 mutex_unlock(&dev
->struct_mutex
);
560 drm_framebuffer_cleanup(fb
);
564 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
565 struct drm_file
*file_priv
,
566 unsigned int *handle
)
568 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
570 return drm_gem_handle_create(file_priv
, radeon_fb
->obj
, handle
);
573 static const struct drm_framebuffer_funcs radeon_fb_funcs
= {
574 .destroy
= radeon_user_framebuffer_destroy
,
575 .create_handle
= radeon_user_framebuffer_create_handle
,
578 struct drm_framebuffer
*
579 radeon_framebuffer_create(struct drm_device
*dev
,
580 struct drm_mode_fb_cmd
*mode_cmd
,
581 struct drm_gem_object
*obj
)
583 struct radeon_framebuffer
*radeon_fb
;
585 radeon_fb
= kzalloc(sizeof(*radeon_fb
), GFP_KERNEL
);
586 if (radeon_fb
== NULL
) {
589 drm_framebuffer_init(dev
, &radeon_fb
->base
, &radeon_fb_funcs
);
590 drm_helper_mode_fill_fb_struct(&radeon_fb
->base
, mode_cmd
);
591 radeon_fb
->obj
= obj
;
592 return &radeon_fb
->base
;
595 static struct drm_framebuffer
*
596 radeon_user_framebuffer_create(struct drm_device
*dev
,
597 struct drm_file
*file_priv
,
598 struct drm_mode_fb_cmd
*mode_cmd
)
600 struct drm_gem_object
*obj
;
602 obj
= drm_gem_object_lookup(dev
, file_priv
, mode_cmd
->handle
);
604 return radeon_framebuffer_create(dev
, mode_cmd
, obj
);
607 static const struct drm_mode_config_funcs radeon_mode_funcs
= {
608 .fb_create
= radeon_user_framebuffer_create
,
609 .fb_changed
= radeonfb_probe
,
612 struct drm_prop_enum_list
{
617 static struct drm_prop_enum_list radeon_tmds_pll_enum_list
[] =
622 static struct drm_prop_enum_list radeon_tv_std_enum_list
[] =
623 { { TV_STD_NTSC
, "ntsc" },
624 { TV_STD_PAL
, "pal" },
625 { TV_STD_PAL_M
, "pal-m" },
626 { TV_STD_PAL_60
, "pal-60" },
627 { TV_STD_NTSC_J
, "ntsc-j" },
628 { TV_STD_SCART_PAL
, "scart-pal" },
629 { TV_STD_PAL_CN
, "pal-cn" },
630 { TV_STD_SECAM
, "secam" },
633 int radeon_modeset_create_props(struct radeon_device
*rdev
)
637 if (rdev
->is_atom_bios
) {
638 rdev
->mode_info
.coherent_mode_property
=
639 drm_property_create(rdev
->ddev
,
642 if (!rdev
->mode_info
.coherent_mode_property
)
645 rdev
->mode_info
.coherent_mode_property
->values
[0] = 0;
646 rdev
->mode_info
.coherent_mode_property
->values
[0] = 1;
649 if (!ASIC_IS_AVIVO(rdev
)) {
650 sz
= ARRAY_SIZE(radeon_tmds_pll_enum_list
);
651 rdev
->mode_info
.tmds_pll_property
=
652 drm_property_create(rdev
->ddev
,
655 for (i
= 0; i
< sz
; i
++) {
656 drm_property_add_enum(rdev
->mode_info
.tmds_pll_property
,
658 radeon_tmds_pll_enum_list
[i
].type
,
659 radeon_tmds_pll_enum_list
[i
].name
);
663 rdev
->mode_info
.load_detect_property
=
664 drm_property_create(rdev
->ddev
,
666 "load detection", 2);
667 if (!rdev
->mode_info
.load_detect_property
)
669 rdev
->mode_info
.load_detect_property
->values
[0] = 0;
670 rdev
->mode_info
.load_detect_property
->values
[0] = 1;
672 drm_mode_create_scaling_mode_property(rdev
->ddev
);
674 sz
= ARRAY_SIZE(radeon_tv_std_enum_list
);
675 rdev
->mode_info
.tv_std_property
=
676 drm_property_create(rdev
->ddev
,
679 for (i
= 0; i
< sz
; i
++) {
680 drm_property_add_enum(rdev
->mode_info
.tv_std_property
,
682 radeon_tv_std_enum_list
[i
].type
,
683 radeon_tv_std_enum_list
[i
].name
);
689 int radeon_modeset_init(struct radeon_device
*rdev
)
694 drm_mode_config_init(rdev
->ddev
);
695 rdev
->mode_info
.mode_config_initialized
= true;
697 rdev
->ddev
->mode_config
.funcs
= (void *)&radeon_mode_funcs
;
699 if (ASIC_IS_AVIVO(rdev
)) {
700 rdev
->ddev
->mode_config
.max_width
= 8192;
701 rdev
->ddev
->mode_config
.max_height
= 8192;
703 rdev
->ddev
->mode_config
.max_width
= 4096;
704 rdev
->ddev
->mode_config
.max_height
= 4096;
707 rdev
->ddev
->mode_config
.fb_base
= rdev
->mc
.aper_base
;
709 ret
= radeon_modeset_create_props(rdev
);
714 if (rdev
->flags
& RADEON_SINGLE_CRTC
)
718 for (i
= 0; i
< num_crtc
; i
++) {
719 radeon_crtc_init(rdev
->ddev
, i
);
722 /* okay we should have all the bios connectors */
723 ret
= radeon_setup_enc_conn(rdev
->ddev
);
727 drm_helper_initial_config(rdev
->ddev
);
731 void radeon_modeset_fini(struct radeon_device
*rdev
)
733 if (rdev
->mode_info
.mode_config_initialized
) {
734 drm_mode_config_cleanup(rdev
->ddev
);
735 rdev
->mode_info
.mode_config_initialized
= false;
739 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc
*crtc
,
740 struct drm_display_mode
*mode
,
741 struct drm_display_mode
*adjusted_mode
)
743 struct drm_device
*dev
= crtc
->dev
;
744 struct drm_encoder
*encoder
;
745 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
746 struct radeon_encoder
*radeon_encoder
;
749 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
750 radeon_encoder
= to_radeon_encoder(encoder
);
751 if (encoder
->crtc
!= crtc
)
755 if (radeon_encoder
->rmx_type
== RMX_OFF
)
756 radeon_crtc
->rmx_type
= RMX_OFF
;
757 else if (mode
->hdisplay
< radeon_encoder
->native_mode
.hdisplay
||
758 mode
->vdisplay
< radeon_encoder
->native_mode
.vdisplay
)
759 radeon_crtc
->rmx_type
= radeon_encoder
->rmx_type
;
761 radeon_crtc
->rmx_type
= RMX_OFF
;
762 /* copy native mode */
763 memcpy(&radeon_crtc
->native_mode
,
764 &radeon_encoder
->native_mode
,
765 sizeof(struct drm_display_mode
));
768 if (radeon_crtc
->rmx_type
!= radeon_encoder
->rmx_type
) {
769 /* WARNING: Right now this can't happen but
770 * in the future we need to check that scaling
771 * are consistent accross different encoder
772 * (ie all encoder can work with the same
775 DRM_ERROR("Scaling not consistent accross encoder.\n");
780 if (radeon_crtc
->rmx_type
!= RMX_OFF
) {
782 a
.full
= rfixed_const(crtc
->mode
.vdisplay
);
783 b
.full
= rfixed_const(radeon_crtc
->native_mode
.hdisplay
);
784 radeon_crtc
->vsc
.full
= rfixed_div(a
, b
);
785 a
.full
= rfixed_const(crtc
->mode
.hdisplay
);
786 b
.full
= rfixed_const(radeon_crtc
->native_mode
.vdisplay
);
787 radeon_crtc
->hsc
.full
= rfixed_div(a
, b
);
789 radeon_crtc
->vsc
.full
= rfixed_const(1);
790 radeon_crtc
->hsc
.full
= rfixed_const(1);